Utilizing Reflow Patents (Class 438/698)
  • Patent number: 7226865
    Abstract: A process for forming a pattern contains steps of: forming a first mask pattern on a film to be etched on a substrate; forming a first pattern of the film to be etched by using the first mask pattern as a mask; forming a second mask pattern having a plane shape different from that of the first mask pattern by deforming the first mask pattern; and forming a second pattern of the film to be etched different from the first pattern by using the second mask pattern. By applying the process for forming a pattern, for example, to the formation of a semiconductor layer and source and drain electrodes of a TFT substrate of a liquid crystal display apparatus, the above-stated formation requiring two photoresist process steps in a conventional manufacturing method of a liquid crystal display apparatus can be carried out by only one process step, thereby reducing manufacturing cost thereof.
    Type: Grant
    Filed: November 7, 2005
    Date of Patent: June 5, 2007
    Assignee: NEC LCD Technologies, Ltd.
    Inventor: Shusaku Kido
  • Patent number: 7192867
    Abstract: In one embodiment, a passivation level includes a low-k dielectric. To prevent the low-k dielectric from absorbing moisture when exposed to air, exposed portions of the low-k dielectric are covered with spacers. As can be appreciated, this facilitates integration of low-k dielectrics in passivation levels. Low-k dielectrics in passivation levels help lower capacitance on metal lines, thereby reducing RC delay and increasing signal propagation speeds.
    Type: Grant
    Filed: June 26, 2002
    Date of Patent: March 20, 2007
    Assignee: Cypress Semiconductor Corporation
    Inventors: Mira Ben-Tzur, Krishnaswamy Ramkumar, Seurabh Dutta Chowdhury, Michal Efrati Fastow
  • Patent number: 7176087
    Abstract: In one aspect, the invention provides a method of forming an electrical connection in an integrated circuitry device. According to one preferred implementation, a diffusion region is formed in semiconductive material. A conductive line is formed which is laterally spaced from the diffusion region. The conductive line is preferably formed relative to and within isolation oxide which separates substrate active areas. The conductive line is subsequently interconnected with the diffusion region. According to another preferred implementation, an oxide isolation grid is formed within semiconductive material. Conductive material is formed within the oxide isolation grid to form a conductive grid therein. Selected portions of the conductive grid are then removed to define interconnect lines within the oxide isolation grid. According to another preferred implementation, a plurality of oxide isolation regions are formed over a semiconductive substrate.
    Type: Grant
    Filed: June 29, 2001
    Date of Patent: February 13, 2007
    Assignee: Micron Technology, Inc.
    Inventor: Wendell P. Noble
  • Patent number: 7144817
    Abstract: The disclosure relates to methods and solutions for precisely and rapidly etching a polyimide resin layer. Etching solutions of the present invention include 3–65% by weight of a diol containing 3 to 6 carbon atoms or a triol containing 4 to 6 carbon atoms, 10–55 % by weight of an alkali compound and water in an amount of 0.75–3.0 times the amount of the alkali compound, and can be used at 65° C. or more to rapidly etch a polyimide resin layer having an imidation degree of 50–98 % without unfavorably affecting the working atmosphere. Even if the resin layer is completely imidated after etching, the etching pattern of the resulting resin layer is not deformed with a decreased contamination by impurity ions as compared with those obtained using conventional etching solutions.
    Type: Grant
    Filed: July 12, 2001
    Date of Patent: December 5, 2006
    Assignees: Sony Corporation, Sony Chemicals Corp.
    Inventor: Hiroshi Samukawa
  • Patent number: 7060623
    Abstract: A method of deforming a pattern comprising the steps of: forming, over a substrate, a layered-structure with an upper surface including at least one selected region and at least a re-flow stopper groove, wherein the re-flow stopper groove extends outside the selected region and separate from the selected region; selectively forming at least one pattern on the selected region; and causing a re-flow of the pattern, wherein a part of an outwardly re-flowed pattern is flowed into the re-flow stopper groove, and then an outward re-flow of the pattern is restricted by the re-flow stopper groove extending outside of the pattern, thereby to form a deformed pattern with at least an outside edge part defined by an outside edge of the re-flow stopper groove.
    Type: Grant
    Filed: July 24, 2002
    Date of Patent: June 13, 2006
    Assignee: NEC LCD Technologies, Ltd.
    Inventor: Shusaku Kido
  • Patent number: 7053407
    Abstract: Disclosed are a liquid crystal display device and a method for manufacturing the same, in which wirings connected between pads and an integrated circuit is protected from being corroded. A pixel array is formed on a display region of a substrate. A plurality of pads are formed on a non-display region of the substrate. An integrated circuit is formed on the non-display region of the substrate and connected to the pads to generate a signal for operating the pixel array. Conductive barrier layers separated from each of the pads are formed on peripheral portions of the pads connected to the integrated circuit. The conductive barrier layers have electric potential equivalent to that of each of the pads in accordance with internal connections of the integrated circuit. When bumps of the integrated circuit and the pads are attached to each other, the conductive barrier layers prevent the pads and the wirings connected to the pads from being corroded.
    Type: Grant
    Filed: July 9, 2004
    Date of Patent: May 30, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-Seok Ma, Eung-Sang Lee, Young-Bae Jung, Won-Kyu Lee
  • Patent number: 7022608
    Abstract: A method, composition, and computer readable medium for planarizing a substrate. In one aspect, the composition includes one or more chelating agents and ions of at least one transition metal, one or more surfactants, one or more oxidizers, one or more corrosion inhibitors, and deionized water. The composition may further comprise one or more agents to adjust the pH and/or abrasive particles. The method comprises planarizing a substrate using a composition including one or more chelating agents and ions of at least one transition metal.
    Type: Grant
    Filed: April 21, 2003
    Date of Patent: April 4, 2006
    Assignee: Applied Materials Inc.
    Inventors: Lizhong Sun, Stan Tsai, Shijian Li
  • Patent number: 7022579
    Abstract: A method of filling vias for a PCRAM cell with a metal is described. A PCRAM intermediate structure including a substrate, a first conductor, and an insulator through which a via extends has a metallic material formed within the via and on a surface of the insulator. The metallic material may be deposited on the surface and within the via. A hard mask of a flowable oxide is deposited over the metallic material in the via to protect the metallic material in the via. A subsequent dry sputter etch removes the metallic material from the surface of the insulator and a portion of the hard mask. After complete removal of the hard mask, a glass material is recessed over the metallic material in the via. Then, a layer of a metal-containing material is formed over the glass material. Finally, a second conductor is formed on the surface of the insulator.
    Type: Grant
    Filed: March 14, 2003
    Date of Patent: April 4, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Li Li, Jiutao Li
  • Patent number: 6979526
    Abstract: A method of manufacturing a resistive semiconductor memory device (10), comprising depositing an insulating layer (34) over a workpiece (30), and defining a pattern for a plurality of alignment marks (22) and a plurality of conductive lines (54) within the insulating layer (34). A resist (50) is formed over the alignment marks (22), and a conductive material (52) is deposited over the wafer to fill the conductive pattern. The wafer is chemically-mechanically polished to remove excess conductive material from over the insulating layer and form conductive lines (54). The resist (50) is removed from over the alignment marks (22), and the alignment marks (22) are used for alignment of subsequently deposited layers of the resistive memory device (10).
    Type: Grant
    Filed: June 3, 2002
    Date of Patent: December 27, 2005
    Assignee: Infineon Technologies AG
    Inventor: Xian J. Ning
  • Patent number: 6972259
    Abstract: The invention is directed towards a method for forming openings in low-k dielectric layers and a structure for forming an opening thereof. A mask layer comprising at least one metal hard mask layer and one or more hard mask layers is applied on the dielectric layer for forming the opening.
    Type: Grant
    Filed: November 13, 2002
    Date of Patent: December 6, 2005
    Assignee: United Microelectronics Corp.
    Inventors: Chih-Jung Wang, Tong-Yu Chen
  • Patent number: 6916743
    Abstract: A semiconductor device manufacturing method that enables accurate recognition of an alignment mark and optimal formation of a buried wiring. The method includes depositing an insulation film above a semiconductor device, and then etching the insulation film to form a buried wiring hole and an alignment mark pit in the insulation film. Subsequently, a conductive film is deposited on the surface of the insulation film that includes the buried wiring hole and the alignment mark pit. The conductive film is deposited so that it is less than the depth of the alignment mark pit and less than half of a minimum opening width of the alignment mark pit.
    Type: Grant
    Filed: July 18, 2002
    Date of Patent: July 12, 2005
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Tomio Yamashita, Yoshio Okayama
  • Patent number: 6914000
    Abstract: A polishing method of the present invention is a polishing method for planarizing a film to be polished that is deposited on a wafer, and includes a step (a) of establishing a polishing rate distribution of the film to be polished that is deposited on the wafer and a target film thickness distribution after polishing of the film to be polished, a step (b) of measuring a film thickness distribution before polishing of the film to be polished, a step (c) of calculating a predicted film thickness distribution after polishing of the film to be polished from the film thickness distribution before polishing and the polishing rate distribution, a step (d) of calculating a pressure against a polishing pad for each of a plurality of regions of the film to be polished and a polishing time from the predicted film thickness distribution and the target film thickness distribution, and a step (e) of polishing while applying the pressure against the film to be polished during the polishing time.
    Type: Grant
    Filed: August 28, 2002
    Date of Patent: July 5, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Hiroyuki Kamada
  • Publication number: 20040266195
    Abstract: A method of planarization allows for the use of chemical mechanical polishing (CMP) in starting structures having films not generally suitable for CMP processes. Two material layers are formed over a starting structure, and the upper layer is planarized in a CMP process. A nonselective etch is then used to transfer the planar topography to the lower level.
    Type: Application
    Filed: June 30, 2003
    Publication date: December 30, 2004
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Omer Dokumaci, Bruce Doris, David Horak, Fen F. Jamin
  • Publication number: 20040266196
    Abstract: The invention provides a method of polishing a substrate comprising (i) contacting a substrate comprising a noble metal layer with a chemical-mechanical polishing system comprising (a) a polishing component, (b) an oxidizing agent, and (c) a liquid carrier, and (ii) abrading at least a portion of the noble metal layer to polish the substrate. The polishing component is selected from the group consisting of an abrasive, a polishing pad, or a combination thereof, and the oxidizing agent is selected from the group consisting of bromates, bromites, hypobromites, chlorates, chlorites, hypochlorites, perchlorates, iodates, hypoiodites, periodates, peroxyacetic acid, organo-halo-oxy compounds, salts thereof, and combinations thereof. The chemical-mechanical polishing system has a pH of about 9 or less, and the oxidizing agent does not produce a substantial amount of elemental halogen.
    Type: Application
    Filed: June 30, 2003
    Publication date: December 30, 2004
    Applicant: Cabot Microelectronics Corporation
    Inventors: Francesco De Rege Thesauro, Vlasta Brusic, Benjamin P. Bayer
  • Publication number: 20040253825
    Abstract: A semiconductor device comprises a base, a semiconductor element having a plurality of electrodes, a plurality of conductive lines connected to the electrodes of the semiconductor element, plating stubs attached to the conductive lines, and a plurality of wiring layers formed in a plurality of layers on the base. The plating stub attached to a first conductive line, and the plating stubs attached to one or a plurality of second conductive lines adjacent to the first conductive line, exist in different conductive wiring layers.
    Type: Application
    Filed: June 7, 2004
    Publication date: December 16, 2004
    Applicant: Matsushita Elec. Ind. Co. Ltd.
    Inventor: Takeshi Kawabata
  • Patent number: 6803308
    Abstract: The present invention is directed to a method of forming a dual damascene pattern in a fabrication process of a semiconductor device, which is capable of simplifying a fabrication process of a semiconductor device by filling a via hole with a photoresist, using a reflow phenomenon of the photoresist, in an ashing process.
    Type: Grant
    Filed: November 12, 2003
    Date of Patent: October 12, 2004
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Sang-Woo Nam
  • Patent number: 6774042
    Abstract: A method of planarizing wafers using shallow trench isolation is described. The method uses a very hard polishing pad and chemical mechanical polishing with no additional etching required. Trenches are formed in a substrate and filled with a trench dielectric, such as silicon dioxide deposited using high density plasma chemical vapor deposition. A layer of resist is then formed on the layer of trench dielectric. The wafer is then planarized using chemical mechanical polishing and a polishing pad having a hardness of at least Shore “D” 52. The hard polishing pad avoids scratch marks on the trench dielectric, the substrate surface, or any other materials deposited on the substrate surface.
    Type: Grant
    Filed: February 26, 2002
    Date of Patent: August 10, 2004
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chia-Der Chang, Yi-Tung Yen
  • Patent number: 6753259
    Abstract: Cu, for its rather low resistivity, will be widely used in sub-quarter micron meter ULSI devices. However, it is well known that Cu is easy to be corroded as exposed in air. In packaging of chips the bonding pads making of Cu will thus oxides. In addition, the reaction between Au-ball and Cu pads is very poor. On the other hand, a native AlOx layer, about 3-4 nm in thickness, will form as Al exposes in air; the formed layer is inert and is capable of protecting Al from corrosion. Furthermore, the reaction between Au-ball and Al was very well. Therefore, with the methods of the present invention, Al or AlCu as a glue and protection layer is implemented on Cu bonding pads for successful Au wiring.
    Type: Grant
    Filed: October 5, 2001
    Date of Patent: June 22, 2004
    Inventors: Syun-Ming Jang, Mong-Song Liang, Chen-Hua Yu, Chung-Shi Liu, Jane-Bai Lai
  • Patent number: 6746888
    Abstract: A transmission type display includes a thin film transistor for driving a pixel electrode, which transistor is provided on a substrate, and a conductive shield layer provided at a position over the thin film transistor and under the pixel electrode. A first planarization film is formed to bury an irregular contour of the thin film transistor and the shield layer is disposed on the planarized surface of the first planarization film, and a second planarization film is formed to bury steps of the shield layer, and the pixel electrode is disposed on the planarized surface of the second planarization film. Since the transmission type display has the structure in which the conductive shield layer is put between the upper second planarization film and the lower first planarization film each of which is made from an insulating material, the shielding performance and the alignment characteristic of the display can be improved.
    Type: Grant
    Filed: September 30, 2002
    Date of Patent: June 8, 2004
    Assignee: Sony Corporation
    Inventors: Makoto Hashimoto, Hisashi Kadota, Hirohide Fukumoto, Takusei Sato
  • Patent number: 6743724
    Abstract: A method of manufacturing semiconductor devices using an improved chemical mechanical planarization process for the planarization of the surfaces of the wafer on which the semiconductor devices are formed. The improved chemical mechanical planarization process includes the formation of a flat planar surface from a deformable coating on the surface of the wafer filling in between the surface irregularities prior to the planarization of the surface through a chemical mechanical planarization process.
    Type: Grant
    Filed: April 11, 2001
    Date of Patent: June 1, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Trung T. Doan, Guy T. Blalock, Mark Durcan, Scott G. Meikle
  • Publication number: 20040082180
    Abstract: There is disclosed a post-CMP treating liquid comprising water, and resin particles dispersed in the water and having a functional group at a surface thereof, or comprising water, resin particles dispersed in the water, and an additive having a functional group and incorporated in the water. The post-CMP treating liquid exhibits a polishing rate both of an insulating film and a conductive film of 10 nm/min or less.
    Type: Application
    Filed: December 30, 2002
    Publication date: April 29, 2004
    Inventors: Gaku Minamihaba, Yukiteru Matsui, Nobuyuki Kurashima, Hiroyuki Yano
  • Patent number: 6716739
    Abstract: A method of forming bumps on the active surface of a silicon wafer. A first under-ball metallic layer is formed over the active surface of the wafer. A second under-ball metallic layer is formed over the first under-ball metallic layer. A portion of the second under-ball metallic layer is removed to expose the first under-ball metallic layer. A plurality of solder blocks is implanted over the second under-ball metallic layer. A reflux operation is conducted and then the exposed first under-ball metallic layer is removed so that only the first under-ball metallic layer underneath the second under-ball metallic layer remains.
    Type: Grant
    Filed: May 3, 2002
    Date of Patent: April 6, 2004
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Ho-Ming Tong, Chun-Chi Lee, Jen-Kuang Fang, Min-Lung Huang, Jau-Shoung Chen, Ching-Huei Su, Chao-Fu Weng, Yung-Chi Lee
  • Patent number: 6682820
    Abstract: A recession resistant coated ceramic part. The ceramic part has a ceramic substrate and a recession resistant coating disposed on the substrate. The coating includes a plurality of layers diffusion bonded to each other and to the substrate respectively. The top most layer is characterized by a greater resistance to recession due to oxidation than that of the substrate.
    Type: Grant
    Filed: October 31, 2002
    Date of Patent: January 27, 2004
    Assignee: Saint-Gobain Ceramics & Plastics, Inc.
    Inventor: Vimal K. Pujari
  • Publication number: 20030216050
    Abstract: As disclosed herein, a method is provided for simultaneously patterning features having a first width in a first portion such as a logic portion of an integrated circuit, and having a second width in a second portion such as an array portion of an integrated circuit. The method includes depositing a feature layer over a substrate and a hardmask material layer thereover. Photoresist patterns are then formed in the first and second portions with a critical dimension mask, and are then used to etch the hardmask material layer into hardmask patterns. Sidewall spacers are provided on sidewalls of the hardmask patterns in the second portion. Then, the feature layer is simultaneously etched in both first and second portions, using the hardmask patterns in the first portion to define features having a first width, and using the hardmask patterns and the sidewall spacers in the second portion to define features having a second width.
    Type: Application
    Filed: May 17, 2002
    Publication date: November 20, 2003
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John Walter Golz, Babar Khan, Joyce C. Liu, Christopher Joseph Waskiewicz, Teresa Jacqueline Wu
  • Patent number: 6645865
    Abstract: Methods, apparatuses and substrate assembly structures for mechanical and chemical-mechanical planarizing processes used in the manufacturing microelectronic-device substrate assemblies. One aspect of the invention is directed toward a method for planarizing a microelectronic-device substrate assembly by removing material from a surface of the substrate assembly, detecting a first change in drag force between the substrate assembly and a polishing pad indicating that the substrate surface is planar, and identifying a second change in drag force between the substrate assembly and the polishing pad indicating that the planar substrate surface is at the endpoint elevation. After the second change in drag force is identified, the planarization process is stopped.
    Type: Grant
    Filed: October 30, 2002
    Date of Patent: November 11, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Karl M. Robinson, Pai Pan
  • Patent number: 6639285
    Abstract: A method for making a semiconductor device is provided. The method allows for depositing a layer of a doped dielectric. The method further allows for executing plasma etching so that one or more etchant gases flow over the layer of doped dielectric. A redepositing step allows for redepositing another layer of doped dielectric over the plasma etched layer. The present invention enables to remove crystal defects that may be present in the doped dielectric surface and improve surface planarity.
    Type: Grant
    Filed: November 15, 2000
    Date of Patent: October 28, 2003
    Assignee: Agere Systems, Inc.
    Inventors: Jonathon Marlon Lobbins, Lauri Monica Nelson, Danica Deshone Smith, Dominique A. Wesby
  • Patent number: 6627551
    Abstract: This invention discloses a method for avoiding microscratch in interlevel dielectric layer chemical mechanical polishing process. There is step height difference on surface of the interlevel dielectric layer between the memory array and the logic device, so, the interlevel dielectric layer over the memory array is etched to form a sidewall and a corner. As a key step of this invention, a dielectric layer is capped over the interlevel dielectric layer to smooth the corner and avoid microscratch thereon when performing chemical mechanical polishing process.
    Type: Grant
    Filed: June 6, 2001
    Date of Patent: September 30, 2003
    Assignee: United Microelectronics Corp.
    Inventor: Wei-Wu Liao
  • Patent number: 6620534
    Abstract: A method of forming a film having enhanced reflow characteristics at low thermal budget is disclosed, in which a surface layer of material is formed above a base layer of material, the surface layer having a lower melting point than the base layer. In this way, a composite film having two layers is created. After reflow, the surface layer can be removed using conventional methods.
    Type: Grant
    Filed: January 31, 2001
    Date of Patent: September 16, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Gurtei Sandhu, Randhir P. S. Thakur
  • Patent number: 6617252
    Abstract: A method for forming a low dielectric constant insulator in a monolithic substrate and the dielectric formed by the method. The method includes formation and patterning of a mask on a silicon substrate followed by anisotropic etching of the silicon to provide a dense array of deep holes. Isotropic etching may be used to form a cavity beneath the dense array of holes and coupling to bottoms of the holes. Sides of the holes are then thermally oxidized. A conventional dielectric is then formed, sealing tops of the holes. The conventional dielectric is optionally densified. Conventional chemical-mechanical polishing then planarizes the dielectric and further conventional processing may be carried out on the wafer to form active circuitry together with passive components such as high Q inductors.
    Type: Grant
    Filed: August 20, 2001
    Date of Patent: September 9, 2003
    Inventor: Robert Bruce Davies
  • Patent number: 6602793
    Abstract: An improved pre-clean chamber of a semiconductor processing system minimizes the generation of particulates during processing, thereby decreasing contamination levels that can adversely affect plasma vapor deposition film properties while also decreasing operational costs. The pre-clean chamber comprises an insulator collar that insulates the outside diameter surface of a wafer pedestal, thereby mitigating the etching of the wafer pedestal during etching. The pre-clean chamber further comprises a gas trench cover that directs a suitable etching gas from a gas inlet trench into streams that are focused up and towards the center of the chamber to reduce the extent to which gas bombards the chamber cover. The pre-clean chamber also comprises a bellows cover which protects the bellows of a wafer lift during etching, further reducing the dislodgment of particulates during etching.
    Type: Grant
    Filed: February 3, 2000
    Date of Patent: August 5, 2003
    Assignee: Newport Fab, LLC
    Inventor: Sean Masterson
  • Publication number: 20030129846
    Abstract: A method for pre-etching a semiconductor wafer prior to a chemical mechanical polishing (CMP) process to achieve a uniform polishing rate including providing a wafer process surface having a layer of an oxide of a metal overlying said metal to be chemically mechanically polished; removing the layer of an oxide of the metal according to an etching process; cleaning the semiconductor wafer to include the wafer process surface according to a wet cleaning process; and, chemically mechanically polishing the wafer process surface according to a CMP process including applying at least an abrasive slurry to the wafer process surface.
    Type: Application
    Filed: January 9, 2002
    Publication date: July 10, 2003
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chi-Wen Liu, Ying-Lang Wang
  • Patent number: 6555461
    Abstract: A method for forming a metal interconnect structure provides a conformal layer of barrier material, such as a nitride, within a patterned opening in a dielectric layer. The barrier material is deposited after the opening is etched to the dielectric layer, stopping on a diffusion barrier. A first layer of a metal barrier material, such as tantalum, is conformally deposited on the barrier material. A directional etch is performed that removes horizontal nitride and tantalum, leaving the nitride and tantalum on the sidewalls of the patterned opening. The barrier material prevents contamination of the dielectric layer from conductive material, such as copper, during the etching of the diffusion barrier overlying the conductive material, and during subsequent sputter etch cleaning. A thin, second metal layer is conformally deposited and forms a suitable barrier on the sidewalls of the opening, while providing low contact resistance between the second metal layer and the underlying substrate.
    Type: Grant
    Filed: June 20, 2001
    Date of Patent: April 29, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Christy Mei-Chu Woo, Suzette K. Pangrle, Minh Van Ngo
  • Publication number: 20030068894
    Abstract: A method of filling a damascene structure with liner and W characterized by improved resistance and resistance spread and adequate adhesion comprising: a given damascene structure coated by a liner which purposely provides poor step coverage into the afore mentioned structure, followed by a CVD W deposition, and followed by a metal isolation technique.
    Type: Application
    Filed: September 28, 2001
    Publication date: April 10, 2003
    Applicant: Infineon Technologies North America Corp.
    Inventors: Roy C. Iggulden, Padraic Shafer, Werner Robl, Kwong Hon Wong
  • Patent number: 6531353
    Abstract: A method for fabricating a semiconductor device is disclosed, which reduces defects of a device by improving the process to improve the production yield.
    Type: Grant
    Filed: July 17, 2001
    Date of Patent: March 11, 2003
    Assignee: Hynix Semiconductor, Inc.
    Inventor: Ki Jik Lee
  • Publication number: 20020187565
    Abstract: In order to have a remarkably planarized substrate easily, a glass thin film is predeposited on a surface of a non-magnetic substrate. The non-magnetic substrate is subjected to heat treatment until the glass thin film is softened to a predetermined viscosity, and then the non-magnetic substrate is cured until the glass thin film is hardened.
    Type: Application
    Filed: March 27, 2002
    Publication date: December 12, 2002
    Inventors: Yoshihiko Inoue, Seiichi Ogata
  • Publication number: 20020168860
    Abstract: This relates to optical devices such as planar light-wave components/circuits which are designed to have a high waveguide pattern density effecting a higher etch selectivity and overall improved dimensional control of the functional waveguides on the optical device.
    Type: Application
    Filed: July 10, 2001
    Publication date: November 14, 2002
    Inventors: Jongik Won, Calvin Ka Kuen Ho, Fan Zhong, Liang Zhao
  • Patent number: 6479389
    Abstract: This invention describes two new methods to form copper alloy films. In the first embodiment of this invention physical vapor deposition (PVD) or sputtering of a copper alloy film, is then followed by a chemical vapor deposition (CVD) or electro-chemical deposition (ECD) of a layer of pure copper. In the second embodiment of this invention chemical vapor deposition (CVD) or electro-chemical deposition (ECD) deposits a layer of pure copper, which is then followed by physical vapor deposition (PVD) or sputtering of a copper alloy film. In yet another embodiment to these methods, special, separate low temperature annealing steps follow said methods to enhance copper alloy formation. By the two deposition techniques briefly described above, high aspect ratio vias and trenches can be filled with copper corrosion and electromigration resistant alloys.
    Type: Grant
    Filed: October 4, 1999
    Date of Patent: November 12, 2002
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Ming-Hsing Tsai, Sheng Hsiang Chen
  • Publication number: 20020137349
    Abstract: A method for forming a low dielectric constant insulator in a monolithic substrate and the dielectric formed by the method. The method includes formation and patterning of a mask on a silicon substrate followed by anisotropic etching of the silicon to provide a dense array of deep holes. Isotropic etching may be used to form a cavity beneath the dense array of holes and coupling to bottoms of the holes. Sides of the holes are then thermally oxidized. A conventional dielectric is then formed, sealing tops of the holes. The conventional dielectric is optionally densified. Conventional chemical-mechanical polishing then planarizes the dielectric and further conventional processing may be carried out on the wafer to form active circuitry together with passive components such as high Q inductors.
    Type: Application
    Filed: August 20, 2001
    Publication date: September 26, 2002
    Inventor: Robert Bruce Davies
  • Patent number: 6451181
    Abstract: A method for forming an improved copper inlaid interconnect (FIG. 11) begins by performing an RF preclean operation (408) on the inlaid structure in a chamber (10). The RF preclean rounds corners (210a and 206a) of the structure to reduce voiding and improve step coverage while not significantly removing copper atoms from the underlying exposed copper interconnects surfaces (202a). A tantalum barrier (220) is then deposited where one portion of the tantalum barrier is more tensile than another portion of the tantalum barrier. After formation of the barrier layer (220), a copper seed layer (222) is formed over a top of the barrier layer. The copper layer is formed while clamping the wafer with an improved clamp (85) which reduces copper peeling and contamination at wafer edges. Copper electroplating and chemical mechanical polishing (CMP) processes are then used to complete the copper interconnect structure.
    Type: Grant
    Filed: March 2, 1999
    Date of Patent: September 17, 2002
    Assignee: Motorola, Inc.
    Inventors: Dean J. Denning, Sam S. Garcia, Bradley P. Smith, Daniel J. Loop, Gregory Norman Hamilton, Md. Rabiul Islam, Brian G. Anthony
  • Publication number: 20020123226
    Abstract: A method of forming a self-aligned contact opening in an insulative layer formed over a substrate in a semiconductor device involves etching the insulative layer with at least one fluorocarbon and ammonia.
    Type: Application
    Filed: January 3, 2001
    Publication date: September 5, 2002
    Inventor: Shane J. Trapp
  • Publication number: 20020098705
    Abstract: A method of lithographically forming a semiconductor device that reduces the effects of edge topography when misalignment occurs. The method comprises forming a dielectric layer (20) having a top surface, etching a trench (22) in the dielectric layer and depositing a liner (26) on the top surface of the dielectric layer and within the trench. A metal layer (24) is then deposited on the liner and polishes until the metal layer is coplanar with the liner on the top surface of the dielectric layer, leaving a portion of the liner exposed. A stack layer (32) is deposited atop the exposed liner and on the polished metal layer and patterned. The exposed liner and non-patterned portion of the stack layer are removed simultaneously. A magnetic RAM (MRAM) can be processed in which undesirable magnetic properties caused by mis-alignment of the magnetic stack are minimized because of the improved edge topography.
    Type: Application
    Filed: January 18, 2002
    Publication date: July 25, 2002
    Applicant: Infineon Technologies North America Corp.
    Inventor: Kia-Seng Low
  • Patent number: 6423638
    Abstract: An ultrasonic driver (105) is used to vibrate a filter disk (103) at ultrasonic frequencies. Vibrations are used to break up agglomerates into smaller pieces that pass through filter disk (103). The energy is controlled to minimize the translational energy given to the particles as they are broken up to prevent reagglomeration. The frequency and amplitude of the vibration is controlled to operate out of or in low energy cavitation.
    Type: Grant
    Filed: September 28, 1999
    Date of Patent: July 23, 2002
    Assignee: Motorola, Inc.
    Inventor: James F. Vanell
  • Patent number: 6413870
    Abstract: A method for removing scratches from a dielectric layer comprising the steps of: providing a layer of a reflowable dielectric material; and heating the dielectric layer to a temperature sufficient to cause the reflowable dielectric material to reflow is provided. This method provides a manner to remove the scratches created during the chemical mechanical polish steps, which can later become filled with metallization, causing shorts in the circuitry and subsequent integrated circuit chip failure.
    Type: Grant
    Filed: September 30, 1996
    Date of Patent: July 2, 2002
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey P. Gambino, William F. Landers
  • Patent number: 6368957
    Abstract: In the method for manufacturing a semiconductor device according to the present invention, after forming a BPSG film 110 on a silicon substrate 100, a preparatory hole 120 that reaches a specific depth and has a larger diameter than a contact hole 118 is formed at a position where the contact hole 118 (see FIG. 4) is to be formed at the BPSG film 110. Thus, polysilicon side walls 114 (see FIG. 4) formed at side portions of a polysilicon film 112 (see FIG. 4) are also formed at the side walls of the preparatory hole 120. As a result, the contact hole 118 (see FIG. 4) free of shape defects can be formed by using an etching mask 116 (see FIG. 4) constituted of the polysilicon film 112 and the polysilicon side walls 114. This structure prevents defects related to the shape of the hole and reduces electrical defects such as shorting.
    Type: Grant
    Filed: April 16, 1999
    Date of Patent: April 9, 2002
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Takuji Horio
  • Publication number: 20020019138
    Abstract: A method for removing structures from a substrate is described. The method includes providing a substrate that has the structures that must be removed, applying a sacrifice layer, and removing the structures and the sacrifice layer in a polishing step. The method has the advantage that the sacrifice layer surrounds the structures that must be removed and stabilizes them, so that the structures can be eroded slowly and successively in the subsequent polishing step without breaking off. This prevents a smearing of the material of the structures such as occurs given direct polishing without a sacrifice layer.
    Type: Application
    Filed: April 30, 2001
    Publication date: February 14, 2002
    Inventors: Gerhard Beitel, Mattias Ahlstedt, Walter Hartner, Gunther Schindler, Marcus Kastner, Volker Weinrich
  • Patent number: 6342448
    Abstract: A method for forming an improved TaN copper barrier for a copper damascene process is described which has improved adhesion to low-k dielectric layers and also improves the wetting of a copper seed layer deposited over it thereby improving the structure of the copper seed layer which is critical to achieving uniform, high quality electrochemical copper deposition. The copper barrier is a composite structure having an lower thin Ta rich TaN portion which mixes into and reacts with the surface of the low-k dielectric layer, forming a strongly bonded transition layer between the low-k material and the remaining portion of the barrier layer. The presence of the transition layer causes compressive film stress rather than tensile stress as found in the conventional TaN barrier. As a result, the barrier layer does not delaminate from the low-k layer during subsequent processing.
    Type: Grant
    Filed: May 31, 2000
    Date of Patent: January 29, 2002
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Jing-Cheng Lin, Shau-Lin Shue, Chen-Hua Yu
  • Publication number: 20020006729
    Abstract: The present invention provides exemplary methods, apparatus and systems for planarizing an insulating layer, such as a borophosphosilicate glass (BPSG) layer, deposited over a substrate. In one embodiment, a substrate (140) is inserted into a substrate processing chamber and a BPSG layer (142) is deposited thereover. The BPSG layer has an upper surface that is generally non-planar, due in part to the underlying nonplanar substrate surface (130). The substrate is exposed to an ultraviolet (UV) light (160) at conditions sufficient to cause a reflow of the BPSG layer so that the BPSG layer upper surface (150) is generally planar. In this manner, photonic energy is used to promote BPSG reflow, thereby reducing the thermal budget requirements for such a process.
    Type: Application
    Filed: March 30, 2001
    Publication date: January 17, 2002
    Inventors: Fabrice Geiger, Frederic Gaillard
  • Patent number: 6331488
    Abstract: A method of manufacturing semiconductor devices using an improved chemical mechanical planarization process for the planarization of the surfaces of the wafer on which the semiconductor devices are formed. The improved chemical mechanical planarization process includes the formation of a flat planar surface from a deformable coating on the surface of the wafer filling in between the surface irregularities prior to the planarization of the surface through a chemical mechanical planarization process.
    Type: Grant
    Filed: May 23, 1997
    Date of Patent: December 18, 2001
    Assignee: Micron Technology, Inc.
    Inventors: Trung T. Doan, Guy T. Blalock, Mark Durcan, Scott G. Meikle
  • Patent number: 6277754
    Abstract: A method of planarizing a dielectric layer comprising the steps of providing a substrate having structures already formed thereon, and then forming a borophosphosilicate glass layer over the substrate. Next, a rapid thermal process is applied heating the borophosphosilicate layer to cause a thermal flow, and then the borophosphosilicate layer is etched back so that a planar surface is obtained. Finally, a passivation layer is formed over the borophosphosilicate glass layer to prevent the formation of pits in subsequent pre-metal wet etching operations.
    Type: Grant
    Filed: April 27, 1998
    Date of Patent: August 21, 2001
    Assignee: United Microelectronics Corp.
    Inventors: Brian Wang, Chih-Ching Hsu
  • Patent number: 6245688
    Abstract: A method to store wafers, immediately after the deposition of a layer of BPSG, into an environment of dry air or dry N2 or dry Ar or a N2O plasma chamber. This storage can occur over a variable period of time and with a variable delay between BPSG deposition and BPSG flow, dependent on which storage environment is applied. The surface of the deposited layer of BPSG is, in doing so, not exposed to H2O and the formation of unstable irregularities on the surface of the deposited BPSG is prevented.
    Type: Grant
    Filed: May 27, 1999
    Date of Patent: June 12, 2001
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Yuan-Shing Jing, Han-Chung Chen, Chiarn-Lung Lee