Planarization By Etching And Coating Patents (Class 438/697)
  • Patent number: 10923363
    Abstract: Techniques herein include a method of patterning semiconductor wafers with improved line edge roughness (LER) and/or line width roughness (LWR), including lines below 12 nm in width. An initial bilayer mandrel is formed. The top layer is trimmed to a particular ratio. A reversal material protects uncovered portions of the lower layer, while a central portion is removed, resulting in two mandrels, each one fifth the initial mandrel width. The resulting mandrels are transferred into two underlying layers to form second bilayer mandrels. Sidewall spacers are formed on the second bilayer mandrels, and a fill material can fill remaining spaces. A planarization step can planarize the substrate to a bottom layer of the second bilayer mandrels, which results in a multi-line layer having square profile lines at 1:1 spacing ratio without spacer rounding.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: February 16, 2021
    Assignee: Tokyo Electron Limited
    Inventors: Sanjana Das, Anton J. deVilliers, Daniel Fulford
  • Patent number: 10325920
    Abstract: A method for manufacturing a semiconductor device includes forming a first mask layer having a first opening on an underlying layer; forming a first layer in a space where the underlying layer is selectively removed via the first opening; forming a second mask layer on the first mask layer and the first layer, the second mask layer having a second opening crossing the first opening; and selectively removing the first layer at a portion where the first opening and the second opening cross. At least one of the first and second mask layers having openings including the first or second opening, the openings being arranged in the first mask layer along a first direction, and/or being arranged in the second mask layer along a second direction, the first opening crossing the second opening in the first direction, and the second opening crossing the first opening in the second direction.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: June 18, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Chihiro Abe, Keisuke Kikutani, Katsumi Yamamoto, Tomoya Oori
  • Patent number: 10002771
    Abstract: A polymer layer on a substrate may be treated with ozone gas or with deionized water and ozone gas to increase a removal rate of the polymer layer in a chemical mechanical polishing (CMP) process. The ozone gas may be diffused directly into the polymer layer or through a thin layer of deionized water on the surface of the polymer layer and into the polymer layer. The deionized water may also be heated during the process to further enhance the diffusion of the ozone gas into the polymer layer.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: June 19, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Prayudi Lianto, Kuma Hsiung, Eric J. Bergman, John L. Klocke, Mohamed Rafi, Muhammad Azim, Guan Huei See, Arvind Sundarrajan
  • Patent number: 9953879
    Abstract: A semiconductor structure includes a strain-relaxed semiconductor substrate, fins on the strain-relaxed semiconductor substrate, the fins each having a bottom inactive region and an exposed top active region. The semiconductor structure further includes a liner layer along sidewalls of the bottom inactive region and adjacent surface areas of the strain-relaxed semiconductor substrate, a densified local fill layer surrounding the bottom inactive regions of the plurality of fins, a densified global fill layer adjacent outer sidewalls of the densified local fill layer, and a hard mask layer separating the densified global fill layer from the substrate and the densified local fill layer, a lack of voids in the densified local fill layer resulting in the bottom inactive regions of the fins being substantially free of oxidation defects. A method to realize the structure is also disclosed, the method preventing oxidation defects in strain-relaxed fins by reducing local gap fill voids.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: April 24, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Min Gyu Sung, Hoon Kim, Chanro Park, Ruilong Xie
  • Patent number: 9543141
    Abstract: Methods for forming a semiconductor structure are provided. The method for forming a semiconductor structure includes forming a flowable layer over a substrate and heating the flowable layer to form a cured layer in a curing process. In addition, the curing process is performed under a pressure of over 2 atmospheres, and the flowable layer reacts with precursors in the flowable layer during the curing process.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: January 10, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Chi-Ming Liao, Ker-Hsun Liao, Chun-Ou Liu, Su-Horng Lin
  • Patent number: 9404178
    Abstract: A method of forming a dielectric layer is described. The method first deposits a silicon-nitrogen-and-hydrogen-containing (polysilazane) layer by radical-component chemical vapor deposition (CVD). The silicon-nitrogen-and-hydrogen-containing layer is formed by combining a radical precursor (excited in a remote plasma) with an unexcited carbon-free silicon precursor. A silicon oxide capping layer may be formed from a portion of the carbon-free silicon-nitrogen-and-hydrogen-containing layer to avoid time-evolution of underlying layer properties prior to conversion into silicon oxide. Alternatively, the silicon oxide capping layer is formed over the silicon-nitrogen-and-hydrogen-containing layer. Either method of formation involves the formation of a local plasma within the substrate processing region.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: August 2, 2016
    Assignee: Applied Materials, Inc.
    Inventors: Jingmei Liang, Xiaolin Chen, Nitin K. Ingle, Shankar Venkataraman
  • Patent number: 9330915
    Abstract: A robust metallization profile is formed by pre-treat an anti-reflective coating layer by plasma before forming a hard mask layer. Pre-treatment is helpful especially in small feature size process, for example, 50 nm and below. By changing constitution of a surface layer of the anti-reflective coating, interface of the anti-reflective coating layer and the hard mask layer is smoothed which results in less overhang and better gap-filling performance.
    Type: Grant
    Filed: December 10, 2013
    Date of Patent: May 3, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shing-Chyang Pan, Ching-Hua Hsieh, Hong-Hui Hsu, Yao-Jen Chang
  • Patent number: 9229312
    Abstract: The present invention provides an exposure apparatus including a projection optical system configured to project a reticle pattern onto a wafer, a selector configured to select a dummy wafer to be placed near an image plane of the projection optical system, from a plurality of dummy wafers having the same shape as that of the wafer and different reflectance with each other, a transfer unit configured to place the dummy wafer selected by the selector near the image plane of the projection optical system, and a controller configured to perform control such that dummy exposure is performed by irradiating the dummy wafer, which is placed near the image plane of the projection optical system by the transfer unit, with light via the projection optical system.
    Type: Grant
    Filed: May 6, 2011
    Date of Patent: January 5, 2016
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Nobuhiko Yabu
  • Patent number: 9099525
    Abstract: A method of forming SSRW FETs with controlled step height between a field oxide and epitaxially grown silicon and the resulting devices are provided. Embodiments include providing a SiN layer on a substrate, forming first, second, and third spaced STI regions of field oxide through the SiN layer and into the substrate, removing a top portion of the field oxide for each STI region by a controlled deglaze, removing the SiN layer, forming an n-type region in the substrate between the first and second STI regions and a p-type region in the substrate between the second and third STI regions, and epitaxially growing a Si based layer on the substrate over the n-type and p-type regions.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: August 4, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Laegu Kang, Vara Govindeswara Reddy Vakada, Michael P. Ganz, Yi Qi, Puneet Khanna, Sri Charan Vemula, Srikanth Samavedam
  • Patent number: 9097994
    Abstract: A process for abrasive-free chemical mechanical planarization of silicon thin film coated EUV mask substrates is disclosed. The process removes bumps and pits on the substrate thereby mitigating reflective errors in the mask. The process employs a two-step polishing procedure, in which the second step is abrasive-free and uses an amine or amine salt as the polishing agent.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: August 4, 2015
    Assignees: Sematech, Inc., Clarkson University
    Inventors: Suryadevara V. Babu, Hariprasad Amanapu, Uma Rames Krishna Laguda, Ranganath Teki
  • Patent number: 9087796
    Abstract: A method of making a semiconductor assembly including the steps of: (i) providing an initial-state assembly including: (a) a fin layer, and (b) a hard mask layer located on top of at least a portion of the fin layer; (ii) performing a first material removal on the initial-state assembly, by CMP, to yield a second-state assembly; and (iii) performing a second material removal on the second-state assembly to yield a third-state assembly. In the first material-removal step: (i) any remaining portion of the soft sacrificial layer is removed, (ii) a portion of the fin layer is removed, and (iii) the lower portion of the hard mask layer is used as a stop layer for the second material removal.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: July 21, 2015
    Assignee: International Business Machines Corporation
    Inventors: Thomas N. Adam, Donald F. Canaperi, Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek, Raghavasimhan Sreenivasan, Charan Veera Venkata Satya Surisetty
  • Patent number: 9018097
    Abstract: A method of forming an interconnect structure for a semiconductor device includes forming a lower antireflective coating layer over a dielectric layer; forming an organic planarizing layer on the lower antireflective coating layer; transferring a wiring pattern through the organic planarizing layer; transferring the wiring pattern through the lower antireflective coating layer; and transferring the wiring pattern through the dielectric layer, wherein unpatterned portions of the lower antireflective coating layer serve as an etch stop layer so as to prevent any bubble defects present in the organic planarizing layer from being transferred to the dielectric layer.
    Type: Grant
    Filed: October 10, 2012
    Date of Patent: April 28, 2015
    Assignee: International Business Machines Corporation
    Inventors: Thomas W. Dyer, Hanako Henry, Tze-Man Ko, Yiheng Xu, Shaoning Yao
  • Patent number: 8980748
    Abstract: A substrate polishing method, a semiconductor device and a fabrication method for a semiconductor device are disclosed by which high planarization polishing can be achieved. In the substrate polishing method, two or more different slurries formed from ceria abrasive grains having different BET values from each other are used to carry out two or more stages of chemical-mechanical polishing processing of a polishing object oxide film on a substrate to flatten the polishing object film.
    Type: Grant
    Filed: January 3, 2008
    Date of Patent: March 17, 2015
    Assignee: Sony Corporation
    Inventors: Hiroko Nakamura, Takaaki Kozuki, Takayuki Enomoto, Yuichi Yamamoto
  • Patent number: 8980753
    Abstract: A method for fabricating a metal gate transistor is disclosed. The method includes the steps of: providing a substrate having a first transistor region and a second transistor region; forming a first metal-oxide semiconductor (MOS) transistor on the first transistor region and a second MOS transistor on the second transistor region, in which the first MOS transistor includes a first dummy gate and the second MOS transistor comprises a second dummy gate; forming a patterned hard mask on the second MOS transistor, in which the hard mask includes at least one metal atom; and using the patterned hard mask to remove the first dummy gate of the first MOS transistor.
    Type: Grant
    Filed: September 21, 2010
    Date of Patent: March 17, 2015
    Assignee: United Mircroelectronics Corp.
    Inventors: Yeng-Peng Wang, Chun-Hsien Lin, Chiu-Hsien Yeh, Chin-Cheng Chien, Chan-Lon Yang
  • Patent number: 8975185
    Abstract: During formation of a charge trap separation in a semiconductor device, a polymer deposition is formed in a reactor using a first chemistry. In a following step, a second chemistry can be used to etch the polymer deposition in the reactor. The same or similar second chemistry can be used in a second etching step to expose a first oxide layer in each of the cells of the semiconductor device and to form a flat upper surface. This additional etch step can also be performed by the reactor, thereby reducing the number of machines required in the formation process.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: March 10, 2015
    Assignee: Spansion, LLC
    Inventor: Angela Tai Hui
  • Patent number: 8927384
    Abstract: A method of fabricating a semiconductor memory device includes forming a hard mask pattern using a damascene method on a lower mold layer stacked on a substrate and etching the lower mold layer using the hard mask pattern as an etch mask to define a protrusion under the hard mask pattern. A support pattern is formed on a top surface of the etched lower mold layer, the top surface of the etched lower mold layer being located at a lower level than a top surface of the protrusion. A lower electrode supported by the support pattern is formed.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: January 6, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Kyu Kim, Sangsup Jeong, Kukhan Yoon, Junsoo Lee, SungII Cho, Yong-Joon Choi
  • Publication number: 20140363976
    Abstract: A substrate processing method is performed to improve surface roughness of a pattern mask formed on a substrate by being exposed and developed. The method includes supplying a first solvent in a gaseous state to a surface of the substrate to dissolve the pattern mask, and supplying a second solvent to the surface of the substrate, which is supplied with the first solvent, to dissolve the pattern mask, wherein a permeability of the second solvent is lower than a permeability of the first solvent.
    Type: Application
    Filed: June 6, 2014
    Publication date: December 11, 2014
    Inventors: Yuichiro MIYATA, Keiichi TANAKA, Kenichi UEDA, Takahiro SHIOZAWA
  • Patent number: 8871647
    Abstract: A group III nitride substrate in one embodiment has a surface layer. The surface layer contains 3 at. % to 25 at. % of carbon and 5×1010 atoms/cm2 to 200×1010 atoms/cm2 of a p-type metal element. The group III nitride substrate has a stable surface.
    Type: Grant
    Filed: August 18, 2011
    Date of Patent: October 28, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Keiji Ishibashi
  • Patent number: 8865007
    Abstract: A method for making three-dimensional nano-structure array is provided. The method includes following steps. A base is provided. A mask layer is located on the base. The mask layer is patterned, and a number of bar-shaped protruding structures is formed on a surface of the mask layer, a lot is defined between each of two adjacent protruding structures of the number of protruding structures to expose a portion of the base. The exposed portion of the base is etched through the slot so that the each of two adjacent protruding structures begin to slant face to face until they are contacting each other to form a protruding pair. The mask layer is removed.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: October 21, 2014
    Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.
    Inventors: Zhen-Dong Zhu, Qun-Qing Li, Li-Hui Zhang, Mo Chen, Yuan-Hao Jin, Shou-Shan Fan
  • Patent number: 8859391
    Abstract: A method for manufacturing a semiconductor device including: forming a wiring layer on a surface side of a first semiconductor wafer; forming a buried film so as to fill in a level difference on the wiring layer, the level difference being formed at a boundary between a peripheral region of the first semiconductor wafer and an inside region being on an inside of the peripheral region, and the level difference being formed as a result of a surface over the wiring layer in the peripheral region being formed lower than a surface over the wiring layer in the inside region, and making the surfaces over the wiring layer in the peripheral region and the inside region substantially flush with each other; and opposing and laminating the surfaces over the wiring layer formed in the first semiconductor wafer to a desired surface of a second semiconductor wafer.
    Type: Grant
    Filed: February 3, 2012
    Date of Patent: October 14, 2014
    Assignee: Sony Corporation
    Inventor: Hiroyasu Matsugai
  • Patent number: 8853088
    Abstract: Methods are provided for forming gates in gate-last processes. The methods may include performing chemical mechanical polishing (CMP) on an interlayer dielectric (ILD) that is on a plurality of dummy gates, each of the plurality of dummy gates including a gate mask in an upper portion thereof, and the CMP exposing the gate mask. The methods may also include removing the gate mask by etching the gate mask. The methods may further include performing CMP on the ILD.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: October 7, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jaeseok Kim, Ho Young Kim
  • Patent number: 8835321
    Abstract: A method of forming fine patterns in a semiconductor device includes forming narrow-width patterns in a first region and wide-width patterns in a second region, where the widths of the narrow-width patterns are smaller than the resolution limitations in a photolithography process used to make the semiconductor device. The first and second regions may comprise cell array regions, with memory cells in the first region and peripheral circuits for operating the memory cells in the second region. The semiconductor device can be, for example, a NAND FLASH memory device. The semiconductor memory device can be variously classified according to the type of memory cells to be integrated in the cell array region, e.g., a DRAM, an SRAM, a PRAM, a RRAM, an MRAM, and a FRAM. In other embodiments, a MEMS device, an optoelectronic device, or a processor, such as CPU or DSP, may be provided on the semiconductor substrate.
    Type: Grant
    Filed: November 14, 2011
    Date of Patent: September 16, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Hyoun-Jee Ha
  • Patent number: 8802561
    Abstract: Techniques disclosed herein prevent wire flaking (collapse). One aspect is an improved way of forming wires over trenches, which may be located in a hookup region of a 3D memory array, and may be used to form electrical connections between conductive lines in the memory array and drivers. The trenches are formed between CMP dummy structures. The trenches are partially filled with a flowable oxide film, which leaves a gap in the trench that is at least as wide as the total pitch of the wires to be formed. A capping layer is formed over the flowable film. After forming a conductive layer over the dielectric layer, the conductive layer is etched to form conductive wires. Some of the capping layer, as well as the CMP dummy structures may be removed. Thus, the conductive wires may be at least temporarily supported by lines of material formed from the capping layer.
    Type: Grant
    Filed: April 12, 2013
    Date of Patent: August 12, 2014
    Assignee: SanDisk 3D LLC
    Inventors: Chao Feng Yeh, Hiroaki Iuchi, Hitomi Fujimoto, Hisayuki Nozawa
  • Publication number: 20140220781
    Abstract: A driving substrate includes: a protective layer including an etching surface; and a film layer including one or more convex portions on a surface thereof. The film layer is in contact with a rear surface of the protective layer. The one or more convex portions each have a surface being flush with the etching surface.
    Type: Application
    Filed: April 7, 2014
    Publication date: August 7, 2014
    Applicant: SONY CORPORATION
    Inventors: Kenta Masuda, Keiichi Akamatsu, Yuichi Kato
  • Patent number: 8765607
    Abstract: A semiconductor device includes CMP dummy tiles (36) that are converted to active tiles by forming well regions (42) at a top surface of the dummy tiles, forming silicide (52) on top of the well regions, and forming a metal interconnect structure (72, 82) in contact with the silicided well tie regions for electrically connecting the dummy tiles to a predetermined supply voltage to provide latch-up protection.
    Type: Grant
    Filed: June 1, 2011
    Date of Patent: July 1, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Robert S. Ruth, Mark A. Kearney, Bernard J. Pappert, Juxiang Ren, Jeff L. Warner
  • Patent number: 8759229
    Abstract: A method for manufacturing an epitaxial wafer that can reduce occurrence of a surface defect or a slip formed on an epitaxial layer is provided. The manufacturing method is characterized by comprising: a smoothing step of controlling application of an etchant to a wafer surface in accordance with a surface shape of a silicon wafer to smooth the wafer surface; and an epitaxial layer forming step of forming an epitaxial layer formed of a silicon single crystal on the surface of the wafer based on epitaxial growth.
    Type: Grant
    Filed: January 24, 2007
    Date of Patent: June 24, 2014
    Assignee: Sumco Corporation
    Inventors: Sakae Koyata, Kazushige Takaishi, Tomohiro Hashii, Katsuhiko Murayama, Takeo Katoh
  • Publication number: 20140141618
    Abstract: A process for overcoming extreme topographies by first planarizing a cavity in a semiconductor substrate in order to create a planar surface for subsequent lithography processing. As a result of the planarizing process for extreme topographies, subsequent lithography processing is enabled including the deposition of features in close proximity to extreme topographic surfaces (e.g., deep cavities or channels) and, including the deposition of features within a cavity. In a first embodiment, the process for planarizing a cavity in a semiconductor substrate includes the application of dry film resists having high chemical resistance. In a second embodiment, the process for planarizing a cavity includes the filling of cavity using materials such as polymers, spin on glasses, and metallurgy.
    Type: Application
    Filed: December 5, 2013
    Publication date: May 22, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Guy M. Cohen, Steven A. Cordes, Sherif A. Goma, Joanna Rosner, Jeannine M. Trewhella
  • Patent number: 8722479
    Abstract: Generally, the present disclosure is directed to a method of at least reducing unwanted erosion of isolation structures of a semiconductor device during fabrication. One illustrative method disclosed includes forming an isolation structure in a semiconducting substrate and forming a conductive protection ring above plurality isolation structure.
    Type: Grant
    Filed: May 25, 2011
    Date of Patent: May 13, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Hans-Juergen Thees, Stephan Kronholz, Joerg Radecker
  • Patent number: 8716094
    Abstract: Approaches for forming a FinFET device using double patterning memorization techniques are provided. Specifically, a device will initially be formed by defining a set of fins, depositing a poly-silicon layer, and depositing a hardmask. Thereafter, a front end of the line (FEOL) lithography-etch, lithography-etch (LELE) process will be performed to form a set of trenches in the device. The set of trenches will be filled with an oxide layer that is subsequently polished. Thereafter, the device is selectively etched to yield a (e.g., poly-silicon) gate pattern.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: May 6, 2014
    Assignee: Global Foundries Inc.
    Inventors: Chang Seo Park, Linus Jang, Jin Cho
  • Patent number: 8691699
    Abstract: A manufacturing method of a semiconductor device includes: forming an insulating layer above a substrate; forming a recessed section in the insulating layer; forming, on the insulating layer, a mask pattern having a first opening which exposes the recessed section, and a second opening which is arranged outside the first opening and does not expose the recessed section; forming a first conductive member and a second conductive member by respectively depositing a conductive material in the first opening and the second opening; and polishing and removing the first conductive member and the second conductive member on the upper side of the insulating layer so as to leave the first conductive member in the recessed section.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: April 8, 2014
    Assignee: Fujitsu Limited
    Inventors: Tsuyoshi Kanki, Shoichi Suda, Shinya Sasaki
  • Patent number: 8685850
    Abstract: According to one embodiment of the invention, the gate contact is formed by a selective deposition on the gate electrode. One acceptable technique for the selective deposition is by plating. Plating is one process by which a metal structure, such as a gate contact, may be formed directly on the gate electrode. The plating is carried out by immersing the semiconductor die in a plating solution with the gate electrode exposed. The gate contact is plated onto the gate electrode and thus is ensured of being fully aligned exactly to the gate electrode. After this, the appropriate dielectric layers are formed adjacent the gate contact and over the source and drain to ensure that the gate electrode is electrically isolated from other components of the transistor.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: April 1, 2014
    Assignees: STMicroelectronics, Inc., International Business Machines Corporation
    Inventors: John H. Zhang, Lawrence A. Clevenger, Carl J. Radens, Yiheng Xu
  • Publication number: 20140087562
    Abstract: A method for processing a silicon substrate includes forming a mask layer on the silicon substrate; forming a hole is farmed in the silicon substrate by alternately repeating (i) an etching step in which plasma etching is performed in a thickness direction of the silicon substrate using the mask layer as a mask and (ii) a deposition step in which a protection film is deposited on an inner wall of the hole formed in the etching step; removing the protection film; and a planarizing a side wall of the hole by etching the inner wall of the hole from which the protection film has been removed. The mask layer includes a material that withstands the removal step. In the planarization step, the inner wall of the hole is etched using the mask layer as a mask.
    Type: Application
    Filed: September 17, 2013
    Publication date: March 27, 2014
    Applicant: Canon Kabushiki Kaisha
    Inventor: Yoichi Ikarashi
  • Publication number: 20140061861
    Abstract: Films of III-nitride for semiconductor device growth are planarized using an etch-back method. The method includes coating a III-nitride surface having surface roughness features in the micron range with a sacrificial planarization material such as an appropriately chosen photoresist. The sacrificial planarization material is then etched together with the III-nitride roughness features using dry etch methods such as inductively coupled plasma reactive ion etching. By closely matching the etch rates of the sacrificial planarization material and the III-nitride material, a planarized III-nitride surface is achieved. The etch-back process together with a high temperature annealing process yields a planarized III-nitride surface with surface roughness features reduced to the nm range. Planarized III-nitride, e.g., GaN, substrates and devices containing them are also provided.
    Type: Application
    Filed: September 4, 2012
    Publication date: March 6, 2014
    Inventors: Theodore D. Moustakas, Adrian D. Williams
  • Patent number: 8664119
    Abstract: A semiconductor device manufacturing method, comprising: providing a semiconductor substrate, on which a gate conductor layer as well as a source region and a drain region positioned on both sides of the gate conductor layer are provided, forming an etch stop layer on the semiconductor substrate, forming an LTO layer on the etch stop layer, chemical mechanical polishing the LTO layer, forming an SOG layer on the polished LTO layer, the etch stop layer, LTO layer and SOG layer forming a front metal insulating layer, back etching the SOG layer and etch stop layer of the front metal insulating layer to expose the gate conductor layer, and removing the gate conductor layer.
    Type: Grant
    Filed: November 28, 2011
    Date of Patent: March 4, 2014
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huaxiang Yin, Qiuxia Xu, Lingkuan Meng, Dapeng Chen
  • Patent number: 8647987
    Abstract: The invention provides a method for improving uniformity of chemical-mechanical planarization process, comprising the steps of: forming features on a substrate; forming a first dielectric isolation layer between the features; planarizing the first dielectric isolation layer until the features are exposed, causing the first dielectric isolation layer between the features to have a recess depth; forming a second dielectric isolation layer on the features and the first dielectric isolation layer, whereby reducing the difference in height between the second dielectric isolation layer between the features and the second dielectric isolation layer on the top of the features; planarizing the second dielectric isolation layer until the features are exposed.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: February 11, 2014
    Assignee: The Institute of Microelectronics, Chinese Academy of Science
    Inventors: Tao Yang, Chao Zhao, Junfeng Li
  • Patent number: 8603846
    Abstract: A process for overcoming extreme topographies by first planarizing a cavity in a semiconductor substrate in order to create a planar surface for subsequent lithography processing. As a result of the planarizing process for extreme topographies, subsequent lithography processing is enabled including the deposition of features in close proximity to extreme topographic surfaces (e.g., deep cavities or channels) and, including the deposition of features within a cavity. In a first embodiment, the process for planarizing a cavity in a semiconductor substrate includes the application of dry film resists having high chemical resistance. In a second embodiment, the process for planarizing a cavity includes the filling of cavity using materials such as polymers, spin on glasses, and metallurgy.
    Type: Grant
    Filed: February 10, 2011
    Date of Patent: December 10, 2013
    Assignee: International Business Machines Corporation
    Inventors: Guy A. Cohen, Steven A. Cordes, Sherif A. Goma, Joanna Rosner, Jeannine M. Trewhella
  • Patent number: 8551888
    Abstract: A method of forming patterns for a semiconductor device. The method includes: forming a first hard mask layer on a layer which is to be etched; forming a second hard mask layer on the first hard mask layer, wherein the second hard mask layer includes a first portion and a second portion formed underneath the first portion, wherein the first portion and second portion are composed of the same material; etching the first portion to form first patterns; forming spacers covering sidewalls of the first patterns; etching the second portion using the spacers as etch masks to form second patterns; etching the first hard mask layer and the spacers using the second patterns disposed underneath the spacers as etch masks to form third patterns; and etching the layer to be etched, using the third patterns.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: October 8, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yun-seung Kang, Jong-chul Park, Kwang-yong Yang, Sang-sup Jeong, Seok-hyun Lim
  • Patent number: 8551886
    Abstract: A method for semiconductor processing is provided wherein a workpiece having an underlying body and a plurality of features extending therefrom, is provided. A first set of the plurality of features extend from the underlying body to a first plane, and a second set of the plurality features extend from the underlying body to a second plane. A protection layer overlies each of the plurality of features and an isolation layer overlies the underlying body and protection layer, wherein the isolation has a non-uniform first oxide density associated therewith. The isolation layer anisotropically etched based on a predetermined pattern, and then isotropically etched, wherein a second oxide density of the isolation layer is substantially uniform across the workpiece. The predetermined pattern is based, at least in part, on a desired oxide density, a location and extension of the plurality of features to the first and second planes.
    Type: Grant
    Filed: April 9, 2008
    Date of Patent: October 8, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Kyle P. Hunt, Leila Elvira Noriega, Billy Alan Wofford, Asadd M. Hosein, Binghua Hu, Xinfen Chen
  • Patent number: 8530355
    Abstract: A method of making a semiconductor device begins with a semiconductor wafer that includes a first semiconductor layer overlying a second semiconductor layer. A first trench is etched in the semiconductor wafer. The first trench is filled with insulating material. A second trench is etched within the first trench and through the insulating material, such that insulating material remains along sidewalls of the first trench. The second trench exposes a portion of the second insulating layer. A semiconductor layer can then be grown within the second trench using the second semiconductor layer as a seed layer.
    Type: Grant
    Filed: December 23, 2005
    Date of Patent: September 10, 2013
    Assignee: Infineon Technologies AG
    Inventors: Jiang Yan, Danny Pak-Chum Shum, Armin Tilke
  • Patent number: 8524606
    Abstract: Planarization methods include depositing a mask material on top of an overburden layer on a semiconductor wafer. The mask material is planarized to remove the mask material from up areas of the overburden layer to expose the overburden layer without removing the mask material from down areas. The exposed overburden layer is wet etched and leaves a thickness remaining over an underlying layer. Remaining portions of the mask layer and the exposed portions of the overburden layer are planarized to expose the underlying layer.
    Type: Grant
    Filed: January 25, 2011
    Date of Patent: September 3, 2013
    Assignees: International Business Machines Corporation, JSR Corporation
    Inventors: Leslie Charns, John M. Cotte, Jason E. Cummings, Lukasz J. Hupka, Dinesh R. Koli, Tomohisa Konno, Mahadevaiyer Krishnan, Michael F. Lofaro, Jakub W. Nalaskowski, Masahiro Noda, Dinesh K. Penigalapati, Tatsuya Yamanaka
  • Patent number: 8524587
    Abstract: Provided is a method of planarizing a semiconductor device. The method includes providing a substrate. The method includes forming a first layer over the substrate. The method includes forming a second layer over the first layer. The first and second layers have different material compositions. The method includes forming a third layer over the second layer. The method includes performing a polishing process on the third layer until the third layer is substantially removed. The method includes performing an etch back process to remove the second layer and a portion of the first layer. Wherein an etching selectivity of the etch back process with respect to the first and second layers is approximately 1:1.
    Type: Grant
    Filed: February 4, 2013
    Date of Patent: September 3, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Neng-Kuo Chen, Jeff J. Xu
  • Publication number: 20130224956
    Abstract: A substrate treatment apparatus is used for treating a major surface of a substrate with a chemical liquid. The substrate treatment apparatus includes: a substrate holding unit which holds the substrate; a chemical liquid supplying unit having a chemical liquid nozzle which supplies the chemical liquid onto the major surface of the substrate held by the substrate holding unit; a heater having an infrared lamp to be located in opposed relation to the major surface of the substrate held by the substrate holding unit to heat the chemical liquid supplied onto the major surface of the substrate by irradiation with infrared radiation emitted from the infrared lamp, the heater having a smaller diameter than the substrate; and a heater moving unit which moves the heater along the major surface of the substrate held by the substrate holding unit.
    Type: Application
    Filed: February 26, 2013
    Publication date: August 29, 2013
    Applicant: DAINIPPON SCREEN MFG. CO., LTD.
    Inventor: DAINIPPON SCREEN MFG. CO., LTD.
  • Patent number: 8513131
    Abstract: A method of forming an integrated circuit (IC) includes forming a first and second plurality of spacers on a substrate, wherein the substrate includes a silicon layer, and wherein the first plurality of spacers have a thickness that is different from a thickness of the second plurality of spacers; and etching the silicon layer in the substrate using the first and second plurality of spacers as a mask, wherein the etched silicon layer forms a first plurality and a second plurality of fin field effect transistor (FINFET) channel regions, and wherein the first plurality of FINFET channel regions each have a respective thickness that corresponds to the thickness of the first plurality of spacers, and wherein the second plurality of FINFET channel regions each have a respective thickness that corresponds to the thickness of the second plurality of spacers.
    Type: Grant
    Filed: March 17, 2011
    Date of Patent: August 20, 2013
    Assignee: International Business Machines Corporation
    Inventors: Ming Cai, Dechao Guo, Chung-hsun Lin, Chun-chen Yeh
  • Publication number: 20130178067
    Abstract: A method of fabricating a semiconductor device may include forming spacer line patterns on sidewalls of photoresist. A planarization etching process may be performed on a subsequently added planarization layer, after forming a mesh-shaped mask pattern from the spacer line patterns.
    Type: Application
    Filed: December 19, 2012
    Publication date: July 11, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: SAMSUNG ELECTRONICS CO., LTD.
  • Publication number: 20130154063
    Abstract: A driving substrate includes: a protective layer including an etching surface; and a film layer including one or more convex portions on a surface thereof, the film layer being in contact with a rear surface of the protective layer, the one or more convex portions each having a surface being flush with the etching surface.
    Type: Application
    Filed: November 16, 2012
    Publication date: June 20, 2013
    Applicant: SONY CORPORATION
    Inventor: SONY CORPORATION
  • Patent number: 8466067
    Abstract: Processes for forming high density gap-filling silicon oxide on a patterned substrate are described. The processes increase the density of gap-filling silicon oxide particularly in narrow trenches. The density may also be increased in wide trenches and recessed open areas. The densities of the gap-filling silicon oxide in the narrow and wide trenches/open areas become more similar following the treatment which allows the etch rates to match more closely. This effect may also be described as a reduction in the pattern loading effect. The process involves forming then planarizing silicon oxide. Planarization exposes a new dielectric interface disposed closer to the narrow trenches. The newly exposed interface facilitates a densification treatment by annealing and/or exposing the planarized surface to a plasma.
    Type: Grant
    Filed: March 8, 2011
    Date of Patent: June 18, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Jingmei Liang, Nitin K. Ingle, Shankar Venkataraman
  • Publication number: 20130137269
    Abstract: A patterning method is provided for fabrication of a semiconductor device structure having conductive contact elements, an interlayer dielectric material overlying the contact elements, an organic planarization layer overlying the interlayer dielectric material, an antireflective coating material overlying the organic planarization layer, and a photoresist material overlying the antireflective coating material. The method creates a patterned photoresist layer from the photoresist material to define oversized openings corresponding to respective conductive contact elements. The antireflective coating is etched using the patterned photoresist as an etch mask. A liner material is deposited overlying the patterned antireflective coating layer. The liner material is etched to create sidewall features, which are used as a portion of an etch mask to form contact recesses for the conductive contact elements.
    Type: Application
    Filed: November 30, 2011
    Publication date: May 30, 2013
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Erik P. Geiss, Peter Baars
  • Patent number: 8445386
    Abstract: A smoothing method for semiconductor material and semiconductor wafers produced by the method are disclosed. Semiconductor wafers with reduced atomic steps, as well with reduced scratches and subsurface defects can be produced. Such wafers feature an improved growth surface that can provide for the growth of an epilayer with reduced macroscopic defects and defect densities. A method of smoothing the surface of a wafer according to example embodiments of the invention includes planarizing the surface of a semiconductor wafer, and then oxidizing the wafer to achieve a specified thickness of oxide on the surface of the wafer. The oxide can then be stripped from the surface of the semiconductor wafer.
    Type: Grant
    Filed: May 27, 2010
    Date of Patent: May 21, 2013
    Assignee: Cree, Inc.
    Inventors: Davis Andrew McClure, Nathaniel Mark Williams
  • Publication number: 20130115773
    Abstract: When forming sophisticated high-k metal gate electrode structures on the basis of a replacement gate approach, pronounced loss of the interlayer dielectric material may be avoided by inserting at least one surface modification process, for instance in the form of a nitridation process. In this manner, leakage paths caused by metal residues formed in the interlayer dielectric material may be significantly reduced.
    Type: Application
    Filed: November 4, 2011
    Publication date: May 9, 2013
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Rohit Pal, Rolf Stephan, Andreas Ott
  • Publication number: 20130115774
    Abstract: According to one embodiment, a method for chemical planarization includes: preparing a treatment liquid containing a hydrosilicofluoric acid aqueous solution containing silicon dioxide dissolved therein at a saturated concentration; and decreasing height of irregularity of a silicon dioxide film. In the decreasing, dissolution rate of convex portions is made larger than dissolution rate of concave portion of the irregularity while changing equilibrium state of the treatment liquid at areas being in contact with the convex portions of the irregularity, in a state in which the silicon dioxide film having the irregularity is brought into contact with the treatment liquid.
    Type: Application
    Filed: March 16, 2012
    Publication date: May 9, 2013
    Inventors: Masako Kodera, Yukiteru Matsui