Combined With Coating Step Patents (Class 438/694)
  • Patent number: 11121228
    Abstract: Disclosed is a manufacturing method of a thin film transistor, comprising: sequentially preparing a gate, a gate insulation layer and an active layer on the substrate; preparing an etching stopper layer on the active layer; depositing an ohmic contact layer film on the etching stopper layer and the active layer, and depositing a source drain conductive film on the ohmic contact layer film; processing the source drain conductive film to form a source and a drain, which are patterned, and processing the ohmic contact layer film by a dry etching process to form an ohmic contact layer, which is patterned; removing the etching stopper layer after preparing the ohmic contact layer. Since the etching stopper layer is disposed above the channel of the transistor before preparing the ohmic contact layer, the damage to the active layer by dry etching can be effectively avoided to improve the performance of the transistor.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: September 14, 2021
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Huafei Xie
  • Patent number: 11106138
    Abstract: The present disclosure provides resist rinse solutions and corresponding lithography techniques that achieve high pattern structural integrity for advanced technology nodes. An example lithography method includes forming a resist layer over a workpiece, exposing the resist layer to radiation, developing the exposed resist layer using a developer that removes an unexposed portion of the exposed resist layer, thereby forming a patterned resist layer, and rinsing the patterned resist layer using a rinse solution. The developer is an organic solution, and the rinse solution includes water.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: August 31, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Wei Wang, Wei-Han Lai, Ching-Yu Chang
  • Patent number: 11088288
    Abstract: A semiconductor structure and formation thereof. The semiconductor structure including: a nano-sheet field-effect transistor; a layer of support material that is located beneath a stack of nano-sheets that are included in the nano-sheet field-effect transistor; and a vertical support that is affixed to a stack of nano-sheets, wherein the vertical support (i) has an end that is affixed to the layer of support material and (ii) a side that is a affixed to at least one nano-sheet of the stack of nano-sheets.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: August 10, 2021
    Assignee: International Business Machines Corporation
    Inventors: Ruilong Xie, Jingyun Zhang, Xin Miao, Alexander Reznicek
  • Patent number: 11089691
    Abstract: The disclosure relates to a microcircuit forming method. The microcircuit forming method according to the disclosure comprises: a seed-layer forming step for forming a high-reflectivity seed layer on a substrate material by using a conductive material; a pattern-layer forming step for forming a pattern layer on the seed layer, the pattern layer having a pattern hole arranged thereon to allow the seed layer to be selectively exposed therethrough; a plating step for filling the pattern hole with a conductive material; a pattern-layer removing step for removing the pattern layer; and a seed-layer patterning step for removing a part of the seed layer which does not overlap the conductive material in the plating step, wherein the high-reflectivity seed layer has a specular reflection property.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: August 10, 2021
    Assignee: InkTec Co., Ltd.
    Inventors: Su Han Kim, Kwang-Choon Chung, Jung Yoon Moon, Sung In Ha, Byung Woong Moon
  • Patent number: 11081360
    Abstract: In an embodiment, in the method for processing a workpiece including an etching target layer containing silicon oxide, a mask provided on the etching target layer, and an opening provided in the mask and exposing the etching target layer, according to the embodiment, the etching target layer is etched by removing the etching target layer for each atomic layer through repetitive execution of a sequence of generating plasma of a first processing gas containing nitrogen, forming a mixed layer containing ions included in the plasma on an atomic layer on an exposed surface of the etching target layer, generating plasma of a second processing gas containing fluorine, and removing the mixed layer by radicals included in the plasma. The plasma of the second processing gas contains the radicals that remove the mixed layer containing silicon nitride.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: August 3, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Masahiro Tabata, Toru Hisamatsu, Yoshihide Kihara, Masanobu Honda
  • Patent number: 11062913
    Abstract: In the disclosed method, a mask is formed on a microstructure. The mask includes a first pattern positioned over a first region of the microstructure and a second pattern positioned over a second region of the microstructure. A first etching process is performed to etch the microstructure according to the first and second patterns formed in the mask. The first etching process transfers the first and second patterns of the mask into the first and second regions of the microstructure, respectively. A protective layer is subsequently formed over the first pattern of the mask that is positioned over the first region of the microstructure. When the protective layer is formed, a second etching process is performed to etch the microstructure and transfer the second pattern of the mask further into the second region of the microstructure. The method also includes removing the mask and the protective layer from the microstructure.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: July 13, 2021
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Yu Qi Wang, Wenjie Zhang, Hong Guang Song, Lipeng Liu, Lianjuan Ren
  • Patent number: 11043381
    Abstract: A directional patterning method includes following steps. A substrate is provided with a mask layer thereon, and the mask layer has at least one opening pattern therein. A cyclic deposition and etching process is performed to increase a length of the at least one opening pattern.
    Type: Grant
    Filed: January 27, 2019
    Date of Patent: June 22, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Chin Chang, Li-Te Lin, Ru-Gun Liu, Wei-Liang Lin, Pinyen Lin, Yu-Tien Shen, Ya-Wen Yeh
  • Patent number: 11037793
    Abstract: According to the invention there is provided a method of plasma etching a silicon-based compound semiconductor substrate, the method comprising providing the substrate within an etch chamber and performing a cyclical process on the substrate, each cycle comprising supplying an etchant gas into the chamber, energising the gas into a plasma, and performing an etch step on the substrate using the plasma; and performing a desorption step, wherein during the desorption step, the only gas that is supplied into the etch chamber is an inert gas, so as to allow reactive species that have adsorbed to the surface of the substrate during the etch step to desorb from the surface of the substrate.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: June 15, 2021
    Assignee: SPTS Technologies Limited
    Inventors: Huma Ashraf, Kevin Riddell, Alex Wood
  • Patent number: 11024798
    Abstract: A magnetic device for magnetic random access memory (MRAM), spin torque MRAM, or spin torque oscillator technology is disclosed wherein a magnetic tunnel junction (MTJ) with a sidewall is formed between a bottom electrode and a top electrode. A passivation layer that is a single layer or multilayer comprising one of B, C, or Ge, or an alloy thereof wherein the B, C, and Ge content, respectively, is at least 10 atomic % is formed on the MTJ sidewall to protect the MTJ from reactive species during subsequent processing including deposition of a dielectric layer that electrically isolates the MTJ from adjacent MTJs, and during annealing steps around 400° C. in CMOS fabrication. The single layer is about 3 to 10 Angstroms thick and may be an oxide or nitride of B, C, or Ge. The passivation layer is preferably amorphous to prevent diffusion of reactive oxygen or nitrogen species.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: June 1, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jodi Mari Iwata, Guenole Jan, Ru-Ying Tong
  • Patent number: 11022878
    Abstract: The present disclosure describes a method for improving post-photolithography critical dimension (CD) uniformity for features printed on a photoresist. A layer can be formed on one or more printed features and subsequently etched to improve overall CD uniformity across the features. For example the method includes a material layer disposed over a substrate and a photoresist over the material layer. The photoresist is patterned to form a first feature with a first critical dimension (CD) and a second feature with a second CD that is larger than the first CD. Further, a layer is formed with one or more deposition/etch cycles in the second feature to form a modified second CD that is nominally equal to the first CD.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: June 1, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co.. Ltd.
    Inventors: Xi-Zong Chen, Cha-Hsin Chao, Yi-Wei Chiu, Li-Te Hsu, Chih-Hsuan Lin
  • Patent number: 11011388
    Abstract: Methods and apparatus for laterally etching unwanted material from the sidewalls of a recessed feature are described herein. In various embodiments, the method involves etching a portion of the sidewalls, depositing a protective film over a portion of the sidewalls, and cycling the etching and deposition operations until the unwanted material is removed from the entire depth of the recessed feature. Each etching and deposition operation may target a particular depth along the sidewalls of the feature. In some cases, the unwanted material is removed from the bottom of the feature up, and in other cases the unwanted material is removed from the top of the feature down. Some combination of these may also be used.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: May 18, 2021
    Assignee: Lam Research Corporation
    Inventors: Kwame Eason, Pilyeon Park, Mark Naoshi Kawaguchi, Seung-Ho Park, Hsiao-Wei Chang
  • Patent number: 11011525
    Abstract: Provided is a landing pad structure including a substrate, a plurality of landing pads, a guard ring, and an edge pattern. The substrate includes a cell region, a periphery region, and a guard ring region located between the cell region and the periphery region. The landing pads are arranged on the substrate in the cell region in a hexagonal close packing (HCP) configuration. The guard ring is disposed on the substrate in the guard ring region in a strip form. The edge pattern is disposed on the substrate in the cell region and close to the guard ring region. A method of manufacturing the landing pad structure is also provided.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: May 18, 2021
    Assignee: Winbond Electronics Corp.
    Inventors: Keng-Ping Lin, Tetsuharu Kurokawa, Tzu-Ming Ou Yang, Shu-Ming Li
  • Patent number: 10998192
    Abstract: A method includes depositing a resist layer onto a hard mask layer to form a multi-layer patterning material film stack on a semiconductor substrate, directing patterning radiation onto the film stack to form a developed pattern in the resist layer and exposing the film stack to at least one gas precursor in connection with a sequential infiltration synthesis process. The film stack is configured to facilitate selective infiltration of the at least one gas precursor into the resist layer.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: May 4, 2021
    Assignee: International Business Machines Corporation
    Inventors: Ekmini Anuja De Silva, Jing Guo, Luciana Meli, Nelson Felix
  • Patent number: 10989843
    Abstract: Provided are a transparent electrode-attached complex which includes a base material, a transparent electrode pattern, an optical adjustment member, and a transparent protective layer in this order, in which the optical adjustment member has at least one layer of low-refractive index layers that are odd-numbered layers from a transparent electrode pattern side and at least one layer of high-refractive index layers that are even-numbered layers from the transparent electrode pattern side, a difference in refractive index between the low-refractive index layer and the high-refractive index layer that are directly adjacent to each other is 0.05 or more, a refractive index of the high-refractive index layer is 2.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: April 27, 2021
    Assignee: FUJIFILM Corporation
    Inventor: Kentaro Toyooka
  • Patent number: 10975468
    Abstract: There is provided a cleaning method for removing a first deposit, formed on an upper electrode through an etching of a metal layer containing a metal, by using a plasma generated between a lower electrode of a lower structure and the upper electrode in a processing chamber of a plasma processing apparatus. The method includes a step of colliding ions with the first deposit formed on the upper electrode and a step of removing a second deposit, which is generated by said colliding and formed on the lower structure. Further, a cycle including the step of colliding and the step of removing is repeated multiple times.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: April 13, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Hiroki Kishi, Mitsuru Hashimoto, Keiichi Shimoda, Eiichi Nishimura, Akitaka Shimizu
  • Patent number: 10950432
    Abstract: Provided is a method of depositing a thin film on a pattern structure of a semiconductor substrate, the method including (a) supplying a source gas; (b) supplying a reactive gas; and (c) supplying plasma, wherein the steps (a), (b), and (c) are sequentially repeated on the semiconductor substrate within a reaction space until a desired thickness is obtained, and a frequency of the plasma is a high frequency of 60 MHz or greater.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: March 16, 2021
    Assignee: ASM IP Holding B.V.
    Inventors: Young Hoon Kim, Yong Gyu Han, Dae Youn Kim, Tae Hee Yoo, Wan Gyu Lim, Jin Geun Yu
  • Patent number: 10930505
    Abstract: The present disclosure provides a method of patterning a target material layer over a semiconductor substrate. The method includes steps of forming a spacer feature over the target material layer using a first sub-layout and performing a photolithographic patterning process using a second sub-layout to form a first feature. A portion of the first feature extends over the spacer feature. The method further includes steps of removing the portion of the first feature extending over the spacer feature and removing the spacer feature. Other methods and associated patterned semiconductor wafers are also provided herein.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: February 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsong-Hua Ou, Ken-Hsien Hsieh, Shih-Ming Chang, Wen-Chun Huang, Chih-Ming Lai, Ru-Gun Liu, Tsai-Sheng Gau
  • Patent number: 10910381
    Abstract: Apparatuses and methods to provide a patterned substrate are described. A plurality of patterned and spaced first lines and carbon material lines and formed on the substrate surface by selectively depositing and etching films extending in a first direction and films extending in a second direction that crosses the first direction to pattern the underlying structures.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: February 2, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Tejinder Singh, Takehito Koshizawa, Abhijit Basu Mallick, Pramit Manna, Nancy Fung, Eswaranand Venkatasubramanian, Ho-yung David Hwang, Samuel E. Gottheim
  • Patent number: 10910466
    Abstract: A method of forming an integrated circuit structure includes forming a first magnetic layer, forming a first conductive line over the first magnetic layer, and coating a photo-sensitive coating on the first magnetic layer. The photo-sensitive coating includes a first portion directly over the first conductive line, and a second portion offset from the first conductive line. The first portion is joined to the second portion. The method further includes performing a first light-exposure on the first portion of the photo-sensitive coating, performing a second light-exposure on both the first portion and the second portion of the photo-sensitive coating, developing the photo-sensitive coating, and forming a second magnetic layer over the photo-sensitive coating.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: February 2, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun Kai Tzeng, Cheng Jen Lin, Yung-Ching Chao, Ming-Da Cheng, Mirng-Ji Lii
  • Patent number: 10910220
    Abstract: A method for flatly covering a semiconductor substrate using a silicon-containing composition. A method for producing a polysiloxane-coated substrate, including a first step for forming a first polysiloxane coating film by applying a first polysiloxane composition for coating to a stepped substrate and firing the composition thereon and a second step for forming a second film by applying a second polysiloxane composition for coating to the first film and firing the composition thereon. The second film has an Iso-dense bias of 50 nm or less; the first polysiloxane contains a hydrolysis-condensation product of a hydrolyzable silane starting material containing a first hydrolyzable silane having four hydrolyzable groups in each molecule at a ratio of 0-100% by mole in all the silanes; and the second polysiloxane contains silanol groups at a ratio of 30% by mole or less relative to Si atoms, while having a weight average molecular weight of 1,000-50,000.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: February 2, 2021
    Assignee: NISSAN CHEMICAL CORPORATION
    Inventors: Shuhei Shigaki, Hiroaki Yaguchi, Makoto Nakajima
  • Patent number: 10901321
    Abstract: Processes for removing a mask layer (e.g., doped amorphous carbon mask layer) from a substrate with high aspect ratio structures are provided. In one example implementation, a process can include depositing a polymer layer on at least a portion of a top end of a high aspect ratio structure on a substrate. The process can further include removing at least a portion of the polymer layer and the doped amorphous carbon film form the substrate using a plasma strip process. In example embodiments, depositing a polymer layer can include plugging one or more high aspect ratio structures with the polymer layer. In example embodiments, depositing a polymer layer can include forming a polymer layer on a sidewall of one or more high aspect ratio structures.
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: January 26, 2021
    Assignees: Mattson Technology, Inc., Beijing E-Town Semiconductor Technology Co., Ltd.
    Inventors: Vijay M. Vaniapura, Shawming Ma, Li Hou
  • Patent number: 10872779
    Abstract: An plasma etching method for etching a film layer includes a plurality of times repeating a step set including a first step of introducing a gas containing hydrogen fluoride into a processing chamber and supplying hydrogen fluoride molecules to the surface of an oxide film, a second step of exhausting the interior of the processing chamber in vacuum to remove the hydrogen fluoride, and a third step of introducing a gas containing hydrogen nitride into the processing chamber and supplying hydrogen nitride to the surface of the oxide film to form a compound layer containing nitrogen, hydrogen, and fluorine on the surface of the film layer, and removing the compound layer formed on the surface of the film layer. Foreign object contamination is prevented by inhibiting mixing of hydrogen fluoride gas and hydrogen nitride gas, and the etching amount is controlled by the number of times of repeating application thereof.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: December 22, 2020
    Assignee: HITACHI HIGH-TECH CORPORATION
    Inventors: Nobuya Miyoshi, Hiroyuki Kobayashi, Kazunori Shinoda, Kohei Kawamura, Kazumasa Ookuma, Yutaka Kouzuma, Masaru Izawa
  • Patent number: 10868238
    Abstract: Certain aspects of the present disclosure provide techniques for fabricating an integrated circuit with a magnetic tunnel junction (MTJ) without a patterning process for the MTJ. An example method generally includes depositing a first diffusion barrier layer above an oxide layer having a conductive pillar therein, forming a first trench in the first diffusion barrier layer above the conductive pillar, depositing a first electrode in the first trench such that the first electrode is coupled to the conductive pillar, removing the oxide layer and the first diffusion barrier layer to expose the conductive pillar and the first electrode, and depositing an MTJ above the first electrode according to a shape of the first electrode.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: December 15, 2020
    Assignee: Qualcomm Incorporated
    Inventors: Xia Li, Wei-Chuan Chen, Seung Hyuk Kang
  • Patent number: 10840129
    Abstract: In an embodiment, a method includes: forming a first dielectric layer over a die, the first dielectric layer including a photo-sensitive material; curing the first dielectric layer to reduce photo-sensitivity of the first dielectric layer; patterning the first dielectric layer by etching to form a first opening; forming a first metallization pattern in the first opening of the first dielectric layer; forming a second dielectric layer over the first metallization pattern and the first dielectric layer, the second dielectric layer including the photo-sensitive material; patterning the second dielectric layer by exposure and development to form a second opening; and forming a second metallization pattern in the second opening of the second dielectric layer, the second metallization pattern electrically connected to the first metallization pattern.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: November 17, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Jui Kuo, Yun Chen Hsieh, Hui-Jung Tsai
  • Patent number: 10796935
    Abstract: An electronic device manufacturing system may include a loadlock. The loadlock may include a plurality of gas line heaters for providing a heated gas to the loadlock to heat a processed substrate therein. Heating a processed substrate may reduce corrosion in the loadlock and subsequent contamination of substrates therein. The loadlock may also include a plurality of embedded heaters in the loadlock housing to reduce moisture therein, further reducing corrosion and contamination. Methods of heating a substrate in a loadlock are also provided, as are other aspects.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: October 6, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Adam J. Wyatt, Edward Ng, Andrew Nguyen
  • Patent number: 10790362
    Abstract: The present disclosure provides a semiconductor structure, including providing a metal layer, an adhesion-enhancing layer over the metal layer, a dielectric stack over the adhesion-enhancing layer, a contact penetrating the dielectric stack and the adhesion-enhancing layer and connecting with the metal layer, a barrier layer disposed between the contact and the dielectric stack, and a high-k dielectric layer disposed between the contact and the barrier layer.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: September 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yao-Wen Chang, Gung-Pei Chang, Ching-Sheng Chu, Chern-Yow Hsu
  • Patent number: 10782613
    Abstract: Self-assembled monolayers (SAMs) were selectively prepared on portions of a substrate surface utilizing compounds comprising a hydrogen-bonding group and polymerizable diacetylene group. The SAMs were photopolymerized using ultraviolet light. The pre-polymerized and polymerized SAMs were more effective barriers against metal deposition in an atomic layer deposition process compared to similar compounds lacking these functional groups.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: September 22, 2020
    Assignee: International Business Machines Corporation
    Inventors: Rudy J. Wojtecki, Noah F. Fine Nathel, Ekmini A. De Silva
  • Patent number: 10784222
    Abstract: A method includes forming a metal bump on a top surface of a first package component, forming a solder region on a top surface of the metal bump, forming a protection layer extending on a sidewall of the metal bump, reflowing the solder region to bond the first package component to a second package component, and dispensing an underfill between the first package component and the second package component. The underfill is in contact with the protection layer.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: September 22, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jung-Hua Chang, Jian-Yang He, Chin-Fu Kao
  • Patent number: 10770355
    Abstract: Provided are semiconductor devices having various line widths and a method of manufacturing the semiconductor device. The semiconductor device includes: a substrate including a first region and a second region, a plurality of first gate lines extending in a first direction in the first region and each having a first width in a second; a plurality of second gate lines extending in the first direction in the second region and each having a second width that is different from the first width in the second direction and a pitch that is the same as a pitch of the plurality of first gate lines; a spacer layer covering opposite side walls of each of the plurality of first gate lines and each of the plurality of second gate lines; and a first base layer arranged between the substrate and the spacer layer in the first region.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: September 8, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Je-min Yoo, Sang-deok Kwon, Yuri Masuoka
  • Patent number: 10755932
    Abstract: To manufacture an integrated circuit device, a diffusion buffer layer and a carbon-containing layer are sequentially formed on a plurality of fin-type active regions formed in a substrate. A carbon-containing mask pattern is formed to have an opening exposing a portion of the diffusion buffer layer by etching the carbon-containing layer using an etching gas including an oxygen atom while the diffusion buffer layer is blocking oxygen from diffusing into the fin-type active regions. Impurity ions are implanted into some fin-type active regions through the opening and the diffusion buffer layer using the carbon-containing mask pattern as an ion-implantation mask, the some fin-type active regions being selected from among the plurality of fin-type active regions.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: August 25, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-woo Kang, Ji-ho Yoo, Dong-hoon Khang, Seon-bae Kim, Moon-han Park
  • Patent number: 10748765
    Abstract: A method includes forming a multi-layer mask over a dielectric layer. Forming the multi-layer mask includes forming a bottom layer over the dielectric layer. A first middle layer is formed over the bottom layer. The first middle layer includes a first silicon-containing material. The first silicon-containing material has a first content of Si—CH3 bonds. A second middle layer is formed over the first middle layer. The second middle layer includes a second silicon-containing material. The second silicon-containing material has a second content of Si—CH3 bonds less than the first content of Si—CH3 bonds.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: August 18, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Joung-Wei Liou, Chin Kun Lan
  • Patent number: 10748766
    Abstract: Based on the fact that a film thickness of a film formed in a film formation processing of repeatedly performing a first sequence varies according to a temperature of the surface on which the film is to be formed, the film formation processing is performed after the temperature of each region of the surface of the wafer is adjusted to reduce a deviation of a trench on the surface of the wafer, so that the film is very precisely formed on the inner surface of the trench while reducing the deviation of the trench on the surface of the wafer. When the trench width is narrower than a reference width, an etching processing of repeatedly performing a second sequence is performed in order to expand the trench width, so that the surface of the film provided in the inner surface of the trench is isotropically and uniformly etched.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: August 18, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Masahiro Tabata
  • Patent number: 10734275
    Abstract: A method includes forming a hard mask over a target layer, performing a treatment on a first portion of the hard mask to form a treated portion, with a second portion of the hard mask left untreated as an untreated portion. The method further includes subjecting both the treated portion and the untreated portion of the hard mask to etching, in which the untreated portion is removed as a result of the etching, and the treated portion remains after the etching. A layer underlying the hard mask is etched, and the treated portion of the hard mask is used as a part of an etching mask in the etching.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: August 4, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiang-Wei Liu, Chia-Tien Wu, Wei-Chen Chu
  • Patent number: 10727517
    Abstract: A solid oxide fuel cell includes an Si support substrate having a through hole, an electrolyte film formed on the surface of an Si support substrate and containing a solid oxide having oxygen ion conductivity, a first electrode formed on a surface of the electrolyte film (surface on the side opposite to the Si support substrate), and a second electrode formed at least on a surface exposed from the through hole in a rear face of the electrolyte film. The electrolyte film includes a porous layer including the solid oxide and containing pores inside, a first dense layer formed on a surface of the porous layer (surface on the side opposite to the Si support substrate), and a second dense layer formed at the interface between a rear face of the porous layer and the Si support substrate.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: July 28, 2020
    Assignee: KABUSHIKI KAISHA TOYOTA CHUO KENKYUSHO
    Inventors: Hidehito Matsuo, Teruhisa Akashi, Hirofumi Funabashi, Hiroko Iguchi, Shigeo Hori, Toshihiko Tani
  • Patent number: 10692724
    Abstract: A method for performing atomic layer etching of a surface of a substrate is provided, including: performing a surface conversion operation by exposing the surface of the substrate to a surface conversion reactant; performing a ligand exchange operation by exposing the surface of the substrate to a ligand containing reactant; performing a desorption operation that effects removal of surface species from the surface of the substrate; performing a purge operation; repeating the surface conversion operation, the ligand exchange operation, the desorption operation, and the purge operation, for a predefined number of cycles.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: June 23, 2020
    Assignee: Lam Research Corporation
    Inventors: David Smith, Thorsten Lill, Andreas Fischer
  • Patent number: 10685849
    Abstract: Exemplary methods of etching semiconductor substrates may include flowing a halogen-containing precursor into a processing region of a semiconductor processing chamber. The processing region may house a substrate having a conductive material and an overlying mask material. The conductive material may be characterized by a first surface in contact with the mask material, and the mask material may define an edge region of the conductive material. The methods may include contacting the edge region of the conductive material with the halogen-containing precursor and the oxygen-containing precursor. The methods may include etching in a first etching operation the edge region of the conductive material to a partial depth through the conductive material to produce a footing of conductive material protruding along the edge region of the conductive material. The methods may also include removing the footing of conductive material in a second etching operation.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: June 16, 2020
    Assignee: Applied Materials, Inc.
    Inventors: He Ren, Jong Mun Kim, Maximillian Clemons, Minrui Yu, Mehul Naik, Chentsau Ying
  • Patent number: 10676491
    Abstract: There is provided a novel isocyanuric acid derivative having two alkoxyalkyl groups and having a trialkoxysilyl group introduced therein, and a method for producing the isocyanuric acid derivative. An isocyanuric acid derivative of formula (1): wherein R1 is a methyl group or an ethyl group; two R2s are each a C1-2 alkylene group; and two R3s are each a methyl group, an ethyl group, or a C2-4 alkoxyalkyl group, which may be liquid at ambient temperature and ambient pressure.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: June 9, 2020
    Assignee: NISSAN CHEMICAL CORPORATION
    Inventors: Shun Kubodera, Yuichi Goto, Wataru Shibayama, Gun Son
  • Patent number: 10672620
    Abstract: Deep reactive ion etching is essential for creating high aspect ratio micro-structures for microelectromechanical systems, sensors and actuators, and emerging flexible electronics. A novel hybrid dual soft/hard mask bilayer may be deposited during semiconductor manufacturing for deep reactive etches. Such a manufacturing process may include depositing a first mask material on a substrate; depositing a second mask material on the first mask material; depositing a third mask material on the second mask material; patterning the third mask material with a pattern corresponding to one or more trenches for transfer to the substrate; transferring the pattern from the third mask material to the second mask material; transferring the pattern from the second mask material to the first mask material; and/or transferring the pattern from the first mask material to the substrate.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: June 2, 2020
    Assignee: KING ABDULLAH UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventor: Mohamed Tarek Ghoneim
  • Patent number: 10664625
    Abstract: A device includes a substrate, an array of metal pads on a first surface of the substrate, a carbon polymer composite covering the array of metal pads, the composite having variations that result in random resistance values between the metal pads usable as a random code. A method of manufacturing a secure device, including forming an array of metal pads on a dielet substrate, the dielet substrate containing at least one memory in which is stored an encryption key, and an RF communication section, covering the array of metal pads with a carbon polymer composite such that variations in the carbon concentration in the polymer forms a unique pattern of resistance, attaching the dielet substrate to a host component, receiving a request from a security server for a unique code determined by the unique pattern of resistance, and using the encryption key, encrypting and providing the unique code to the security server.
    Type: Grant
    Filed: January 6, 2016
    Date of Patent: May 26, 2020
    Assignee: SRI International
    Inventor: Michael G. Kane
  • Patent number: 10643846
    Abstract: Methods and apparatuses for selectively growing metal-containing hard masks are provided herein. Methods include providing a substrate having a pattern of spaced apart features, each feature having a top horizontal surface, filling spaces between the spaced apart features with carbon-containing material to form a planar surface having the top horizontal surfaces of the features and carbon-containing material, selectively depositing a metal-containing hard mask on the top horizontal surfaces of the features relative to the carbon-containing material, and selectively removing the carbon-containing material relative to the metal-containing hard mask and features.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: May 5, 2020
    Assignee: Lam Research Corporation
    Inventors: David Charles Smith, Jon Henri, Dennis M. Hausmann, Paul C. Lemaire
  • Patent number: 10636672
    Abstract: A method for manufacturing an interconnect structure includes providing a metal interconnect layer, forming a first dielectric layer on the metal interconnect layer, forming a fluorocarbon layer on the first dielectric layer, forming a second dielectric layer on the fluorocarbon layer, and performing an etch process on the second dielectric layer using the fluorocarbon layer as an etch stop mask to form an opening. The interconnect structure thus formed has an improved uniformity and reduced parasitic capacitance.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: April 28, 2020
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Ming Zhou
  • Patent number: 10629430
    Abstract: Methods and apparatus for processing a substrate are described herein. A vacuum multi-chamber deposition tool can include a degas chamber with both a heating mechanism and a variable frequency microwave source. The methods described herein use variable frequency microwave radiation to increased quality and speed of the degas process without damaging the various components.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: April 21, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Loke Yuen Wong, Ke Chang, Yueh Sheng Ow, Ananthkrishna Jupudi, Glen T. Mori, Aksel Kitowski, Arkajit Roy Barman
  • Patent number: 10608177
    Abstract: The present disclosure discloses a self-gated RRAM cell and a manufacturing method thereof; which belong to the field of microelectronic technology. The self-gated RRAM cell comprises: a stacked structure containing multiple layers of conductive lower electrodes; a vertical trench formed by etching the stacked structure; a M8XY6 gated layer formed on an inner wall and a bottom of the vertical trench; a resistance transition layer formed on a surface of the M8XY6, gated layer; and a conductive upper electrode formed on a surface of the resistance transition layer, the vertical trench being filled with the conductive upper electrode. The present disclosure is implemented on a basis of using the self-gated RRAM as a memory cell.
    Type: Grant
    Filed: December 26, 2014
    Date of Patent: March 31, 2020
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Hangbing Lv, Ming Liu, Qi Liu, Shibing Long
  • Patent number: 10599039
    Abstract: Processes for removing a mask layer (e.g., doped amorphous carbon mask layer) from a substrate with high aspect ratio structures are provided. In one example implementation, a process can include depositing a polymer layer on at least a portion of a top end of a high aspect ratio structure on a substrate. The process can further include removing at least a portion of the polymer layer and the doped amorphous carbon film form the substrate using a plasma strip process. In example embodiments, depositing a polymer layer can include plugging one or more high aspect ratio structures with the polymer layer. In example embodiments, depositing a polymer layer can include forming a polymer layer on a sidewall of one or more high aspect ratio structures.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: March 24, 2020
    Assignees: MATTSON TECHNOLOGY, INC., BEIJING E-TOWN SEMICONDUCTOR TECHNOLOGY, CO., LTD
    Inventors: Vijay M. Vaniapura, Shawming Ma, Li Hou
  • Patent number: 10580651
    Abstract: The present disclosure relates to a method for creating regions of different device types on a substrate having different pitches. The method includes dividing a substrate into a first device type region and a second device type region. The method further includes forming a target etch layer on the substrate. The method further includes forming a bottom mandrel layer on the target etch layer. The method further includes forming a plurality of alternating first pillars of a top mandrel material and first trenches between the first pillars on the bottom mandrel layer in the first device type region. The plurality of first pillars has a first pitch. The method further includes forming a plurality of alternating second pillars of the top mandrel material and second trenches between the second pillars on the bottom mandrel layer in the second device type region. The plurality of second pillars has a second pitch. The method further includes depositing tone inversion material in the first trenches.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: March 3, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Min Gyu Sung, Sony Varghese
  • Patent number: 10573530
    Abstract: Disclosed is a pattern forming method including: forming an acrylic resin layer on an underlayer; forming an intermediate layer on the acrylic resin layer; forming a patterned EUV resist layer on the intermediate layer; forming a pattern on the acrylic resin layer by etching the intermediate layer and the acrylic resin layer with the EUV resist layer as an etching mask; removing the EUV resist layer and the intermediate layer after the pattern is formed on the acrylic resin layer; and smoothing a surface of the acrylic resin layer after the EUV resist layer and the intermediate layer are removed.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: February 25, 2020
    Assignee: Tokyo Electron Limited
    Inventor: Hidetami Yaegashi
  • Patent number: 10553442
    Abstract: The present disclosure relates to an etching method including: a first step of forming an etching assistance layer on a surface of at least one of a plurality of silicon-containing regions by plasma of a processing gas generated in a processing container; and a second step of imparting energy to the etching assistance layer. The energy is equal to or greater than energy at which the etching assistance layer is removed, and smaller than energy at which a region located immediately below the etching assistance layer is sputtered, and a sequence including the first step and the second step is executed repeatedly.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: February 4, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Akihiro Tsuji
  • Patent number: 10541170
    Abstract: There is provided a technique, including: a process chamber in which a substrate is processed; a substrate support member configured to support the substrate; an elevator configured to elevate the substrate support member; a gas supply port configured to supply a gas to the substrate; and a controller configured to control an elevating operation of the elevator so as to differentiate an interval between the gas supply port and the substrate supported by the substrate support member, when a gas is supplied from the gas supply port.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: January 21, 2020
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventors: Takashi Yahata, Naofumi Ohashi, Shun Matsui
  • Patent number: 10541429
    Abstract: A novel method to produce thin films spatially disposed on desired areas of workpieces is disclosed. Examples of include the formation of a yttria stabilized zirconia (YSZ) film formed on a desired portion of a stainless steel interconnect for solid oxide fuel cells by Atomic Layer Deposition (ALD). A number of methods to produce the spatially disposed YSZ film structures are described including polymeric and silicone rubber masks. The thin film structures have utility for preventing the reaction of glasses with metals, in particular alkali-earth containing glasses with ferritic stainless steels, allowing high temperature bonding of these materials.
    Type: Grant
    Filed: October 22, 2017
    Date of Patent: January 21, 2020
    Assignee: Sonata Scientific LLC
    Inventors: Jeffrey F. Roeder, Peter C. Van Buskirk
  • Patent number: 10529583
    Abstract: An etching method is provided. A processing target object includes a first region made of silicon oxide and a second region made of silicon nitride. The second region is extended to provide a recess and has a bottom region extended on a bottom of the recess. The first region is configured to cover the second region. In the etching method, a deposit of fluorocarbon is formed on the processing target object, and the first region is etched by irradiating ions of atoms of a rare gas toward the processing target object. Then, on the bottom region, a modified region is formed by supplying hydrogen ions. Subsequently, the deposit of fluorocarbon is formed on the processing target object, and the modified region is etched by irradiating ions of atoms of the rare gas toward the processing target object.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: January 7, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Mitsuhiro Iwano, Masanori Hosoya