Combined With Coating Step Patents (Class 438/694)
  • Patent number: 10273143
    Abstract: The present disclosure involves forming a method of fabricating a Micro-Electro-Mechanical System (MEMS) device. A plurality of openings is formed in a first side of a first substrate. A dielectric layer is formed over the first side of the substrate. A plurality of segments of the dielectric layer fills the openings. The first side of the first substrate is bonded to a second substrate that contains a cavity. The bonding is performed such that the segments of the dielectric layer are disposed over the cavity. A portion of the first substrate disposed over the cavity is transformed into a plurality of movable components of a MEMS device. The movable components are in physical contact with the dielectric the layer. Thereafter, a portion of the dielectric layer is removed without using liquid chemicals.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: April 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Lee-Chuan Tseng, Chang-Ming Wu, Shih-Chang Liu, Yuan-Chih Hsieh
  • Patent number: 10256112
    Abstract: Exemplary methods for removing tungsten-containing material may include flowing a chlorine-containing precursor into a processing region of a semiconductor processing chamber. The methods may also include flowing methane into the processing region of the semiconductor processing chamber. The methods may include forming a plasma from the chlorine-containing precursor and the methane to produce plasma effluents. The methods may also include contacting a substrate with the plasma effluents. The substrate may include an exposed region of a tungsten-containing material. The plasma effluents may produce an oxychloride of tungsten. The methods may also include recessing the exposed region of the tungsten-containing material.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: April 9, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Xikun Wang, Nitin Ingle
  • Patent number: 10229849
    Abstract: Disclosed is a substrate processing apparatus including a disc provided so as to be rotatable on its axis, at least one susceptor disposed on the disc such that a substrate is seated on an upper surface thereof, the susceptor being configured to rotate on its axis and to revolve around a center of the disc as the disc rotates on its axis, a metal ring coupled to a lower portion of the susceptor, the metal ring being arranged such that a center thereof coincides with a center of the susceptor, and a magnet provided below the disc so as to be radially arranged on a basis of the center of the disc, at least a portion of the magnet being opposite the metal ring in a vertical direction.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: March 12, 2019
    Assignee: JUSUNG ENGINEERING CO., LTD.
    Inventors: Ki Bum Kim, Seung Youb Sa, Ram Woo, Myung Jin Lee, Seung Dae Choi, Jong Sung Choi, Ho Boem Her
  • Patent number: 10224212
    Abstract: A method for isotropically etching film on a substrate with atomic layer control includes a) providing a substrate including a material selected from a group consisting of silicon (Si), germanium (Ge) and silicon germanium (SiGe). The method includes b) depositing a sacrificial layer on the material in a processing chamber by: cooling a lower portion of the substrate; one of creating or supplying an oxidant-containing plasma in the processing chamber; and increasing a surface temperature of the substrate for a predetermined period using rapid thermal heating while creating or supplying the oxidant-containing plasma in the processing chamber. The method includes c) purging the processing chamber. The method includes d) etching the sacrificial layer and the material by supplying an etch gas mixture and striking plasma in the processing chamber.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: March 5, 2019
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Yunsang Kim, Hyuk-Jun Kwon, Dong Woo Paeng, He Zhang
  • Patent number: 10199235
    Abstract: Methods and techniques for fabricating metal interconnects, lines, or vias by subtractive etching and liner deposition methods are provided. Methods involve depositing a blanket copper layer, removing regions of the blanket copper layer to form a pattern, treating the patterned metal, depositing a copper-dielectric interface material such that the copper-dielectric interface material adheres only to the patterned copper, depositing a dielectric barrier layer on the substrate, and depositing a dielectric bulk layer on the substrate.
    Type: Grant
    Filed: January 18, 2018
    Date of Patent: February 5, 2019
    Assignee: Lam Research Corporation
    Inventors: Hui-Jung Wu, Thomas Joseph Knisley, Nagraj Shankar, Meihua Shen, John Hoang, Prithu Sharma
  • Patent number: 10134600
    Abstract: A method for forming a semiconductor device in a plasma processing chamber is provided. An atomic layer etch selectively etches SiO with respect to SiN and deposits a fluorinated polymer. The fluorinated polymer layer is stripped, comprising flowing a stripping gas comprising oxygen into the plasma processing chamber, forming a plasma from the stripping gas, and stopping the flow of the stripping gas. A SiN layer is selectively etched with respect to SiO and SiGe and Si.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: November 20, 2018
    Assignee: Lam Research Corporation
    Inventors: Leonid Romm, Alan Jensen, Xin Zhang, Gerardo Delgadino
  • Patent number: 10121822
    Abstract: A light-emitting device may include an active layer. The light-emitting device may include a first semiconductor layer of a first conductivity type. The first semiconductor layer may be in physical contact with the active layer. The light-emitting device may also include a second semiconductor layer of a second conductivity type. The second semiconductor layer may be in physical contact with the active layer and opposite the first conductive layer. The light-emitting device may further include a first electrode in physical contact with a first side of the first semiconductor layer. The light-emitting device may additionally include a second electrode in physical contact with a second side of the first semiconductor layer. The second side of the first semiconductor layer may be different from the first side of the first semiconductor layer. The light-emitting device may also include a third electrode in physical contact with the second semiconductor layer.
    Type: Grant
    Filed: November 18, 2014
    Date of Patent: November 6, 2018
    Assignee: NANYANG TECHNOLOGICAL UNIVERSITY
    Inventors: Xueliang Zhang, Zi-Hui Zhang, Yun Ji, Zhen Gang Ju, Wei Liu, Swee Tiam Tan, Xiaowei Sun, Hilmi Volkan Demir
  • Patent number: 10115585
    Abstract: Provided is a material composition and method for that includes forming a silicon-based resin over a substrate. In various embodiments, the silicon-based resin includes a nitrobenzyl functional group. In some embodiments, a baking process is performed to cross-link the silicon-based resin. Thereafter, the cross-linked silicon-based resin is patterned and an underlying layer is etched using the patterned cross-linked silicon-based resin as an etch mask. In various examples, the cross-linked silicon-based resin is exposed to a radiation source, thereby de-cross-linking the silicon-based resin. In some embodiments, the de-cross-linked silicon-based resin is removed using an organic solution.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: October 30, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Yu Liu, Ching-Yu Chang, Chin-Hsiang Lin
  • Patent number: 10083271
    Abstract: Provided is a method of fabricating a semiconductor device. An integrated circuit (IC) layout plan is obtained. The IC layout plan contains critical features and non-critical features. Locational information regarding a defect on a blank reticle is obtained. The blank reticle is a candidate reticle for being patterned with the IC layout plan. Based on the locational information regarding the defect and the IC layout plan, a determination is made that at some of the critical features will intersect with the defect if the blank reticle is patterned with the IC layout plan, regardless of whether the IC layout plan is globally manipulated or not before being patterned onto the blank reticle. In response to the determination, selected local portions of the IC layout plan are re-arranged such that none of the critical features will intersect with the defect if the blank reticle is patterned with the IC layout plan.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: September 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Ming Chang, Chia-Hao Yu
  • Patent number: 10079313
    Abstract: A graphene electronic device includes a gate insulating layer on a conductive substrate, a channel layer on the gate insulating layer, and a source electrode on one end of the channel layer and a drain electrode on another end of the channel layer. The channel layer includes a semiconductor layer and a graphene layer in direct contact with the semiconductor layer, and the graphene layer includes a plurality of graphene islands spaced apart from each other.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: September 18, 2018
    Assignees: Samsung Electronics Co., Ltd., Research & Business Foundation Sungkyunkwan University
    Inventors: Kiyoung Lee, Jinseong Heo, Woojong Yu, Yongseon Shin
  • Patent number: 10062615
    Abstract: A semiconductor device comprises first stack of nanowires arranged on a substrate comprises a first nanowire and a second nanowire, the second nanowire is arranged substantially co-planar in a first plane with the first nanowire the first nanowire and the second nanowire arranged substantially parallel with the substrate, a second stack of nanowires comprises a third nanowire and a fourth nanowire, the third nanowire and the fourth nanowire arranged substantially co-planar in the first plane with the first nanowire, and the first nanowire and the second nanowire comprises a first semiconductor material and the third nanowire and the fourth nanowire comprises a second semiconductor material, the first semiconductor material dissimilar from the second semiconductor material.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: August 28, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Ramachandra Divakaruni, Juntao Li
  • Patent number: 10050149
    Abstract: A method of forming a semiconductor device includes forming a source/drain region and spacers on a substrate. The method further includes forming an etch stop layer on the spacers and the source/drain region and forming a gate structure between the spacers. The method further includes etching back the gate structure, etching back the spacers and the etch back layer, and forming a gate capping structure on the etched back gate structure, spacers, and etch stop layer.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: August 14, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Lien Huang, Tsai-Chun Li, Ching-Feng Fu, Ming-Huan Tsai, D. T. Lee, Cheng-Hua Yang, Yi-Chen Lo
  • Patent number: 10042255
    Abstract: Block copolymers comprise a first block comprising an alternating copolymer, and a second block comprising a unit comprising a hydrogen acceptor. The block copolymers find particular use in pattern shrink compositions and methods in semiconductor device manufacture for the provision of high resolution patterns.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: August 7, 2018
    Assignees: Dow Global Technologies LLC, Rohm and Haas Electronic Materials LLC
    Inventors: Huaxing Zhou, Vipul Jain, Jin Wuk Sung, Peter Trefonas, III, Phillip D. Hustad, Mingqi Li
  • Patent number: 10043772
    Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole of the first interconnection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first interconnection member and the semiconductor chip; a second interconnection member disposed on the first interconnection member and the semiconductor chip; and connection terminals disposed on the second interconnection member. The first interconnection member and the second interconnection member respectively include redistribution layers electrically connected to the connection pads of the semiconductor chip, and a connection pad and a connection terminal are electrically connected to each other by a pathway passing through the redistribution layer of the first interconnection member.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: August 7, 2018
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Sang Kyu Lee, Jin Gu Kim
  • Patent number: 10037902
    Abstract: A substrate processing device includes a holding member for holding a substrate, and an opposed member having a body portion and an extended portion extending from at least a part of a peripheral edge part of the body portion. A protrusion is provided on one part of a tip side part of the extended portion and a side surface part of the holding member, and the other part is provided with a restricting structure disposed opposite to the protrusion and restricting relative motion of the protrusion. The relative motion between the holding member and the opposed member is restricted, and the substrate processing device further includes a rotating mechanism, and a nozzle for discharging a processing solution and the protrusion and the restricting structure are disposed below an upper surface of the holding member.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: July 31, 2018
    Assignee: SCREEN Holdings Co., Ltd.
    Inventors: Daichi Yoshitomi, Kazuki Inoue, Masaki Iwami, Hiroaki Ishii
  • Patent number: 10032638
    Abstract: A method includes forming mask patterns spaced apart from each other by at least one opening on an etch target layer, filling the opening with a block copolymer material including first and second polymer blocks of different properties, and annealing the block copolymer material to form first patterns and second patterns, the first patterns in contact with facing sidewalls of adjacent ones of the mask patterns, respectively, and at least one of the second patterns between the first patterns. The first patterns include the first polymer blocks and the second patterns include the second polymer blocks.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: July 24, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Shigenobu Maeda, Jeong Ju Park, Eunsung Kim, Hyunwoo Kim, Shiyong Yi
  • Patent number: 10017610
    Abstract: In an example, a silicone-based thermal interface material includes a thermally conductive material and a silicone-based polymeric material having a solubility parameter that is not less than 9.09 cal1/2 cm?3/2.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: July 10, 2018
    Assignee: International Business Machines Corporation
    Inventors: Sarah K. Czaplewski, Joseph Kuczynski, Jason T. Wertz, Jing Zhang
  • Patent number: 10014182
    Abstract: According to one embodiment, a pattern formation method includes forming a base structure including first and second guide portions each including a pinning portion, and a neutral portion, forming a block copolymer film containing first and second polymers on the bass structure, performing a predetermined treatment for the block copolymer film, thereby forming first and second pattern portions formed of the first polymer, forming third and fourth pattern portions formed of the second polymer, and forming a fifth pattern portion formed of the first and second polymers. The fifth pattern portion includes a plurality of first portions formed of the second polymer, and a second portion formed of the first polymer and provided on the neutral portion and the first portions.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: July 3, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yuriko Seino
  • Patent number: 10014179
    Abstract: Methods for processing a substrate include: (a) depositing a cobalt layer to a first thickness within a first plurality of features and a second plurality of features formed in a substrate, wherein each of the first plurality of features and each of the second plurality of features comprises an opening, and wherein a width of the openings of the first plurality of features is less than a width of the openings of the second plurality of features; and (b) heating the substrate to a first temperature to fill the first plurality of features with cobalt material while simultaneously depositing a fill material on the substrate to fill the second plurality of features.
    Type: Grant
    Filed: February 9, 2016
    Date of Patent: July 3, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Rong Tao, Tae Hong Ha, Xianmin Tang, Joung Joo Lee
  • Patent number: 9997404
    Abstract: Methods of semiconductor device fabrication are provided including those that provide a substrate having a plurality of trenches disposed in a dielectric layer formed above the substrate. A spacer material layer is formed over the plurality of trenches. A via pattern including a plurality of openings is formed over the spacer material layer and plurality of trenches. Via holes can be etched in the dielectric layer using the via pattern and spacer material layer as a masking element.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: June 12, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Hsu Wu, Cheng-Hsiung Tsai, Yu-Sheng Chang, Chia-Tien Wu, Chung-Ju Lee, Yung-Sung Yen, Chun-Kuang Chen, Tien-I Bao, Ru-Gun Liu, Shau-Lin Shue
  • Patent number: 9997373
    Abstract: Various embodiments herein relate to methods, apparatus and systems for forming a recessed feature in dielectric material on a semiconductor substrate. Separate etching and deposition operations are employed in a cyclic manner. Each etching operation partially etches the feature. Each deposition operation forms a protective coating on the sidewalls of the feature to prevent lateral etch of the dielectric material during the etching operations. The protective coating may be deposited using methods that result in formation of the protective coating along substantially the entire length of the sidewalls. The protective coating may be deposited using particular reactants having low sticking coefficients in some embodiments. The protective coating may also be deposited using particular reaction mechanisms that result in substantially complete sidewall coating. In some cases the protective coating is deposited using plasma assisted atomic layer deposition or plasma assisted chemical vapor deposition.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: June 12, 2018
    Assignee: Lam Research Corporation
    Inventor: Eric A. Hudson
  • Patent number: 9984916
    Abstract: A method for providing a uniform recess depth between different fin gap sizes includes depositing a dielectric material between fins on a substrate. Etch lag is tuned for etching the dielectric material between narrow gaps faster than the dielectric material between wider gaps such that the dielectric material in the narrow gaps reaches a target depth. An etch block is formed in the narrow gaps. The wider gaps are etched to the target depth. The etch block is removed.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: May 29, 2018
    Assignee: International Business Machines Corporation
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Michael Rizzolo, Jay W. Strane
  • Patent number: 9971342
    Abstract: According to one embodiment, a pattern data creating method includes a calculation process, a determination process, and a correction process. In the calculation process, it is calculated a stress distribution of stresses that are applied to a template when a distance between the template and a substrate on which resist are disposed is predetermined, the template including a template pattern. In the determination process, it is determined whether or not there is a stress concentration spot in the template pattern at which a stress value larger than a predetermined criterion value is to appear. If the stress concentration spot is present, in the correction process, it is a corrected pattern data of the template pattern such that the stress value at the stress concentration spot becomes a stress value not larger than the predetermined criterion value.
    Type: Grant
    Filed: February 25, 2015
    Date of Patent: May 15, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Mitsuko Shimizu, Sachiko Kobayashi
  • Patent number: 9954165
    Abstract: In the examples provided herein, a device is described that has a stack of structure layers including a first structure layer and a second structure layer that are different materials, where the first structure layer is positioned higher in the stack than the second structure layer. The device also has a first sidewall spacer deposited conformally and circumferentially around an upper portion of the stack that includes the first structure layer. Further, the device has a second sidewall spacer deposited conformally and circumferentially around the first sidewall spacer and an additional portion of the stack that includes the second structure layer, where a height of the first sidewall spacer along the stack is different from a height of the second sidewall spacer.
    Type: Grant
    Filed: January 9, 2015
    Date of Patent: April 24, 2018
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Hans S. Cho, Yoocharn Jeon
  • Patent number: 9929019
    Abstract: A patterns forming method begins with performing a lithography process on a photoresist film with a photomask having first apertures in a first mask region and second apertures in a second mask region to respectively form first main features and dummy features, on which the second mask region is located between the border of the photomask and the first mask region, and a size of each of the first apertures is greater than a size of each of the second apertures. Subsequently, a material is filled into the first main features to respectively form second main features and into the dummy features to seal the dummy features. Then, a substrate is etched to form patterned features by using the photoresist film having the second main features.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: March 27, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Kuo-Yao Chou
  • Patent number: 9929012
    Abstract: A method is disclosed to prepare a substrate for photolithography. The method includes forming an underlayer over a surface of the substrate; depositing an interface hardmask layer on the underlayer using one of a vapor phase deposition process or an atomic layer deposition process; and forming a layer of extreme UV (EUV) resist on the interface hardmask layer, where the interface hardmask layer is comprised of material having a composition and properties tuned to achieve a certain secondary electron yield from the interface hardmask layer. Also disclosed is a structure configured for photolithography. The structure includes a substrate; an underlayer over a surface of the substrate; an interface hardmask layer disposed on the underlayer; and a layer of EUV resist disposed on the interface hardmask layer. The interface hardmask layer contains material having a composition and properties tuned to achieve a certain secondary electron yield from the interface hardmask layer.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: March 27, 2018
    Assignee: International Business Machines Corporation
    Inventors: Michael P Belyansky, Ravi K Bonam, Anuja Desilva, Scott Halle
  • Patent number: 9922944
    Abstract: A first film (3) is formed on a front surface of a semiconductor wafer (1). A second film (4) is formed on the first film (3). A surface protection film (5) is formed to cover the first film (3) and second film (4). After forming the surface protection film (5), a reverse surface of the semiconductor wafer (1) is etched with a chemical liquid. The first film (3) is formed on an outer peripheral section of the semiconductor wafer (1). The second film (4) is not formed on the outer peripheral section of the semiconductor wafer (1). The first film (3) and the surface protection film (5) are adhered to each other in the outer peripheral section of the semiconductor wafer (1). The first film (3) has a higher adhesion to the surface protection film (5) than the second film (4).
    Type: Grant
    Filed: February 12, 2015
    Date of Patent: March 20, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventor: Shunichi Watabe
  • Patent number: 9921699
    Abstract: In one embodiment, a conductive line structure includes a substrate and a plurality of conductive lines thereon. The substrate has a first area and a second area, and the two areas are separated by at least one borderline. The plurality of conductive lines are disposed at the first area and the second area of the substrate, respectively. The at least one borderline may be a straight line, and the conductive lines disposed at the second area are inclined relative to the at least one borderline. A sensing device using the conductive line structure is also provided.
    Type: Grant
    Filed: November 11, 2015
    Date of Patent: March 20, 2018
    Assignee: Industrial Technology Research Institute
    Inventors: Sheng-Feng Chung, Chun-Ting Liu, Su-Tsai Lu
  • Patent number: 9922839
    Abstract: Provided herein are methods and related apparatus to smooth the edges of features patterned using extreme ultraviolet (EUV) lithography. In some embodiments, at least one cycle of depositing passivation layer that preferentially collects in crevices of a feature leaving protuberances exposed, and etching the feature to remove the exposed protuberances, thereby smoothing the feature, is performed. The passivation material may preferentially collect in the crevices due to a higher surface to volume ratio in the crevices than in the protuberances. In some embodiments, local critical dimension uniformity (LCDU), a measure of roughness in contact holes, is reduced. In some embodiments, at least one cycle of depositing a thin layer in a plurality of holes formed in photoresist, the holes having different CDs, wherein the thin layer preferentially deposits in the larger CD holes, and anisotropically removing the thin layer to remove it at the bottoms of the holes, is performed.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: March 20, 2018
    Assignee: Lam Research Corporation
    Inventors: Richard Wise, Nader Shamma
  • Patent number: 9922972
    Abstract: A lithography method and accompanying structure for decreasing the critical dimension (CD) and improving the CD uniformity within semiconductor devices uses a layer of silicon carbide as an embedded blocking mask for defining semiconductor architectures, including contact trench openings to form trench silicide contacts.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: March 20, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Xiaofeng Qiu, Haigou Huang, Chang Ho Maeng
  • Patent number: 9916988
    Abstract: Techniques and structures for protecting etched features during etch mask removal. In embodiments, a mask is patterned and a substrate layer etched to transfer the pattern. Subsequent to etching the substrate layer, features patterned into the substrate are covered with a sacrificial material backfilling the etch mask. At least a top portion of the mask is removed with the substrate features protected by the sacrificial material. The sacrificial material and any remaining portion of the mask are then removed. In further embodiments, a gate contact opening etched into a substrate layer is protected with a sacrificial material having the same composition as a first material layer of a multi-layered etch mask. A second material layer of the etch mask having a similar composition as the substrate layer is removed before subsequently removing the sacrificial material concurrently with the first mask material layer.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: March 13, 2018
    Assignee: Intel Corporation
    Inventors: Shakuntala Sundararajan, Nadia Rahhal-Orabi, Leonard P Guler, Michael Harper, Ralph Thomas Troeger
  • Patent number: 9899213
    Abstract: On an RAMO4 substrate containing a single crystal represented by the general formula RAMO4 (wherein R represents one or a plurality of trivalent elements selected from a group of elements including: Sc, In, Y, and a lanthanoid element, A represents one or a plurality of trivalent elements selected from a group of elements including: Fe(III), Ga, and Al, and M represents one or a plurality of divalent elements selected from a group of elements including: Mg, Mn, Fe(II), Co, Cu, Zn, and Cd), a buffer layer containing a nitride of In and a Group III element except for In is formed, and a Group III nitride crystal is formed on the buffer layer.
    Type: Grant
    Filed: February 9, 2017
    Date of Patent: February 20, 2018
    Assignee: PANASONIC CORPORATION
    Inventors: Akio Ueta, Akihiko Ishibashi
  • Patent number: 9852923
    Abstract: A hard mask layer is deposited on a feature layer over a substrate. The hard mask layer comprises an organic mask layer. An opening in the organic mask layer is formed using a first gas comprising a halogen element at a first temperature greater than a room temperature to expose a portion of the feature layer. In one embodiment, a gas comprising a halogen element is supplied to a chamber. An organic mask layer on an insulating layer over a substrate is etched using the halogen element at a first temperature to form an opening to expose a portion of the insulating layer.
    Type: Grant
    Filed: April 2, 2015
    Date of Patent: December 26, 2017
    Assignee: Applied Materials, Inc.
    Inventors: Gene Lee, Lucy Chen
  • Patent number: 9852908
    Abstract: The present disclosure provides a method of patterning a target material layer over a semiconductor substrate. The method includes steps of forming a spacer feature over the target material layer using a first sub-layout and performing a photolithographic patterning process using a second sub-layout to form a first feature. A portion of the first feature extends over the spacer feature. The method further includes steps of removing the portion of the first feature extending over the spacer feature and removing the spacer feature. Other methods and associated patterned semiconductor wafers are also provided herein.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: December 26, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsong-Hua Ou, Ken-Hsien Hsieh, Shih-Ming Chang, Wen-Chun Huang, Chih-Ming Lai, Ru-Gun Liu, Tsai-Sheng Gau
  • Patent number: 9831471
    Abstract: The method for producing an organic EL display panel includes, in the given order, the steps of: forming a first light-emitting layer by forming a film from a luminescent material of a first luminescent color in a first pixel; performing the etching treatment to remove, while leaving the first light-emitting layer to remain, a thin film of the luminescent material of the first luminescent color which adhered to the second pixel in the step; forming a second light-emitting layer by forming a film from a luminescent material of a second luminescent color different from the first luminescent color in the second pixel; and performing the etching treatment to remove, while leaving the second light-emitting layer to remain, a thin film of the luminescent material of the second luminescent color which adhered to the first pixel in the step.
    Type: Grant
    Filed: September 17, 2014
    Date of Patent: November 28, 2017
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Kazuki Matsunaga, Katsuhiro Kikuchi, Shinichi Kawato, Satoshi Inoue, Yuhki Kobayashi, Takashi Ochi
  • Patent number: 9786607
    Abstract: An interconnect structure includes an insulator stack on an upper surface of a semiconductor substrate. The insulator stack includes a first insulator layer having at least one semiconductor device embedded therein and an etch stop layer interposed between the first insulator layer and a second insulator layer. At least one electrically conductive local contact extends through each of the second insulator layer, etch stop layer and, first insulator layer to contact the at least one semiconductor device. The interconnect structure further includes at least one first layer contact element disposed on the etch stop layer and against the at least one conductive local contact.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: October 10, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Su Chen Fan, Sukwon Hong, William J. Taylor, Jr.
  • Patent number: 9780038
    Abstract: A method including forming a dielectric layer on a contact point of an integrated circuit structure; forming a hardmask including a dielectric material on a surface of the dielectric layer; and forming at least one via in the dielectric layer to the contact point using the hardmask as a pattern. An apparatus including a circuit substrate including at least one active layer including a contact point; a dielectric layer on the at least one active layer; a hardmask including a dielectric material having a least one opening therein for an interconnect material; and an interconnect material in the at least one opening of the hardmask and through the dielectric layer to the contact point.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: October 3, 2017
    Assignee: Intel Corporation
    Inventors: Ruth A. Brain, Kevin J. Fischer, Michael A. Childs
  • Patent number: 9779956
    Abstract: A method for selectively etching SiO and SiN with respect to SiGe or Si of a structure is provided. A plurality of cycles of atomic layer etching is provided, where each cycle comprises a fluorinated polymer deposition phase and an activation phase. The fluorinated polymer deposition phase comprises flowing a fluorinated polymer deposition gas comprising a fluorocarbon gas, forming the fluorinated polymer deposition gas into a plasma, which deposits a fluorocarbon polymer layer on the structure, and stopping the flow of the fluorinated polymer deposition gas. The activation phase comprises flowing an activation gas comprising an inert bombardment gas and H2, forming the activation gas into a plasma, wherein the inert bombardment gas activates fluorine in the fluorinated polymer which with the plasma components from H2 cause SiO and SiN to be selectively etched with respect to SiGe and Si, and stopping the flow of the activation gas.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: October 3, 2017
    Assignee: Lam Research Corporation
    Inventors: Xin Zhang, Alan Jensen, Gerardo Delgadino, Daniel Le
  • Patent number: 9768027
    Abstract: Embodiments are directed to a method of forming a dielectric region of a fin-type field effect transistor (FinFET). The method includes forming at least one fin, and forming a dielectric region adjacent a lower portion of the at least one fin, wherein the dielectric region includes a top surface. The method further includes forming a blocking layer on the top surface of the dielectric region, wherein the blocking layer is configured to prevent at least one subsequent FinFET fabrication operation from impacting the top surface of the dielectric region.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: September 19, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dechao Guo, Zuoguang Liu, Tenko Yamashita, Chun-Chen Yeh
  • Patent number: 9768059
    Abstract: High-chi diblock copolymers are disclosed whose self-assembly properties are suitable for forming hole and bar openings for conductive interconnects in a multi-layered structure. The hole and bar openings have reduced critical dimension, improved uniformity, and improved placement error compared to the industry standard poly(styrene)-b-poly(methyl methacrylate) block copolymer (PS-b-PMMA). The BCPs comprise a poly(styrene) block, which can optionally include repeat units derived from trimethylsilyl styrene, and a second block that can be a polycarbonate block or a polyester block. Block copolymers comprising a fluorinated linking group L? comprising 1-25 fluorines between the blocks can provide further improvement in uniformity of the openings.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: September 19, 2017
    Assignee: International Business Machines Corporation
    Inventors: Chi-Chun Liu, Teddie P. Magbitang, Daniel P. Sanders, Kristin Schmidt, Ankit Vora
  • Patent number: 9696628
    Abstract: According to one embodiment, a pattern forming method includes forming a resist pattern on an under-layer, forming a recessed portion in the under-layer by etching the under-layer using the resist pattern as a mask, slimming the resist pattern, forming a neutral layer having an affinity for first and second polymers on a region of the under-layer not covered with the slimmed resist pattern, forming a block copolymer film containing the first polymer and the second polymer on the slimmed resist pattern and the neutral layer, and forming a microphase separation pattern comprising a first portion formed of the first polymer and a second portion formed of the second polymer by applying microphase separation processing to the block copolymer film.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: July 4, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yusuke Kasahara, Hideki Kanai
  • Patent number: 9685534
    Abstract: Provided is a method of forming a semiconductor device. The method includes providing a substrate; depositing a flowable dielectric material layer over the substrate; performing a wet annealing process and a dry annealing process to the flowable dielectric material layer. The wet annealing process includes a first portion followed by a second portion. The second portion is performed at a temperature above 850 degrees Celsius, and the first portion is performed at a temperature lower than that of the second portion and is performed for longer duration than the second portion. The dry annealing process is performed at a temperature at least 500 degrees Celsius.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: June 20, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Hsiung Tsai, Wei-Yuan Lu
  • Patent number: 9685319
    Abstract: A method for filling gaps of semiconductor device and a semiconductor device with insulation gaps formed by the same are provided. First, a silicon substrate with plural protruding portions is provided, and the protruding portions are spaced apart from each other by gaps with predetermined depths. A nitride-containing layer is formed above the silicon substrate for covering the protruding portions and surfaces of the gaps as a liner nitride. Then, an amorphous silicon layer is formed on the nitride-containing layer. An insulating layer is formed on the amorphous silicon layer, and the gaps are filled up with the insulating layer.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: June 20, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ping-Wei Huang, Keng-Jen Lin, Yi-Hui Lin, Yu-Ren Wang
  • Patent number: 9673114
    Abstract: Methods, devices and systems for patterning of substrates using charged particle beams without photomasks and without a resist layer. Material can be removed from a substrate, as directed by a design layout database, localized to positions targeted by multiple, matched charged particle beams. Reducing the number of process steps, and eliminating lithography steps, in localized material removal has the dual benefit of reducing manufacturing cycle time and increasing yield by lowering the probability of defect introduction. Furthermore, highly localized, precision material removal allows for controlled variation of removal rate and enables creation of 3D structures or profiles. Local gas injectors and detectors, and local photon injectors and detectors, are local to corresponding ones of the columns, and can be used to facilitate rapid, accurate, targeted substrate processing.
    Type: Grant
    Filed: April 24, 2015
    Date of Patent: June 6, 2017
    Assignee: Multibeam Corporation
    Inventors: David K. Lam, Kevin M. Monahan, Michael C. Smayling, Theodore A. Prescop
  • Patent number: 9674956
    Abstract: A method of manufacturing an intermediate product for an interposer including a glass substrate having a plurality of through holes is provided. The method includes a step of forming a resin layer on a support substrate, and a step of forming a laminated body by adhering the glass substrate having the plurality of through holes on the resin layer. The glass substrate having the plurality of through holes has a thickness within a range of 0.05 mm to 0.3 mm.
    Type: Grant
    Filed: February 25, 2015
    Date of Patent: June 6, 2017
    Assignee: Asahi Glass Company, Limited
    Inventor: Shintaro Takahashi
  • Patent number: 9666474
    Abstract: A method for providing a uniform recess depth between different fin gap sizes includes depositing a dielectric material between fins on a substrate. Etch lag is tuned for etching the dielectric material between narrow gaps faster than the dielectric material between wider gaps such that the dielectric material in the narrow gaps reaches a target depth. An etch block is formed in the narrow gaps. The wider gaps are etched to the target depth. The etch block is removed.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: May 30, 2017
    Assignee: International Business Machines Corporation
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Michael Rizzolo, Jay W. Strane
  • Patent number: 9640576
    Abstract: An image sensing device includes: an active layer with a plurality of photo-sensing elements; a color pattern disposed over one of the photo-sensing elements, wherein the color pattern has a color selected from the group consisting of red (R), green (G), and blue (B); a microlens disposed on the color pattern; and a transmissive pattern being adjacent to the color pattern and over another one of the photo-sensing elements, wherein the transmissive pattern includes a color filter portion and a microlens portion, and an absolute value of a difference of refractive indexes between the microlens and the color pattern is less than 0.3, and there is no difference of refractive indexes between the microlens portion and the color filter portion of the transmissive pattern.
    Type: Grant
    Filed: August 20, 2014
    Date of Patent: May 2, 2017
    Assignee: VISERA TECHNOLOGIES COMPANY LIMITED
    Inventors: Han-Lin Wu, Chieh-Yuan Cheng, Yu-Kun Hsiao, Huang-Jen Chen
  • Patent number: 9633847
    Abstract: A method for treating a microelectronic substrate to form a chemical template includes patterning the substrate to form a trench structure with a plurality of trenches of a defined trench width and depositing a photoactive material on the substrate to overfill the trench structure to form a fill portion in the plurality of trenches and an overfill portion above the trench structure. The method further includes exposing the photoactive material to electromagnetic radiation comprising a wavelength that is at least four times greater than the defined trench width such that the overfill portion is modified by the exposure while the electromagnetic radiation fails to penetrate into the plurality of trenches leaving the fill portion unmodified and removing the modified overfill portion of the photoactive material to form a planarized filled trench structure for use as a chemical template for selective reactive ion etching, selective deposition, or directed self-assembly.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: April 25, 2017
    Assignee: Tokyo Electron Limited
    Inventors: Benjamen M. Rathsack, Mark H. Somervell
  • Patent number: 9633684
    Abstract: According to one embodiment, a magnetic recording medium includes a silicon oxide underlayer having a recess pattern having a plurality of recesses, a nonmagnetic underlayer having a first hole pattern having a plurality of holes corresponding to the recess pattern, and a magnetic recording layer having a second hole pattern having a plurality of holes connected with the first hole pattern. The silicon oxide underlayer, the nonmagnetic underlayer, and the magnetic recording layer are formed in order on the substrate.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: April 25, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Akira Watanabe, Soichi Oikawa
  • Patent number: 9627201
    Abstract: In a method of forming holes, a plurality of guide patterns physically spaced apart from each other is formed on an object layer. The guide pattern has a ring shape and includes a first opening therein. A self-aligned layer is formed on the object layer and the guide patterns to fill the first opening. Preliminary holes are formed by removing portions of the self-aligned layer which are self-assembled in the first opening and between the guide patterns neighboring each other. The object layer is partially etched through the preliminary holes.
    Type: Grant
    Filed: April 15, 2015
    Date of Patent: April 18, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Woo Nam, Eun-Sung Kim