Combined With Coating Step Patents (Class 438/694)
  • Patent number: 10734275
    Abstract: A method includes forming a hard mask over a target layer, performing a treatment on a first portion of the hard mask to form a treated portion, with a second portion of the hard mask left untreated as an untreated portion. The method further includes subjecting both the treated portion and the untreated portion of the hard mask to etching, in which the untreated portion is removed as a result of the etching, and the treated portion remains after the etching. A layer underlying the hard mask is etched, and the treated portion of the hard mask is used as a part of an etching mask in the etching.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: August 4, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiang-Wei Liu, Chia-Tien Wu, Wei-Chen Chu
  • Patent number: 10727517
    Abstract: A solid oxide fuel cell includes an Si support substrate having a through hole, an electrolyte film formed on the surface of an Si support substrate and containing a solid oxide having oxygen ion conductivity, a first electrode formed on a surface of the electrolyte film (surface on the side opposite to the Si support substrate), and a second electrode formed at least on a surface exposed from the through hole in a rear face of the electrolyte film. The electrolyte film includes a porous layer including the solid oxide and containing pores inside, a first dense layer formed on a surface of the porous layer (surface on the side opposite to the Si support substrate), and a second dense layer formed at the interface between a rear face of the porous layer and the Si support substrate.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: July 28, 2020
    Assignee: KABUSHIKI KAISHA TOYOTA CHUO KENKYUSHO
    Inventors: Hidehito Matsuo, Teruhisa Akashi, Hirofumi Funabashi, Hiroko Iguchi, Shigeo Hori, Toshihiko Tani
  • Patent number: 10692724
    Abstract: A method for performing atomic layer etching of a surface of a substrate is provided, including: performing a surface conversion operation by exposing the surface of the substrate to a surface conversion reactant; performing a ligand exchange operation by exposing the surface of the substrate to a ligand containing reactant; performing a desorption operation that effects removal of surface species from the surface of the substrate; performing a purge operation; repeating the surface conversion operation, the ligand exchange operation, the desorption operation, and the purge operation, for a predefined number of cycles.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: June 23, 2020
    Assignee: Lam Research Corporation
    Inventors: David Smith, Thorsten Lill, Andreas Fischer
  • Patent number: 10685849
    Abstract: Exemplary methods of etching semiconductor substrates may include flowing a halogen-containing precursor into a processing region of a semiconductor processing chamber. The processing region may house a substrate having a conductive material and an overlying mask material. The conductive material may be characterized by a first surface in contact with the mask material, and the mask material may define an edge region of the conductive material. The methods may include contacting the edge region of the conductive material with the halogen-containing precursor and the oxygen-containing precursor. The methods may include etching in a first etching operation the edge region of the conductive material to a partial depth through the conductive material to produce a footing of conductive material protruding along the edge region of the conductive material. The methods may also include removing the footing of conductive material in a second etching operation.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: June 16, 2020
    Assignee: Applied Materials, Inc.
    Inventors: He Ren, Jong Mun Kim, Maximillian Clemons, Minrui Yu, Mehul Naik, Chentsau Ying
  • Patent number: 10676491
    Abstract: There is provided a novel isocyanuric acid derivative having two alkoxyalkyl groups and having a trialkoxysilyl group introduced therein, and a method for producing the isocyanuric acid derivative. An isocyanuric acid derivative of formula (1): wherein R1 is a methyl group or an ethyl group; two R2s are each a C1-2 alkylene group; and two R3s are each a methyl group, an ethyl group, or a C2-4 alkoxyalkyl group, which may be liquid at ambient temperature and ambient pressure.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: June 9, 2020
    Assignee: NISSAN CHEMICAL CORPORATION
    Inventors: Shun Kubodera, Yuichi Goto, Wataru Shibayama, Gun Son
  • Patent number: 10672620
    Abstract: Deep reactive ion etching is essential for creating high aspect ratio micro-structures for microelectromechanical systems, sensors and actuators, and emerging flexible electronics. A novel hybrid dual soft/hard mask bilayer may be deposited during semiconductor manufacturing for deep reactive etches. Such a manufacturing process may include depositing a first mask material on a substrate; depositing a second mask material on the first mask material; depositing a third mask material on the second mask material; patterning the third mask material with a pattern corresponding to one or more trenches for transfer to the substrate; transferring the pattern from the third mask material to the second mask material; transferring the pattern from the second mask material to the first mask material; and/or transferring the pattern from the first mask material to the substrate.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: June 2, 2020
    Assignee: KING ABDULLAH UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventor: Mohamed Tarek Ghoneim
  • Patent number: 10664625
    Abstract: A device includes a substrate, an array of metal pads on a first surface of the substrate, a carbon polymer composite covering the array of metal pads, the composite having variations that result in random resistance values between the metal pads usable as a random code. A method of manufacturing a secure device, including forming an array of metal pads on a dielet substrate, the dielet substrate containing at least one memory in which is stored an encryption key, and an RF communication section, covering the array of metal pads with a carbon polymer composite such that variations in the carbon concentration in the polymer forms a unique pattern of resistance, attaching the dielet substrate to a host component, receiving a request from a security server for a unique code determined by the unique pattern of resistance, and using the encryption key, encrypting and providing the unique code to the security server.
    Type: Grant
    Filed: January 6, 2016
    Date of Patent: May 26, 2020
    Assignee: SRI International
    Inventor: Michael G. Kane
  • Patent number: 10643846
    Abstract: Methods and apparatuses for selectively growing metal-containing hard masks are provided herein. Methods include providing a substrate having a pattern of spaced apart features, each feature having a top horizontal surface, filling spaces between the spaced apart features with carbon-containing material to form a planar surface having the top horizontal surfaces of the features and carbon-containing material, selectively depositing a metal-containing hard mask on the top horizontal surfaces of the features relative to the carbon-containing material, and selectively removing the carbon-containing material relative to the metal-containing hard mask and features.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: May 5, 2020
    Assignee: Lam Research Corporation
    Inventors: David Charles Smith, Jon Henri, Dennis M. Hausmann, Paul C. Lemaire
  • Patent number: 10636672
    Abstract: A method for manufacturing an interconnect structure includes providing a metal interconnect layer, forming a first dielectric layer on the metal interconnect layer, forming a fluorocarbon layer on the first dielectric layer, forming a second dielectric layer on the fluorocarbon layer, and performing an etch process on the second dielectric layer using the fluorocarbon layer as an etch stop mask to form an opening. The interconnect structure thus formed has an improved uniformity and reduced parasitic capacitance.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: April 28, 2020
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Ming Zhou
  • Patent number: 10629430
    Abstract: Methods and apparatus for processing a substrate are described herein. A vacuum multi-chamber deposition tool can include a degas chamber with both a heating mechanism and a variable frequency microwave source. The methods described herein use variable frequency microwave radiation to increased quality and speed of the degas process without damaging the various components.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: April 21, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Loke Yuen Wong, Ke Chang, Yueh Sheng Ow, Ananthkrishna Jupudi, Glen T. Mori, Aksel Kitowski, Arkajit Roy Barman
  • Patent number: 10608177
    Abstract: The present disclosure discloses a self-gated RRAM cell and a manufacturing method thereof; which belong to the field of microelectronic technology. The self-gated RRAM cell comprises: a stacked structure containing multiple layers of conductive lower electrodes; a vertical trench formed by etching the stacked structure; a M8XY6 gated layer formed on an inner wall and a bottom of the vertical trench; a resistance transition layer formed on a surface of the M8XY6, gated layer; and a conductive upper electrode formed on a surface of the resistance transition layer, the vertical trench being filled with the conductive upper electrode. The present disclosure is implemented on a basis of using the self-gated RRAM as a memory cell.
    Type: Grant
    Filed: December 26, 2014
    Date of Patent: March 31, 2020
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Hangbing Lv, Ming Liu, Qi Liu, Shibing Long
  • Patent number: 10599039
    Abstract: Processes for removing a mask layer (e.g., doped amorphous carbon mask layer) from a substrate with high aspect ratio structures are provided. In one example implementation, a process can include depositing a polymer layer on at least a portion of a top end of a high aspect ratio structure on a substrate. The process can further include removing at least a portion of the polymer layer and the doped amorphous carbon film form the substrate using a plasma strip process. In example embodiments, depositing a polymer layer can include plugging one or more high aspect ratio structures with the polymer layer. In example embodiments, depositing a polymer layer can include forming a polymer layer on a sidewall of one or more high aspect ratio structures.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: March 24, 2020
    Assignees: MATTSON TECHNOLOGY, INC., BEIJING E-TOWN SEMICONDUCTOR TECHNOLOGY, CO., LTD
    Inventors: Vijay M. Vaniapura, Shawming Ma, Li Hou
  • Patent number: 10580651
    Abstract: The present disclosure relates to a method for creating regions of different device types on a substrate having different pitches. The method includes dividing a substrate into a first device type region and a second device type region. The method further includes forming a target etch layer on the substrate. The method further includes forming a bottom mandrel layer on the target etch layer. The method further includes forming a plurality of alternating first pillars of a top mandrel material and first trenches between the first pillars on the bottom mandrel layer in the first device type region. The plurality of first pillars has a first pitch. The method further includes forming a plurality of alternating second pillars of the top mandrel material and second trenches between the second pillars on the bottom mandrel layer in the second device type region. The plurality of second pillars has a second pitch. The method further includes depositing tone inversion material in the first trenches.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: March 3, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Min Gyu Sung, Sony Varghese
  • Patent number: 10573530
    Abstract: Disclosed is a pattern forming method including: forming an acrylic resin layer on an underlayer; forming an intermediate layer on the acrylic resin layer; forming a patterned EUV resist layer on the intermediate layer; forming a pattern on the acrylic resin layer by etching the intermediate layer and the acrylic resin layer with the EUV resist layer as an etching mask; removing the EUV resist layer and the intermediate layer after the pattern is formed on the acrylic resin layer; and smoothing a surface of the acrylic resin layer after the EUV resist layer and the intermediate layer are removed.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: February 25, 2020
    Assignee: Tokyo Electron Limited
    Inventor: Hidetami Yaegashi
  • Patent number: 10553442
    Abstract: The present disclosure relates to an etching method including: a first step of forming an etching assistance layer on a surface of at least one of a plurality of silicon-containing regions by plasma of a processing gas generated in a processing container; and a second step of imparting energy to the etching assistance layer. The energy is equal to or greater than energy at which the etching assistance layer is removed, and smaller than energy at which a region located immediately below the etching assistance layer is sputtered, and a sequence including the first step and the second step is executed repeatedly.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: February 4, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Akihiro Tsuji
  • Patent number: 10541170
    Abstract: There is provided a technique, including: a process chamber in which a substrate is processed; a substrate support member configured to support the substrate; an elevator configured to elevate the substrate support member; a gas supply port configured to supply a gas to the substrate; and a controller configured to control an elevating operation of the elevator so as to differentiate an interval between the gas supply port and the substrate supported by the substrate support member, when a gas is supplied from the gas supply port.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: January 21, 2020
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventors: Takashi Yahata, Naofumi Ohashi, Shun Matsui
  • Patent number: 10541429
    Abstract: A novel method to produce thin films spatially disposed on desired areas of workpieces is disclosed. Examples of include the formation of a yttria stabilized zirconia (YSZ) film formed on a desired portion of a stainless steel interconnect for solid oxide fuel cells by Atomic Layer Deposition (ALD). A number of methods to produce the spatially disposed YSZ film structures are described including polymeric and silicone rubber masks. The thin film structures have utility for preventing the reaction of glasses with metals, in particular alkali-earth containing glasses with ferritic stainless steels, allowing high temperature bonding of these materials.
    Type: Grant
    Filed: October 22, 2017
    Date of Patent: January 21, 2020
    Assignee: Sonata Scientific LLC
    Inventors: Jeffrey F. Roeder, Peter C. Van Buskirk
  • Patent number: 10529583
    Abstract: An etching method is provided. A processing target object includes a first region made of silicon oxide and a second region made of silicon nitride. The second region is extended to provide a recess and has a bottom region extended on a bottom of the recess. The first region is configured to cover the second region. In the etching method, a deposit of fluorocarbon is formed on the processing target object, and the first region is etched by irradiating ions of atoms of a rare gas toward the processing target object. Then, on the bottom region, a modified region is formed by supplying hydrogen ions. Subsequently, the deposit of fluorocarbon is formed on the processing target object, and the modified region is etched by irradiating ions of atoms of the rare gas toward the processing target object.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: January 7, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Mitsuhiro Iwano, Masanori Hosoya
  • Patent number: 10529366
    Abstract: A data storage medium may have increased data capacity by being configured with first and second patterned pedestals that are each separated from a substrate by a seed layer. A first polymer brush layer can be positioned between the first and second patterned pedestals atop the seed layer and a second polymer brush layer may be positioned atop each patterned pedestal. The first and second polymer brush layers may be chemically different and a block copolymer can be deposited to self-assemble into separate magnetic domains aligned with either the first or second polymer brush layers.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: January 7, 2020
    Assignee: Seagate Technology LLC
    Inventors: Austin P. Lane, Xiaomin Yang, ShuaiGang Xiao, Kim Yang Lee, David S. Kuo
  • Patent number: 10515812
    Abstract: A method includes forming a metal-containing material layer over a substrate, patterning the metal-containing material layer, where the patterned material layer has an average roughness, and electrochemically treating the patterned metal-containing material layer to reduce the average roughness. The treatment may be implemented by exposing the patterned metal-containing material layer to an electrically conducting solution, and applying a potential between the patterned material layer and a counter electrode exposed to the solution, such that the treating reduces the average roughness of the patterned material layer. The electrically conducting solution may include an ionic compound dissolved in water, alcohol, and/or a surfactant.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: December 24, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Wei Wang, Joy Cheng, Ching-Yu Chang, Chin-Hsiang Lin
  • Patent number: 10515953
    Abstract: Semiconductor devices having void-free dielectric structures and methods of fabricating same are disclosed herein. An exemplary semiconductor device includes a plurality of fin structures disposed over a substrate having isolation features disposed therein and a plurality of gate structures disposed over the plurality of fin structures. The plurality of gate structures traverse the plurality of fin structures. The semiconductor device further includes a dielectric structure defined between the plurality of fin structures and the plurality of gate structures. The dielectric structure has an aspect ratio of about 5 to about 16. The dielectric structure includes a first dielectric layer disposed over the substrate and a second dielectric layer disposed on the first dielectric layer. The first dielectric layer and the second dielectric layer are disposed on sidewalls of the plurality of fin structures and sidewalls of the plurality of gate structures.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: December 24, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ying-Hao Su, Yu-Chung Su, Yu-Lun Liu, Chi-Kang Chang, Chia-Chu Liu, Kuei-Shun Chen
  • Patent number: 10515818
    Abstract: To pattern a gate electrode, a mandrel of material is initially deposited and then patterned. In an embodiment the patterning is performed by performing a first etching process and to obtain a rough target and then to perform a second etching process with different etch parameters to obtain a precise target. The mandrel is then used to form spacers which can then be used to form masks to pattern the gate electrode.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: December 24, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Kang Liu, Jr-Jung Lin, Huan-Just Lin, Ming-Hsi Yeh, Sung-Hsun Wu
  • Patent number: 10504972
    Abstract: An organic light emitting display panel and a method for manufacturing the same are provided. The organic light emitting display panel includes: an organic light emitting element array substrate; a thin film encapsulation layer covering the organic light emitting element array substrate and including at least one inorganic layer and at least one organic layer; a wettability adjustment layer disposed on an organic layer or inorganic layer of the thin film encapsulation layer and including a plurality of wettability adjustment pattern zones and a plurality of hollow zones, and touch electrodes made of metal. The touch electrodes are in a meshed shape and disposed in the hollow zones. A wetting angle between material of the touch electrodes and the wettability adjustment pattern zones is greater than a wetting angle between the material of the touch electrodes and the organic layer or the inorganic layer.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: December 10, 2019
    Assignees: SHANGHAI TIANMA MICRO-ELECTRONICS CO., LTD., TIANMA MICRO-ELECTRONICS CO., LTD.
    Inventor: Yu Cai
  • Patent number: 10504844
    Abstract: A three-dimensional (3D) semiconductor device includes a substrate having a cell array region and a peripheral circuit region. A cell array structure is in the cell array region and includes a 3D memory cell array. A peripheral logic structure is in the peripheral circuit region and includes a peripheral circuit transistor. A cell insulating layer insulates the cell array structure. A peripheral insulating layer is insulated from the peripheral logic structure and the cell array region and has a porous layer.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: December 10, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-woo Kim, Joon-sung Lim, Jang-gn Yun, Sung-min Hwang
  • Patent number: 10497567
    Abstract: Implementations described herein generally relate to an etching process for etching materials with high selectivity. In one implementation, a method of etching a gate material to form features in the gate material is provided. The method includes (a) exposing a cobalt mask layer to a fluorine-containing gas mixture in a first mode to form a passivation film on the cobalt mask layer. The cobalt mask layer exposes a portion of a gate material disposed on a substrate. The method further comprises (b) exposing the portion of the gate material to an etching gas mixture in a second mode to etch the portion of the gate material. The portion of the gate material is etched through openings defined in the cobalt mask layer and the portion of the gate material is etched at a greater rate than the cobalt mask layer having the passivation layer disposed thereon.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: December 3, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Hailong Zhou, Yangchung Lee, Chain Lee, Hui Sun, Jonathan Sungehul Kim
  • Patent number: 10490643
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region, a second region, a third region, and a fourth region; forming a tuning layer on the second region; forming a first work function metal layer on the first region and the tuning layer of the second region; forming a second work function metal layer on the first region, the second region, and the fourth region; and forming a top barrier metal (TBM) layer on the first region, the second region, the third region, and the fourth region.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: November 26, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kuo-Chih Lai, Yun-Tzu Chang, Wei-Ming Hsiao, Nien-Ting Ho, Shih-Min Chou, Yang-Ju Lu, Ching-Yun Chang, Yen-Chen Chen, Kuan-Chun Lin, Chi-Mao Hsu
  • Patent number: 10461031
    Abstract: According to various embodiments, a method for processing an electronic device may include: forming a patterned hard mask layer over a power metallization layer, the patterned hard mask layer exposing at least one surface region of the power metallization layer; and patterning the power metallization layer by wet etching of the exposed at least one surface region of the power metallization layer.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: October 29, 2019
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Petra Fischer, Johanna Schlaminger, Monika Cornelia Voerckel, Peter Zorn
  • Patent number: 10446394
    Abstract: Methods and apparatuses for spacer profile control using atomic layer deposition (ALD) in multi-patterning processes are described herein. A silicon oxide spacer is deposited over a patterned core material and a target layer of a substrate in a multi-patterning scheme. A first thickness of the silicon oxide spacer is deposited by multiple ALD cycles under a first oxidation condition that includes an oxidation time, a plasma power, and a substrate temperature. A second thickness of the silicon oxide spacer is deposited by multiple ALD cycles under a second oxidation condition, where the second oxidation condition is different than the first oxidation condition by one or more parameters. After etching the patterned core material, a resulting profile of the silicon oxide spacer is dependent at least in part on the first and second oxidation conditions.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: October 15, 2019
    Assignee: Lam Research Corporation
    Inventors: Mirzafer Abatchev, Qian Fu, Yoko Yamaguchi, Aaron Eppler
  • Patent number: 10431492
    Abstract: A method of manufacturing a semiconductor structure includes forming a lower hard mask layer on a substrate. A patterned middle hard mask layer is formed on the lower hard mask layer, and the patterned middle hard mask layer has a plurality of openings exposing a portion of the lower hard mask layer. A patterned lower hard mask layer and a textured substrate having a plurality of trenches are formed by etching the exposed portion of the lower hard mask layer and a portion of the substrate under the exposed portion of the lower hard mask layer. A steam treatment is then performed on the textured substrate having the trenchess. An isolation oxide layer is formed to fill the trenches.
    Type: Grant
    Filed: May 28, 2018
    Date of Patent: October 1, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Shing-Yih Shih, Hsin-Hung Ting
  • Patent number: 10427944
    Abstract: A composition for forming a silica based layer, the composition including a silicon-containing polymer having polydispersity ranging from about 3.0 to about 30 and a solvent, and having viscosity ranging from about 1.30 centipoise (cps) to about 1.80 cps at 25° C. Also, a silica based layer is formed of the composition, and an electronic device includes the silica based layer.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: October 1, 2019
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Jun-Young Jang, Taek-Soo Kwak, Woo-Han Kim, Hui-Chan Yun, Jin-Hee Bae, Bo-Sun Kim, Yoong-Hee Na, Sae-Mi Park, Han-Song Lee, Wan-Hee Lim
  • Patent number: 10388788
    Abstract: A method for forming a semiconductor device is disclosed. A p-type field-effect transistor (p-FET) is formed on a semiconductor substrate. A dielectric layer is formed on the semiconductor substrate and completely covers the p-FET. At least an opening is formed in the dielectric layer and exposes a source/drain region of the p-FET. A conductive material is then formed filling the opening, wherein the conductive material comprises a first stress; specifically, a tensile stress between 400 and 800 MPa.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: August 20, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shao-Ping Chen, Huan-Chi Ma, Chien-Wen Yu, Kuo-Chin Hung
  • Patent number: 10370556
    Abstract: Disclosed is a method for mechanically anchoring polymers on the surface of a porous substrate by trapping polymer chains within the pores of the substrate under capillary forces. Surface modification of the porous substrate is achieved by anchoring one end of the polymer chains within the pores while one or more other ends of the polymer chains dangle from the surface of the porous substrate. The method provides a unique way of modifying the surface of a material without chemical reactions or precursor-substrate interactions.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: August 6, 2019
    Assignee: International Business Machines Corporation
    Inventors: Geraud J. M. Dubois, Krystelle Lionti, Teddie P. Magbitang, Willi Volksen
  • Patent number: 10359699
    Abstract: A process flow for shrinking a critical dimension (CD) in photoresist features and reducing CD non-uniformity across a wafer is disclosed. A photoresist pattern is treated with halogen plasma to form a passivation layer with thickness (t1) on feature sidewalls, and thickness (t2) on the photoresist top surface where t2>t1. Thereafter, an etch based on O2, or O2 with a fluorocarbon or halogen removes the passivation layer and shrinks the CD. The passivation layer slows the etch such that photoresist thickness is maintained while CD shrinks to a greater extent for features having a width (d1) than on features having width (d2) where d1>d2. Accordingly, CD non-uniformity is reduced from 2.3% to 1% when d2 is 70 nm and is shrunk to 44 nm after the aforementioned etch. After a second etch through a MTJ stack to form MTJ cells, CD non-uniformity is maintained at 1%.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: July 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi Yang, Dongna Shen, Jesmin Haq, Yu-Jen Wang
  • Patent number: 10273143
    Abstract: The present disclosure involves forming a method of fabricating a Micro-Electro-Mechanical System (MEMS) device. A plurality of openings is formed in a first side of a first substrate. A dielectric layer is formed over the first side of the substrate. A plurality of segments of the dielectric layer fills the openings. The first side of the first substrate is bonded to a second substrate that contains a cavity. The bonding is performed such that the segments of the dielectric layer are disposed over the cavity. A portion of the first substrate disposed over the cavity is transformed into a plurality of movable components of a MEMS device. The movable components are in physical contact with the dielectric the layer. Thereafter, a portion of the dielectric layer is removed without using liquid chemicals.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: April 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Lee-Chuan Tseng, Chang-Ming Wu, Shih-Chang Liu, Yuan-Chih Hsieh
  • Patent number: 10256112
    Abstract: Exemplary methods for removing tungsten-containing material may include flowing a chlorine-containing precursor into a processing region of a semiconductor processing chamber. The methods may also include flowing methane into the processing region of the semiconductor processing chamber. The methods may include forming a plasma from the chlorine-containing precursor and the methane to produce plasma effluents. The methods may also include contacting a substrate with the plasma effluents. The substrate may include an exposed region of a tungsten-containing material. The plasma effluents may produce an oxychloride of tungsten. The methods may also include recessing the exposed region of the tungsten-containing material.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: April 9, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Xikun Wang, Nitin Ingle
  • Patent number: 10229849
    Abstract: Disclosed is a substrate processing apparatus including a disc provided so as to be rotatable on its axis, at least one susceptor disposed on the disc such that a substrate is seated on an upper surface thereof, the susceptor being configured to rotate on its axis and to revolve around a center of the disc as the disc rotates on its axis, a metal ring coupled to a lower portion of the susceptor, the metal ring being arranged such that a center thereof coincides with a center of the susceptor, and a magnet provided below the disc so as to be radially arranged on a basis of the center of the disc, at least a portion of the magnet being opposite the metal ring in a vertical direction.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: March 12, 2019
    Assignee: JUSUNG ENGINEERING CO., LTD.
    Inventors: Ki Bum Kim, Seung Youb Sa, Ram Woo, Myung Jin Lee, Seung Dae Choi, Jong Sung Choi, Ho Boem Her
  • Patent number: 10224212
    Abstract: A method for isotropically etching film on a substrate with atomic layer control includes a) providing a substrate including a material selected from a group consisting of silicon (Si), germanium (Ge) and silicon germanium (SiGe). The method includes b) depositing a sacrificial layer on the material in a processing chamber by: cooling a lower portion of the substrate; one of creating or supplying an oxidant-containing plasma in the processing chamber; and increasing a surface temperature of the substrate for a predetermined period using rapid thermal heating while creating or supplying the oxidant-containing plasma in the processing chamber. The method includes c) purging the processing chamber. The method includes d) etching the sacrificial layer and the material by supplying an etch gas mixture and striking plasma in the processing chamber.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: March 5, 2019
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Yunsang Kim, Hyuk-Jun Kwon, Dong Woo Paeng, He Zhang
  • Patent number: 10199235
    Abstract: Methods and techniques for fabricating metal interconnects, lines, or vias by subtractive etching and liner deposition methods are provided. Methods involve depositing a blanket copper layer, removing regions of the blanket copper layer to form a pattern, treating the patterned metal, depositing a copper-dielectric interface material such that the copper-dielectric interface material adheres only to the patterned copper, depositing a dielectric barrier layer on the substrate, and depositing a dielectric bulk layer on the substrate.
    Type: Grant
    Filed: January 18, 2018
    Date of Patent: February 5, 2019
    Assignee: Lam Research Corporation
    Inventors: Hui-Jung Wu, Thomas Joseph Knisley, Nagraj Shankar, Meihua Shen, John Hoang, Prithu Sharma
  • Patent number: 10134600
    Abstract: A method for forming a semiconductor device in a plasma processing chamber is provided. An atomic layer etch selectively etches SiO with respect to SiN and deposits a fluorinated polymer. The fluorinated polymer layer is stripped, comprising flowing a stripping gas comprising oxygen into the plasma processing chamber, forming a plasma from the stripping gas, and stopping the flow of the stripping gas. A SiN layer is selectively etched with respect to SiO and SiGe and Si.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: November 20, 2018
    Assignee: Lam Research Corporation
    Inventors: Leonid Romm, Alan Jensen, Xin Zhang, Gerardo Delgadino
  • Patent number: 10121822
    Abstract: A light-emitting device may include an active layer. The light-emitting device may include a first semiconductor layer of a first conductivity type. The first semiconductor layer may be in physical contact with the active layer. The light-emitting device may also include a second semiconductor layer of a second conductivity type. The second semiconductor layer may be in physical contact with the active layer and opposite the first conductive layer. The light-emitting device may further include a first electrode in physical contact with a first side of the first semiconductor layer. The light-emitting device may additionally include a second electrode in physical contact with a second side of the first semiconductor layer. The second side of the first semiconductor layer may be different from the first side of the first semiconductor layer. The light-emitting device may also include a third electrode in physical contact with the second semiconductor layer.
    Type: Grant
    Filed: November 18, 2014
    Date of Patent: November 6, 2018
    Assignee: NANYANG TECHNOLOGICAL UNIVERSITY
    Inventors: Xueliang Zhang, Zi-Hui Zhang, Yun Ji, Zhen Gang Ju, Wei Liu, Swee Tiam Tan, Xiaowei Sun, Hilmi Volkan Demir
  • Patent number: 10115585
    Abstract: Provided is a material composition and method for that includes forming a silicon-based resin over a substrate. In various embodiments, the silicon-based resin includes a nitrobenzyl functional group. In some embodiments, a baking process is performed to cross-link the silicon-based resin. Thereafter, the cross-linked silicon-based resin is patterned and an underlying layer is etched using the patterned cross-linked silicon-based resin as an etch mask. In various examples, the cross-linked silicon-based resin is exposed to a radiation source, thereby de-cross-linking the silicon-based resin. In some embodiments, the de-cross-linked silicon-based resin is removed using an organic solution.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: October 30, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Yu Liu, Ching-Yu Chang, Chin-Hsiang Lin
  • Patent number: 10083271
    Abstract: Provided is a method of fabricating a semiconductor device. An integrated circuit (IC) layout plan is obtained. The IC layout plan contains critical features and non-critical features. Locational information regarding a defect on a blank reticle is obtained. The blank reticle is a candidate reticle for being patterned with the IC layout plan. Based on the locational information regarding the defect and the IC layout plan, a determination is made that at some of the critical features will intersect with the defect if the blank reticle is patterned with the IC layout plan, regardless of whether the IC layout plan is globally manipulated or not before being patterned onto the blank reticle. In response to the determination, selected local portions of the IC layout plan are re-arranged such that none of the critical features will intersect with the defect if the blank reticle is patterned with the IC layout plan.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: September 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Ming Chang, Chia-Hao Yu
  • Patent number: 10079313
    Abstract: A graphene electronic device includes a gate insulating layer on a conductive substrate, a channel layer on the gate insulating layer, and a source electrode on one end of the channel layer and a drain electrode on another end of the channel layer. The channel layer includes a semiconductor layer and a graphene layer in direct contact with the semiconductor layer, and the graphene layer includes a plurality of graphene islands spaced apart from each other.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: September 18, 2018
    Assignees: Samsung Electronics Co., Ltd., Research & Business Foundation Sungkyunkwan University
    Inventors: Kiyoung Lee, Jinseong Heo, Woojong Yu, Yongseon Shin
  • Patent number: 10062615
    Abstract: A semiconductor device comprises first stack of nanowires arranged on a substrate comprises a first nanowire and a second nanowire, the second nanowire is arranged substantially co-planar in a first plane with the first nanowire the first nanowire and the second nanowire arranged substantially parallel with the substrate, a second stack of nanowires comprises a third nanowire and a fourth nanowire, the third nanowire and the fourth nanowire arranged substantially co-planar in the first plane with the first nanowire, and the first nanowire and the second nanowire comprises a first semiconductor material and the third nanowire and the fourth nanowire comprises a second semiconductor material, the first semiconductor material dissimilar from the second semiconductor material.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: August 28, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Ramachandra Divakaruni, Juntao Li
  • Patent number: 10050149
    Abstract: A method of forming a semiconductor device includes forming a source/drain region and spacers on a substrate. The method further includes forming an etch stop layer on the spacers and the source/drain region and forming a gate structure between the spacers. The method further includes etching back the gate structure, etching back the spacers and the etch back layer, and forming a gate capping structure on the etched back gate structure, spacers, and etch stop layer.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: August 14, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Lien Huang, Tsai-Chun Li, Ching-Feng Fu, Ming-Huan Tsai, D. T. Lee, Cheng-Hua Yang, Yi-Chen Lo
  • Patent number: 10042255
    Abstract: Block copolymers comprise a first block comprising an alternating copolymer, and a second block comprising a unit comprising a hydrogen acceptor. The block copolymers find particular use in pattern shrink compositions and methods in semiconductor device manufacture for the provision of high resolution patterns.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: August 7, 2018
    Assignees: Dow Global Technologies LLC, Rohm and Haas Electronic Materials LLC
    Inventors: Huaxing Zhou, Vipul Jain, Jin Wuk Sung, Peter Trefonas, III, Phillip D. Hustad, Mingqi Li
  • Patent number: 10043772
    Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole of the first interconnection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first interconnection member and the semiconductor chip; a second interconnection member disposed on the first interconnection member and the semiconductor chip; and connection terminals disposed on the second interconnection member. The first interconnection member and the second interconnection member respectively include redistribution layers electrically connected to the connection pads of the semiconductor chip, and a connection pad and a connection terminal are electrically connected to each other by a pathway passing through the redistribution layer of the first interconnection member.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: August 7, 2018
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Sang Kyu Lee, Jin Gu Kim
  • Patent number: 10037902
    Abstract: A substrate processing device includes a holding member for holding a substrate, and an opposed member having a body portion and an extended portion extending from at least a part of a peripheral edge part of the body portion. A protrusion is provided on one part of a tip side part of the extended portion and a side surface part of the holding member, and the other part is provided with a restricting structure disposed opposite to the protrusion and restricting relative motion of the protrusion. The relative motion between the holding member and the opposed member is restricted, and the substrate processing device further includes a rotating mechanism, and a nozzle for discharging a processing solution and the protrusion and the restricting structure are disposed below an upper surface of the holding member.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: July 31, 2018
    Assignee: SCREEN Holdings Co., Ltd.
    Inventors: Daichi Yoshitomi, Kazuki Inoue, Masaki Iwami, Hiroaki Ishii
  • Patent number: 10032638
    Abstract: A method includes forming mask patterns spaced apart from each other by at least one opening on an etch target layer, filling the opening with a block copolymer material including first and second polymer blocks of different properties, and annealing the block copolymer material to form first patterns and second patterns, the first patterns in contact with facing sidewalls of adjacent ones of the mask patterns, respectively, and at least one of the second patterns between the first patterns. The first patterns include the first polymer blocks and the second patterns include the second polymer blocks.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: July 24, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Shigenobu Maeda, Jeong Ju Park, Eunsung Kim, Hyunwoo Kim, Shiyong Yi
  • Patent number: 10017610
    Abstract: In an example, a silicone-based thermal interface material includes a thermally conductive material and a silicone-based polymeric material having a solubility parameter that is not less than 9.09 cal1/2 cm?3/2.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: July 10, 2018
    Assignee: International Business Machines Corporation
    Inventors: Sarah K. Czaplewski, Joseph Kuczynski, Jason T. Wertz, Jing Zhang