Abstract: A micro-device structure comprises a source substrate having a sacrificial layer comprising a sacrificial portion adjacent to an anchor portion, a micro-device disposed completely over the sacrificial portion, the micro-device having a top side opposite the sacrificial portion and a bottom side adjacent to the sacrificial portion and comprising an etch hole that extends through the micro-device from the top side to the bottom side, and a tether that physically connects the micro-device to the anchor portion. A micro-device structure comprises a micro-device disposed on a target substrate. Micro-devices can be any one or more of an antenna, a micro-heater, a power device, a MEMs device, and a micro-fluidic reservoir.

Abstract: Methods, systems, and devices for operating memory cell(s) are described. A resistance of a storage element included in a memory cell may be programmed by applying a voltage to the memory cell that causes ion movement within the storage element, where the storage element remains in a single phase and has different resistivity based on a location of the ions within the storage element. In some cases, multiple of such storage elements may be included in a memory cell, where ions within the storage elements respond differently to electric pulses, and a non-binary logic value may be stored in the memory cell by applying a series of voltages or currents to the memory cell.

Abstract: In a method of manufacturing a semiconductor device, underlying structures comprising gate electrodes and source/drain epitaxial layers are formed, one or more layers are formed over the underlying structures, a hard mask layer is formed over the one or more layers, one or more first resist layers are formed over the hard mask layer, a first photo resist pattern is formed over the one or more first resist layers, a width of the first photo resist pattern is adjusted, the one or more first resist layers are patterned by using the first photo resist pattern as an etching mask, thereby forming a first hard mask pattern, and the hard mask layer is patterned by using the first hard mask pattern, thereby forming a second hard mask pattern.

Abstract: A structure of flash memory cell includes a substrate. A floating gate is disposed on the substrate. A low dielectric constant (low-K) spacer is disposed on a sidewall of the floating gate. A trench isolation structure has a base part disposed in the substrate and a protruding part above the substrate protruding from the base part. The low-K spacer is sandwiched between the floating gate and the protruding part of the trench isolation structure.

Abstract: A semiconductor optical module includes a semiconductor laser element region having an active layer, a first cladding layer which is formed such that the active layer is embedded therein, a second cladding layer which is formed underneath the active layer and the first cladding layer, and a heater unit which produces a temperature change in a waveguide; an optical waveguide element region including a spot-size converter which converts a spot size of incident laser light, and an optical waveguide core layer which is formed such that the spot-size converter is embedded therein, the first cladding layer contains InP, the second cladding layer is made of a material lower in refractive index and higher in thermal conductivity than the first cladding layer, and a third cladding layer which is made of a material lower in refractive index and lower in thermal conductivity than the second cladding layer is formed underneath the spot-size converter and the heater unit.

Abstract: Light detection devices and related methods are provided. The devices may comprise a reaction structure for containing a reaction solution with a relatively high or low pH and a plurality of reaction sites that generate light emissions. The devices may comprise a device base comprising a plurality of light sensors, device circuitry coupled to the light sensors, and a plurality of light guides that block excitation light but permit the light emissions to pass to a light sensor. The device base may also include a shield layer extending about each light guide between each light guide and the device circuitry, and a protection layer that is chemically inert with respect to the reaction solution extending about each light guide between each light guide and the shield layer. The protection layer prevents reaction solution that passes through the reaction structure and the light guide from interacting with the device circuitry.

Abstract: The disclosure provides a pattern collapse free wet clean process for fabricating semiconductor devices. By performing post reactive ion etching (RIE) using a fluorine-containing gas such as C2F6, followed by cleaning in a single wafer cleaner (SWC) with diluted hydrofluoric acid (HF) or in a solution of ammonia and HF, a substrate with multiple pattern collapse free high aspect ratio shallow trench isolation (STI) features can be obtained.

Abstract: Described herein are various inventions and embodiments thereof, directed to systems, devices, and methods for analysis of a biofluid, as well as controlling a biofluid analysis system using a microfluidic device. Embodiments of biofluid analysis systems disclosed herein may provide analysis of a biofluid to identify and characterize one or more analytes. An apparatus may include a first layer defining a first opening and a second opening. The first layer may be substantially transparent. A second layer may be coupled to the first layer and define a microfluidic channel that establishes a fluid communication path between the first opening and the second opening. At least a portion of the second layer may be substantially opaque.

Abstract: A waveguide assembly is disclosed herein. In an embodiment, a waveguide assembly includes a circuit board, a housing and a waveguide filter channel. The circuit board has at least one waveguide interface formed from an electrically conductive material. The housing is configured to be attached to the circuit board so as to align with the at least one waveguide interface. The waveguide filter channel is formed between the circuit board and the housing, with the circuit board and the housing each forming at least a portion of the waveguide filter channel. The waveguide filter channel is configured to at least one of (i) receive a radio frequency signal from the at least one waveguide interface or (ii) output the radio frequency signal to the at least one waveguide interface.

Abstract: To provide modified colloidal silica capable of improving the stability of the polishing speed with time when used as abrasive grains in a polishing composition for polishing a polishing object that contains a material to which charged modified colloidal silica easily adheres, such as a SiN wafer, and to provide a method for producing the modified colloidal silica. Modified colloidal silica, being obtained by modifying raw colloidal silica, wherein the raw colloidal silica has a number distribution ratio of 10% or less of microparticles having a particle size of 40% or less relative to a volume average particle size based on Heywood diameter (equivalent circle diameter) as determined by image analysis using a scanning electron microscope.

Abstract: Method for producing coating composition applied to patterned resist film in lithography process for solvent development to reverse pattern. The method including: step obtaining hydrolysis condensation product by hydrolyzing and condensing hydrolyzable silane in non-alcoholic hydrophilic solvent; step of solvent replacement wherein non-alcoholic hydrophilic solvent replaced with hydrophobic solvent for hydrolysis condensation product. Method for producing semiconductor device, including: step of applying resist composition to substrate and forming resist film; step of exposing and developing formed resist film; step applying composition obtained by above production method to patterned resist film obtained during or after development in step, forming coating film between patterns; step of removing patterned resist film by etching and reversing patterns. Production method that exposure is performed using ArF laser (with wavelength of 193 nm) or EUV (with wavelength of 13.5 nm).

Abstract: There is provided a plasma annealing device that can change the crystal structure of a film by processing the film (coating) on a substrate and that has excellent productivity. A method for producing a film includes step (A) irradiating a film on a substrate with atmospheric pressure plasma, wherein the crystal structure of a constituent of the film is changed. The step (A) may include generating plasma under atmospheric pressure by energization at a frequency of 10 hertz to 100 megahertz and a voltage of 60 volts to 1,000,000 volts, and directly irradiating the film on the substrate with the generated plasma. A method for changing a crystal structure of a constituent of a film includes step (A). A plasma generation device used in step (A). An electronic device produced through step (A).

Abstract: Methods and systems for selective deposition of conductive a cap for FAV features are described. In an embodiment, a method may include receiving a substrate having an interlayer dielectrics (ILD) layer, the ILD layer having a recess, the recess having a conductive layer formed therein, the conductive layer comprising a first conductive material. Additionally, such a method may include forming a cap within a region defined by the recess and in contact with a surface of the conductive layer, the cap comprising a second conductive material. The method may also include forming a conformal etch stop layer in contact with a surface of the cap and in contact with a region of the ILD layer. Further, the method may include selectively etching the etch stop layer using a plasma etch process, wherein the plasma etch process removes the etch stop layer selective to the second conductive material comprising the cap.

Abstract: A method of forming a semiconductor device includes forming a mask layer over a substrate and forming an opening in the mask layer. A gap-filling material is deposited in the opening. A plasma treatment is performed on the gap-filling material. The height of the gap-filling material is reduced. The mask layer is removed. The substrate is patterned using the gap-filling material as a mask.

Abstract: An etching method includes (a) performing a plasma etching on an organic film, having a mask formed thereon, to form a recess in the organic film; (b) forming an organic protective film on a side wall surface of the recess in the organic film; and (c) performing an additional plasma etching on the organic film after (b).

Abstract: A substrate treatment apparatus includes: a substrate holding unit; a rotator for rotating the substrate holding unit; a first liquid nozzle for supplying a rinsing liquid; a second liquid nozzle for supplying a low surface tension liquid; a heater; a lifting mechanism for relatively moving up and down the heater between a contact position allowing the heater to be brought into contact with the lower surface of the substrate and a separation position allowing the heater to be separated from the substrate; a gas nozzle provided in an upper surface of the heater to suck the substrate; a suction pump for sucking an atmosphere above the heater through the gas nozzle; a gas supply source for supplying an inert gas toward above the heater through the gas nozzle; and a controller for selectively performing suction of the atmosphere or supply of the inert gas, through the gas nozzle.

Abstract: A silicon etching solution includes a mixed solution comprising a quaternary alkylammonium hydroxide and water and further comprises a compound represented by the following formula (1): R1O—(CmH2mO)n—R2??(1) wherein R1 is a hydrogen atom or an alkyl group having 1 to 3 carbon atoms, R2 is a hydrogen atom or an alkyl group having 1 to 6 carbon atoms, m is an integer of 2 to 6, and n is 1 or 2.

Abstract: A method for fabricating a semiconductor device may include forming a stopper layer; forming an intermediate pattern material layer over the stopper layer; forming a plurality of first preliminary intermediate patterns by patterning the intermediate pattern material layer; forming a plurality of second preliminary intermediate patterns by shrinking the first preliminary intermediate patterns; forming a conductive material layer to cover the second preliminary intermediate patterns; forming a plurality of preliminary conductive interconnection patterns by patterning the conductive material layer; forming a filling layer between the preliminary conductive interconnection patterns; and forming a plurality of intermediate patterns, a plurality of conductive interconnection patterns and a plurality of filling patterns by removing top portions of the filling layer, the preliminary conductive interconnection patterns and the second preliminary intermediate patterns.

Abstract: A method of selectively etching a silicon nitride film includes a first step of disposing a target substrate having the silicon nitride film formed thereon in a processing space, a second step of introducing a gas containing H and F into the processing space, and a third step of selectively introducing radicals of an inert gas into the processing space.

Abstract: An apparatus and method process a substrate in a first session and a second session. In the first session, a hybrid gas application cycle is performed in a chamber that holds the substrate. A first gas is introduced for a first time period so components of the first gas adsorb onto the substrate. Subsequently, a second gas is introduced for a second time period so the second gas reacts with the components of the first gas to provide a protective layer on sidewalls of a pattern of the substrate, and the second gas etches a bottom portion of the pattern, a ratio of the first time period to the second time period being a use-ratio. Then, in a second session, the hybrid gas application cycle is repeated with a different use-ratio that corresponds with a vertical dimension of the pattern.

Abstract: A mask pattern, a semiconductor structure and a method for forming the semiconductor structure are provided. The mask pattern includes a first mask pattern and a second mask pattern. The first mask pattern includes a plurality of first target patterns, and the plurality of first target patterns are arranged along a first direction. The second mask pattern includes a plurality of second target patterns, and the plurality of second target patterns are arranged along the first direction. When the first mask pattern overlaps the second mask pattern, one of the plurality of first target patterns partially overlaps a corresponding one of the plurality of second target patterns.

Abstract: An electrophotographic member comprises a base member and an elastic layer on the base member. The elastic layer contains a silicone rubber, an ionic electroconductive agent, and an inorganic particle, and the inorganic particle contains a hydroxide of at least one of magnesium or aluminum, and has a silicon atom on a surface thereof in an amount of 0.50 to 2.00 atomic %. An aqueous dispersion of which 5 mg of the inorganic particle is dispersed in 10 ml of water has a turbidity of 200 NTU or more and 1,240 NTU or less.

Abstract: [Subject] There is provided a gap filling composition which can reduce pattern collapse and a pattern forming method using the composition. [Solution means] There is provided a gap filling composition including a polymer having a certain structure and an organic solvent. There is provided a pattern forming method using a certain polymer.

Abstract: Embodiments provide raised pad formations for step contacts in three-dimensional structures formed on microelectronic workpieces. Steps are formed in a multilayer stack that is used for the three-dimensional structure. The multilayer stack includes alternating non-conductive and conductive layers. For one embodiment, alternating oxide and polysilicon layers are used. The steps expose contact regions on different conductive layers. Material layers are formed on the contact regions to form raised pads. The material layers preferably have a high selectivity with respect to the non-conductive material for etch processes. A protective layer is formed over the steps and the raised pads, and contact holes are formed through the protective layer to the raised pads. Contacts are then formed within the contact holes. The raised pads inhibit punch-through of the non-conductive layers during the forming of the contact holes thereby improving performance of resulting devices formed in the microelectronic workpieces.

Abstract: Disclosed are apparatuses and methods for performing atomic layer etching. A method may include supporting and thermally floating a substrate in a processing chamber, modifying one or more surface layers of material on the substrate by chemical adsorption, without using a plasma, while the substrate is maintained at a first temperature, and removing the one or more modified surface layers by desorption, without using a plasma, while the substrate is maintained at a second temperature, the first temperature being different than the second temperature. An apparatus may include a processing chamber and support features configured to support and thermally float a substrate in the chamber, a process gas unit configured to flow a first process gas onto the substrate, a substrate heating unit configured to heat the substrate, and a substrate cooling unit configured to actively cool the substrate.

Abstract: A method for manufacturing a semiconductor device includes forming a first insulating film over a semiconductor substrate and forming a second insulating film on the first insulating film. The first insulating film is a tensile film having a first tensile stress and the second insulating film is either a tensile film having a second tensile stress that is less than the first tensile stress or a compressive film. The first insulating film and second insulating film are formed of a same material. A metal hard mask layer is formed on the second insulating film.

Abstract: An electrostatic chuck includes a support assembly including a base, a chuck placed at the base and configured to carry a workpiece, and a fastening assembly configured to removably fix the chuck at the base.

Abstract: The present disclosure relates to a method for forming a semiconductor structure includes depositing a dielectric layer on a substrate and depositing a patterning layer on the dielectric layer. The method also includes performing a first etching process on the patterning layer to form a first region including a first plurality of blocks at a first pattern density and a second region including a second plurality of blocks at a second pattern density that is lower than the first pattern density. The method also includes performing a second etching process on the second plurality of blocks to decrease a width of each block of the second plurality of blocks and etching the dielectric layer and the substrate using the first and second pluralities of blocks to form a plurality of fin structures.

Abstract: An anodic-oxidation equipment for forming a porous layer on a substrate to be treated, including: an electrolytic bath filled with an electrolytic solution; an anode and a cathode disposed in the electrolytic solution; and a power supply for applying current between the anode and the cathode in the electrolytic solution, wherein the anode is the substrate to be treated, and the cathode is a silicon substrate having a surface on which a nitride film is formed. This provides a cathode material in anodic-oxidation for forming porous silicon by an electrochemical reaction in an HF solution, the cathode material having a resistance to electrochemical reaction in an HF solution and no metallic contamination, etc., and furthermore, being less expensive than a conventional cathode material. Furthermore, high-quality porous silicon is provided at a lower cost than has been conventional.

Abstract: A method and equipment for forming gaps in a material layer are provided. The equipment includes a supporter and an etching device. The supporter is configured to support a semiconductor device. In the method for forming gaps in a material layer, at first, the semiconductor device is provided. Then, a material layer of the semiconductor device is etched to form vertical gaps in the material layer. Thereafter, the vertical sidewall of each of the vertical gaps is etched in accordance with a predetermined gap profile by using directional charged particle beams. The directional charged particle beams are provided by the etching device, and each of the directional charged particle beams has two energy peaks.

Abstract: A semiconductor device and a method of forming the same, the semiconductor includes a substrate and a material disposed on the substrate. The material layer includes plural first patterns arranged parallel and separately in an array within a first region of the substrate, and plural second patterns parallel and separately disposed at two opposite sides of the first patterns, and plural third patterns parallel and separately disposed at another two opposite sides of the first patterns, wherein each of the third patterns has a relative greater dimension than that of each of the first patterns.

Abstract: A method of forming a semiconductor device includes removing a dummy gate from over a semiconductor fin; depositing a glue layer and a fill metal over the semiconductor fin; and simultaneously etching the glue layer and the fill metal with a wet etching solution, the wet etching solution etching the glue layer at a faster rate than the fill metal and reshaping the fill metal.

Abstract: A display device includes a substrate having flexibility, a transistor having a gate insulating film and further having a semiconductor layer and a gate electrode that sandwich the gate insulating film, the transistor formed in an area where the substrate is bent, and a gate wiring line so formed on the substrate as to be connected to the gate electrode, and the gate electrode has an area that is present in an area where the gate electrode overlaps with the semiconductor layer and is thinner than at least part of the gate wiring line.

Abstract: Fabrication method and semiconductor device are provided. The method includes: providing a base substrate including a first region and a second region adjacent to the first region, with first fins disposed on the base substrate in the first region and on the base substrate in the second region, and initial openings disposed between adjacent first fins; forming sidewall spacers on sidewalls of the first fins to form openings from the initial openings; and forming the second fins in the openings of the second region.

Abstract: Systems and methods for processing a workpiece are provided. In one example, a method includes placing a workpiece on a workpiece support in a processing chamber. The method includes performing a spacer treatment process to expose the workpiece to species generated from a first process gas in a first plasma to perform a spacer treatment process on a spacer layer on the workpiece. The first plasma can be generated in the processing chamber. After performing the spacer treatment process, the method can include performing a spacer etch process to expose the workpiece to neutral radicals generated from a second process gas in a second plasma to etch at least a portion of the spacer layer on the workpiece. The second plasma can be generated in a plasma chamber that is remote from the processing chamber.

Abstract: A method for forming a semiconductor device includes forming a metal contact on a substrate, forming a first dielectric on the metal contact, forming a first opening in the first dielectric, and performing a wet etch on a bottom surface of the first opening through a first etch stop layer (ESL) over the metal contact. The wet etch forms a first recess in a top surface of the metal contact. An upper width of the first recess is smaller than a lower width of the first recess. A first conductive feature is formed in the first recess and the first opening.

Abstract: Methods of making blended, isoporous, asymmetric (graded) films (e.g. ultrafiltration membranes) comprising two or more chemically distinct block copolymers and blended, isoporous, asymmetric (graded) films (e.g. ultrafiltration membranes) comprising two or more chemically distinct block copolymers. The generation of blended membranes by mixing two chemically distinct block copolymers in the casting solution demonstrates a pathway to advanced asymmetric block copolymer derived films, which can be used as ultrafiltration membranes, in which different pore surface chemistries and associated functionalities can be integrated into a single membrane via standard membrane fabrication, i.e. without requiring laborious post-fabrication modification steps. The block copolymers may be diblock, triblock and/or multiblock mixes and some block copolymers in the mix may be functionally modified. Triblock copolymers comprising a reactive group (e.g.

Abstract: Methods and apparatuses for reducing roughness using integrated atomic layer deposition (ALD) and etch processes are described herein. In some implementations, after a mask is provided on a substrate, methods include depositing a conformal layer on the mask by ALD to reduce roughness and etching a layer underlying the mask to form patterned features having a reduced roughness. In some implementations, after a substrate is etched to a first depth to form features at the first depth in the substrate, methods include depositing a conformal layer by ALD on sidewalls of the features to protect sidewalls and reduce roughness during a subsequent etch process. The ALD and etch processes may be performed in a plasma chamber.

Abstract: Methods of forming fins include masking a region on a three-color hardmask fin pattern, leaving a fin of a first color exposed. The exposed fin of the first color is etched away with a selective etch that does not remove fins of a second color or a third color. The mask and all fins of a second color are etched away. Fins are etched into a fin base layer using the fins of the first color and the fins of the third color.

Abstract: A substrate processing method includes a first processing step of processing a substrate using phosphoric acid set to a first temperature in a processing tank, and a second processing step of processing the substrate using phosphoric acid set to a second temperature in the processing tank.

Abstract: Etching gases are disclosed for plasma etching channel holes, gate trenches, staircase contacts, capacitor holes, contact holes, etc., in Si-containing layers on a substrate and plasma etching methods of using the same. The etching gases are trans-1,1,1,4,4,4-hexafluoro-2-butene; cis-1,1,1,4,4,4-hexafluoro-2-butene; hexafluoroisobutene; hexafluorocyclobutane (trans-1,1,2,2,3,4); pentafluorocyclobutane (1,1,2,2,3-); tetrafluorocyclobutane (1,1,2,2-); or hexafluorocyclobutane (cis-1,1,2,2,3,4). The etching gases may provide improved selectivity between the Si-containing layers and mask material, less damage to channel region, a straight vertical profile, and reduced bowing in pattern high aspect ratio structures.

Abstract: The present disclosure provides a method that includes coating an edge portion of a wafer by a first chemical solution including a chemical mixture of an acid-labile group, a solubility control unit and a thermal acid generator; curing the first chemical solution to form a first protecting layer on the edge portion of the wafer; coating a resist layer on a front surface of the wafer; removing the first protecting layer by a first removing solution; and performing an exposing process to the resist layer.

Abstract: Disclosed is a manufacturing method of a thin film transistor, comprising: sequentially preparing a gate, a gate insulation layer and an active layer on the substrate; preparing an etching stopper layer on the active layer; depositing an ohmic contact layer film on the etching stopper layer and the active layer, and depositing a source drain conductive film on the ohmic contact layer film; processing the source drain conductive film to form a source and a drain, which are patterned, and processing the ohmic contact layer film by a dry etching process to form an ohmic contact layer, which is patterned; removing the etching stopper layer after preparing the ohmic contact layer. Since the etching stopper layer is disposed above the channel of the transistor before preparing the ohmic contact layer, the damage to the active layer by dry etching can be effectively avoided to improve the performance of the transistor.

Abstract: The present disclosure provides resist rinse solutions and corresponding lithography techniques that achieve high pattern structural integrity for advanced technology nodes. An example lithography method includes forming a resist layer over a workpiece, exposing the resist layer to radiation, developing the exposed resist layer using a developer that removes an unexposed portion of the exposed resist layer, thereby forming a patterned resist layer, and rinsing the patterned resist layer using a rinse solution. The developer is an organic solution, and the rinse solution includes water.

Abstract: The disclosure relates to a microcircuit forming method. The microcircuit forming method according to the disclosure comprises: a seed-layer forming step for forming a high-reflectivity seed layer on a substrate material by using a conductive material; a pattern-layer forming step for forming a pattern layer on the seed layer, the pattern layer having a pattern hole arranged thereon to allow the seed layer to be selectively exposed therethrough; a plating step for filling the pattern hole with a conductive material; a pattern-layer removing step for removing the pattern layer; and a seed-layer patterning step for removing a part of the seed layer which does not overlap the conductive material in the plating step, wherein the high-reflectivity seed layer has a specular reflection property.

Abstract: A semiconductor structure and formation thereof. The semiconductor structure including: a nano-sheet field-effect transistor; a layer of support material that is located beneath a stack of nano-sheets that are included in the nano-sheet field-effect transistor; and a vertical support that is affixed to a stack of nano-sheets, wherein the vertical support (i) has an end that is affixed to the layer of support material and (ii) a side that is a affixed to at least one nano-sheet of the stack of nano-sheets.

Abstract: In an embodiment, in the method for processing a workpiece including an etching target layer containing silicon oxide, a mask provided on the etching target layer, and an opening provided in the mask and exposing the etching target layer, according to the embodiment, the etching target layer is etched by removing the etching target layer for each atomic layer through repetitive execution of a sequence of generating plasma of a first processing gas containing nitrogen, forming a mixed layer containing ions included in the plasma on an atomic layer on an exposed surface of the etching target layer, generating plasma of a second processing gas containing fluorine, and removing the mixed layer by radicals included in the plasma. The plasma of the second processing gas contains the radicals that remove the mixed layer containing silicon nitride.

Abstract: In the disclosed method, a mask is formed on a microstructure. The mask includes a first pattern positioned over a first region of the microstructure and a second pattern positioned over a second region of the microstructure. A first etching process is performed to etch the microstructure according to the first and second patterns formed in the mask. The first etching process transfers the first and second patterns of the mask into the first and second regions of the microstructure, respectively. A protective layer is subsequently formed over the first pattern of the mask that is positioned over the first region of the microstructure. When the protective layer is formed, a second etching process is performed to etch the microstructure and transfer the second pattern of the mask further into the second region of the microstructure. The method also includes removing the mask and the protective layer from the microstructure.

Abstract: A directional patterning method includes following steps. A substrate is provided with a mask layer thereon, and the mask layer has at least one opening pattern therein. A cyclic deposition and etching process is performed to increase a length of the at least one opening pattern.

Abstract: According to the invention there is provided a method of plasma etching a silicon-based compound semiconductor substrate, the method comprising providing the substrate within an etch chamber and performing a cyclical process on the substrate, each cycle comprising supplying an etchant gas into the chamber, energising the gas into a plasma, and performing an etch step on the substrate using the plasma; and performing a desorption step, wherein during the desorption step, the only gas that is supplied into the etch chamber is an inert gas, so as to allow reactive species that have adsorbed to the surface of the substrate during the etch step to desorb from the surface of the substrate.