Combined With Coating Step Patents (Class 438/694)
  • Patent number: 11443954
    Abstract: An apparatus and method process a substrate in a first session and a second session. In the first session, a hybrid gas application cycle is performed in a chamber that holds the substrate. A first gas is introduced for a first time period so components of the first gas adsorb onto the substrate. Subsequently, a second gas is introduced for a second time period so the second gas reacts with the components of the first gas to provide a protective layer on sidewalls of a pattern of the substrate, and the second gas etches a bottom portion of the pattern, a ratio of the first time period to the second time period being a use-ratio. Then, in a second session, the hybrid gas application cycle is repeated with a different use-ratio that corresponds with a vertical dimension of the pattern.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: September 13, 2022
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Takayuki Katsunuma
  • Patent number: 11443952
    Abstract: A method of selectively etching a silicon nitride film includes a first step of disposing a target substrate having the silicon nitride film formed thereon in a processing space, a second step of introducing a gas containing H and F into the processing space, and a third step of selectively introducing radicals of an inert gas into the processing space.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: September 13, 2022
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Akitaka Shimizu, Shuichiro Uda, Takeshi Saito, Taiki Kato
  • Patent number: 11424122
    Abstract: A mask pattern, a semiconductor structure and a method for forming the semiconductor structure are provided. The mask pattern includes a first mask pattern and a second mask pattern. The first mask pattern includes a plurality of first target patterns, and the plurality of first target patterns are arranged along a first direction. The second mask pattern includes a plurality of second target patterns, and the plurality of second target patterns are arranged along the first direction. When the first mask pattern overlaps the second mask pattern, one of the plurality of first target patterns partially overlaps a corresponding one of the plurality of second target patterns.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: August 23, 2022
    Assignees: Semiconductor Manufacturing International (Beijing) Corporation, Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Qiang Shu, Yingchun Zhang, Liusha Qin
  • Patent number: 11415913
    Abstract: An electrophotographic member comprises a base member and an elastic layer on the base member. The elastic layer contains a silicone rubber, an ionic electroconductive agent, and an inorganic particle, and the inorganic particle contains a hydroxide of at least one of magnesium or aluminum, and has a silicon atom on a surface thereof in an amount of 0.50 to 2.00 atomic %. An aqueous dispersion of which 5 mg of the inorganic particle is dispersed in 10 ml of water has a turbidity of 200 NTU or more and 1,240 NTU or less.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: August 16, 2022
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Naoko Kasai, Toshio Tanaka, Yasutomo Tsuji
  • Patent number: 11392035
    Abstract: [Subject] There is provided a gap filling composition which can reduce pattern collapse and a pattern forming method using the composition. [Solution means] There is provided a gap filling composition including a polymer having a certain structure and an organic solvent. There is provided a pattern forming method using a certain polymer.
    Type: Grant
    Filed: May 29, 2017
    Date of Patent: July 19, 2022
    Assignee: MERCK PATENT GMBH
    Inventors: Xiaowei Wang, Tatsuro Nagahara
  • Patent number: 11380556
    Abstract: Disclosed are apparatuses and methods for performing atomic layer etching. A method may include supporting and thermally floating a substrate in a processing chamber, modifying one or more surface layers of material on the substrate by chemical adsorption, without using a plasma, while the substrate is maintained at a first temperature, and removing the one or more modified surface layers by desorption, without using a plasma, while the substrate is maintained at a second temperature, the first temperature being different than the second temperature. An apparatus may include a processing chamber and support features configured to support and thermally float a substrate in the chamber, a process gas unit configured to flow a first process gas onto the substrate, a substrate heating unit configured to heat the substrate, and a substrate cooling unit configured to actively cool the substrate.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: July 5, 2022
    Assignee: Lam Research Corporation
    Inventors: Theodoros Panagopoulos, Andreas Fischer, Thorsten Lill
  • Patent number: 11380697
    Abstract: Embodiments provide raised pad formations for step contacts in three-dimensional structures formed on microelectronic workpieces. Steps are formed in a multilayer stack that is used for the three-dimensional structure. The multilayer stack includes alternating non-conductive and conductive layers. For one embodiment, alternating oxide and polysilicon layers are used. The steps expose contact regions on different conductive layers. Material layers are formed on the contact regions to form raised pads. The material layers preferably have a high selectivity with respect to the non-conductive material for etch processes. A protective layer is formed over the steps and the raised pads, and contact holes are formed through the protective layer to the raised pads. Contacts are then formed within the contact holes. The raised pads inhibit punch-through of the non-conductive layers during the forming of the contact holes thereby improving performance of resulting devices formed in the microelectronic workpieces.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: July 5, 2022
    Assignee: Tokyo Electron Limited
    Inventors: Soo Doo Chae, Sang Cheol Han, Youngwoo Park
  • Patent number: 11282735
    Abstract: An electrostatic chuck includes a support assembly including a base, a chuck placed at the base and configured to carry a workpiece, and a fastening assembly configured to removably fix the chuck at the base.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: March 22, 2022
    Assignee: BEIJING NAURA MICROELECTRONICS EQUIPMENT CO., LTD.
    Inventors: Quanyu Shi, Shuaitao Shi, Mengxin Zhao, Jinrong Zhao
  • Patent number: 11282712
    Abstract: A method for manufacturing a semiconductor device includes forming a first insulating film over a semiconductor substrate and forming a second insulating film on the first insulating film. The first insulating film is a tensile film having a first tensile stress and the second insulating film is either a tensile film having a second tensile stress that is less than the first tensile stress or a compressive film. The first insulating film and second insulating film are formed of a same material. A metal hard mask layer is formed on the second insulating film.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: March 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jung-Hau Shiu, Chung-Chi Ko, Tze-Liang Lee, Yu-Yun Peng
  • Patent number: 11264281
    Abstract: The present disclosure relates to a method for forming a semiconductor structure includes depositing a dielectric layer on a substrate and depositing a patterning layer on the dielectric layer. The method also includes performing a first etching process on the patterning layer to form a first region including a first plurality of blocks at a first pattern density and a second region including a second plurality of blocks at a second pattern density that is lower than the first pattern density. The method also includes performing a second etching process on the second plurality of blocks to decrease a width of each block of the second plurality of blocks and etching the dielectric layer and the substrate using the first and second pluralities of blocks to form a plurality of fin structures.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: March 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Lun Chen, Li-Te Lin, Chao-Hsien Huang
  • Patent number: 11248306
    Abstract: An anodic-oxidation equipment for forming a porous layer on a substrate to be treated, including: an electrolytic bath filled with an electrolytic solution; an anode and a cathode disposed in the electrolytic solution; and a power supply for applying current between the anode and the cathode in the electrolytic solution, wherein the anode is the substrate to be treated, and the cathode is a silicon substrate having a surface on which a nitride film is formed. This provides a cathode material in anodic-oxidation for forming porous silicon by an electrochemical reaction in an HF solution, the cathode material having a resistance to electrochemical reaction in an HF solution and no metallic contamination, etc., and furthermore, being less expensive than a conventional cathode material. Furthermore, high-quality porous silicon is provided at a lower cost than has been conventional.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: February 15, 2022
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Tsuyoshi Ohtsuki, Masaro Tamatsuka
  • Patent number: 11244829
    Abstract: A semiconductor device and a method of forming the same, the semiconductor includes a substrate and a material disposed on the substrate. The material layer includes plural first patterns arranged parallel and separately in an array within a first region of the substrate, and plural second patterns parallel and separately disposed at two opposite sides of the first patterns, and plural third patterns parallel and separately disposed at another two opposite sides of the first patterns, wherein each of the third patterns has a relative greater dimension than that of each of the first patterns.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: February 8, 2022
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Yu-Cheng Tung, Fu-Che Lee
  • Patent number: 11244856
    Abstract: A method and equipment for forming gaps in a material layer are provided. The equipment includes a supporter and an etching device. The supporter is configured to support a semiconductor device. In the method for forming gaps in a material layer, at first, the semiconductor device is provided. Then, a material layer of the semiconductor device is etched to form vertical gaps in the material layer. Thereafter, the vertical sidewall of each of the vertical gaps is etched in accordance with a predetermined gap profile by using directional charged particle beams. The directional charged particle beams are provided by the etching device, and each of the directional charged particle beams has two energy peaks.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: February 8, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chan-Syun David Yang, Li-Te Lin, Yu-Ming Lin
  • Patent number: 11227940
    Abstract: A method of forming a semiconductor device includes removing a dummy gate from over a semiconductor fin; depositing a glue layer and a fill metal over the semiconductor fin; and simultaneously etching the glue layer and the fill metal with a wet etching solution, the wet etching solution etching the glue layer at a faster rate than the fill metal and reshaping the fill metal.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: January 18, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jian-Jou Lian, Chun-Neng Lin, Ming-Hsi Yeh, Chieh-Wei Chen, Tzu-Ang Chiang
  • Patent number: 11217681
    Abstract: Fabrication method and semiconductor device are provided. The method includes: providing a base substrate including a first region and a second region adjacent to the first region, with first fins disposed on the base substrate in the first region and on the base substrate in the second region, and initial openings disposed between adjacent first fins; forming sidewall spacers on sidewalls of the first fins to form openings from the initial openings; and forming the second fins in the openings of the second region.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: January 4, 2022
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Nan Wang
  • Patent number: 11217646
    Abstract: A display device includes a substrate having flexibility, a transistor having a gate insulating film and further having a semiconductor layer and a gate electrode that sandwich the gate insulating film, the transistor formed in an area where the substrate is bent, and a gate wiring line so formed on the substrate as to be connected to the gate electrode, and the gate electrode has an area that is present in an area where the gate electrode overlaps with the semiconductor layer and is thinner than at least part of the gate wiring line.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: January 4, 2022
    Assignee: Japan Display Inc.
    Inventors: Yasukazu Kimura, Masato Hiramatsu, Takuma Nishinohara, Toshihiko Itoga
  • Patent number: 11195752
    Abstract: A method for forming a semiconductor device includes forming a metal contact on a substrate, forming a first dielectric on the metal contact, forming a first opening in the first dielectric, and performing a wet etch on a bottom surface of the first opening through a first etch stop layer (ESL) over the metal contact. The wet etch forms a first recess in a top surface of the metal contact. An upper width of the first recess is smaller than a lower width of the first recess. A first conductive feature is formed in the first recess and the first opening.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: December 7, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu Shih Wang, Kuo-Bin Huang, Ming-Hsi Yeh, Po-Nan Yeh
  • Patent number: 11195718
    Abstract: Systems and methods for processing a workpiece are provided. In one example, a method includes placing a workpiece on a workpiece support in a processing chamber. The method includes performing a spacer treatment process to expose the workpiece to species generated from a first process gas in a first plasma to perform a spacer treatment process on a spacer layer on the workpiece. The first plasma can be generated in the processing chamber. After performing the spacer treatment process, the method can include performing a spacer etch process to expose the workpiece to neutral radicals generated from a second process gas in a second plasma to etch at least a portion of the spacer layer on the workpiece. The second plasma can be generated in a plasma chamber that is remote from the processing chamber.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: December 7, 2021
    Assignees: Beijing E-Town Semiconductor Technology Co., Ltd., Mattson Technology, Inc.
    Inventors: Tsai Wen Sung, Chun Yan, Hua Chung, Michael X. Yang, Dixit V. Desai, Peter J. Lembesis
  • Patent number: 11180616
    Abstract: Methods of making blended, isoporous, asymmetric (graded) films (e.g. ultrafiltration membranes) comprising two or more chemically distinct block copolymers and blended, isoporous, asymmetric (graded) films (e.g. ultrafiltration membranes) comprising two or more chemically distinct block copolymers. The generation of blended membranes by mixing two chemically distinct block copolymers in the casting solution demonstrates a pathway to advanced asymmetric block copolymer derived films, which can be used as ultrafiltration membranes, in which different pore surface chemistries and associated functionalities can be integrated into a single membrane via standard membrane fabrication, i.e. without requiring laborious post-fabrication modification steps. The block copolymers may be diblock, triblock and/or multiblock mixes and some block copolymers in the mix may be functionally modified. Triblock copolymers comprising a reactive group (e.g.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: November 23, 2021
    Assignee: CORNELL UNIVERSITY
    Inventors: Ulrich B. Wiesner, Yuk Mun Li, Qi Zhang
  • Patent number: 11171002
    Abstract: Methods of forming fins include masking a region on a three-color hardmask fin pattern, leaving a fin of a first color exposed. The exposed fin of the first color is etched away with a selective etch that does not remove fins of a second color or a third color. The mask and all fins of a second color are etched away. Fins are etched into a fin base layer using the fins of the first color and the fins of the third color.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: November 9, 2021
    Assignee: Tessera, Inc.
    Inventors: John C. Arnold, Anuja E. DeSilva, Nelson M. Felix, Chi-Chun Liu, Yann A. M. Mignot, Stuart A. Sieg
  • Patent number: 11170997
    Abstract: Methods and apparatuses for reducing roughness using integrated atomic layer deposition (ALD) and etch processes are described herein. In some implementations, after a mask is provided on a substrate, methods include depositing a conformal layer on the mask by ALD to reduce roughness and etching a layer underlying the mask to form patterned features having a reduced roughness. In some implementations, after a substrate is etched to a first depth to form features at the first depth in the substrate, methods include depositing a conformal layer by ALD on sidewalls of the features to protect sidewalls and reduce roughness during a subsequent etch process. The ALD and etch processes may be performed in a plasma chamber.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: November 9, 2021
    Assignee: Lam Research Corporation
    Inventors: Xiang Zhou, Naveed Ansari, Yoshie Kimura, Si-Yi Yi Li, Kazi Sultana, Radhika Mani, Duming Zhang, Haseeb Kazi, Chen Xu, Mitchell Brooks, Ganesh Upadhyaya
  • Patent number: 11164750
    Abstract: A substrate processing method includes a first processing step of processing a substrate using phosphoric acid set to a first temperature in a processing tank, and a second processing step of processing the substrate using phosphoric acid set to a second temperature in the processing tank.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: November 2, 2021
    Assignee: SCREEN Holdings Co., Ltd.
    Inventors: Tomohiro Takahashi, Kei Takechi
  • Patent number: 11152223
    Abstract: Etching gases are disclosed for plasma etching channel holes, gate trenches, staircase contacts, capacitor holes, contact holes, etc., in Si-containing layers on a substrate and plasma etching methods of using the same. The etching gases are trans-1,1,1,4,4,4-hexafluoro-2-butene; cis-1,1,1,4,4,4-hexafluoro-2-butene; hexafluoroisobutene; hexafluorocyclobutane (trans-1,1,2,2,3,4); pentafluorocyclobutane (1,1,2,2,3-); tetrafluorocyclobutane (1,1,2,2-); or hexafluorocyclobutane (cis-1,1,2,2,3,4). The etching gases may provide improved selectivity between the Si-containing layers and mask material, less damage to channel region, a straight vertical profile, and reduced bowing in pattern high aspect ratio structures.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: October 19, 2021
    Assignee: American Air Liquide, Inc.
    Inventors: Curtis Anderson, Rahul Gupta, Vincent M. Omarjee, Nathan Stafford, Christian Dussarrat
  • Patent number: 11137685
    Abstract: The present disclosure provides a method that includes coating an edge portion of a wafer by a first chemical solution including a chemical mixture of an acid-labile group, a solubility control unit and a thermal acid generator; curing the first chemical solution to form a first protecting layer on the edge portion of the wafer; coating a resist layer on a front surface of the wafer; removing the first protecting layer by a first removing solution; and performing an exposing process to the resist layer.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: October 5, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: An-Ren Zi, Joy Cheng, Ching-Yu Chang, Chin-Hsiang Lin
  • Patent number: 11121228
    Abstract: Disclosed is a manufacturing method of a thin film transistor, comprising: sequentially preparing a gate, a gate insulation layer and an active layer on the substrate; preparing an etching stopper layer on the active layer; depositing an ohmic contact layer film on the etching stopper layer and the active layer, and depositing a source drain conductive film on the ohmic contact layer film; processing the source drain conductive film to form a source and a drain, which are patterned, and processing the ohmic contact layer film by a dry etching process to form an ohmic contact layer, which is patterned; removing the etching stopper layer after preparing the ohmic contact layer. Since the etching stopper layer is disposed above the channel of the transistor before preparing the ohmic contact layer, the damage to the active layer by dry etching can be effectively avoided to improve the performance of the transistor.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: September 14, 2021
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Huafei Xie
  • Patent number: 11106138
    Abstract: The present disclosure provides resist rinse solutions and corresponding lithography techniques that achieve high pattern structural integrity for advanced technology nodes. An example lithography method includes forming a resist layer over a workpiece, exposing the resist layer to radiation, developing the exposed resist layer using a developer that removes an unexposed portion of the exposed resist layer, thereby forming a patterned resist layer, and rinsing the patterned resist layer using a rinse solution. The developer is an organic solution, and the rinse solution includes water.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: August 31, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Wei Wang, Wei-Han Lai, Ching-Yu Chang
  • Patent number: 11089691
    Abstract: The disclosure relates to a microcircuit forming method. The microcircuit forming method according to the disclosure comprises: a seed-layer forming step for forming a high-reflectivity seed layer on a substrate material by using a conductive material; a pattern-layer forming step for forming a pattern layer on the seed layer, the pattern layer having a pattern hole arranged thereon to allow the seed layer to be selectively exposed therethrough; a plating step for filling the pattern hole with a conductive material; a pattern-layer removing step for removing the pattern layer; and a seed-layer patterning step for removing a part of the seed layer which does not overlap the conductive material in the plating step, wherein the high-reflectivity seed layer has a specular reflection property.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: August 10, 2021
    Assignee: InkTec Co., Ltd.
    Inventors: Su Han Kim, Kwang-Choon Chung, Jung Yoon Moon, Sung In Ha, Byung Woong Moon
  • Patent number: 11088288
    Abstract: A semiconductor structure and formation thereof. The semiconductor structure including: a nano-sheet field-effect transistor; a layer of support material that is located beneath a stack of nano-sheets that are included in the nano-sheet field-effect transistor; and a vertical support that is affixed to a stack of nano-sheets, wherein the vertical support (i) has an end that is affixed to the layer of support material and (ii) a side that is a affixed to at least one nano-sheet of the stack of nano-sheets.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: August 10, 2021
    Assignee: International Business Machines Corporation
    Inventors: Ruilong Xie, Jingyun Zhang, Xin Miao, Alexander Reznicek
  • Patent number: 11081360
    Abstract: In an embodiment, in the method for processing a workpiece including an etching target layer containing silicon oxide, a mask provided on the etching target layer, and an opening provided in the mask and exposing the etching target layer, according to the embodiment, the etching target layer is etched by removing the etching target layer for each atomic layer through repetitive execution of a sequence of generating plasma of a first processing gas containing nitrogen, forming a mixed layer containing ions included in the plasma on an atomic layer on an exposed surface of the etching target layer, generating plasma of a second processing gas containing fluorine, and removing the mixed layer by radicals included in the plasma. The plasma of the second processing gas contains the radicals that remove the mixed layer containing silicon nitride.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: August 3, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Masahiro Tabata, Toru Hisamatsu, Yoshihide Kihara, Masanobu Honda
  • Patent number: 11062913
    Abstract: In the disclosed method, a mask is formed on a microstructure. The mask includes a first pattern positioned over a first region of the microstructure and a second pattern positioned over a second region of the microstructure. A first etching process is performed to etch the microstructure according to the first and second patterns formed in the mask. The first etching process transfers the first and second patterns of the mask into the first and second regions of the microstructure, respectively. A protective layer is subsequently formed over the first pattern of the mask that is positioned over the first region of the microstructure. When the protective layer is formed, a second etching process is performed to etch the microstructure and transfer the second pattern of the mask further into the second region of the microstructure. The method also includes removing the mask and the protective layer from the microstructure.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: July 13, 2021
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Yu Qi Wang, Wenjie Zhang, Hong Guang Song, Lipeng Liu, Lianjuan Ren
  • Patent number: 11043381
    Abstract: A directional patterning method includes following steps. A substrate is provided with a mask layer thereon, and the mask layer has at least one opening pattern therein. A cyclic deposition and etching process is performed to increase a length of the at least one opening pattern.
    Type: Grant
    Filed: January 27, 2019
    Date of Patent: June 22, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Chin Chang, Li-Te Lin, Ru-Gun Liu, Wei-Liang Lin, Pinyen Lin, Yu-Tien Shen, Ya-Wen Yeh
  • Patent number: 11037793
    Abstract: According to the invention there is provided a method of plasma etching a silicon-based compound semiconductor substrate, the method comprising providing the substrate within an etch chamber and performing a cyclical process on the substrate, each cycle comprising supplying an etchant gas into the chamber, energising the gas into a plasma, and performing an etch step on the substrate using the plasma; and performing a desorption step, wherein during the desorption step, the only gas that is supplied into the etch chamber is an inert gas, so as to allow reactive species that have adsorbed to the surface of the substrate during the etch step to desorb from the surface of the substrate.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: June 15, 2021
    Assignee: SPTS Technologies Limited
    Inventors: Huma Ashraf, Kevin Riddell, Alex Wood
  • Patent number: 11022878
    Abstract: The present disclosure describes a method for improving post-photolithography critical dimension (CD) uniformity for features printed on a photoresist. A layer can be formed on one or more printed features and subsequently etched to improve overall CD uniformity across the features. For example the method includes a material layer disposed over a substrate and a photoresist over the material layer. The photoresist is patterned to form a first feature with a first critical dimension (CD) and a second feature with a second CD that is larger than the first CD. Further, a layer is formed with one or more deposition/etch cycles in the second feature to form a modified second CD that is nominally equal to the first CD.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: June 1, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co.. Ltd.
    Inventors: Xi-Zong Chen, Cha-Hsin Chao, Yi-Wei Chiu, Li-Te Hsu, Chih-Hsuan Lin
  • Patent number: 11024798
    Abstract: A magnetic device for magnetic random access memory (MRAM), spin torque MRAM, or spin torque oscillator technology is disclosed wherein a magnetic tunnel junction (MTJ) with a sidewall is formed between a bottom electrode and a top electrode. A passivation layer that is a single layer or multilayer comprising one of B, C, or Ge, or an alloy thereof wherein the B, C, and Ge content, respectively, is at least 10 atomic % is formed on the MTJ sidewall to protect the MTJ from reactive species during subsequent processing including deposition of a dielectric layer that electrically isolates the MTJ from adjacent MTJs, and during annealing steps around 400° C. in CMOS fabrication. The single layer is about 3 to 10 Angstroms thick and may be an oxide or nitride of B, C, or Ge. The passivation layer is preferably amorphous to prevent diffusion of reactive oxygen or nitrogen species.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: June 1, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jodi Mari Iwata, Guenole Jan, Ru-Ying Tong
  • Patent number: 11011388
    Abstract: Methods and apparatus for laterally etching unwanted material from the sidewalls of a recessed feature are described herein. In various embodiments, the method involves etching a portion of the sidewalls, depositing a protective film over a portion of the sidewalls, and cycling the etching and deposition operations until the unwanted material is removed from the entire depth of the recessed feature. Each etching and deposition operation may target a particular depth along the sidewalls of the feature. In some cases, the unwanted material is removed from the bottom of the feature up, and in other cases the unwanted material is removed from the top of the feature down. Some combination of these may also be used.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: May 18, 2021
    Assignee: Lam Research Corporation
    Inventors: Kwame Eason, Pilyeon Park, Mark Naoshi Kawaguchi, Seung-Ho Park, Hsiao-Wei Chang
  • Patent number: 11011525
    Abstract: Provided is a landing pad structure including a substrate, a plurality of landing pads, a guard ring, and an edge pattern. The substrate includes a cell region, a periphery region, and a guard ring region located between the cell region and the periphery region. The landing pads are arranged on the substrate in the cell region in a hexagonal close packing (HCP) configuration. The guard ring is disposed on the substrate in the guard ring region in a strip form. The edge pattern is disposed on the substrate in the cell region and close to the guard ring region. A method of manufacturing the landing pad structure is also provided.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: May 18, 2021
    Assignee: Winbond Electronics Corp.
    Inventors: Keng-Ping Lin, Tetsuharu Kurokawa, Tzu-Ming Ou Yang, Shu-Ming Li
  • Patent number: 10998192
    Abstract: A method includes depositing a resist layer onto a hard mask layer to form a multi-layer patterning material film stack on a semiconductor substrate, directing patterning radiation onto the film stack to form a developed pattern in the resist layer and exposing the film stack to at least one gas precursor in connection with a sequential infiltration synthesis process. The film stack is configured to facilitate selective infiltration of the at least one gas precursor into the resist layer.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: May 4, 2021
    Assignee: International Business Machines Corporation
    Inventors: Ekmini Anuja De Silva, Jing Guo, Luciana Meli, Nelson Felix
  • Patent number: 10989843
    Abstract: Provided are a transparent electrode-attached complex which includes a base material, a transparent electrode pattern, an optical adjustment member, and a transparent protective layer in this order, in which the optical adjustment member has at least one layer of low-refractive index layers that are odd-numbered layers from a transparent electrode pattern side and at least one layer of high-refractive index layers that are even-numbered layers from the transparent electrode pattern side, a difference in refractive index between the low-refractive index layer and the high-refractive index layer that are directly adjacent to each other is 0.05 or more, a refractive index of the high-refractive index layer is 2.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: April 27, 2021
    Assignee: FUJIFILM Corporation
    Inventor: Kentaro Toyooka
  • Patent number: 10975468
    Abstract: There is provided a cleaning method for removing a first deposit, formed on an upper electrode through an etching of a metal layer containing a metal, by using a plasma generated between a lower electrode of a lower structure and the upper electrode in a processing chamber of a plasma processing apparatus. The method includes a step of colliding ions with the first deposit formed on the upper electrode and a step of removing a second deposit, which is generated by said colliding and formed on the lower structure. Further, a cycle including the step of colliding and the step of removing is repeated multiple times.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: April 13, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Hiroki Kishi, Mitsuru Hashimoto, Keiichi Shimoda, Eiichi Nishimura, Akitaka Shimizu
  • Patent number: 10950432
    Abstract: Provided is a method of depositing a thin film on a pattern structure of a semiconductor substrate, the method including (a) supplying a source gas; (b) supplying a reactive gas; and (c) supplying plasma, wherein the steps (a), (b), and (c) are sequentially repeated on the semiconductor substrate within a reaction space until a desired thickness is obtained, and a frequency of the plasma is a high frequency of 60 MHz or greater.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: March 16, 2021
    Assignee: ASM IP Holding B.V.
    Inventors: Young Hoon Kim, Yong Gyu Han, Dae Youn Kim, Tae Hee Yoo, Wan Gyu Lim, Jin Geun Yu
  • Patent number: 10930505
    Abstract: The present disclosure provides a method of patterning a target material layer over a semiconductor substrate. The method includes steps of forming a spacer feature over the target material layer using a first sub-layout and performing a photolithographic patterning process using a second sub-layout to form a first feature. A portion of the first feature extends over the spacer feature. The method further includes steps of removing the portion of the first feature extending over the spacer feature and removing the spacer feature. Other methods and associated patterned semiconductor wafers are also provided herein.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: February 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsong-Hua Ou, Ken-Hsien Hsieh, Shih-Ming Chang, Wen-Chun Huang, Chih-Ming Lai, Ru-Gun Liu, Tsai-Sheng Gau
  • Patent number: 10910381
    Abstract: Apparatuses and methods to provide a patterned substrate are described. A plurality of patterned and spaced first lines and carbon material lines and formed on the substrate surface by selectively depositing and etching films extending in a first direction and films extending in a second direction that crosses the first direction to pattern the underlying structures.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: February 2, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Tejinder Singh, Takehito Koshizawa, Abhijit Basu Mallick, Pramit Manna, Nancy Fung, Eswaranand Venkatasubramanian, Ho-yung David Hwang, Samuel E. Gottheim
  • Patent number: 10910220
    Abstract: A method for flatly covering a semiconductor substrate using a silicon-containing composition. A method for producing a polysiloxane-coated substrate, including a first step for forming a first polysiloxane coating film by applying a first polysiloxane composition for coating to a stepped substrate and firing the composition thereon and a second step for forming a second film by applying a second polysiloxane composition for coating to the first film and firing the composition thereon. The second film has an Iso-dense bias of 50 nm or less; the first polysiloxane contains a hydrolysis-condensation product of a hydrolyzable silane starting material containing a first hydrolyzable silane having four hydrolyzable groups in each molecule at a ratio of 0-100% by mole in all the silanes; and the second polysiloxane contains silanol groups at a ratio of 30% by mole or less relative to Si atoms, while having a weight average molecular weight of 1,000-50,000.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: February 2, 2021
    Assignee: NISSAN CHEMICAL CORPORATION
    Inventors: Shuhei Shigaki, Hiroaki Yaguchi, Makoto Nakajima
  • Patent number: 10910466
    Abstract: A method of forming an integrated circuit structure includes forming a first magnetic layer, forming a first conductive line over the first magnetic layer, and coating a photo-sensitive coating on the first magnetic layer. The photo-sensitive coating includes a first portion directly over the first conductive line, and a second portion offset from the first conductive line. The first portion is joined to the second portion. The method further includes performing a first light-exposure on the first portion of the photo-sensitive coating, performing a second light-exposure on both the first portion and the second portion of the photo-sensitive coating, developing the photo-sensitive coating, and forming a second magnetic layer over the photo-sensitive coating.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: February 2, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun Kai Tzeng, Cheng Jen Lin, Yung-Ching Chao, Ming-Da Cheng, Mirng-Ji Lii
  • Patent number: 10901321
    Abstract: Processes for removing a mask layer (e.g., doped amorphous carbon mask layer) from a substrate with high aspect ratio structures are provided. In one example implementation, a process can include depositing a polymer layer on at least a portion of a top end of a high aspect ratio structure on a substrate. The process can further include removing at least a portion of the polymer layer and the doped amorphous carbon film form the substrate using a plasma strip process. In example embodiments, depositing a polymer layer can include plugging one or more high aspect ratio structures with the polymer layer. In example embodiments, depositing a polymer layer can include forming a polymer layer on a sidewall of one or more high aspect ratio structures.
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: January 26, 2021
    Assignees: Mattson Technology, Inc., Beijing E-Town Semiconductor Technology Co., Ltd.
    Inventors: Vijay M. Vaniapura, Shawming Ma, Li Hou
  • Patent number: 10872779
    Abstract: An plasma etching method for etching a film layer includes a plurality of times repeating a step set including a first step of introducing a gas containing hydrogen fluoride into a processing chamber and supplying hydrogen fluoride molecules to the surface of an oxide film, a second step of exhausting the interior of the processing chamber in vacuum to remove the hydrogen fluoride, and a third step of introducing a gas containing hydrogen nitride into the processing chamber and supplying hydrogen nitride to the surface of the oxide film to form a compound layer containing nitrogen, hydrogen, and fluorine on the surface of the film layer, and removing the compound layer formed on the surface of the film layer. Foreign object contamination is prevented by inhibiting mixing of hydrogen fluoride gas and hydrogen nitride gas, and the etching amount is controlled by the number of times of repeating application thereof.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: December 22, 2020
    Assignee: HITACHI HIGH-TECH CORPORATION
    Inventors: Nobuya Miyoshi, Hiroyuki Kobayashi, Kazunori Shinoda, Kohei Kawamura, Kazumasa Ookuma, Yutaka Kouzuma, Masaru Izawa
  • Patent number: 10868238
    Abstract: Certain aspects of the present disclosure provide techniques for fabricating an integrated circuit with a magnetic tunnel junction (MTJ) without a patterning process for the MTJ. An example method generally includes depositing a first diffusion barrier layer above an oxide layer having a conductive pillar therein, forming a first trench in the first diffusion barrier layer above the conductive pillar, depositing a first electrode in the first trench such that the first electrode is coupled to the conductive pillar, removing the oxide layer and the first diffusion barrier layer to expose the conductive pillar and the first electrode, and depositing an MTJ above the first electrode according to a shape of the first electrode.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: December 15, 2020
    Assignee: Qualcomm Incorporated
    Inventors: Xia Li, Wei-Chuan Chen, Seung Hyuk Kang
  • Patent number: 10840129
    Abstract: In an embodiment, a method includes: forming a first dielectric layer over a die, the first dielectric layer including a photo-sensitive material; curing the first dielectric layer to reduce photo-sensitivity of the first dielectric layer; patterning the first dielectric layer by etching to form a first opening; forming a first metallization pattern in the first opening of the first dielectric layer; forming a second dielectric layer over the first metallization pattern and the first dielectric layer, the second dielectric layer including the photo-sensitive material; patterning the second dielectric layer by exposure and development to form a second opening; and forming a second metallization pattern in the second opening of the second dielectric layer, the second metallization pattern electrically connected to the first metallization pattern.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: November 17, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Jui Kuo, Yun Chen Hsieh, Hui-Jung Tsai
  • Patent number: 10796935
    Abstract: An electronic device manufacturing system may include a loadlock. The loadlock may include a plurality of gas line heaters for providing a heated gas to the loadlock to heat a processed substrate therein. Heating a processed substrate may reduce corrosion in the loadlock and subsequent contamination of substrates therein. The loadlock may also include a plurality of embedded heaters in the loadlock housing to reduce moisture therein, further reducing corrosion and contamination. Methods of heating a substrate in a loadlock are also provided, as are other aspects.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: October 6, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Adam J. Wyatt, Edward Ng, Andrew Nguyen
  • Patent number: 10790362
    Abstract: The present disclosure provides a semiconductor structure, including providing a metal layer, an adhesion-enhancing layer over the metal layer, a dielectric stack over the adhesion-enhancing layer, a contact penetrating the dielectric stack and the adhesion-enhancing layer and connecting with the metal layer, a barrier layer disposed between the contact and the dielectric stack, and a high-k dielectric layer disposed between the contact and the barrier layer.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: September 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yao-Wen Chang, Gung-Pei Chang, Ching-Sheng Chu, Chern-Yow Hsu