Utilizing Multilayered Mask Patents (Class 438/736)
  • Patent number: 10147608
    Abstract: A method for preparing a patterned target layer is provided. A target layer is formed over a substrate. A multi-layered hard mask layer is formed over the target layer. The multi-layered hard mask layer includes a first hard mask layer over the target layer, a second hard mask layer between the target layer and the first hard mask layer, and a third hard mask layer between the target layer and the second hard mask layer, wherein a material of the second hard mask layer is different from a material of the first hard mask layer and a material of the third hard mask layer. The multi-layered hard mask layer is used as a hard mask layer to prepare a fine pattern on the target layer.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: December 4, 2018
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Shing-Yih Shih, Chih-Wei Cheng, Ming-Tsung Ko
  • Patent number: 10048418
    Abstract: A method of manufacturing a polarizer includes forming a first layer on a base substrate, forming a first partition wall layer on the first layer, forming a second partition wall layer on the first partition wall, forming a plurality of first partition wall patterns and a plurality of second partition walls disposed on the first partition wall patterns by etching the first partition wall and the second partition wall at the same time, forming a block copolymer layer on the first layer on which the plurality of first partition wall patterns are formed, forming a plurality of fine patterns from the block copolymer layer, and patterning the first layer using the fine patterns and the second partition wall patterns as a mask.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: August 14, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sung-Won Cho, Jung-Ha Son, Su-Bin Bae, Yun-Jong Yeo, Joo-Hyung Lee
  • Patent number: 10032639
    Abstract: Exemplary methods of patterning a device layer are described, including operations of patterning a protector layer and forming a first opening in a first patterning layer to expose a first portion of the protector layer and a first portion of the hard mask layer, which are then are exposed to a first etch to form a first opening in the first portion of the hard mask layer. A second opening is formed in a second patterning layer to expose a second portion of the protector layer and a second portion of the hard mask layer. The second portion of the protector layer and the second portion of the hard mask layer are exposed to an etch to form a second opening in the second portion of the hard mask layer. Exposed portions of the device layer are then etched through the first opening and the second opening.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: July 24, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Cheng Hung, Chun-Kuang Chen, De-Fang Chen, Wei-Liang Lin, Yu-Tien Shen
  • Patent number: 9431291
    Abstract: According to an embodiment, a method for manufacturing a semiconductor device includes transferring a continuous second layer, forming a third layer, and removing the second layer. The second layer is transferred onto a first layer. The first layer has a first opening. The second layer covers the first opening to form a first air gap. The third layer is formed on the first layer. The third layer has a second opening. The second opening is positioned on the first air gap. The second layer is removed through the second opening.
    Type: Grant
    Filed: April 22, 2015
    Date of Patent: August 30, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Keisuke Nakazawa
  • Patent number: 9406614
    Abstract: A method of fabricating a semiconductor device comprises forming a first dielectric material layer on a semiconductor substrate. The first dielectric material layer is patterned to form a plurality of vias therein. A metal layer is formed on the first dielectric material layer, wherein the metal layer fills the plurality of vias. The metal layer is etched such that portions of the metal layer above the first dielectric material layer are patterned to form a plurality of metal features aligned with the plurality of vias respectively. A self-assembled monolayer film is formed on surfaces of the plurality of metal features.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: August 2, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Min Huang, Chung-Ju Lee
  • Patent number: 9368362
    Abstract: Methods of forming a semiconductor device are provided. A method of forming a semiconductor device may include forming a capping layer on a metal pattern and on an adjacent portion of an insulating layer, the capping layer comprising a first etch selectivity, with respect to the insulating layer, on the metal pattern and a second etch selectivity, with respect to the insulating layer, on the portion of the insulating layer. Moreover, the method may include forming a recess region adjacent the metal pattern by removing the capping layer from the portion of the insulating layer. At least a portion of the capping layer may remain on an uppermost surface of the metal pattern after removing the capping layer from the portion of the insulating layer. Related semiconductor devices are also provided.
    Type: Grant
    Filed: May 22, 2014
    Date of Patent: June 14, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sangho Rha, Jongmin Baek, Wookyung You, Sanghoon Ahn, Nae-In Lee
  • Patent number: 9312204
    Abstract: An integrated circuit and a method of forming an integrated circuit including a first dielectric layer including a surface, a plurality of first trenches defined in the dielectric layer surface, and a plurality of first wires, wherein each of the first wires are formed in each of the first trenches. The integrated circuit also includes a plurality of second trenches defined in the dielectric layer surface, and a plurality of second wires, wherein each of the second wires are formed in each of the second trenches. Further, the first wires comprise a first material having a first bulk resistivity and the second wires comprise a second material having a second bulk resistivity, wherein the first bulk resistivity and the second bulk resistivity are different.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: April 12, 2016
    Assignee: Intel Corporation
    Inventors: James S. Clarke, Anthony C. Schmitz, Richard E. Schenker
  • Patent number: 9287175
    Abstract: A fabrication method for dicing semiconductor wafers using laser cutting techniques, which can effectively prevent the devices on semiconductor die units from the phenomenon of etching undercut caused by the sequential steps after laser cutting, comprises following steps: covering the wafer surface with a protection layer; dicing the wafer by laser and separating the die units from each other; removing the laser cutting residues on the devices on the die units via wet etching by an acidic water solution; removing the protection layer by a non-acidic water solution and cleaning the devices on the die units. The selection of materials for the protection layer must consider the following factors: where (1) the materials for the protection layer must have relatively good properties for adhering and covering on the wafer; (2) the materials for the protection layer must be corrosion-resistant to the acidic water solution for etching residues.
    Type: Grant
    Filed: January 3, 2014
    Date of Patent: March 15, 2016
    Assignee: WIN SEMICONDUCTORS CORP.
    Inventors: Chang-Huang Hua, Ping Wei Chen, Kevin Huang, Benny Ho, Chen-Che Chin
  • Patent number: 9240346
    Abstract: Self-aligned double patterning methods that can be used in back-end-of-line (BEOL) processing and other stages of integrate circuit device manufacturing. In these methods, line termini are masked prior to self-aligned double patterning. The self-aligned double patterning involves forming a mandrel, the shape of which is determined by a lithographic mask. That same lithographic mask is used prior to self-aligned double patterning to trim the mask that determines the locations of line termini. The methods provide precise positioning of the line termini mask relative to the line locations determined by self-aligned double patterning. The methods forms consistent end-of-line shapes and allow line termini to be placed more closely together than would otherwise be feasible.
    Type: Grant
    Filed: June 18, 2013
    Date of Patent: January 19, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Ying Lee, Jyu-Horng Shieh
  • Patent number: 9117654
    Abstract: A method of fabricating an integrated circuit device includes forming first and second mask structures on respective first and second regions of a feature layer. Each of the first and second mask structures includes a dual mask pattern and an etch mask pattern thereon having an etch selectivity relative to the dual mask pattern. The etch mask patterns of the first and second mask structures are etched to partially remove the etch mask pattern from the second mask structure. Spacers are formed on opposing sidewalls of the first and second mask structures. The first mask structure is selectively removed from between the spacers in the first region to define a first mask pattern including the opposing sidewall spacers with a void therebetween in the first region, and a second mask pattern including the opposing sidewall spacers with the second mask structure therebetween in the second region.
    Type: Grant
    Filed: May 14, 2012
    Date of Patent: August 25, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Ho Lee, Jae-Kwan Park, Jae-Hwang Sim, Sang-Yong Park
  • Patent number: 9105699
    Abstract: The invention concerns a method comprising: forming a plurality of parallel lines (502, 504, 506) of a sacrificial material over a layer of conductive material (510) of an integrated circuit, said parallel lines being separated by trenches, at least one of said lines being interrupted along its length by an opening (516) dividing it into first and second line portions (504A, 504B) separated by a space (S); forming spacers (522, 524, 526, 528, 530) in said trenches on lateral sides of said line portions and filling at least a bottom part of said opening between the line portions; removing the sacrificial material by etching; and forming interconnection lines (302, 304A, 304B, 306A, 306B, 308, 310) of said conductive material based on a pattern defined by said spacers.
    Type: Grant
    Filed: January 29, 2014
    Date of Patent: August 11, 2015
    Assignee: STMICROELECTRONICS (CROLLES 2) SAS
    Inventor: Vincent Farys
  • Patent number: 9040428
    Abstract: Hemispheres and spheres are formed and employed for a plurality of applications. Hemispheres are employed to form a substrate having an upper surface and a lower surface. The upper surface includes peaks of pillars which have a base attached to the lower surface. The peaks have a density defined at the upper surface by an array of hemispherical metal structures that act as a mask during an etch to remove substrate material down to the lower surface during formation of the pillars. The pillars are dense and uniform and include a microscale average diameter. The spheres are formed as independent metal spheres or nanoparticles for other applications.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: May 26, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Augustin J. Hong, Woo-Shik Jung, Jeehwan Kim, Jae-Woong Nahum, Devendra K. Sadana
  • Patent number: 9040423
    Abstract: A method for manufacturing a semiconductor device is provided. A substrate having a first area with a first poly layer and a second area with a second poly layer is provided. A nitride HM film is then deposited above the first poly layer of a first device in the first area and above the second poly layer in the second area. Afterwards, a first patterned passivation is formed on the nitride HM film in the first area to cover the nitride HM film and the first device, and a second patterned passivation is formed above the second poly layer in the second area. The second poly layer in the second area is defined by the second patterned passivation.
    Type: Grant
    Filed: July 17, 2013
    Date of Patent: May 26, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wan-Fang Chung, Ping-Chia Shih, Hsiang-Chen Lee, Che-Hao Chang, Jhih-Long Lin, Wei-Pin Huang, Shao-Nung Huang, Yu-Cheng Wang, Jaw-Jiun Tu, Chung-Che Huang
  • Patent number: 9034762
    Abstract: A triple patterning method is provided. The method includes providing a substrate having a first region and a second region; and forming a first material layer. The method also includes forming a second material layer; and forming a plurality of core patterns on the second material layer in the first region. Further, the method includes forming sidewall spacers on side surfaces of the core patterns; and forming first patterns on the first material layer. Further, the method includes forming a third material layer on the first material layer and the first patterns; and forming second patterns on the third material layer in the first region and third patterns on the third material layer in the second region. Further, the method also includes forming fourth patterns; and forming triple patterns on the substrate in the first region and fifth patterns on the substrate in the second region.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: May 19, 2015
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Zhongshan Hong
  • Patent number: 9034748
    Abstract: Embodiments include a method comprising depositing a hard mask layer over a first layer, the hard mask layer including; lower hard mask layer, hard mask stop layer, and upper hard mask. The hard mask layer and the first layer are patterned and a spacer deposited on the patterned sidewall. The upper hard mask layer and top portion of the spacer are removed by selective etching with respect to the hard mask stop layer, the remaining spacer material extending to a first predetermined position on the sidewall. The hard mask stop layer is removed by selective etching with respect to the lower hard mask layer and spacer. The first hard mask layer and top portion of the spacer are removed by selectively etching the lower hard mask layer and the spacer with respect to the first layer, the remaining spacer material extending to a second predetermined position on the sidewall.
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: May 19, 2015
    Assignee: International Business Machines Corporation
    Inventors: Christopher V. Baiocco, Kevin K. Chan, Young-Hee Kim, Masaharu Kobayashi, Effendi Leobandung, Fei Liu, Dae-Gyu Park, Helen Wang, Xinhui Wang, Min Yang
  • Patent number: 9017564
    Abstract: A plasma etching method performs plasma etching on a sample, which has laminated films containing a variable layer of a magnetic film, a barrier layer of an insulating material, and a fixed layer of a magnetic film, using a hard mask, which includes at least one of a Ta film and a TiN film. The plasma etching method includes a first step of etching the laminated films using N2 gas; and a second step of etching the laminated films after the first step using mixed gas of N2 gas and gas containing carbon elements.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: April 28, 2015
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Atsushi Yoshida, Naohiro Yamamoto, Makoto Suyama, Kentaro Yamada, Daisuke Fujita
  • Patent number: 9018103
    Abstract: A method for etching features in a stack is provided. A combination hardmask is formed by forming a first hardmask layer comprising carbon or silicon oxide over the stack, forming a second hardmask layer comprising metal over the first hardmask layer, and patterning the first and second hardmask layers. The stack is etched through the combination hardmask.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: April 28, 2015
    Assignee: Lam Research Corporation
    Inventors: Joydeep Guha, Sirish K. Reddy, Kaushik Chattopadhyay, Thomas W. Mountsier, Aaron Eppler, Thorsten Lill, Vahid Vahedi, Harmeet Singh
  • Patent number: 8999848
    Abstract: A method of forming a fine pattern of a semiconductor device using double SPT process, which is capable of implementing a line and space pattern having a uniform fine line width by applying a double SPT process including a negative SPT process, is provided. The method includes a first SPT process and a second SPT process and the second SPT process includes a Negative SPT process.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: April 7, 2015
    Assignee: SK hynix Inc.
    Inventors: Ki Lyoung Lee, Cheol Kyu Bok, Won Kyu Kim
  • Patent number: 8992792
    Abstract: Methods of fabricating ultra low-k dielectric self-aligned vias are described. In an example, a method of forming a self-aligned via (SAV) in a low-k dielectric film includes forming a trench pattern in a metal nitride hardmask layer formed above a low-k dielectric film formed above a substrate. A via pattern is formed in a masking layer formed above the metal nitride hardmask layer. The via pattern is etched at least partially into the low-k dielectric film, the etching comprising using a plasma etch using a chemistry based on CF4, H2, and a diluent inert gas composition.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: March 31, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Chih-Yang Chang, Sean S. Kang, Chia-Ling Kao, Nikolaos Bekiaris
  • Patent number: 8986921
    Abstract: A lithographic material stack including a metal-compound hard mask layer is provided. The lithographic material stack includes a lower organic planarizing layer (OPL), a dielectric hard mask layer, and the metal-compound hard mask layer, an upper OPL, an optional anti-reflective coating (ARC) layer, and a photoresist layer. The metal-compound hard mask layer does not attenuate optical signals from lithographic alignment marks in underlying material layers, and can facilitate alignment between different levels in semiconductor manufacturing.
    Type: Grant
    Filed: January 15, 2013
    Date of Patent: March 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Daniel C. Edelstein, Bryan G. Morris, Tuan A. Vo, Christopher J. Waskiewicz, Yunpeng Yin
  • Patent number: 8980753
    Abstract: A method for fabricating a metal gate transistor is disclosed. The method includes the steps of: providing a substrate having a first transistor region and a second transistor region; forming a first metal-oxide semiconductor (MOS) transistor on the first transistor region and a second MOS transistor on the second transistor region, in which the first MOS transistor includes a first dummy gate and the second MOS transistor comprises a second dummy gate; forming a patterned hard mask on the second MOS transistor, in which the hard mask includes at least one metal atom; and using the patterned hard mask to remove the first dummy gate of the first MOS transistor.
    Type: Grant
    Filed: September 21, 2010
    Date of Patent: March 17, 2015
    Assignee: United Mircroelectronics Corp.
    Inventors: Yeng-Peng Wang, Chun-Hsien Lin, Chiu-Hsien Yeh, Chin-Cheng Chien, Chan-Lon Yang
  • Patent number: 8980762
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a film having different filling properties dependent on space width above the patterning film to cover the first line patterns and the second line patterns to form the film on the first line patterns and on the first inter-line pattern space while making a cavity in the first inter-line pattern space and to form the film on at least a bottom portion of the second inter-line pattern space and a side wall of each of the second line patterns. The method includes performing etch-back of the film to remove the film on the first line patterns and on the first inter-line pattern space while causing the film to remain on at least the side wall of the second line patterns.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: March 17, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazunori Iida, Yuji Kobayashi
  • Patent number: 8969214
    Abstract: A method of forming a pattern on a substrate includes forming spaced first features derived from a first lithographic patterning step. Sidewall spacers are formed on opposing sides of the first features. After forming the sidewall spacers, spaced second features derived from a second lithographic patterning step are formed. At least some of individual of the second features are laterally between and laterally spaced from immediately adjacent of the first features in at least one straight-line vertical cross-section that passes through the first and second features. After the second lithographic patterning step, all of only some of the sidewall spacers in said at least one cross-section is removed.
    Type: Grant
    Filed: May 14, 2013
    Date of Patent: March 3, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Scott L. Light, Kyle Armstrong, Michael D. Hyatt, Vishal Sipani
  • Patent number: 8969215
    Abstract: Methods of fabricating semiconductor devices and semiconductor devices fabricated thereby are provided. Two photolithography processes and two spacer processes are performed to provide final patterns that have a pitch that is smaller than a limitation of photolithography process. Furthermore, since initial patterns are formed to have line and pad portions simultaneously by performing a first photolithography process, there is no necessity to perform an additional photolithography process for forming the pad portion.
    Type: Grant
    Filed: November 13, 2013
    Date of Patent: March 3, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Hwang Sim, Jinhyun Shin
  • Patent number: 8968584
    Abstract: A method for manufacturing a liquid ejection head includes the steps of: disposing an etching mask layer on a substrate having a first face and a second face that is on an opposite side of the first face, the etching mask layer being disposed on the second face; forming a concave line pattern at a region of the etching mask layer other than a region where an opening for the support port is to be formed; providing an etching opening at the etching mask layer; performing anisotropic etching from a side of the second face using the etching mask layer provided with the etching opening as a mask, thus forming the supply port at the substrate; comparing the line pattern with a recess generated at the substrate, thus selecting a device chip for liquid ejection; and connecting the selected device chip to a liquid supply part.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: March 3, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventors: Jun Yamamuro, Yoshinori Tagawa, Satoshi Ibe, Hiroto Komiyama, Kouji Hasegawa, Shiro Sujaku
  • Patent number: 8962491
    Abstract: The method includes forming an array of first separation walls on an underlying layer. A block co-polymer (BCP) layer is formed to fill inside regions of the first separation walls and gaps between the first separation walls. The BCP layer is phase-separated to include first domains that provide second separation walls covering inner sidewalls and outer sidewalls of the first separation walls and second domains that are separated from each other by the first domains.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: February 24, 2015
    Assignee: SK Hynix Inc.
    Inventors: Keun Do Ban, Jung Gun Heo, Cheol Kyu Bok, Myoung Soo Kim
  • Patent number: 8956886
    Abstract: In some embodiments, a method of controlling a photoresist trimming process in a semiconductor manufacturing process may include forming a photoresist layer atop a first surface of a substrate, wherein the photoresist layer comprises a lower layer having a first pattern to be etched into the first surface of the substrate, and an upper layer having a second pattern that is not etched into the first surface of the substrate; trimming the photoresist layer in a direction parallel to the first surface of the substrate; measuring a trim rate of the second pattern using an optical measuring tool during the trimming process; and correlating the trim rate of the second pattern to a trim rate of the first pattern to control the trim rate of the first pattern during the trimming process.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: February 17, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Samer Banna, Olivier Joubert, Lei Lian, Maxime Darnon, Nicolas Posseme, Laurent Vallier
  • Patent number: 8956982
    Abstract: According to one embodiment, a stacked film including at least a silicon oxide film is formed by stacking a plurality of films formed of different materials and a hard mask pattern is formed on the stacked film. Then, a stacked film pattern of a predetermined shape is formed by performing anisotropic etching on the stacked film by using the hard mask pattern as an etching mask and the hard mask pattern is removed. The hard mask pattern is formed by stacking at least one first hard mask layer and at least one second hard mask layer. The first hard mask layer is formed of a material having a higher removability in wet etching than the second hard mask layer. The first hard mask layer is arranged immediately above the stacked film.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: February 17, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shuichi Tsubata, Hirotaka Ogihara
  • Patent number: 8946091
    Abstract: A method for etching features in an etch layer is provided. An organic mask layer is etched, using a hard mask as an etch mask. The hard mask is removed, by selectively etching the hard mask with respect to the organic mask and etch layer. Features are etched in the etch layer, using the organic mask as an etch mask.
    Type: Grant
    Filed: April 28, 2011
    Date of Patent: February 3, 2015
    Assignee: Lam Research Corporation
    Inventors: Youn-Jin Oh, Kenji Takeshita, Hitoshi Takahashi
  • Patent number: 8945820
    Abstract: The present invention is a silicon-containing resist underlayer film-forming composition containing a condensation product and/or a hydrolysis condensation product of a mixture comprising: one or more kinds of a compound (A) selected from the group consisting of an organic boron compound shown by the general formula (1) and a condensation product thereof and one or more kinds of a silicon compound (B) shown by the general formula (2). Thereby, there can be provided a silicon-containing resist underlayer film-forming composition being capable of forming a pattern having a good adhesion, forming a silicon-containing film which can be used as a dry-etching mask between a photoresist film which is the upperlayer film of the silicon-containing film and an organic film which is the underlayer film thereof, and suppressing deformation of the upperlayer resist during the time of dry etching of the silicon-containing film; and a patterning process.
    Type: Grant
    Filed: November 2, 2012
    Date of Patent: February 3, 2015
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Tsutomu Ogihara, Takafumi Ueda, Yoshinori Taneda
  • Patent number: 8932960
    Abstract: Different portions of a continuous loop of semiconductor material are electrically isolated from one another. In some embodiments, the end of the loop is electrically isolated from mid-portions of the loop. In some embodiments, loops of semiconductor material, having two legs connected together at their ends, are formed by a pitch multiplication process in which loops of spacers are formed on sidewalls of mandrels. The mandrels are removed and a block of masking material is overlaid on at least one end of the spacer loops. In some embodiments, the blocks of masking material overlay each end of the spacer loops. The pattern defined by the spacers and the blocks are transferred to a layer of semiconductor material. The blocks electrically connect together all the loops. A select gate is formed along each leg of the loops. The blocks serve as sources/drains.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: January 13, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Luan C. Tran
  • Patent number: 8932961
    Abstract: An illustrative test structure is disclosed herein that includes a plurality of first line features and a plurality of second line features. In this embodiment, each of the second line features have first and second opposing ends and the first and second line features are arranged in a grating pattern such that the first ends of the first line features are aligned to define a first side of the grating structure and the second ends of the first features are aligned to define a second side of the grating structure that is opposite the first side of the grating structure. The first end of the second line features has a first end that extends beyond the first side of the grating structure while the second end of the second line features has a first end that extends beyond the second side of the grating structure.
    Type: Grant
    Filed: February 13, 2012
    Date of Patent: January 13, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Sohan Mehta, Tong Qing Chen, Vikrant Chauhan, Ravi Srivastava, Catherine Labelle, Mark Kelling
  • Patent number: 8920664
    Abstract: According to one embodiment, a pattern forming method includes forming a physical guide that includes a first predetermined pattern in a first region on a lower layer film, and includes a second predetermined pattern and a dummy pattern in a second region on the lower layer film, forming a block polymer inside the physical guide, making the block polymer microphase-separated to form a pattern having a first polymer section and a second polymer section, removing the second polymer section to form a hole pattern, and processing the lower layer film after removal of the second polymer section, with the physical guide and the first polymer section used as a mask. Shapes of the hole patterns in the first and the second predetermined patterns are transferred to the lower layer film. A shape of the hole pattern in the dummy pattern is not transferred to the lower layer film.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: December 30, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuriko Seino, Hirokazu Kato, Hiroki Yonemitsu
  • Patent number: 8916051
    Abstract: The present invention provides a method of forming via holes. First, a substrate is provided. A plurality of first areas is defined on the substrate. A dielectric layer and a blocking layer are formed on the substrate. A patterned photoresist layer is formed on the blocking layer. The patterned photoresist layer includes a plurality of holes arranged in a regular array wherein the area of the hole array is greater than those of the first areas. The blocking layer in the first areas is removed by using the patterned photoresist layer as a mask. Lastly, the dielectric layer is patterned to form at least a via hole in the dielectric layer in the first area.
    Type: Grant
    Filed: December 23, 2010
    Date of Patent: December 23, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Cheng-Han Wu, Chun-Chi Yu
  • Patent number: 8907456
    Abstract: A method of fabricating integrated circuits is described. A multi-material hard mask is formed on an underlying layer to be patterned. In a first patterning process, portions of the first material of the hard mask are etched, the first patterning process being selective to etch the first material over the second material. In a second patterning process, portions of the second material of the hard mask are etched, the second patterning process being selective to etch the second material over the first material. The first and second patterning processes forming a desired pattern in the hard mask which is then transferred to the underlying layer.
    Type: Grant
    Filed: March 20, 2008
    Date of Patent: December 9, 2014
    Assignee: Olambda, Inc.
    Inventor: Haiqing Wei
  • Patent number: 8895453
    Abstract: A layer with a laterally varying thickness, a substrate with a first surface and an insulation layer formed on the first surface of the substrate is provided. A plurality of at least one of recesses and openings is formed in the insulation layer, wherein the plurality is arranged at a pitch. Each of the at least one of recesses and openings has a lateral width, wherein at least one of the pitch and the lateral width varies in a lateral direction. The plurality of the at least one of recesses and openings defines a given region in the insulation layer. The insulation layer having the plurality of the at least one of the recesses and openings is tempered at elevated temperatures so that the insulation layer at least partially diffluences to provide the insulation layer with a laterally varying thickness at least in the given region.
    Type: Grant
    Filed: April 12, 2013
    Date of Patent: November 25, 2014
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Johannes Laven, Holger Schulze
  • Patent number: 8883575
    Abstract: A process may include forming a mask directly on and above a region selected as an initial semiconductor fin on a substrate and reducing the initial semiconductor fin forming a semiconductor fin that is laterally thinned from the initial semiconductor fin. The process may be carried out causing the mask to recede to a greater degree in the lateral direction than the vertical direction. In various embodiments, the process may include removing material from the fin semiconductor to achieve a thinned semiconductor fin, which has receded beneath the shadow of the laterally receded mask. Electronic devices may include the thinned semiconductor fin as part of a semiconductor device.
    Type: Grant
    Filed: April 5, 2012
    Date of Patent: November 11, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Mark Fischer, T. Earl Allen, H. Montgomery Manning
  • Patent number: 8883649
    Abstract: An improved method of performing sidewall spacer imager transfer is presented. The method includes forming a set of sidewall spacers next to a plurality of mandrels, the set of sidewall spacers being directly on top of a hard-mask layer; transferring image of at least a portion of the set of sidewall spacers to the hard-mask layer to form a device pattern; and transferring the device pattern from the hard-mask layer to a substrate underneath the hard-mask layer.
    Type: Grant
    Filed: March 23, 2011
    Date of Patent: November 11, 2014
    Assignee: International Business Machines Corporation
    Inventors: Yunpeng Yin, John C. Arnold, Matthew E. Colburn, Sean D. Burns
  • Patent number: 8871651
    Abstract: A mask for use in fabricating one or more semiconductor devices is fabricated by: providing sacrificial spacing structures disposed over a substrate structure, and including protective hard masks at upper surfaces of the spacing structures; disposing a sidewall spacer layer conformally over the sacrificial spacing structures; selectively removing the sidewall spacer layer from above the sacrificial spacing structures to expose the protective hard masks of the spacing structures, the selectively removing including leaving sidewall spacers along sidewalls of the sacrificial spacing structures; providing a protective material over the substrate structure; and removing the exposed protective hard masks from the sacrificial spacing structures, and thereafter, removing remaining sacrificial spacing structures and the protective material, leaving the sidewall spacers over the substrate structure as a mask.
    Type: Grant
    Filed: July 12, 2013
    Date of Patent: October 28, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Dae Han Choi, Zhuangfei Chen, Fangyu Wu
  • Patent number: 8865598
    Abstract: Multiple pitch-multiplied spacers are used to form mask patterns having features with exceptionally small critical dimensions. One of each pair of spacers formed mandrels is removed and alternating layers, formed of two mutually selectively etchable materials, are deposited around the remaining spacers. Layers formed of one of the materials are then etched, leaving behind vertically-extending layers formed of the other of the materials, which form a mask pattern. Alternatively, instead of depositing alternating layers, amorphous carbon is deposited around the remaining spacers followed by a plurality of cycles of forming pairs of spacers on the amorphous carbon, removing one of the pairs of spacers and depositing an amorphous carbon layer. The cycles can be repeated to form the desired pattern. Because the critical dimensions of some features in the pattern can be set by controlling the width of the spaces between spacers, exceptionally small mask features can be formed.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: October 21, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Sanket Sant, Gurtej Sandhu, Neal R. Rueger
  • Patent number: 8852962
    Abstract: Embodiments of the present invention provide methods and apparatus for forming a patterned magnetic layer for use in magnetic media. According to embodiments of the present application, a silicon oxide layer formed by low temperature chemical vapor deposition is used to form a pattern in a hard mask layer, and the patterned hard mask is used to form a patterned magnetic layer by plasma ion implantation.
    Type: Grant
    Filed: October 24, 2012
    Date of Patent: October 7, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Steven Verhaverbeke, Roman Gouk, Li-Qun Xia, Mei-yee Shek, Yu Jin
  • Patent number: 8853096
    Abstract: The disclosure relates to a method for making a grating. The method includes the following steps. First, a substrate is provided. Second, a photoresist film is formed on a surface of the substrate. Third, a nano-pattern is formed on the photoresist film by nano-imprint lithography. Fourth, the photoresist film is etched to form a patterned photoresist layer. Fifth, a mask layer is covered on the patterned photoresist layer and the surface of the substrate exposed to the patterned photoresist layer. Sixth, the patterned photoresist layer and the mask layer thereon are removed to form a patterned mask layer. Seventh, the substrate is etched through the patterned mask layer by reactive ion etching, wherein etching gases includes carbon tetrafluoride (CF4), sulfur hexafluoride (SF6) and argon (Ar2). Finally, the patterned mask layer is removed.
    Type: Grant
    Filed: October 23, 2012
    Date of Patent: October 7, 2014
    Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.
    Inventors: Zhen-Dong Zhu, Qun-Qing Li, Li-Hui Zhang, Mo Chen
  • Patent number: 8846525
    Abstract: Hardmask films having high hardness and low stress are provided. In some embodiments a film has a stress of between about ?600 MPa and 600 MPa and hardness of at least about 12 GPa. In some embodiments, a hardmask film is prepared by depositing multiple sub-layers of doped or undoped silicon carbide using multiple densifying plasma post-treatments in a PECVD process chamber. In some embodiments, a hardmask film includes a high-hardness boron-containing film selected from the group consisting of SixByCz, SixByNz, SixByCzNw, BxCy, and BxNy. In some embodiments, a hardmask film includes a germanium-rich GeNx material comprising at least about 60 atomic % of germanium. These hardmasks can be used in a number of back-end and front-end processing schemes in integrated circuit fabrication.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: September 30, 2014
    Assignee: Novellus Systems, Inc.
    Inventors: Vishwanathan Rangarajan, George Andrew Antonelli, Ananda Banerji, Bart Van Schravendijk
  • Patent number: 8846541
    Abstract: Methods of forming a semiconductor device may include providing a feature layer having a first region and a second region. The methods may also include forming a dual mask layer on the feature layer. The methods may further include forming a variable mask layer on the dual mask layer. The methods may additionally include forming a first structure on the feature layer in the first region and a second structure on the feature layer in the second region by patterning the variable mask layer and the dual mask layer. The methods may also include forming a first spacer on a sidewall of the first structure and a second spacer on a sidewall of the second structure. The methods may further include removing the first structure while maintaining at least a portion of the second structure.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: September 30, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Ho Min, O-Ik Kwon, Bum-Soo Kim, Dong-Chan Kim, Myeong-Cheol Kim
  • Patent number: 8835328
    Abstract: Methods for fabricating integrated circuits are provided herein. In an embodiment, a method for fabricating an integrated circuit includes providing a mandrel layer overlying a semiconductor substrate and patterning the mandrel layer into mandrel structures. The method further includes forming a protective layer between the mandrel structures. Spacers are formed around each of the mandrel structures and overlying the protective layer to define exposed regions of the protective layer and covered regions of the protective layer. The exposed regions of the protective layer are etched using the spacers and the mandrel structures as a mask. The spacers are removed from the covered regions of the protective layer. The covered regions of the protective layer form mask segments for etching the semiconductor substrate. The method removes the mandrel structures and etches the semiconductor substrate exposed between mask segments to form semiconductor fin structures.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: September 16, 2014
    Assignee: Globalfoundries, Inc.
    Inventors: Wontae Hwang, Il Goo Kim, Dae-Han Choi, Sang Cheol Han
  • Patent number: 8828815
    Abstract: First, a semiconductor substrate having a first active region and a second active region is provided. The first active region includes a first transistor and the second active region includes a second transistor. A first etching stop layer, a stress layer, and a second etching stop layer are disposed on the first transistor, the second transistor and the isolation structure. A first etching process is performed by using a patterned photoresist disposed on the first active region as a mask to remove the second etching stop layer and a portion of the stress layer from the second active region. The patterned photoresist is removed, and a second etching process is performed by using the second etching stop layer of the first active region as a mask to remove the remaining stress layer and a portion of the first etching stop layer from the second active region.
    Type: Grant
    Filed: December 3, 2010
    Date of Patent: September 9, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Pei-Yu Chou, Shih-Fang Tzou, Jiunn-Hsiung Liao
  • Patent number: 8802510
    Abstract: Methods for forming uniformly spaced and uniformly shaped fine lines in semiconductor processes using double patterning. Dummy lines are formed over a substrate. Sidewall spacer material is deposited over the top and sides of each of the dummy lines. Etching is performed to remove the top surface sidewall spacer material from the tops of the dummy lines. The dummy material is removed by selective etching leaving the spacer material. A photolithographic mask is formed defining inner lines that are desired for a substrate etching step, and temporary lines outside of the desired lines. The temporary lines are partially masked. The temporary lines are partially removed while the inner desired lines are retained. A transfer etch process then patterns an underlying mask layer corresponding to the inner desired lines, and the mask layer is used for etching lines in an underlying semiconductor substrate.
    Type: Grant
    Filed: February 22, 2012
    Date of Patent: August 12, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Wei Chang, Ryan Chia-Jen Chen
  • Patent number: 8802574
    Abstract: One illustrative method disclosed herein involves creating an overall target pattern that includes an odd-jogged feature with a crossover region that connects first and second line portions, wherein the crossover region has a first dimension in a first direction that is greater than a second dimension that is transverse to the first direction, decomposing the overall target pattern into a first sub-target pattern and a second sub-target pattern, wherein each of the sub-target patterns comprise a line portion and a first portion of the crossover region, and generating first and second sets of mask data corresponding to the first and second sub-target patterns, respectively.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: August 12, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Lei Yuan, Jongwook Kye
  • Patent number: 8796150
    Abstract: A method and structure for transferring a lithographic pattern into a substrate includes forming a dielectric hardmask layer over a dielectric substrate. A metal hardmask layer is formed over the dielectric hardmask layer. A protective capping hardmask layer or capping film is formed over the metal hardmask layer, and a lithographic structure for pattern transfer is formed over the capping layer. A pattern is transferred into the dielectric substrate using the defined lithographic structure. The capping hardmask layer can be removed during subsequent processing.
    Type: Grant
    Filed: January 24, 2011
    Date of Patent: August 5, 2014
    Assignee: International Business Machines Corporation
    Inventors: Hakeem B. S. Akinmade-Yusuff, Samuel Sung Shik Choi, Edward R. Engbrecht, John A. Fitzsimmons
  • Patent number: 8796156
    Abstract: A method of forming an integrated circuit structure includes providing a semiconductor substrate; providing a first lithography mask, a second lithography mask, and a third lithography mask; forming a first mask layer over the semiconductor substrate, wherein a pattern of the first mask layer is defined using the first lithography mask; performing a first etch to the semiconductor substrate to define an active region using the first mask layer; forming a second mask layer having a plurality of mask strips over the semiconductor substrate and over the active region; forming a third mask layer over the second mask layer, wherein a middle portion of the plurality of mask strips is exposed through an opening in the third mask layer, and end portions of the plurality of mask strips are covered by the third mask layer; and performing a second etch to the semiconductor substrate through the opening.
    Type: Grant
    Filed: January 4, 2012
    Date of Patent: August 5, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Feng Shieh, Tsung-Lin Lee, Chang-Yun Chang