Vapor Phase Etching (i.e., Dry Etching) Patents (Class 438/706)
  • Patent number: 11565936
    Abstract: The present invention relates to the unexpected discovery of novel methods of preparing nanodevices and/or microdevices with predetermined patterns. In one aspect, the methods of the invention allow for engineering structures and films with continuous thickness equal to or less than 50 nm.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: January 31, 2023
    Assignees: The Regents of the University of Colorado, DRS Network & Imaging Systems, LLC
    Inventors: Steven M. George, Victor M. Bright, Joseph J. Brown, Jonas Gertsch, Nathan Thomas Eigenfeld, George Skidmore
  • Patent number: 11527413
    Abstract: A method for processing a substrate includes performing a cyclic plasma etch process including a plurality of cycles, where each cycle of the plurality of cycles includes: causing chemical reactions with the surface of the substrate by exposing a surface of the substrate to fluorine radicals extracted from a first gas discharge plasma formed using a first gaseous mixture including a non-polymerizing fluorine compound; cooling the substrate and concurrently removing residual gaseous byproducts by flowing a second gaseous mixture over the substrate, and at the same time, suppressing the chemical reactions with the surface of the substrate; and performing a plasma surface modification process by exposing the surface of the substrate to hydrogen radicals extracted from a second gas discharge plasma formed using a third gaseous mixture including gases including nitrogen and hydrogen.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: December 13, 2022
    Assignee: Tokyo Electron Limited
    Inventors: Yun Han, Peter Ventzek, Alok Ranjan
  • Patent number: 11488857
    Abstract: Semiconductor devices and methods of manufacture are described herein. A method includes forming an opening through an interlayer dielectric (ILD) layer to expose a contact etch stop layer (CESL) disposed over a conductive feature in a metallization layer. The opening is formed using photo sensitive materials, lithographic techniques, and a dry etch process that stops on the CESL. Once the CESL is exposed, a CESL breakthrough process is performed to extend the opening through the CESL and expose the conductive feature. The CESL breakthrough process is a flexible process with a high selectivity of the CESL to ILD layer. Once the CESL breakthrough process has been performed, a conductive fill material may be deposited to fill or overfill the opening and is then planarized with the ILD layer to form a contact plug over the conductive feature in an intermediate step of forming a semiconductor device.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: November 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Shih Wang, Po-Nan Yeh, U-Ting Chiu, Chun-Neng Lin, Chia-Cheng Chen, Liang-Yin Chen, Ming-Hsi Yeh, Kuo-Bin Huang
  • Patent number: 11450531
    Abstract: The present invention relates to an atomic layer etching method for etching a surface of a substrate by using an atomic layer etching apparatus.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: September 20, 2022
    Assignee: WONIK IPS CO., LTD.
    Inventors: Jun Hyuck Kwon, Jin Sung Chun, Sang Jun Park, Byung Chul Cho, Kwang Seon Jin
  • Patent number: 11398388
    Abstract: Exemplary methods of etching gallium oxide from a semiconductor substrate may include selectively etching gallium oxide relative to gallium nitride. The method may include flowing a reagent in a substrate processing region housing the semiconductor substrate. The reagent may include at least one of chloride and bromide. The method may further include contacting an exposed region of gallium oxide with the at least one of chloride and bromide from the reagent to form a gallium-containing gas. The gallium-containing gas may be removed by purging the substrate processing region with an inert gas. The method includes recessing a surface of the gallium oxide. The method may include repeated cycles to achieve a desired depth.
    Type: Grant
    Filed: September 8, 2020
    Date of Patent: July 26, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Feng Q. Liu, Lisa J. Enman, Lakmal C. Kalutarage, Mark J. Saly
  • Patent number: 11377731
    Abstract: A film-forming device that includes a cylindrical chamber capable of maintaining vacuum therein, a workpiece holder that is constructed to align and hold workpieces to be processed in multiple stages such that main surfaces of the workpieces are oriented in a vertical direction relative to a central axis of the chamber, a deposition material supply pipe, a modifier supply pipe, a carrier gas supply pipe, and an exhaust mechanism, wherein in a cross section of the chamber in a direction parallel to the main surfaces of the workpieces, the exhaust mechanism is located on a side opposite to an opening direction of gas outlets of the deposition, modifier, and carrier gas supply pipes, and a total gas flow from the deposition, modifier, and carrier gas supply pipes is symmetric about a centerline of the chamber.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: July 5, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yasuhiro Chikaishi, Shigeki Yamane
  • Patent number: 11367622
    Abstract: A manufacturing method of a semiconductor device includes etching a film using etching gas that has a first or second molecule which has a C3F4 group and in which the number of carbon atoms is four or five. Further, the first molecule has an R1 group that bonds to a carbon atom in the C3F4 group through a double bond, and the R1 group contains carbon and also chlorine, bromine, iodine, or oxygen. Further, the second molecule has an R2 group that bonds to a carbon atom in the C3F4 group through a single bond and an R3 group that bonds to the carbon atom in the C3F4 group through a single bond, the R2 group or the R3 group or both containing carbon, and both the R2 group and the R3 group containing hydrogen, fluorine, chlorine, bromine, iodine, or oxygen.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: June 21, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Mitsunari Horiuchi, Toshiyuki Sasaki, Tomo Hasegawa
  • Patent number: 11335563
    Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: May 17, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Baosuo Zhou, Mirzafer K. Abatchev, Ardavan Niroomand, Paul A. Morgan, Shuang Meng, Joseph Neil Greeley, Brian J. Coppa
  • Patent number: 11315828
    Abstract: A method includes providing a dielectric layer; forming a metal line in the dielectric layer; forming an etch stop layer on the metal line, wherein the etch stop layer includes a metal atom bonded with a hydroxyl group; performing a treatment process to the etch stop layer to displace hydrogen in the hydroxyl group with an element other than hydrogen; partially etching the etch stop layer to expose the metal line; and forming a conductive feature above the etch stop layer and in physical contact with the metal line.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: April 26, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kai-Fang Cheng, Chi-Lin Teng, Hsin-Yen Huang, Hai-Ching Chen
  • Patent number: 11302521
    Abstract: A plasma processing system includes processing modules, a transfer device connected to the processing modules, and a control unit for controlling an oxygen partial pressure and a water vapor partial pressure in the transfer device. The control unit controls the oxygen partial pressure and the water vapor partial pressure in the transfer device to 127 Pa or less and 24.1 Pa or less, respectively. The processing modules include a first processing module for performing etching on the target object, a second processing module for performing surface treatment on the target object, and a third processing module for performing a deposition process on the target object. The second processing module performs the surface treatment using hydrogen radicals generated by a high frequency antenna. The high frequency antenna resonates at one half of a wavelength of a signal supplied from a high frequency power supply used in the processing system.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: April 12, 2022
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Kenji Matsumoto
  • Patent number: 11296289
    Abstract: A thin film transistor includes a gate electrode, a semiconductor layer overlapped with the gate electrode, a gate insulating layer between the gate electrode and the semiconductor layer, and a source electrode and a drain electrode electrically connected to the semiconductor layer. The semiconductor layer includes a plurality of holes. The gate insulating layer may include a plurality of recess portions at a surface of the gate insulating layer facing the semiconductor layer. A method of manufacturing the thin film transistor is provided. A thin film transistor array panel and an electronic device may include the thin film transistor.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: April 5, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joo Young Kim, Byong Gwon Song, Jeong Il Park, Jiyoung Jung
  • Patent number: 11289329
    Abstract: Methods and apparatus for method for filling a feature with copper. In some embodiments, the methods include: (a) depositing a first cobalt layer via a physical vapor deposition (PVD) process atop a substrate field and atop a sidewall and a bottom surface of a feature disposed in a substrate to form a first cobalt portion atop the substrate field and a second cobalt portion atop the sidewall; (b) depositing copper atop the first cobalt portion atop the substrate field; and (c) flowing the copper disposed atop the first cobalt portion atop the substrate field over the second cobalt portion and into the feature, wherein the first cobalt portion atop the substrate field reduces the mobility of copper compared to the mobility of copper over the second cobalt portion.
    Type: Grant
    Filed: January 25, 2020
    Date of Patent: March 29, 2022
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Rui Li, Xiangjin Xie, Fuhong Zhang, Shirish Pethe, Adolph Allen, Lanlan Zhong, Xianmin Tang
  • Patent number: 11289337
    Abstract: In a method of forming pattern, a target layer is formed on a semiconductor substrate, and pluralities of first spacers having cylindrical shapes protruding from the target layer are formed. A second spacer layer is formed to cover the first spacers, provide interstitial spaces between the first spacers, and provide second inner spaces within first inner spaces of the first spacers, respectively. The second spacer layer is etched to form first opening portions in which the second inner spaces and the interstitial spaces extend into the target layer.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: March 29, 2022
    Assignee: SK hynix Inc.
    Inventor: You Song Kim
  • Patent number: 11276579
    Abstract: A substrate processing method for reducing a surface roughness of a semiconductor wafer by processing a film structure having at least two types of films beforehand disposed on the substrate, including steps of repeating an adsorption step of supplying activated particles into the processing chamber and allowing the particles to be adsorbed to a surface of a desirable film to be etched in the at least two types of films to allow the particles to combine with a material of the desirable film to form a reaction layer, a removal step of using plasma generated by supplying oxygen into the processing chamber to remove a deposit containing particles adhering to a surface of an undesirable film to be etched in the films, and a desorption step of desorbing and removing the reaction layer on the desirable film to be etched by heating the sample.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: March 15, 2022
    Assignee: HITACHI HIGH-TECH CORPORATION
    Inventors: Hiroyuki Kobayashi, Nobuya Miyoshi, Kazunori Shinoda, Yutaka Kouzuma, Masaru Izawa
  • Patent number: 11264234
    Abstract: Disclosed are methods and systems for providing silicon carbide films. A layer of silicon carbide can be provided under process conditions that employ one or more silicon-containing precursors that have one or more silicon-hydrogen bonds and/or silicon-silicon bonds. The silicon-containing precursors may also have one or more silicon-oxygen bonds and/or silicon-carbon bonds. One or more radical species in a substantially low energy state can react with the silicon-containing precursors to form the silicon carbide film. The one or more radical species can be formed in a remote plasma source.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: March 1, 2022
    Assignee: NOVELLUS SYSTEMS, INC.
    Inventors: Bhadri N. Varadarajan, Bo Gong, Zhe Gui
  • Patent number: 11251305
    Abstract: A fin field effect transistor device structure includes a fin structure formed over a substrate. The structure also includes a gate structure formed across the fin structure. The structure also includes a cap layer formed over the gate structure. The structure also includes a contact structure formed over the gate structure penetrating through the cap layer. The structure also includes an isolation film formed over sidewalls of the contact structure. The isolation film is separated from the gate structure, and a bottom surface of the isolation film is below a top surface of the cap layer.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: February 15, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Lin-Yu Huang, Li-Zhen Yu, Chia-Hao Chang, Cheng-Chi Chuang, Yu-Ming Lin, Chih-Hao Wang
  • Patent number: 11195725
    Abstract: A microelectronic device includes a metal layer on a first dielectric layer. An etch stop layer is disposed over the metal layer and on the dielectric layer directly adjacent to the metal layer. The etch stop layer includes a metal oxide, and is less than 10 nanometers thick. A second dielectric layer is disposed over the etch stop layer. The second dielectric layer is removed from an etched region which extends down to the etch stop layer. The etched region extends at least partially over the metal layer. In one version of the microelectronic device, the etch stop layer may extend over the metal layer in the etched region. In another version, the etch stop layer may be removed in the etched region. The microelectronic device is formed by etching the second dielectric layer using a plasma etch process, stopping on the etch stop layer.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: December 7, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sebastian Meier, Michael Hans Enzelberger-Heim, Reiner Port
  • Patent number: 11189559
    Abstract: A semiconductor device includes a substrate, a capacitor disposed on the substrate, and an interconnection structure. The capacitor is disposed on the substrate within a capacitor region and includes a lower electrode, an upper electrode, a stacked dielectric layer, and an intermediate dielectric layer. The upper electrode is disposed over the lower electrode, and the stacked dielectric layer is disposed between the lower electrode and the upper electrode. The intermediate dielectric layer is disposed between the lower electrode and the upper electrode and disposed only within the capacitor region. The relative permittivity of the intermediate dielectric layer is greater than the relative permittivity of the stacked dielectric layer. The interconnection structure including a plug and a stack of metal layers is disposed within an interconnection region abutting the capacitor region and is disposed at at least one side of the intermediate dielectric layer.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: November 30, 2021
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Chi-Hua Yu, Shih-Tsung Kung, Wen-Chun Chung, Yi-Hong Hong
  • Patent number: 11152455
    Abstract: Various embodiments of the present application are directed towards a method for forming a metal-insulator-metal (MIM) capacitor comprising an enhanced interfacial layer to reduce breakdown failure. In some embodiments, a bottom electrode layer is deposited over a substrate. A native oxide layer is formed on a top surface of the bottom electrode layer and has a first adhesion strength with the top surface. A plasma treatment process is performed to replace the native oxide layer with an interfacial layer. The interfacial layer is conductive and has a second adhesion strength with the top surface of the bottom electrode layer, and the second adhesion strength is greater than the first adhesion strength. An insulator layer is deposited on the interfacial layer. A top electrode layer is deposited on the insulator layer. The top and bottom electrode layers, the insulator layer, and the interfacial layer are patterned to form a MIM capacitor.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: October 19, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsing-Lien Lin, Chii-Ming Wu, Chia-Shiung Tsai, Chung-Yi Yu, Rei-Lin Chu
  • Patent number: 11139168
    Abstract: Exemplary methods of semiconductor processing may include depositing a material on a substrate seated on a substrate support housed in a processing region of a semiconductor processing chamber. The processing region may be at least partially defined by the substrate support and a faceplate. The substrate support may be at a first position within the processing region relative to the faceplate. The methods may include translating the substrate support to a second position relative to the faceplate. The methods may include forming a plasma of an etchant precursor within the processing region of the semiconductor processing chamber. The methods may include etching an edge region of the substrate.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: October 5, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Jun Ma, Amit Bansal, Tuan A. Nguyen
  • Patent number: 11131932
    Abstract: A cleaning liquid usable for cleaning a substrate provided with a metal resist, the cleaning liquid including a solvent, an organic acid, and a compound (A) represented by general formula (a-1) shown below (in the formula, Ra1 and Ra2 each independently represents an alkyl group having 1 to 3 carbon atoms).
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: September 28, 2021
    Assignee: Tokyo Ohka Kogyo Co., Ltd.
    Inventors: Tomoya Kumagai, Takahiro Akiyoshi
  • Patent number: 11114305
    Abstract: An etching method which includes treating a workpiece having a stacked film (5) of a silicon oxide layer (2) and a silicon nitride layer (3) with an etching gas containing an unsaturated halon represented by the chemical formula: C2HxF(3?x)Br (in the chemical formula, x stands for 0, 1, or 2) so as to control the respective etch rates of the silicon nitride layer and the silicon oxide layer to the same level and form a high-aspect-ratio hole having a desirable profile at a high etch rate. Also disclosed is a method of manufacturing a semiconductor which includes by carrying out the etching method.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: September 7, 2021
    Assignee: SHOWA DENKO K.K.
    Inventor: Yosuke Tanimoto
  • Patent number: 11049726
    Abstract: A substrate is disposed on a substrate holder within a process module. The substrate includes a mask material overlying a target material with at least one portion of the target material exposed through an opening in the mask material. A plasma is generated in exposure to the substrate. For a first duration, a bias voltage is applied at the substrate holder at a first bias voltage setting corresponding to a high bias voltage level. For a second duration, after completion of the first duration, a bias voltage is applied at the substrate holder at a second bias voltage setting corresponding to a low bias voltage level. The second bias voltage setting is greater than 0 V. The first and second durations are repeated in an alternating and successive manner for an overall period of time necessary to remove a required amount of the target material exposed on the substrate.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: June 29, 2021
    Assignee: Lam Research Corporation
    Inventors: Zhongkui Tan, Qian Fu, Ying Wu, Qing Xu, John Drewery
  • Patent number: 11049805
    Abstract: In an embodiment, a device includes: a first redistribution structure including a first dielectric layer; a die adhered to a first side of the first redistribution structure; an encapsulant laterally encapsulating the die, the encapsulant being bonded to the first dielectric layer with first covalent bonds; a through via extending through the encapsulant; and first conductive connectors electrically connected to a second side of the first redistribution structure, a subset of the first conductive connectors overlapping an interface of the encapsulant and the die.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: June 29, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo Lung Pan, Shu-Rong Chun, Teng-Yuan Lo, Hung-Yi Kuo, Chih-Horng Chang, Tin-Hao Kuo, Hao-Yi Tsai
  • Patent number: 11049756
    Abstract: Etch uniformity is improved by providing a thermal pad between an insert ring and electrostatic chuck in an etching chamber. The thermal pad provides a continuous passive heat path to dissipate heat from the insert ring and wafer edge to the electrostatic chuck. The thermal pad helps to keep the temperature of the various components in contact with or near the wafer at a more consistent temperature. Because temperature may affect etch rate, such as with etching hard masks over dummy gate formations, a more consistent etch rate is attained. The thermal pad also provides for etch rate uniformity across the whole wafer and not just at the edge. The thermal pad may be used in an etch process to perform gate replacement by removing hard mask layer(s) over a dummy gate electrode.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: June 29, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Huei Chiu, Tsung Fan Yin, Chen-Yi Liu, Hua-Li Hung, Xi-Zong Chen, Yi-Wei Chiu
  • Patent number: 11028321
    Abstract: An etching composition is provided. The etching composition includes phosphoric acid, phosphoric anhydride, a silane compound represented by Formula 1 below and water: wherein R1 to R6 are independently hydrogen, halogen, a substituted or unsubstituted C1-C20 hydrocarbyl group, a C1-C20 alkoxy group, a carboxy group, a carbonyl group, a nitro group, a tri(C1-C20-alkyl)silyl group, a phosphoryl group, or a cyano group. L is a direct bond or C1 to C3 hydrocarbylene, and A is an n-valent radical, while n is an integer of 1 to 4.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: June 8, 2021
    Assignees: SK Innovation Co., Ltd., SK-Materials Co., Ltd.
    Inventors: Cheol Woo Kim, Yu Na Shim, Kwang Kuk Lee, Jae Hoon Kwak, Young Bom Kim, Jong Ho Lee, Jin Kyung Jo
  • Patent number: 11018052
    Abstract: A method for fabricating a semiconductor device that includes forming a mask stack over a semiconductor structure. The mask stack has a first mask layer and a second mask layer, where the second mask layer is arranged between the first mask layer and the semiconductor structure. The method further includes patterning a first pattern in the mask stack. The first pattern includes a first opening having first sidewalls formed in the first mask layer, a second opening having second sidewalls formed in the second mask layer, and a third opening having third sidewalls formed in the semiconductor structure. The first, second, and third sidewalls of the respective openings of the first pattern are formed around a central axis, where the second sidewalls of the second opening are located further away from the central axis than both the first and third sidewalls of the first and third openings, respectively.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: May 25, 2021
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventor: Gang Yang
  • Patent number: 11011383
    Abstract: There is provided an etching method which includes: supplying an etching gas to a workpiece including a first SiGe-based material and a second SiGe-based material having different Ge concentrations; and selectively etching the first SiGe-based material and the second SiGe-based material with respect to the other using a difference in incubation time until the first SiGe-based material and the second SiGe-based material begin to be etched by the etching gas.
    Type: Grant
    Filed: January 21, 2019
    Date of Patent: May 18, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Yasuo Asada, Takehiko Orii, Nobuhiro Takahashi
  • Patent number: 11004862
    Abstract: Provided herein may be a semiconductor device and a method of manufacturing the same. The method may include forming a second preliminary stack on a first preliminary stack; forming a first hard mask layer on the second preliminary stack; etching the first hard mask layer and forming holes through which the second preliminary stack is exposed; forming a second hard mask layer on the first hard mask layer to fill the holes; forming a linear trench by etching the second hard mask layer; forming a waved select line separation mask pattern by etching the exposed first hard mask layer; forming a select line separation trench by etching the exposed second preliminary stack using the select line separation mask pattern as an etching mask; and forming a select line separation layer by filling the select line separation trench with a non-conductor.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: May 11, 2021
    Assignee: SK hynix Inc.
    Inventor: Do Youn Kim
  • Patent number: 10957685
    Abstract: A semiconductor device and method of manufacturing a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a semiconductor layer located on the substrate; at least one shallow trench and at least one deep trench. Each of the at least one shallow trench and the at least one deep trench extending from a first major surface of the semiconductor layer. Sidewall regions and base regions of the trenches comprise a doped trench region and the trenches are at least partially filled with a conductive material contacting the doped region. The shallow trenches terminate in the semiconductor layer and the deep trench terminates in the semiconductor substrate.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: March 23, 2021
    Assignee: Nexperia B.V.
    Inventors: Steffen Holland, Zhihao Pan, Jochen Wynants, Hans-Martin Ritter, Tobias Sprogies, Thomas Igel-Holtzendorff, Wolfgang Schnitt, Joachim Utzig
  • Patent number: 10943789
    Abstract: A substrate is disposed on a substrate holder within a process module. The substrate includes a mask material overlying a target material with at least one portion of the target material exposed through an opening in the mask material. A plasma is generated in exposure to the substrate. For a first duration, a bias voltage is applied at the substrate holder at a first bias voltage setting corresponding to a high bias voltage level. For a second duration, after completion of the first duration, a bias voltage is applied at the substrate holder at a second bias voltage setting corresponding to a low bias voltage level. The second bias voltage setting is greater than 0 V. The first and second durations are repeated in an alternating and successive manner for an overall period of time necessary to remove a required amount of the target material exposed on the substrate.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: March 9, 2021
    Assignee: Lam Research Corporation
    Inventors: Zhongkui Tan, Qian Fu, Ying Wu, Qing Xu, John Drewery
  • Patent number: 10941301
    Abstract: A surface treatment method for a substrate surface; a surface treatment agent used for the surface treatment method; and a method for forming a film on a substrate in a region-selective manner. The method includes exposing the surface to a surface treatment agent including a silylation agent and a nitrogen-containing heterocyclic compound, the surface including two or more regions, adjacent regions in the two or more regions having different materials, and a reaction between the silylation agent and the two or more regions causing contact angles of water to differ from each other with respect to adjacent regions in the two or more regions.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: March 9, 2021
    Assignee: Tokyo Ohka Kogyo Co., Ltd.
    Inventor: Kenji Seki
  • Patent number: 10916639
    Abstract: The present application discloses a semiconductor device structure and a method for preparing the same. The method includes forming a ring structure over a substrate; performing an etching process to form an annular semiconductor fin under the ring structure; forming a lower source/drain region on the surface of the substrate in contact with a bottom portion of the annular semiconductor fin; forming an inner gate structure in contact with an inner sidewall of the annular semiconductor fin and forming an outer gate structure in contact with an outer sidewall of the annular semiconductor fin; and forming an upper source/drain region on an upper portion of the annular semiconductor fin.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: February 9, 2021
    Assignee: Nanya Technology Corporation
    Inventor: Yuan-Yuan Lin
  • Patent number: 10903065
    Abstract: A chamber is formed to enclose a processing region. A passageway is configured to provide for entry of a substrate into the processing region and removal of the substrate from the processing region. A substrate support structure is disposed within the processing region and configured to support the substrate within the processing region. At least one gas input is configured to supply one or more gases to the processing region. At least one gas output is configured to exhaust gases from the processing region. A humidity control device is configured to control a relative humidity within the processing region. At least one heating device is disposed to provide temperature control of the substrate within the processing region. The processing region of the chamber is directly accessible from a substrate handling module configured to operate at atmospheric pressure.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: January 26, 2021
    Assignee: Lam Research Corporation
    Inventors: Travis R. Taylor, Adam Bateman, Todd A. Lopes, Sankaranarayanan Ravi, Silvia Aguilar, Derek Witkowicki
  • Patent number: 10891461
    Abstract: Facilitating live fingerprint detection utilizing an integrated ultrasound and infrared (IR) sensor is presented herein. A fingerprint sensor can comprise a first substrate comprising the IR sensor, and a second substrate comprising an ultrasonic transducer. The second substrate is attached to a top portion of the first substrate, and a temperature output of the IR sensor facilitates a determination that a fingerprint output of the ultrasonic transducer corresponds to a finger. The IR sensor can comprise polysilicon comprising a thermopile and an array of photonic crystals thermally coupled to the thermopile.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: January 12, 2021
    Assignee: INVENSENSE, INC.
    Inventors: Fang Liu, Peter Hartwell, Martin Lim
  • Patent number: 10818507
    Abstract: Embodiments provide isotropic and selective etching of silicon nitride layers for the manufacture of microelectronic workpieces through sequential exposure of silicon nitride layers to plasma including hydrogen radicals and plasma including fluorine radicals. For example, the sequential application of plasma etch steps can use: (1) a first plasma gas including hydrogen (H2) and argon (Ar), and (2) a second plasma gas including nitrogen trifluoride (NF3), oxygen (O2), and Ar. These plasma gases are ignited within a processing region or chamber under sufficient pressure to generate the hydrogen radicals and the fluorine radicals. Other plasma gas chemistries can also be used under sufficient pressures to generate alternating application of hydrogen radicals and fluorine radicals.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: October 27, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Sonam D. Sherpa, Alok Ranjan
  • Patent number: 10818513
    Abstract: The present disclosure provides a method for manufacturing a conductive line. The method includes steps of providing a substrate; forming a metal layer on the substrate; patterning the metal layer by etching a portion of the metal layer; and performing a post-treatment process on the patterned metal layer in a chamber by injecting a CxHyFz gas and water vapor into the chamber, such that the patterned metal layer avoids from being corroded after the post-treatment process is performed.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: October 27, 2020
    Assignee: Wuhan China Star Optoelectronics Semiconductor Display Co., Ltd.
    Inventor: Pengbin Zhang
  • Patent number: 10804113
    Abstract: A manufacturing method of a semiconductor device includes etching a film using etching gas that has a first or second molecule which has a C3F4 group and in which the number of carbon atoms is four or five. Further, the first molecule has an R1 group that bonds to a carbon atom in the C3F4 group through a double bond, and the R1 group contains carbon and also chlorine, bromine, iodine, or oxygen. Further, the second molecule has an R2 group that bonds to a carbon atom in the C3F4 group through a single bond and an R3 group that bonds to the carbon atom in the C3F4 group through a single bond, the R2 group or the R3 group or both containing carbon, and both the R2 group and the R3 group containing hydrogen, fluorine, chlorine, bromine, iodine, or oxygen.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: October 13, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Mitsunari Horiuchi, Toshiyuki Sasaki, Tomo Hasegawa
  • Patent number: 10793951
    Abstract: Apparatus for improving substrate temperature uniformity in a substrate processing chamber are provided herein. In some embodiments, a substrate support processing chamber may include a chamber body having a bottom portion and a sidewall having a slit valve opening to load and unload substrates, a pin lift mechanism, disposed in a pin lift mechanism opening formed in the bottom portion of the chamber body, having a plurality of substrate support pins coupled to the pin lift mechanism, a movable substrate support heater having substrate support portion and a shaft, and a cover plate disposed about the shaft of the movable substrate support, wherein the cover plate covers the pin lift mechanism and pin lift mechanism opening.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: October 6, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Gwo-Chuan Tzu, Kazuya Daito, Sang-Hyeob Lee
  • Patent number: 10763591
    Abstract: A slot array antenna includes: an electrically conductive member having an electrically conductive surface and slots therein, the slots being arrayed in a first direction which extends along the conductive surface; a waveguide member having an electrically conductive waveguide face which opposes the slots and extends along the first direction; and an artificial magnetic conductor extending on both sides of the waveguide member. At least one of the conductive member and the waveguide member includes dents on the conductive surface and/or the waveguide face, the dents each serving to broaden a spacing between the conductive surface and the waveguide face relative to any adjacent site. The dents include a first, second, and third dents which are adjacent to one another and consecutively follow along the first direction. A distance between centers of the first and second dents is different from a distance between centers of the second and third dents.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: September 1, 2020
    Assignees: NIDEC CORPORATION, WGR CO., LTD.
    Inventors: Hideki Kirino, Hiroyuki Kamo
  • Patent number: 10755897
    Abstract: In a plasma processing apparatus, a placement electrode includes an inner peripheral electrode for electrostatically adsorbing a wafer and an outer peripheral electrode disposed outside the inner peripheral electrode for electrostatically adsorbing the wafer, and a DC power supply unit on which the wafer is placed supplies a first radio frequency power to the inner peripheral electrode via an inner peripheral transmission path. A DC power supply unit supplies a second radio frequency power having the same frequency as the frequency of the first radio frequency power to the outer peripheral electrode via an outer peripheral transmission path. An electromagnetic wave generating power supply supplies a third radio frequency power for generating plasma.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: August 25, 2020
    Assignee: HITACHI HIGH-TECH CORPORATION
    Inventors: Norihiko Ikeda, Kazuya Yamada, Naoki Yasui
  • Patent number: 10727080
    Abstract: Methods are described herein for etching tantalum-containing films with various potential additives while still retaining other desirable patterned substrate portions. The methods include exposing a tantalum-containing film to a chlorine-containing precursor (e.g. Cl2) with a concurrent plasma. The plasma-excited chlorine-containing precursor selectively etches the tantalum-containing film and other industrially-desirable additives. Chlorine is then removed from the substrate processing region. A hydrogen-containing precursor (e.g. H2) is delivered to the substrate processing region (also with plasma excitation) to produce a relatively even and residue-free tantalum-containing surface. The methods presented remove tantalum while retaining materials elsewhere on the patterned substrate.
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: July 28, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Xikun Wang, Naomi Yoshida, Soumendra N. Barman, Nitin K. Ingle
  • Patent number: 10707086
    Abstract: Embodiments described herein relate to apparatus and methods for performing electron beam reactive plasma etching (EBRPE). In one embodiment, an apparatus for performing EBRPE processes includes an electrode formed from a material having a high secondary electron emission coefficient. In another embodiment, methods for etching a substrate include generating a plasma and bombarding an electrode with ions from the plasma to cause the electrode to emit electrons. The electrons are accelerated toward a substrate to induce etching of the substrate.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: July 7, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Yang Yang, Kartik Ramaswamy, Kenneth S. Collins, Steven Lane, Gonzalo Monroy, Lucy Zhiping Chen, Yue Guo
  • Patent number: 10707089
    Abstract: A microelectronic device includes a metal layer on a first dielectric layer. An etch stop layer is disposed over the metal layer and on the dielectric layer directly adjacent to the metal layer. The etch stop layer includes a metal oxide, and is less than 10 nanometers thick. A second dielectric layer is disposed over the etch stop layer. The second dielectric layer is removed from an etched region which extends down to the etch stop layer. The etched region extends at least partially over the metal layer. In one version of the microelectronic device, the etch stop layer may extend over the metal layer in the etched region. In another version, the etch stop layer may be removed in the etched region. The microelectronic device is formed by etching the second dielectric layer using a plasma etch process, stopping on the etch stop layer.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: July 7, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sebastian Meier, Michael Hans Enzelberger-Heim, Reiner Port
  • Patent number: 10685829
    Abstract: A substrate processing method includes a liquid film forming step of forming a liquid film of the low surface tension liquid, an opening-forming step of forming an opening in the center region of the liquid film, a liquid film removal step of removing the liquid film from the upper surface of the substrate by widening the opening, a low surface tension liquid supply step of supplying a low surface tension liquid toward a first liquid landing point which is set on the outside of the opening, a hydrophobic agent supply step of supplying a hydrophobic agent toward a second liquid landing point which is set on the outside of the opening and further from the opening than the first liquid landing point, and a liquid landing point moving step of moving the first liquid landing point and the second liquid landing point so as to follow widening of the opening.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: June 16, 2020
    Assignee: SCREEN Holdings Co., Ltd.
    Inventors: Taiki Hinode, Sadamu Fujii, Rei Takeaki
  • Patent number: 10672622
    Abstract: An etching method includes loading, first and second supplying, removing and etching steps. In the loading step, a target object is loaded into a chamber. In the first supply step, a first gas containing carbon, hydrogen and fluorine is supplied into the chamber. In the modification step, plasma of the first gas is generated to modify a surface of a mask film and a surface of an organic film which is not covered with the mask film. In the second supply step, a second gas for etching the organic film is supplied into the chamber. In the removal step, a modified layer formed on the surface of the organic film is removed by applying a first high frequency bias power. In the etching step, the organic film below the modified layer is etched by applying a second high frequency bias power lower than the first high frequency bias power.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: June 2, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Yusuke Shimizu, Akinori Kitamura, Masahiko Takahashi
  • Patent number: 10665516
    Abstract: The present invention relates to an etching method including a reaction layer forming step of forming a reaction layer by adsorption of a gas on a surface of an etching target material, a desorption step of desorbing the reaction layer after the reaction layer forming step, and a removal step of removing the reaction layer or a deposited film, characterized in that the surface of the etching target material is etched by the reaction layer forming step and the desorption step.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: May 26, 2020
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Miyako Matsui, Kenichi Kuwahara, Naoki Yasui, Masaru Izawa, Tatehito Usui, Takeshi Ohmori
  • Patent number: 10629446
    Abstract: A substrate treatment method capable of obtaining a flat processing target film. Molecules of an HF gas are adsorbed onto a corner SiO2 layer remaining in a corner portion of a groove of a wafer subjected to an oxide film removal process. An excess HF gas is discharged. An NH3 gas is supplied toward the corner SiO2 layer onto which the molecules of the HF gas are adsorbed. AFS is formed by reacting the corner SiO2 layer, the HF gas and the NH3 gas with each other. The AFS is sublimated and removed.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: April 21, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Masahiko Tomita, Hiroyuki Takahashi
  • Patent number: 10622269
    Abstract: The present invention relates to an etching method including a reaction layer forming step of forming a reaction layer by adsorption of a gas on a surface of an etching target material, a desorption step of desorbing the reaction layer after the reaction layer forming step, and a removal step of removing the reaction layer or a deposited film, characterized in that the surface of the etching target material is etched by the reaction layer forming step and the desorption step.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: April 14, 2020
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Miyako Matsui, Kenichi Kuwahara, Naoki Yasui, Masaru Izawa, Tatehito Usui, Takeshi Ohmori
  • Patent number: 10607851
    Abstract: Various embodiments comprise methods of selectively etching oxides over nitrides in a vapor-etch cyclic process. In one embodiment, the method includes, in a first portion of the vapor-etch cyclic process, exposing a substrate having oxide features and nitride features formed thereon to selected etchants in a vapor-phase chamber; transferring the substrate to a post-etch heat treatment chamber; and heating the substrate to remove etchant reaction products from the substrate. In a second portion of the vapor-etch cyclic process, the method continues with transferring the substrate from the post-etch heat treatment chamber to the vapor-phase chamber; exposing the substrate to the selected etchants in the vapor-phase chamber; transferring the substrate to the post-etch heat treatment chamber; and heating the substrate to remove additional etchant reaction products from the substrate. Apparatuses for performing the method and additional methods are also disclosed.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: March 31, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Andrew L. Li, Prashant Raghu, Sanjeev Sapra, Rita J. Klein, Sanh D. Tang, Sourabh Dhir