Vapor Phase Etching (i.e., Dry Etching) Patents (Class 438/706)
  • Patent number: 10818507
    Abstract: Embodiments provide isotropic and selective etching of silicon nitride layers for the manufacture of microelectronic workpieces through sequential exposure of silicon nitride layers to plasma including hydrogen radicals and plasma including fluorine radicals. For example, the sequential application of plasma etch steps can use: (1) a first plasma gas including hydrogen (H2) and argon (Ar), and (2) a second plasma gas including nitrogen trifluoride (NF3), oxygen (O2), and Ar. These plasma gases are ignited within a processing region or chamber under sufficient pressure to generate the hydrogen radicals and the fluorine radicals. Other plasma gas chemistries can also be used under sufficient pressures to generate alternating application of hydrogen radicals and fluorine radicals.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: October 27, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Sonam D. Sherpa, Alok Ranjan
  • Patent number: 10818513
    Abstract: The present disclosure provides a method for manufacturing a conductive line. The method includes steps of providing a substrate; forming a metal layer on the substrate; patterning the metal layer by etching a portion of the metal layer; and performing a post-treatment process on the patterned metal layer in a chamber by injecting a CxHyFz gas and water vapor into the chamber, such that the patterned metal layer avoids from being corroded after the post-treatment process is performed.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: October 27, 2020
    Assignee: Wuhan China Star Optoelectronics Semiconductor Display Co., Ltd.
    Inventor: Pengbin Zhang
  • Patent number: 10804113
    Abstract: A manufacturing method of a semiconductor device includes etching a film using etching gas that has a first or second molecule which has a C3F4 group and in which the number of carbon atoms is four or five. Further, the first molecule has an R1 group that bonds to a carbon atom in the C3F4 group through a double bond, and the R1 group contains carbon and also chlorine, bromine, iodine, or oxygen. Further, the second molecule has an R2 group that bonds to a carbon atom in the C3F4 group through a single bond and an R3 group that bonds to the carbon atom in the C3F4 group through a single bond, the R2 group or the R3 group or both containing carbon, and both the R2 group and the R3 group containing hydrogen, fluorine, chlorine, bromine, iodine, or oxygen.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: October 13, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Mitsunari Horiuchi, Toshiyuki Sasaki, Tomo Hasegawa
  • Patent number: 10793951
    Abstract: Apparatus for improving substrate temperature uniformity in a substrate processing chamber are provided herein. In some embodiments, a substrate support processing chamber may include a chamber body having a bottom portion and a sidewall having a slit valve opening to load and unload substrates, a pin lift mechanism, disposed in a pin lift mechanism opening formed in the bottom portion of the chamber body, having a plurality of substrate support pins coupled to the pin lift mechanism, a movable substrate support heater having substrate support portion and a shaft, and a cover plate disposed about the shaft of the movable substrate support, wherein the cover plate covers the pin lift mechanism and pin lift mechanism opening.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: October 6, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Gwo-Chuan Tzu, Kazuya Daito, Sang-Hyeob Lee
  • Patent number: 10763591
    Abstract: A slot array antenna includes: an electrically conductive member having an electrically conductive surface and slots therein, the slots being arrayed in a first direction which extends along the conductive surface; a waveguide member having an electrically conductive waveguide face which opposes the slots and extends along the first direction; and an artificial magnetic conductor extending on both sides of the waveguide member. At least one of the conductive member and the waveguide member includes dents on the conductive surface and/or the waveguide face, the dents each serving to broaden a spacing between the conductive surface and the waveguide face relative to any adjacent site. The dents include a first, second, and third dents which are adjacent to one another and consecutively follow along the first direction. A distance between centers of the first and second dents is different from a distance between centers of the second and third dents.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: September 1, 2020
    Assignees: NIDEC CORPORATION, WGR CO., LTD.
    Inventors: Hideki Kirino, Hiroyuki Kamo
  • Patent number: 10755897
    Abstract: In a plasma processing apparatus, a placement electrode includes an inner peripheral electrode for electrostatically adsorbing a wafer and an outer peripheral electrode disposed outside the inner peripheral electrode for electrostatically adsorbing the wafer, and a DC power supply unit on which the wafer is placed supplies a first radio frequency power to the inner peripheral electrode via an inner peripheral transmission path. A DC power supply unit supplies a second radio frequency power having the same frequency as the frequency of the first radio frequency power to the outer peripheral electrode via an outer peripheral transmission path. An electromagnetic wave generating power supply supplies a third radio frequency power for generating plasma.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: August 25, 2020
    Assignee: HITACHI HIGH-TECH CORPORATION
    Inventors: Norihiko Ikeda, Kazuya Yamada, Naoki Yasui
  • Patent number: 10727080
    Abstract: Methods are described herein for etching tantalum-containing films with various potential additives while still retaining other desirable patterned substrate portions. The methods include exposing a tantalum-containing film to a chlorine-containing precursor (e.g. Cl2) with a concurrent plasma. The plasma-excited chlorine-containing precursor selectively etches the tantalum-containing film and other industrially-desirable additives. Chlorine is then removed from the substrate processing region. A hydrogen-containing precursor (e.g. H2) is delivered to the substrate processing region (also with plasma excitation) to produce a relatively even and residue-free tantalum-containing surface. The methods presented remove tantalum while retaining materials elsewhere on the patterned substrate.
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: July 28, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Xikun Wang, Naomi Yoshida, Soumendra N. Barman, Nitin K. Ingle
  • Patent number: 10707086
    Abstract: Embodiments described herein relate to apparatus and methods for performing electron beam reactive plasma etching (EBRPE). In one embodiment, an apparatus for performing EBRPE processes includes an electrode formed from a material having a high secondary electron emission coefficient. In another embodiment, methods for etching a substrate include generating a plasma and bombarding an electrode with ions from the plasma to cause the electrode to emit electrons. The electrons are accelerated toward a substrate to induce etching of the substrate.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: July 7, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Yang Yang, Kartik Ramaswamy, Kenneth S. Collins, Steven Lane, Gonzalo Monroy, Lucy Zhiping Chen, Yue Guo
  • Patent number: 10707089
    Abstract: A microelectronic device includes a metal layer on a first dielectric layer. An etch stop layer is disposed over the metal layer and on the dielectric layer directly adjacent to the metal layer. The etch stop layer includes a metal oxide, and is less than 10 nanometers thick. A second dielectric layer is disposed over the etch stop layer. The second dielectric layer is removed from an etched region which extends down to the etch stop layer. The etched region extends at least partially over the metal layer. In one version of the microelectronic device, the etch stop layer may extend over the metal layer in the etched region. In another version, the etch stop layer may be removed in the etched region. The microelectronic device is formed by etching the second dielectric layer using a plasma etch process, stopping on the etch stop layer.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: July 7, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sebastian Meier, Michael Hans Enzelberger-Heim, Reiner Port
  • Patent number: 10685829
    Abstract: A substrate processing method includes a liquid film forming step of forming a liquid film of the low surface tension liquid, an opening-forming step of forming an opening in the center region of the liquid film, a liquid film removal step of removing the liquid film from the upper surface of the substrate by widening the opening, a low surface tension liquid supply step of supplying a low surface tension liquid toward a first liquid landing point which is set on the outside of the opening, a hydrophobic agent supply step of supplying a hydrophobic agent toward a second liquid landing point which is set on the outside of the opening and further from the opening than the first liquid landing point, and a liquid landing point moving step of moving the first liquid landing point and the second liquid landing point so as to follow widening of the opening.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: June 16, 2020
    Assignee: SCREEN Holdings Co., Ltd.
    Inventors: Taiki Hinode, Sadamu Fujii, Rei Takeaki
  • Patent number: 10672622
    Abstract: An etching method includes loading, first and second supplying, removing and etching steps. In the loading step, a target object is loaded into a chamber. In the first supply step, a first gas containing carbon, hydrogen and fluorine is supplied into the chamber. In the modification step, plasma of the first gas is generated to modify a surface of a mask film and a surface of an organic film which is not covered with the mask film. In the second supply step, a second gas for etching the organic film is supplied into the chamber. In the removal step, a modified layer formed on the surface of the organic film is removed by applying a first high frequency bias power. In the etching step, the organic film below the modified layer is etched by applying a second high frequency bias power lower than the first high frequency bias power.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: June 2, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Yusuke Shimizu, Akinori Kitamura, Masahiko Takahashi
  • Patent number: 10665516
    Abstract: The present invention relates to an etching method including a reaction layer forming step of forming a reaction layer by adsorption of a gas on a surface of an etching target material, a desorption step of desorbing the reaction layer after the reaction layer forming step, and a removal step of removing the reaction layer or a deposited film, characterized in that the surface of the etching target material is etched by the reaction layer forming step and the desorption step.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: May 26, 2020
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Miyako Matsui, Kenichi Kuwahara, Naoki Yasui, Masaru Izawa, Tatehito Usui, Takeshi Ohmori
  • Patent number: 10629446
    Abstract: A substrate treatment method capable of obtaining a flat processing target film. Molecules of an HF gas are adsorbed onto a corner SiO2 layer remaining in a corner portion of a groove of a wafer subjected to an oxide film removal process. An excess HF gas is discharged. An NH3 gas is supplied toward the corner SiO2 layer onto which the molecules of the HF gas are adsorbed. AFS is formed by reacting the corner SiO2 layer, the HF gas and the NH3 gas with each other. The AFS is sublimated and removed.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: April 21, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Masahiko Tomita, Hiroyuki Takahashi
  • Patent number: 10622269
    Abstract: The present invention relates to an etching method including a reaction layer forming step of forming a reaction layer by adsorption of a gas on a surface of an etching target material, a desorption step of desorbing the reaction layer after the reaction layer forming step, and a removal step of removing the reaction layer or a deposited film, characterized in that the surface of the etching target material is etched by the reaction layer forming step and the desorption step.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: April 14, 2020
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Miyako Matsui, Kenichi Kuwahara, Naoki Yasui, Masaru Izawa, Tatehito Usui, Takeshi Ohmori
  • Patent number: 10607899
    Abstract: An apparatus for and methods of repairing and manufacturing integrated circuits using the apparatus. The apparatus, comprising: a vacuum chamber containing: a movable stage configured to hold a substrate; an inspection and analysis probe; a heat source; a gas injector; and a gas manifold connecting multiple gas sources to the gas injector.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: March 31, 2020
    Assignee: International Business Machines Corporation
    Inventors: Shawn A. Adderly, Jeffrey P. Gambino, Eric A. Joseph, Anthony C. Speranza
  • Patent number: 10607851
    Abstract: Various embodiments comprise methods of selectively etching oxides over nitrides in a vapor-etch cyclic process. In one embodiment, the method includes, in a first portion of the vapor-etch cyclic process, exposing a substrate having oxide features and nitride features formed thereon to selected etchants in a vapor-phase chamber; transferring the substrate to a post-etch heat treatment chamber; and heating the substrate to remove etchant reaction products from the substrate. In a second portion of the vapor-etch cyclic process, the method continues with transferring the substrate from the post-etch heat treatment chamber to the vapor-phase chamber; exposing the substrate to the selected etchants in the vapor-phase chamber; transferring the substrate to the post-etch heat treatment chamber; and heating the substrate to remove additional etchant reaction products from the substrate. Apparatuses for performing the method and additional methods are also disclosed.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: March 31, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Andrew L. Li, Prashant Raghu, Sanjeev Sapra, Rita J. Klein, Sanh D. Tang, Sourabh Dhir
  • Patent number: 10529582
    Abstract: A plasma etching method includes performing a plasma etching using a gas containing C2F4. An emission intensity of CF2 is equal to or more than 3.5 times an emission intensity of C2 while generating plasma.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: January 7, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Mitsunari Horiuchi
  • Patent number: 10522464
    Abstract: A method includes receiving a substrate having a substrate feature; forming a first material layer over the substrate and in physical contact with the substrate feature; forming an etch mask over the first material layer; and applying a dynamic-angle (DA) plasma etching process to the first material layer through the etch mask to form a first material feature. Plasma flux of the DA plasma etching process has an angle of incidence with respect to a normal of the first material layer and the angle of incidence changes in a dynamic mode during the DA plasma etching process.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Ming Chang, Chih-Tsung Shih
  • Patent number: 10517178
    Abstract: A method for producing a via-filled substrate includes a metal film forming step of forming a metal film containing an active metal on a hole part wall surface of an insulating substrate having a hole part, a filling step of filling a conductor paste having a volume change rate before and after firing of ?10 to 20% in the hole part in which the metal film is formed, and a firing step of firing the insulating substrate in which the conductor paste is filled.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: December 24, 2019
    Assignee: Mitsuboshi Belting Ltd.
    Inventors: Osamu Mamezaki, Yoko Hayashi
  • Patent number: 10468268
    Abstract: There is provided an etching method for etching an object to be processed by using a substrate processing apparatus including a process chamber including a first electrode and a second electrode disposed opposite to the first electrode to receive the object to be processed thereon. The etching method includes a process of removing at least one of a first polymer and a second polymer by etching the object to be processed on which a pattern of the first polymer and the second polymer is formed by phase separation of a block copolymer containing the first polymer and the second polymer at a temperature lower than or equal to 10 degrees C. by using plasma of a process gas.
    Type: Grant
    Filed: August 18, 2014
    Date of Patent: November 5, 2019
    Assignee: Tokyo Electron Limited
    Inventor: Ryoichi Yoshida
  • Patent number: 10468282
    Abstract: Embodiments of the present invention provide an apparatus for transferring substrates and confining a processing environment in a chamber. One embodiment of the present invention provides a hoop assembly for using a processing chamber. The hoop assembly includes a confinement ring defining a confinement region therein, and three or more lifting fingers attached to the hoop. The three or more lifting fingers are configured to support a substrate outside the inner volume of the confinement ring.
    Type: Grant
    Filed: April 26, 2018
    Date of Patent: November 5, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Jared Ahmad Lee, Martin Jeff Salinas, Paul B. Reuter, Imad Yousif, Aniruddha Pal
  • Patent number: 10453811
    Abstract: A method of manufacturing a semiconductor structure. The method includes depositing a conductive material over a substrate, and removing a portion of the conductive material to form a conductive structure having a barrel shape. A width of a body portion of the conductive structure is greater than a width of an upper portion and a width of a bottom portion of the conductive structure.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: October 22, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-An Lin, Alan Kuo, C. C. Chang, Yu-Lung Shih
  • Patent number: 10273142
    Abstract: The present disclosure provides a structure. The structure comprises a cavity enclosed by a first substrate and a second substrate opposite to the first substrate. The structure also includes a movable membrane in the cavity. Further, the structure includes a mesa in the cavity and the mesa is protruded from a surface of the first substrate. In addition, the structure includes a dielectric layer over the mesa, wherein the dielectric layer includes a first surface in contact with the mesa and a second surface opposite to the first surface is positioned toward the cavity.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: April 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yuan-Chih Hsieh, Hsing-Lien Lin, Jung-Huei Peng, Yi-Chien Wu
  • Patent number: 10262862
    Abstract: The present disclosure provides a method of forming fine interconnection for semiconductor devices. The method includes the following steps: A substrate is provided. A first core layer is formed over the substrate. The first core layer includes a base portion, a plurality of extending line portions extending from the base portion along a first direction, and a plurality of isolated line portions isolated from the base portion. Subsequently, a spacer is formed on the sidewalls of the first core layer. A second core layer is then formed to over the substrate. The second core layer includes a plurality of surrounding line portions surrounding the plurality of isolated line portions, and includes a plurality of enclosed line portions enclosed by the plurality of extending line portions. The spacer is removed to form a plurality of openings between the first core layer and the second core layer.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: April 16, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chiang-Lin Shih, Shing-Yih Shih
  • Patent number: 10229837
    Abstract: A method for performing atomic layer etching (ALE) on a substrate is provided, including the following operations: performing a surface modification operation on a substrate surface, the surface modification operation configured to convert at least one monolayer of the substrate surface to a modified layer, wherein a bias voltage is applied during the surface modification operation, the bias voltage configured to control a depth of the substrate surface that is converted by the surface modification operation; performing a removal operation on the substrate surface, the removal operation configured to remove at least a portion of the modified layer from the substrate surface, wherein removing the portion of the modified layer is effected via a ligand exchange reaction that is configured to volatilize the portion of the modified layer. A plasma treatment can be performed to remove residues from the substrate surface following the removal operation.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: March 12, 2019
    Assignee: Lam Research Corporation
    Inventors: Andreas Fischer, Thorsten Lill, Richard Janek
  • Patent number: 10199223
    Abstract: An etch stop layer comprises a metal oxide comprising a metal selected from the group consisting of metals of Group 4 of the periodic table, metals of Group 5 of the periodic table, metals of Group 6 of the periodic table, and yttrium. The metal oxide forms exceptionally thin layers that are resistant to ashing and HF exposure. Subjecting the etch stop layer to both ashing and HF etch processes removes less than 0.3 nm of the thickness of the etch stop layer, and more preferably less than 0.25 nm. The etch stop layer may be thin and may have a thickness of about 0.5-2 nm. In some embodiments, the etch stop layer comprises tantalum oxide (TaO).
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: February 5, 2019
    Assignee: ASM IP HOLDING B.V.
    Inventors: Dieter Pierreux, Werner Knaepen, Bert Jongbloed
  • Patent number: 10192918
    Abstract: An image sensor includes a substrate having a pixel region and a periphery region. The image sensor further includes a first isolation structure formed in the pixel region; the first isolation structure including a first trench having a first depth. The image sensor further includes a second isolation structure formed in the periphery region; the second isolation structure including a second trench having a second depth. The second depth is greater than the first depth.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: January 29, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jeng-Shyan Lin, Dun-Nian Yaung, Jen-Cheng Liu, Chun-Chieh Chuang, Volume Chien
  • Patent number: 10090168
    Abstract: The present invention is a plasma etching method comprising subjecting a silicon-containing film to plasma etching using a process gas, the process gas comprising a linear saturated fluorohydrocarbon compound represented by a formula (1), and a gaseous fluorine-containing compound (excluding the compound represented by the formula (1)) that functions as a fluorine radical source under plasma etching conditions, wherein x represents 3 or 4, y represents an integer from 5 to 9, and z represents an integer from 1 to 3. The present invention provides a plasma etching method that can selectively etch the silicon-containing film with respect to the mask, and form a hole or a trench having a good shape within a short time.
    Type: Grant
    Filed: January 19, 2016
    Date of Patent: October 2, 2018
    Assignee: ZEON CORPORATION
    Inventor: Hirotoshi Inui
  • Patent number: 10043668
    Abstract: Methods for preparing a patterned directed self-assembly layer generally include providing a substrate having a block copolymer layer including a first phase-separated polymer defining a first pattern in the block copolymer layer and a second phase-separated polymer defining a second pattern in the block copolymer layer. The block polymer layer is exposed to a gas pulsing carbon monoxide polymer. The gas pulsing is configured to provide multiple cycles of an etching plasma and a deposition plasma to selectively remove the second pattern of the second phase-separated polymer while leaving behind the first pattern of the first phase-separated polymer on the substrate.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: August 7, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sebastian U. Engelmann, Ashish V. Jagtiani, Hiroyuki Miyazoe, Hsinyu Tsai
  • Patent number: 10032604
    Abstract: Embodiments of an apparatus having an improved coil antenna assembly with a remote plasma source and an electron beam generation system that can provide enhanced plasma in a processing chamber. In one embodiment, a plasma processing chamber includes a chamber body, a lid enclosing an interior volume of the chamber body, a substrate support disposed in the interior volume, a dual inductively coupled source including a coil antenna assembly coupled to the chamber body through the lid, and a remote plasma source coupled to the chamber body through the lid.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: July 24, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventor: Rajinder Dhindsa
  • Patent number: 10014225
    Abstract: One aspect of the present disclosure is a method of fabricating metal gate by forming a silicon-nitride layer (SiN) over a dummy gate at a second metal gate type transistor region (e.g. NMOS) avoid dummy gate loss during a CMP process for a PMOS gate. The method can comprise after performing a patterning process to remove hard masks at PMOS and NMOS regions, forming a SiN layer over the NMOS region; performing a patterning process to open the PMOS region and filling gate materials in the PMOS region; performing a CMP to polish a top surface of PMOS such that the polishing stops at SiN. In this way, dummy gate loss can be reduced during the first aluminum CMP step and thus can reduce initial height of dummy gate as compared to the convention method, and improve the filling process of the dummy gate as compared to the conventional method.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: July 3, 2018
    Assignee: SHANGHAI HUALI MICROELECTRONICS CORPORATION
    Inventor: Yu Bao
  • Patent number: 9991134
    Abstract: Systems, chambers, and processes are provided for controlling process defects caused by moisture contamination. The systems may provide configurations for chambers to perform multiple operations in a vacuum or controlled environment. The chambers may include configurations to provide additional processing capabilities in combination chamber designs. The methods may provide for the limiting, prevention, and correction of aging defects that may be caused as a result of etching processes performed by system tools.
    Type: Grant
    Filed: April 7, 2014
    Date of Patent: June 5, 2018
    Assignee: Applied Materials, Inc.
    Inventors: Anchuan Wang, Xinglong Chen, Zihui Li, Hiroshi Hamana, Zhijun Chen, Ching-Mei Hsu, Jiayin Huang, Nitin K. Ingle, Dmitry Lubomirsky, Shankar Venkataraman, Randhir Thakur
  • Patent number: 9991128
    Abstract: Methods and apparatus for etching substrates using self-limiting reactions based on removal energy thresholds determined by evaluating the material to be etched and the chemistries used to etch the material involve flow of continuous plasma. Process conditions permit controlled, self-limiting anisotropic etching without alternating between chemistries used to etch material on a substrate. A well-controlled etch front allows a synergistic effect of reactive radicals and inert ions to perform the etching, such that material is etched when the substrate is modified by reactive radicals and removed by inert ions, but not etched when material is modified by reactive radicals but no inert ions are present, or when inert ions are present but material is not modified by reactive radicals.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: June 5, 2018
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Zhongkui Tan, Yiting Zhang, Ying Wu, Qing Xu, Qian Fu, Yoko Yamaguchi, Lin Cui
  • Patent number: 9947527
    Abstract: A method of manufacturing a semiconductor device according to the invention includes the step S1 of cleaning the silicon carbide substrate 1 surface, the step S2 of bringing a material gas into a plasma and irradiating the atoms contained in the material gas to silicon carbide substrate 1 for growing silicon nitride film 2 on silicon carbide substrate 1, the step S3 of depositing silicon oxide film 3 on silicon nitride film 2 by the ECR plasma CVD method, and the step S4 of annealing silicon carbide substrate 1 including silicon nitride film 2 and silicon oxide film 3 formed thereon in a nitrogen atmosphere. By the method of manufacturing a semiconductor device according to the invention, a semiconductor device that exhibits excellent interface properties including an interface state density and a flat band voltage is obtained.
    Type: Grant
    Filed: May 21, 2012
    Date of Patent: April 17, 2018
    Assignees: FUJI ELECTRIC CO., LTD., KYUSHU UNIVERSITY, NATIONAL UNIVERSITY CORPORATION
    Inventors: Hiroshi Nakashima, Haigui Yang, Hitoshi Sumida
  • Patent number: 9919916
    Abstract: A method of forming microneedles where through a series of coating and etching processes microneedles are formed from a surface as an array. The microneedles have a bevelled end and bore which are formed as part of the process with no need to use a post manufacturing process to finish the microneedle.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: March 20, 2018
    Assignee: Semitechnologies Llimited
    Inventors: Yufei Lui, Owen Guy
  • Patent number: 9922803
    Abstract: The invention provides a plasma processing device, wherein the upper electrode and the lower electrode are in the vacuum chamber. The chip is placed in the lower electrode. The first plate is placed between the upper electrode and the lower electrode, and the first plate includes a plurality of first voids. The second plate is placed between the first plate and the lower electrode, and the second plate includes a plurality of second voids. The high frequency power is provided by the upper electrode and the lower electrode in the vacuum chamber, and the plasma is generated between the third plate and the upper electrode. The plasma is filtered by the third void, the first void, and the second void.
    Type: Grant
    Filed: October 17, 2012
    Date of Patent: March 20, 2018
    Assignee: CHANG GUNG UNIVERSITY
    Inventors: Chi-Hsien Huang, Chao-Sung Lai, Chien Chou, Chu-Fa Chan
  • Patent number: 9922842
    Abstract: A method for heat treatment of a plurality of semiconductor wafers horizontally placed on a supporting member coated with SiC in a vertical heat treatment furnace includes performing heat treatments while switching the supporting member and a heat treatment condition such that the supporting member is continuously used in a heat treatment under either one of a first condition and a second condition for a certain period of time and then continuously used in a heat treatment under the other condition for a certain period of time, wherein the heat treatment under the first condition is performed at 1000° C. or higher in an atmosphere containing a rare gas and not containing oxygen, and the heat treatment under the second condition is performed at 1000° C. or higher in an atmosphere containing oxygen and not containing a rare gas. As a result, slip dislocation can be inhibited.
    Type: Grant
    Filed: October 27, 2014
    Date of Patent: March 20, 2018
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventor: Masahiro Kato
  • Patent number: 9893215
    Abstract: A solar cell with a dielectric double layer and also a method for the manufacture thereof are described. A first dielectric layer (3), which contains aluminum oxide or consists of aluminum oxide, and a second, hydrogen-containing dielectric layer (5) are produced by means of atomic layer deposition, allowing very good passivation of the surface of solar cells to be achieved.
    Type: Grant
    Filed: November 6, 2008
    Date of Patent: February 13, 2018
    Assignees: HANWHA Q CELLS CO., LTD, SOLARWORLD INDUSTRIES GMBH
    Inventors: Jan Schmidt, Bram Hoex
  • Patent number: 9842843
    Abstract: In a method of manufacturing an SRAM device, an insulating layer is formed over a substrate. First dummy patterns are formed over the insulating layer. Sidewall spacer layers, as second dummy patterns, are formed on sidewalls of the first dummy patterns. The first dummy patterns are removed, thereby leaving the second dummy patterns over the insulating layer. After removing the first dummy patterns, the second dummy patterns are divided. A mask layer is formed over the insulating layer and between the divided second dummy patterns. After forming the mask layer, the divided second dummy patterns are removed, thereby forming a hard mask layer having openings that correspond to the patterned second dummy patterns. The insulating layer is formed by using the hard mask layer as an etching mask, thereby forming via openings in the insulating layer. A conductive material is filled in the via openings, thereby forming contact bars.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: December 12, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jhon Jhy Liaw
  • Patent number: 9786664
    Abstract: A dual gate CMOS structure including a semiconductor substrate; a first channel structure including a first semiconductor material and a second channel structure including a second semiconductor material on the substrate. The first semiconductor material including SixGe1-x where x=0 to 1 and the second semiconductor material including a group III-V compound material. A first gate stack on the first channel structure includes: a first native oxide layer as an interface control layer, the first native oxide layer comprising an oxide of the first semiconductor material; a first high-k dielectric layer; a first metal gate layer. A second gate stack on the second channel structure includes a second high-k dielectric layer; a second metal gate layer. The interface between the second channel structure and the second high-k dielectric layer is free of any native oxides of the second semiconductor material.
    Type: Grant
    Filed: February 10, 2016
    Date of Patent: October 10, 2017
    Assignee: International Business Machines Corporation
    Inventors: Lukas Czornomaz, Veeresh Vidyadhar Deshpande, Vladimir Djara, Jean Fompeyrine
  • Patent number: 9768029
    Abstract: A method of forming a semiconductor device is disclosed. A substrate having a dielectric layer thereon is provided. The dielectric layer has a gate trench therein and a gate dielectric layer is formed on a bottom of the gate trench. A work function metal layer and a top barrier layer are sequentially formed in the gate trench. A treatment is performed to the top barrier layer so as to form a silicon-containing top barrier layer. A low-resistivity metal layer is formed in the gate trench.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: September 19, 2017
    Assignee: United Microelectronics Corp.
    Inventors: Chun-Hsien Lin, Min-Hsien Chen
  • Patent number: 9721803
    Abstract: In one embodiment of the present invention, an etching method for a substrate to be processed comprises: (a1) a step in which etchant gas is supplied into a processing container than accommodates a substrate to be processed; (b1) a step in which the inside of the processing container is evacuated; (c1) a step in which a noble gas is supplied into the processing container; and (d1) a step in which microwaves are supplied into the processing container so as to excite the plasma of the noble gas inside the processing container. The sequential process including the step of supplying the etchant of supplying the etchant gas, the evacuating step, the step of supplying the noble gas, and the step of exciting the plasma of the noble gas may be repeated.
    Type: Grant
    Filed: April 10, 2013
    Date of Patent: August 1, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Hiroyuki Takaba
  • Patent number: 9704974
    Abstract: A process of manufacturing a Fin-FET device, and the process includes following steps. An active fin structure and a dummy fin structure are formed from a substrate, and an isolation layer is covered over the active fin structure and the dummy fin structure. Then, the isolation layer above the dummy fin structure is removed, and the dummy fin structure is selectively etched, which a selective ratio of the dummy fin structure to the isolation layer is over 8.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: July 11, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Wei Chang, An-Shen Chang, Eric Chih-Fang Liu, Ryan Chia-Jen Chen, Chia-Tai Lin, Chih-Tang Peng
  • Patent number: 9698013
    Abstract: Trenches (and processes for forming the trenches) are provided that reduce or prevent crystaline defects in selective epitaxial growth of type III-V or Germanium (Ge) material (e.g., a “buffer” material) from a top surface of a substrate material. The defects may result from collision of selective epitaxial sidewall growth with oxide trench sidewalls. Such trenches include (1) a trench having sloped sidewalls at an angle of between 40 degrees and 70 degrees (e.g., such as 55 degrees) with respect to a substrate surface; and/or (2) a combined trench having an upper trench over and surrounding the opening of a lower trench (e.g., the lower trench may have the sloped sidewalls, short vertical walls, or tall vertical walls). These trenches reduce or prevent defects in the epitaxial sidewall growth where the growth touches or grows against vertical sidewalls of a trench it is grown in.
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: July 4, 2017
    Assignee: Intel Corporation
    Inventors: Niloy Mukherjee, Niti Goel, Sanaz K. Gardner, Pragyansri Pathi, Matthew V. Metz, Sansaptak Dasgupta, Seung Hoon Sung, James M. Powers, Gilbert Dewey, Benjamin Chu-Kung, Jack T. Kavalieros, Robert S. Chau
  • Patent number: 9653318
    Abstract: Methods for processing a substrate are described herein. Methods can include positioning a substrate with an exposed surface comprising a silicon oxide layer in a processing chamber, biasing the substrate, treating the substrate to roughen a portion of the silicon oxide layer, heating the substrate to a first temperature, exposing the exposed surface of the substrate to ammonium fluoride to form one or more volatile products while maintaining the first temperature, and heating the substrate to a second temperature, which is higher than the first temperature, to sublimate the volatile products.
    Type: Grant
    Filed: January 26, 2016
    Date of Patent: May 16, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: David T. Or, Joshua Collins, Mei Chang
  • Patent number: 9653291
    Abstract: Native oxides and residue are removed from surfaces of a substrate by performing a multiple-stage native oxide cleaning process. In one example, the method for removing native oxides from a substrate includes supplying a first gas mixture including an inert gas onto a surface of a material layer disposed on a substrate into a first processing chamber, wherein the material layer is a III-V group containing layer for a first period of time, supplying a second gas mixture including an inert gas and a hydrogen containing gas onto the surface of the material layer for a second period of time, and supplying a third gas mixture including a hydrogen containing gas to the surface of the material layer while maintaining the substrate at a temperature less than 550 degrees Celsius.
    Type: Grant
    Filed: November 13, 2014
    Date of Patent: May 16, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Chun Yan, Xinyu Bao
  • Patent number: 9647206
    Abstract: Provided is a method for etching an etching target layer of a workpiece. The workpiece has a mask on the etching target layer. The etching target layer and the mask are formed from respective materials for which etching efficiency by a plasma of a rare gas having an atomic number greater than an atomic number of argon is higher than etching efficiency for the materials by a plasma of argon gas. The mask is formed from a material having a melting point higher than that of the etching target layer. The method includes (a) exposing the workpiece to a plasma of a first process gas containing a first rare gas having an atomic number greater than the atomic number of argon, and (b) exposing the workpiece to a plasma of a second process gas containing a second rare gas having an atomic number less than the atomic number of argon.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: May 9, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Mitsuru Hashimoto, Takashi Sone, Eiichi Nishimura, Keiichi Shimoda
  • Patent number: 9570312
    Abstract: Provided is a plasma etching method capable of favorably forming masks used when etching a multilayer film. This plasma etching method for etching boron-doped amorphous carbon involves using a plasma of a gas mixture comprising a chlorine gas and an oxygen gas, and setting the temperature of a mounting stage (3) to 100° C. or greater.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: February 14, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Ryohei Takeda, Mitsuhiro Tomura, Akinori Kitamura, Shinji Higashitsutsumi, Hiroto Ohtake, Takashi Tsukamoto
  • Patent number: 9564341
    Abstract: A method of etching silicon oxide on patterned heterogeneous structures is described and includes a gas phase etch using anhydrous vapor-phase HF. The HF is combined with an additional precursor in the substrate processing region. The HF may enter through one channel(s) and the additional precursor may flow through another channel(s) prior to forming the combination. The combination may be formed near the substrate. The silicon oxide etch selectivity relative to silicon nitride from is selectable from about one to several hundred. In all cases, the etch rate of exposed silicon, if present, is negligible. No precursors are excited in any plasma either outside or inside the substrate processing region according to embodiments. The additional precursor may be a nitrogen-and-hydrogen-containing precursor such as ammonia.
    Type: Grant
    Filed: August 4, 2015
    Date of Patent: February 7, 2017
    Assignee: Applied Materials, Inc.
    Inventors: Jingjing Xu, Anchuan Wang, Nitin K. Ingle
  • Patent number: 9543163
    Abstract: Methods for etching a material layer disposed on the substrate using a combination of a main etching step and a cyclical etching process are provided. The method includes performing a main etching process in a processing chamber to an oxide layer, forming a feature with a first predetermined depth in the oxide layer, performing a treatment process on the substrate by supplying a treatment gas mixture into the processing chamber to treat the etched feature in the oxide layer, performing a chemical etching process on the substrate by supplying a chemical etching gas mixture into the processing chamber, wherein the chemical etching gas includes at least an ammonium gas and a nitrogen trifluoride, wherein the chemical etching process further etches the feature to a second predetermined depth, and performing a transition process on the etched substrate by supplying a transition gas mixture into the processing chamber.
    Type: Grant
    Filed: October 21, 2013
    Date of Patent: January 10, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Mang-Mang Ling, Jungmin Ko, Sean S. Kang, Jeremiah T. Pender, Srinivas D. Nemani, Bradley Howard