Vapor Phase Etching (i.e., Dry Etching) Patents (Class 438/706)
  • Patent number: 10273142
    Abstract: The present disclosure provides a structure. The structure comprises a cavity enclosed by a first substrate and a second substrate opposite to the first substrate. The structure also includes a movable membrane in the cavity. Further, the structure includes a mesa in the cavity and the mesa is protruded from a surface of the first substrate. In addition, the structure includes a dielectric layer over the mesa, wherein the dielectric layer includes a first surface in contact with the mesa and a second surface opposite to the first surface is positioned toward the cavity.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: April 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yuan-Chih Hsieh, Hsing-Lien Lin, Jung-Huei Peng, Yi-Chien Wu
  • Patent number: 10262862
    Abstract: The present disclosure provides a method of forming fine interconnection for semiconductor devices. The method includes the following steps: A substrate is provided. A first core layer is formed over the substrate. The first core layer includes a base portion, a plurality of extending line portions extending from the base portion along a first direction, and a plurality of isolated line portions isolated from the base portion. Subsequently, a spacer is formed on the sidewalls of the first core layer. A second core layer is then formed to over the substrate. The second core layer includes a plurality of surrounding line portions surrounding the plurality of isolated line portions, and includes a plurality of enclosed line portions enclosed by the plurality of extending line portions. The spacer is removed to form a plurality of openings between the first core layer and the second core layer.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: April 16, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chiang-Lin Shih, Shing-Yih Shih
  • Patent number: 10229837
    Abstract: A method for performing atomic layer etching (ALE) on a substrate is provided, including the following operations: performing a surface modification operation on a substrate surface, the surface modification operation configured to convert at least one monolayer of the substrate surface to a modified layer, wherein a bias voltage is applied during the surface modification operation, the bias voltage configured to control a depth of the substrate surface that is converted by the surface modification operation; performing a removal operation on the substrate surface, the removal operation configured to remove at least a portion of the modified layer from the substrate surface, wherein removing the portion of the modified layer is effected via a ligand exchange reaction that is configured to volatilize the portion of the modified layer. A plasma treatment can be performed to remove residues from the substrate surface following the removal operation.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: March 12, 2019
    Assignee: Lam Research Corporation
    Inventors: Andreas Fischer, Thorsten Lill, Richard Janek
  • Patent number: 10199223
    Abstract: An etch stop layer comprises a metal oxide comprising a metal selected from the group consisting of metals of Group 4 of the periodic table, metals of Group 5 of the periodic table, metals of Group 6 of the periodic table, and yttrium. The metal oxide forms exceptionally thin layers that are resistant to ashing and HF exposure. Subjecting the etch stop layer to both ashing and HF etch processes removes less than 0.3 nm of the thickness of the etch stop layer, and more preferably less than 0.25 nm. The etch stop layer may be thin and may have a thickness of about 0.5-2 nm. In some embodiments, the etch stop layer comprises tantalum oxide (TaO).
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: February 5, 2019
    Assignee: ASM IP HOLDING B.V.
    Inventors: Dieter Pierreux, Werner Knaepen, Bert Jongbloed
  • Patent number: 10192918
    Abstract: An image sensor includes a substrate having a pixel region and a periphery region. The image sensor further includes a first isolation structure formed in the pixel region; the first isolation structure including a first trench having a first depth. The image sensor further includes a second isolation structure formed in the periphery region; the second isolation structure including a second trench having a second depth. The second depth is greater than the first depth.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: January 29, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jeng-Shyan Lin, Dun-Nian Yaung, Jen-Cheng Liu, Chun-Chieh Chuang, Volume Chien
  • Patent number: 10090168
    Abstract: The present invention is a plasma etching method comprising subjecting a silicon-containing film to plasma etching using a process gas, the process gas comprising a linear saturated fluorohydrocarbon compound represented by a formula (1), and a gaseous fluorine-containing compound (excluding the compound represented by the formula (1)) that functions as a fluorine radical source under plasma etching conditions, wherein x represents 3 or 4, y represents an integer from 5 to 9, and z represents an integer from 1 to 3. The present invention provides a plasma etching method that can selectively etch the silicon-containing film with respect to the mask, and form a hole or a trench having a good shape within a short time.
    Type: Grant
    Filed: January 19, 2016
    Date of Patent: October 2, 2018
    Assignee: ZEON CORPORATION
    Inventor: Hirotoshi Inui
  • Patent number: 10043668
    Abstract: Methods for preparing a patterned directed self-assembly layer generally include providing a substrate having a block copolymer layer including a first phase-separated polymer defining a first pattern in the block copolymer layer and a second phase-separated polymer defining a second pattern in the block copolymer layer. The block polymer layer is exposed to a gas pulsing carbon monoxide polymer. The gas pulsing is configured to provide multiple cycles of an etching plasma and a deposition plasma to selectively remove the second pattern of the second phase-separated polymer while leaving behind the first pattern of the first phase-separated polymer on the substrate.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: August 7, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sebastian U. Engelmann, Ashish V. Jagtiani, Hiroyuki Miyazoe, Hsinyu Tsai
  • Patent number: 10032604
    Abstract: Embodiments of an apparatus having an improved coil antenna assembly with a remote plasma source and an electron beam generation system that can provide enhanced plasma in a processing chamber. In one embodiment, a plasma processing chamber includes a chamber body, a lid enclosing an interior volume of the chamber body, a substrate support disposed in the interior volume, a dual inductively coupled source including a coil antenna assembly coupled to the chamber body through the lid, and a remote plasma source coupled to the chamber body through the lid.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: July 24, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventor: Rajinder Dhindsa
  • Patent number: 10014225
    Abstract: One aspect of the present disclosure is a method of fabricating metal gate by forming a silicon-nitride layer (SiN) over a dummy gate at a second metal gate type transistor region (e.g. NMOS) avoid dummy gate loss during a CMP process for a PMOS gate. The method can comprise after performing a patterning process to remove hard masks at PMOS and NMOS regions, forming a SiN layer over the NMOS region; performing a patterning process to open the PMOS region and filling gate materials in the PMOS region; performing a CMP to polish a top surface of PMOS such that the polishing stops at SiN. In this way, dummy gate loss can be reduced during the first aluminum CMP step and thus can reduce initial height of dummy gate as compared to the convention method, and improve the filling process of the dummy gate as compared to the conventional method.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: July 3, 2018
    Assignee: SHANGHAI HUALI MICROELECTRONICS CORPORATION
    Inventor: Yu Bao
  • Patent number: 9991128
    Abstract: Methods and apparatus for etching substrates using self-limiting reactions based on removal energy thresholds determined by evaluating the material to be etched and the chemistries used to etch the material involve flow of continuous plasma. Process conditions permit controlled, self-limiting anisotropic etching without alternating between chemistries used to etch material on a substrate. A well-controlled etch front allows a synergistic effect of reactive radicals and inert ions to perform the etching, such that material is etched when the substrate is modified by reactive radicals and removed by inert ions, but not etched when material is modified by reactive radicals but no inert ions are present, or when inert ions are present but material is not modified by reactive radicals.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: June 5, 2018
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Zhongkui Tan, Yiting Zhang, Ying Wu, Qing Xu, Qian Fu, Yoko Yamaguchi, Lin Cui
  • Patent number: 9991134
    Abstract: Systems, chambers, and processes are provided for controlling process defects caused by moisture contamination. The systems may provide configurations for chambers to perform multiple operations in a vacuum or controlled environment. The chambers may include configurations to provide additional processing capabilities in combination chamber designs. The methods may provide for the limiting, prevention, and correction of aging defects that may be caused as a result of etching processes performed by system tools.
    Type: Grant
    Filed: April 7, 2014
    Date of Patent: June 5, 2018
    Assignee: Applied Materials, Inc.
    Inventors: Anchuan Wang, Xinglong Chen, Zihui Li, Hiroshi Hamana, Zhijun Chen, Ching-Mei Hsu, Jiayin Huang, Nitin K. Ingle, Dmitry Lubomirsky, Shankar Venkataraman, Randhir Thakur
  • Patent number: 9947527
    Abstract: A method of manufacturing a semiconductor device according to the invention includes the step S1 of cleaning the silicon carbide substrate 1 surface, the step S2 of bringing a material gas into a plasma and irradiating the atoms contained in the material gas to silicon carbide substrate 1 for growing silicon nitride film 2 on silicon carbide substrate 1, the step S3 of depositing silicon oxide film 3 on silicon nitride film 2 by the ECR plasma CVD method, and the step S4 of annealing silicon carbide substrate 1 including silicon nitride film 2 and silicon oxide film 3 formed thereon in a nitrogen atmosphere. By the method of manufacturing a semiconductor device according to the invention, a semiconductor device that exhibits excellent interface properties including an interface state density and a flat band voltage is obtained.
    Type: Grant
    Filed: May 21, 2012
    Date of Patent: April 17, 2018
    Assignees: FUJI ELECTRIC CO., LTD., KYUSHU UNIVERSITY, NATIONAL UNIVERSITY CORPORATION
    Inventors: Hiroshi Nakashima, Haigui Yang, Hitoshi Sumida
  • Patent number: 9919916
    Abstract: A method of forming microneedles where through a series of coating and etching processes microneedles are formed from a surface as an array. The microneedles have a bevelled end and bore which are formed as part of the process with no need to use a post manufacturing process to finish the microneedle.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: March 20, 2018
    Assignee: Semitechnologies Llimited
    Inventors: Yufei Lui, Owen Guy
  • Patent number: 9922803
    Abstract: The invention provides a plasma processing device, wherein the upper electrode and the lower electrode are in the vacuum chamber. The chip is placed in the lower electrode. The first plate is placed between the upper electrode and the lower electrode, and the first plate includes a plurality of first voids. The second plate is placed between the first plate and the lower electrode, and the second plate includes a plurality of second voids. The high frequency power is provided by the upper electrode and the lower electrode in the vacuum chamber, and the plasma is generated between the third plate and the upper electrode. The plasma is filtered by the third void, the first void, and the second void.
    Type: Grant
    Filed: October 17, 2012
    Date of Patent: March 20, 2018
    Assignee: CHANG GUNG UNIVERSITY
    Inventors: Chi-Hsien Huang, Chao-Sung Lai, Chien Chou, Chu-Fa Chan
  • Patent number: 9922842
    Abstract: A method for heat treatment of a plurality of semiconductor wafers horizontally placed on a supporting member coated with SiC in a vertical heat treatment furnace includes performing heat treatments while switching the supporting member and a heat treatment condition such that the supporting member is continuously used in a heat treatment under either one of a first condition and a second condition for a certain period of time and then continuously used in a heat treatment under the other condition for a certain period of time, wherein the heat treatment under the first condition is performed at 1000° C. or higher in an atmosphere containing a rare gas and not containing oxygen, and the heat treatment under the second condition is performed at 1000° C. or higher in an atmosphere containing oxygen and not containing a rare gas. As a result, slip dislocation can be inhibited.
    Type: Grant
    Filed: October 27, 2014
    Date of Patent: March 20, 2018
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventor: Masahiro Kato
  • Patent number: 9893215
    Abstract: A solar cell with a dielectric double layer and also a method for the manufacture thereof are described. A first dielectric layer (3), which contains aluminum oxide or consists of aluminum oxide, and a second, hydrogen-containing dielectric layer (5) are produced by means of atomic layer deposition, allowing very good passivation of the surface of solar cells to be achieved.
    Type: Grant
    Filed: November 6, 2008
    Date of Patent: February 13, 2018
    Assignees: HANWHA Q CELLS CO., LTD, SOLARWORLD INDUSTRIES GMBH
    Inventors: Jan Schmidt, Bram Hoex
  • Patent number: 9842843
    Abstract: In a method of manufacturing an SRAM device, an insulating layer is formed over a substrate. First dummy patterns are formed over the insulating layer. Sidewall spacer layers, as second dummy patterns, are formed on sidewalls of the first dummy patterns. The first dummy patterns are removed, thereby leaving the second dummy patterns over the insulating layer. After removing the first dummy patterns, the second dummy patterns are divided. A mask layer is formed over the insulating layer and between the divided second dummy patterns. After forming the mask layer, the divided second dummy patterns are removed, thereby forming a hard mask layer having openings that correspond to the patterned second dummy patterns. The insulating layer is formed by using the hard mask layer as an etching mask, thereby forming via openings in the insulating layer. A conductive material is filled in the via openings, thereby forming contact bars.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: December 12, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jhon Jhy Liaw
  • Patent number: 9786664
    Abstract: A dual gate CMOS structure including a semiconductor substrate; a first channel structure including a first semiconductor material and a second channel structure including a second semiconductor material on the substrate. The first semiconductor material including SixGe1-x where x=0 to 1 and the second semiconductor material including a group III-V compound material. A first gate stack on the first channel structure includes: a first native oxide layer as an interface control layer, the first native oxide layer comprising an oxide of the first semiconductor material; a first high-k dielectric layer; a first metal gate layer. A second gate stack on the second channel structure includes a second high-k dielectric layer; a second metal gate layer. The interface between the second channel structure and the second high-k dielectric layer is free of any native oxides of the second semiconductor material.
    Type: Grant
    Filed: February 10, 2016
    Date of Patent: October 10, 2017
    Assignee: International Business Machines Corporation
    Inventors: Lukas Czornomaz, Veeresh Vidyadhar Deshpande, Vladimir Djara, Jean Fompeyrine
  • Patent number: 9768029
    Abstract: A method of forming a semiconductor device is disclosed. A substrate having a dielectric layer thereon is provided. The dielectric layer has a gate trench therein and a gate dielectric layer is formed on a bottom of the gate trench. A work function metal layer and a top barrier layer are sequentially formed in the gate trench. A treatment is performed to the top barrier layer so as to form a silicon-containing top barrier layer. A low-resistivity metal layer is formed in the gate trench.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: September 19, 2017
    Assignee: United Microelectronics Corp.
    Inventors: Chun-Hsien Lin, Min-Hsien Chen
  • Patent number: 9721803
    Abstract: In one embodiment of the present invention, an etching method for a substrate to be processed comprises: (a1) a step in which etchant gas is supplied into a processing container than accommodates a substrate to be processed; (b1) a step in which the inside of the processing container is evacuated; (c1) a step in which a noble gas is supplied into the processing container; and (d1) a step in which microwaves are supplied into the processing container so as to excite the plasma of the noble gas inside the processing container. The sequential process including the step of supplying the etchant of supplying the etchant gas, the evacuating step, the step of supplying the noble gas, and the step of exciting the plasma of the noble gas may be repeated.
    Type: Grant
    Filed: April 10, 2013
    Date of Patent: August 1, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Hiroyuki Takaba
  • Patent number: 9704974
    Abstract: A process of manufacturing a Fin-FET device, and the process includes following steps. An active fin structure and a dummy fin structure are formed from a substrate, and an isolation layer is covered over the active fin structure and the dummy fin structure. Then, the isolation layer above the dummy fin structure is removed, and the dummy fin structure is selectively etched, which a selective ratio of the dummy fin structure to the isolation layer is over 8.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: July 11, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Wei Chang, An-Shen Chang, Eric Chih-Fang Liu, Ryan Chia-Jen Chen, Chia-Tai Lin, Chih-Tang Peng
  • Patent number: 9698013
    Abstract: Trenches (and processes for forming the trenches) are provided that reduce or prevent crystaline defects in selective epitaxial growth of type III-V or Germanium (Ge) material (e.g., a “buffer” material) from a top surface of a substrate material. The defects may result from collision of selective epitaxial sidewall growth with oxide trench sidewalls. Such trenches include (1) a trench having sloped sidewalls at an angle of between 40 degrees and 70 degrees (e.g., such as 55 degrees) with respect to a substrate surface; and/or (2) a combined trench having an upper trench over and surrounding the opening of a lower trench (e.g., the lower trench may have the sloped sidewalls, short vertical walls, or tall vertical walls). These trenches reduce or prevent defects in the epitaxial sidewall growth where the growth touches or grows against vertical sidewalls of a trench it is grown in.
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: July 4, 2017
    Assignee: Intel Corporation
    Inventors: Niloy Mukherjee, Niti Goel, Sanaz K. Gardner, Pragyansri Pathi, Matthew V. Metz, Sansaptak Dasgupta, Seung Hoon Sung, James M. Powers, Gilbert Dewey, Benjamin Chu-Kung, Jack T. Kavalieros, Robert S. Chau
  • Patent number: 9653291
    Abstract: Native oxides and residue are removed from surfaces of a substrate by performing a multiple-stage native oxide cleaning process. In one example, the method for removing native oxides from a substrate includes supplying a first gas mixture including an inert gas onto a surface of a material layer disposed on a substrate into a first processing chamber, wherein the material layer is a III-V group containing layer for a first period of time, supplying a second gas mixture including an inert gas and a hydrogen containing gas onto the surface of the material layer for a second period of time, and supplying a third gas mixture including a hydrogen containing gas to the surface of the material layer while maintaining the substrate at a temperature less than 550 degrees Celsius.
    Type: Grant
    Filed: November 13, 2014
    Date of Patent: May 16, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Chun Yan, Xinyu Bao
  • Patent number: 9653318
    Abstract: Methods for processing a substrate are described herein. Methods can include positioning a substrate with an exposed surface comprising a silicon oxide layer in a processing chamber, biasing the substrate, treating the substrate to roughen a portion of the silicon oxide layer, heating the substrate to a first temperature, exposing the exposed surface of the substrate to ammonium fluoride to form one or more volatile products while maintaining the first temperature, and heating the substrate to a second temperature, which is higher than the first temperature, to sublimate the volatile products.
    Type: Grant
    Filed: January 26, 2016
    Date of Patent: May 16, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: David T. Or, Joshua Collins, Mei Chang
  • Patent number: 9647206
    Abstract: Provided is a method for etching an etching target layer of a workpiece. The workpiece has a mask on the etching target layer. The etching target layer and the mask are formed from respective materials for which etching efficiency by a plasma of a rare gas having an atomic number greater than an atomic number of argon is higher than etching efficiency for the materials by a plasma of argon gas. The mask is formed from a material having a melting point higher than that of the etching target layer. The method includes (a) exposing the workpiece to a plasma of a first process gas containing a first rare gas having an atomic number greater than the atomic number of argon, and (b) exposing the workpiece to a plasma of a second process gas containing a second rare gas having an atomic number less than the atomic number of argon.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: May 9, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Mitsuru Hashimoto, Takashi Sone, Eiichi Nishimura, Keiichi Shimoda
  • Patent number: 9570312
    Abstract: Provided is a plasma etching method capable of favorably forming masks used when etching a multilayer film. This plasma etching method for etching boron-doped amorphous carbon involves using a plasma of a gas mixture comprising a chlorine gas and an oxygen gas, and setting the temperature of a mounting stage (3) to 100° C. or greater.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: February 14, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Ryohei Takeda, Mitsuhiro Tomura, Akinori Kitamura, Shinji Higashitsutsumi, Hiroto Ohtake, Takashi Tsukamoto
  • Patent number: 9564341
    Abstract: A method of etching silicon oxide on patterned heterogeneous structures is described and includes a gas phase etch using anhydrous vapor-phase HF. The HF is combined with an additional precursor in the substrate processing region. The HF may enter through one channel(s) and the additional precursor may flow through another channel(s) prior to forming the combination. The combination may be formed near the substrate. The silicon oxide etch selectivity relative to silicon nitride from is selectable from about one to several hundred. In all cases, the etch rate of exposed silicon, if present, is negligible. No precursors are excited in any plasma either outside or inside the substrate processing region according to embodiments. The additional precursor may be a nitrogen-and-hydrogen-containing precursor such as ammonia.
    Type: Grant
    Filed: August 4, 2015
    Date of Patent: February 7, 2017
    Assignee: Applied Materials, Inc.
    Inventors: Jingjing Xu, Anchuan Wang, Nitin K. Ingle
  • Patent number: 9543163
    Abstract: Methods for etching a material layer disposed on the substrate using a combination of a main etching step and a cyclical etching process are provided. The method includes performing a main etching process in a processing chamber to an oxide layer, forming a feature with a first predetermined depth in the oxide layer, performing a treatment process on the substrate by supplying a treatment gas mixture into the processing chamber to treat the etched feature in the oxide layer, performing a chemical etching process on the substrate by supplying a chemical etching gas mixture into the processing chamber, wherein the chemical etching gas includes at least an ammonium gas and a nitrogen trifluoride, wherein the chemical etching process further etches the feature to a second predetermined depth, and performing a transition process on the etched substrate by supplying a transition gas mixture into the processing chamber.
    Type: Grant
    Filed: October 21, 2013
    Date of Patent: January 10, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Mang-Mang Ling, Jungmin Ko, Sean S. Kang, Jeremiah T. Pender, Srinivas D. Nemani, Bradley Howard
  • Patent number: 9536922
    Abstract: A fabricating method of a recess with asymmetric walls includes the steps of providing a substrate comprising a top surface. A recess is formed in the substrate, wherein the recess comprises a first wall, a second wall and a bottom. A patterned mask is formed to cover the substrate. Part of the top surface adjacent to the second wall is exposed through the patterned mask. Finally, the substrate is removed to form a sloping wall, wherein the sloping wall, the first wall and the bottom form a recess with asymmetric walls.
    Type: Grant
    Filed: December 2, 2014
    Date of Patent: January 3, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ming-Te Lai, Chih-Hong Wu, Feng-Ying Hsu
  • Patent number: 9524881
    Abstract: Method of forming a termination angle in a titanium tungsten layer include providing a titanium tungsten layer and applying a photo resist material to the titanium tungsten layer. The photo resist material is exposed under a defocus condition to generate a resist mask, wherein an edge of the exposed photo resist material corresponds to the sloped termination. The titanium tungsten layer is etched with an etching material, wherein the etching material at least partially etches the photo resist material exposed under the defocused condition, and wherein the etching results in the sloped termination in the titanium tungsten layer.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: December 20, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Neng Jiang, Maciej Blasiak, Nicholas S. Dellas, Brian E. Goodlin
  • Patent number: 9520294
    Abstract: Atomic layer etching using alternating passivation and etching processes is performed with an electron beam plasma source, in which the ion energy is set to a low level below the etch threshold of the material to be etched during passivation and to a higher level above the etch threshold during etching but below the etch threshold of the unpassivated material.
    Type: Grant
    Filed: October 2, 2014
    Date of Patent: December 13, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Ankur Agarwal, Rajinder Dhindsa, Shahid Rauf
  • Patent number: 9474163
    Abstract: In some embodiments, a method for integrated circuit fabrication includes removing oxide material from a surface of a substrate, where the surface includes silicon and germanium. Removing the oxide material includes depositing a halogen-containing pre-clean material on a silicon oxide-containing surface and sublimating a portion of the halogen-containing pre-clean material to expose the silicon on the surface. A passivation film is deposited on the exposed silicon. The passivation film may include chlorine. The passivation film may prevent contamination of the silicon surface by chemical species from the later sublimation, which may be at a higher temperature than the earlier sublimation. Subsequently, a remaining portion of the halogen-containing pre-clean material and the passivation film are sublimated. A target material, such as a conductive material, may subsequently be deposited on the substrate surface.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: October 18, 2016
    Assignee: ASM IP HOLDING B.V.
    Inventors: John Tolle, Matthew G. Goodman
  • Patent number: 9466491
    Abstract: One illustrative method disclosed herein includes, among other things, forming a sacrificial gate structure above a semiconductor substrate, forming a sidewall spacer adjacent opposite sides of the sacrificial gate structure, removing the sacrificial gate structure and forming a replacement gate structure in its place, at some point after forming the replacement gate structure, performing an etching process to reduce the height of the spacers so as to thereby define recessed spacers having an upper surface that partially defines a spacer recess, and forming a spacer etch block cap on the upper surface of each recessed spacer structure and within the spacer recess.
    Type: Grant
    Filed: May 2, 2014
    Date of Patent: October 11, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Daniel T. Pham, Hyun-Jin Cho, Ruilong Xie
  • Patent number: 9466507
    Abstract: An etching method includes a modification process of supplying a mixture gas to a surface of a silicon oxide film, modifying the silicon oxide film to generate a reaction product, and a heating process of heating and removing the reaction product. The modification process includes a first modification process of supplying the mixture gas containing a gas including a halogen element and an alkaline gas to the surface of the silicon oxide film, and a second modification process of stopping supplying the alkaline gas and supplying the mixture gas containing the gas including the halogen element to the surface of the silicon oxide film.
    Type: Grant
    Filed: June 13, 2014
    Date of Patent: October 11, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Shigeki Tozawa, Tomoaki Ogiwara
  • Patent number: 9449838
    Abstract: In a semiconductor device manufacturing method, a target object including a multilayer film and a mask formed on the multilayer film is prepared in a processing chamber of a plasma processing apparatus. The multilayer film is formed by alternately stacking a silicon oxide film and a silicon nitride film. The multilayer film is etched by supplying a processing gas containing hydrogen gas, hydrogen bromide gas, nitrogen trifluoride gas and at least one of hydrocarbon gas, fluorohydrocarbon gas and fluorocarbon gas into the processing chamber of the plasma processing apparatus and generating a plasma of the processing gas in the processing chamber.
    Type: Grant
    Filed: April 24, 2015
    Date of Patent: September 20, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Kazuto Ogawa, Kazuki Narishige, Takanori Sato
  • Patent number: 9436091
    Abstract: A method for forming a fine pattern includes forming an etching target material layer on a substrate, forming a first photoresist layer on the etching target material layer, forming a metal pattern on the first photoresist layer, the metal pattern having a plurality of lines and thin film lines alternately arranged, the lines having predetermined linewidth and thickness and are spaced apart from each other by a predetermined distance, exciting surface plasmons in the metal pattern by light irradiation to produce a surface plasmon resonance that exposes a fine first pattern shape in the first photoresist layer, forming a first photoresist pattern by removing the metal pattern and developing the first photoresist layer, and etching the etching target material layer by using the first photoresist pattern as a mask.
    Type: Grant
    Filed: July 28, 2014
    Date of Patent: September 6, 2016
    Assignee: Samsung Display Co., Ltd.
    Inventors: Yong Son, Min Kang, Bong-Yeon Kim, Dong-Eon Lee, Hyun-joo Lee
  • Patent number: 9418867
    Abstract: A gas comprising hydrogen is supplied to a plasma source. Plasma comprising hydrogen plasma particles is generated from the gas. A passivation layer is deposited on a first mask layer on a second mask layer over a substrate using the hydrogen plasma particles.
    Type: Grant
    Filed: January 10, 2014
    Date of Patent: August 16, 2016
    Assignee: Applied Materials, Inc.
    Inventors: Byungkook Kong, Hung Sang Kim, Hoon Sang Lee, Jeong Hyun Yoo, Jun-Wan Kim
  • Patent number: 9385069
    Abstract: An embodiment includes a substrate, wherein a portion of the substrate extends upwards forming a fin, a gate dielectric over a top surface and at least portions of sidewalls of the fin, a gate electrode over the gate dielectric, and a contact over and extending into the gate electrode, wherein the contact has a first width above the gate electrode and a second width within the gate electrode, the first width being smaller than the second width.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: July 5, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Wen Liu, Chao-Hsiung Wang
  • Patent number: 9378758
    Abstract: The present invention provides, in a plasma etching method for plasma-etching a magnetic film, a plasma etching method that allows a desired etching depth to be obtained regardless of the opening size of a mask. The present invention is, in a plasma etching method for plasma-etching a magnetic film by using a tantalum film as a mask, characterized by including: a first process to plasma-etch the magnetic film to a desired depth by using a mixed gas of an ammonia gas and a helium gas; and a second process, after the first process, to plasma-etch the magnetic film etched to the prescribed depth by using a mixed gas of an ammonia gas and a gas containing the oxygen element or a mixed gas of an ammonia gas and a gas containing a hydroxyl group.
    Type: Grant
    Filed: April 9, 2014
    Date of Patent: June 28, 2016
    Assignee: HITACHI HIGH-TECHNOLOGIES CORPORATION
    Inventors: Takahiro Abe, Naohiro Yamamoto, Kentaro Yamada, Makoto Suyama, Daisuke Fujita
  • Patent number: 9379015
    Abstract: A wafer processing method divides a wafer into individual devices along crossing streets formed on the front side of the wafer. The wafer has a substrate and a functional layer formed on the front side of the substrate. The individual devices are formed from the functional layer and are partitioned by the streets. A laser beam is applied along the streets from the front side of the functional layer to thereby remove the functional layer along the streets. A resist film is formed on the front side of the functional layer except on each street. The substrate of the wafer is plasma-etched along each street where the functional layer is absent to the depth corresponding to the finished thickness of each device, thereby forming a division groove along each street and also etching off a modified layer formed on the opposite sides of each street.
    Type: Grant
    Filed: November 1, 2013
    Date of Patent: June 28, 2016
    Assignee: DISCO CORPORATION
    Inventors: Sakae Matsuzaki, Junichi Arami
  • Patent number: 9352520
    Abstract: There is provided a pattern forming method, including: forming an organic film layer on a substrate; forming a patterned photoresist mask on the organic film layer; and performing a specific dry etching process to form a pattern on the organic layer.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: May 31, 2016
    Assignee: FUJIFILM Corporation
    Inventors: Mitsuji Yoshibayashi, Yasuo Sugishima
  • Patent number: 9343749
    Abstract: In at least one embodiment, a method of forming a platinum thin film is provided, including performing a first atomic layer deposition (ALD) process on a substrate using a first platinum organometallic precursor in a first step and an oxidizing precursor in a second step to form an at least partially coated substrate. A second ALD process is then performed on the at least partially coated substrate using a second platinum organometallic precursor in a first step and a reducing precursor in a second step to form a thin film of platinum on the substrate. The first ALD process may be performed for 5 to 150 cycles to nucleate platinum on the substrate surface and the second ALD process may be performed thereafter to grow the thin film and remove surface oxides. A conformal platinum thin film having a thickness of 1 to 10 monolayers may be deposited.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: May 17, 2016
    Assignee: FORD GLOBAL TECHNOLOGIES, LLC
    Inventors: Patrick Pietrasz, Jun Yang
  • Patent number: 9318696
    Abstract: Systems and methods for forming precise and self-aligned top metal contact for a Magnetoresistive random-access memory (MRAM) device include forming a magnetic tunnel junction (MTJ) in a common interlayer metal dielectric (IMD) layer with a logic element. A low dielectric constant (K) etch stop layer is selectively retained over an exposed top surface of the MTJ. Etching is selectively performed through a top IMD layer formed over the low K etch stop layer and the common IMD layer, based on a first chemistry which prevents etching through the low K etch stop layer. By switching chemistry to a second chemistry which precisely etches through the low K etch stop layer, an opening is created for forming a self-aligned top contact to the exposed top surface of the MTJ.
    Type: Grant
    Filed: March 3, 2014
    Date of Patent: April 19, 2016
    Assignee: QUALCOMM INCORPORATED
    Inventors: Yu Lu, Xia Li, Seung Hyuk Kang, Shiqun Gu
  • Patent number: 9299611
    Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask is exposed to a plasma treatment process to increase an etch resistance of the mask. The mask is patterned with a laser scribing process to provide gaps in the mask, the gaps exposing regions of the semiconductor wafer between the integrated circuits. Subsequent to exposing the mask to the plasma treatment process, the semiconductor wafer is plasma etched through the gaps in the mask to singulate the integrated circuits.
    Type: Grant
    Filed: January 29, 2014
    Date of Patent: March 29, 2016
    Assignee: Applied Materials, Inc.
    Inventors: Wei-Sheng Lei, Brad Eaton, Ajay Kumar, James S. Papanu, Jungrae Park
  • Patent number: 9293346
    Abstract: In a method for etching an organic film according to an embodiment, a target object that has an organic film is set in a processing chamber. Then, a processing gas containing COS gas and O2 gas is supplied to the processing chamber and a microwave for plasma excitation is supplied to the inside of the processing chamber to etch the organic film.
    Type: Grant
    Filed: March 26, 2013
    Date of Patent: March 22, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Hiroyuki Takaba, Hironori Matsuoka
  • Patent number: 9287495
    Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes forming a silicon nitride layer on a metal layer, forming a plasma of a gas mixture of carbon oxide and oxygen, and selectively etching the silicon nitride layer with respect to the metal layer by using the plasma of the gas mixture.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: March 15, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Kazuhiro Tomioka
  • Patent number: 9281470
    Abstract: In a plasma processing method for plasma-etching magnetic layer by using a plasma processing device including a processing chamber in which a sample is plasma-processed, a dielectric window to seal an upper part of the processing chamber hermetically, an inductive coupling antenna disposed above the dielectric window, a radio-frequency power source to supply radio-frequency electric power to the inductive coupling antenna and a Faraday shield disposed between the inductive coupling antenna and the dielectric window, a deposit layer is formed on the plasma-etched magnetic layer by plasma processing while applying radio-frequency voltage to the Faraday shield after the magnetic layer is plasma-etched.
    Type: Grant
    Filed: July 31, 2014
    Date of Patent: March 8, 2016
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Takahiro Abe, Naohiro Yamamoto, Makoto Suyama, Masato Ishimaru
  • Patent number: 9263283
    Abstract: An etching method and apparatus for etching a silicon oxide film selectively with respect to a silicon nitride film formed on a substrate are provided. A processing gas containing a plasma excitation gas and a CHF-based gas is introduced into a processing chamber such that a flow rate ratio of the CHF-based gas to the plasma excitation gas is 1/15 or higher. By generating a plasma in the processing chamber, the silicon oxide film is etched selectively with respect to the silicon nitride film formed on the substrate in the processing chamber.
    Type: Grant
    Filed: September 25, 2012
    Date of Patent: February 16, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Takayuki Sekine, Masaru Sasaki, Naoki Matsumoto, Eiichirou Shinpuku
  • Patent number: 9222837
    Abstract: This invention involves structure and fabrication method of a black silicon-based MEMS thermopile IR detector. The high-performance black silicon-based MEMS thermopile IR detector includes a substrate; a releasing barrier band on the substrate; a thermal isolation cavity constructed by the releasing barrier band; a black silicon-based IR absorber located right above the thermal isolation cavity; a number of thermocouples are set around the lateral sides of the black silicon-based IR absorber. The thermopiles around the black silicon-based IR absorber are electrically connected in series thus to form a thermopile. Metallic electrodes are located beside the electrically-connected thermopiles for signal output. The cold junctions of the thermopile are connected to the substrate through the first thermal-conductive-electrical-isolated structures, the heat conductor is located at the lateral sides of the thermal isolation cavity.
    Type: Grant
    Filed: January 21, 2013
    Date of Patent: December 29, 2015
    Assignee: JIANGSU R&D CENTER FOR INTERNET OF THINGS
    Inventors: Haiyang Mao, Wen Ou
  • Patent number: 9218975
    Abstract: Disclosed herein are various methods of forming a replacement gate structure with a gate electrode comprised of a deposited intermetallic compound material. In one example, the method includes removing at least a sacrificial gate electrode structure to define a gate cavity, forming a gate insulation layer in the gate cavity, performing a deposition process to deposit an intermetallic compound material in the gate cavity above the gate insulation layer, and performing at least one process operation to remove portions of intermetallic compound material positioned outside of the gate cavity.
    Type: Grant
    Filed: August 17, 2012
    Date of Patent: December 22, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Kisik Choi, Mark V. Raymond