Differential Etching Of Semiconductor Substrate Patents (Class 438/735)
  • Patent number: 10923356
    Abstract: A method for the dry removal of a material on a microelectronic workpiece is described. The method includes receiving a substrate having a working surface exposing a silicon-germanium alloy and at least one other material, the silicon-germanium alloy represented as SixGe1-x, wherein x is a real number ranging from 0 to 1; and selectively etching the silicon-germanium alloy relative to the other material by exposing the substrate to a controlled gas-phase environment containing an anhydrous halogen compound, such as a diatomic halogen or an interhalogen compound.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: February 16, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Subhadeep Kal, Masashi Matsumoto, Daisuke Ito, Yusuke Muraki, Aelan Mosden
  • Patent number: 10553433
    Abstract: A method for preparing a semiconductor structure includes the following steps: providing a substrate including a first region and a second region defined thereon, forming a first mask structure over the substrate, forming a plurality of first features in the first mask structure in the first region, forming a second mask structure over the first mask structure, simultaneously forming a plurality of second features in the second mask structure in the second region and a plurality of third features in the second mask structure in the first region, and transferring the second features and the third features to the first mask structure to simultaneously form a plurality of islanding features in the first region and a plurality of line features in the second region.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: February 4, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Shing-Yih Shih
  • Patent number: 10439048
    Abstract: A method of forming fine patterns including forming a plurality of first sacrificial patterns on a target layer, the target layer on a substrate, forming first spacers on respective sidewalls of the first sacrificial patterns, removing the first sacrificial patterns, forming a plurality of second sacrificial patterns, the second sacrificial patterns intersecting with the first spacers, each of the second sacrificial patterns including a line portion and a tab portion, and the tab portion having a width wider than the line portion, forming second spacers on respective sidewalls of the second sacrificial patterns, removing the second sacrificial patterns, and etching the target layer through hole regions, the hole regions defined by the first spacers and the second spacers, to expose the substrate may be provided.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: October 8, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Bum Lim, Jong-Ryul Jun, Eun-A Kim, Jong-Min Lee
  • Patent number: 10120134
    Abstract: A micro-optical bench device is fabricated by a process that provides control over one or more properties of the micro-optical bench device and/or one or more properties of optical surfaces in the micro-optical bench device. The process includes etching a substrate to form a permanent structure including optical elements and a temporary structure. The shape of the temporary structure and gaps between the temporary structure and permanent structure facilitate control of a property of the micro-optical bench and/or optical surfaces therein. The process further includes removing the temporary structure from an optical path of the micro-optical bench device.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: November 6, 2018
    Assignee: SI-WARE SYSTEMS
    Inventors: Bassam Saadany, Yasser M. Sabry, Mostafa Medhat, Bassem Mortada, Muhammed Nagi, Mohamed Sadek, Yasseen Nada, Khaled Hassan
  • Patent number: 9997372
    Abstract: Various embodiments herein relate to methods, apparatus and systems for forming a recessed feature in dielectric material on a semiconductor substrate. Separate etching and deposition operations are employed in a cyclic manner. Each etching operation partially etches the feature. Each deposition operation forms a protective coating on the sidewalls of the feature to prevent lateral etch of the dielectric material during the etching operations. The protective coating may be deposited using methods that result in formation of the protective coating along substantially the entire length of the sidewalls. The protective coating may be deposited using particular reactants having low sticking coefficients in some embodiments. The protective coating may also be deposited using particular reaction mechanisms that result in substantially complete sidewall coating. In some cases the protective coating is deposited using plasma assisted atomic layer deposition or plasma assisted chemical vapor deposition.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: June 12, 2018
    Assignee: Lam Research Corporation
    Inventors: Joseph Scott Briggs, Eric A. Hudson
  • Patent number: 9887097
    Abstract: Various embodiments herein relate to methods, apparatus and systems for forming a recessed feature in dielectric material on a semiconductor substrate. Separate etching and deposition operations are employed in a cyclic manner. Each etching operation partially etches the feature. Each deposition operation forms a protective coating on the sidewalls of the feature to prevent lateral etch of the dielectric material during the etching operations. The protective coating may be deposited using methods that result in formation of the protective coating along substantially the entire length of the sidewalls. The protective coating may be deposited using particular reactants and/or reaction mechanisms that result in substantially complete sidewall coating at relatively low temperatures without the use of plasma. In some cases the protective coating is deposited using molecular layer deposition techniques. In certain implementations the protective coating is fluorinated.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: February 6, 2018
    Assignee: Lam Research Corporation
    Inventor: Eric A. Hudson
  • Patent number: 9847227
    Abstract: A method for forming patterns of a semiconductor device includes preparing an etch target layer defined with a first region and a second region; forming a regular first feature which is positioned over the etch target layer in the first region and a random feature which is positioned over the etch target layer in the second region; forming a regular second feature over the regular first feature; forming first and second cutting barriers which expose a portion of the random feature, over the random feature; cutting the regular first feature using the regular second feature, to form a regular array feature; cutting the random feature using the first cutting barrier and the second cutting barrier, to form a random array feature; and etching the etch target layer by using the regular array feature and the random array feature, to form a regular array pattern and a random array pattern.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: December 19, 2017
    Assignee: SK Hynix Inc.
    Inventor: Chun-Soo Kang
  • Patent number: 9818611
    Abstract: Techniques disclosed herein provide a method for pitch reduction (increasing pitch/feature density) for creating high-resolution features and also for cutting on pitch of sub-resolution features. Techniques include using multiple materials having different etch characteristics to selectively etch features and create cuts where specified. A sequence of materials or repeating pattern of lines of materials is used that provides selective self-alignment based on different etch resistivities. Combined with an underlying transfer or memorization layer, multiple different etch selectivities can be accessed. An etch mask defines which regions of the lines of multiple materials can be etched.
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: November 14, 2017
    Assignee: Tokyo Electron Limited
    Inventor: Anton J. deVilliers
  • Patent number: 9696750
    Abstract: The semiconductor device includes a command generator, an information signal storage unit, a termination signal generator and a code generator. The command generator generates a mode register write command signal, a start command signal and a termination command signal from external command signals. The information signal storage unit extracts information signals from the external command signals to store the information signals and output the information signals. The termination signal generator generates a termination signal in response to the information signals. The code generator generates code signals to control a timing of a control signal.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: July 4, 2017
    Assignee: SK hynix Inc.
    Inventor: Bok Rim Ko
  • Patent number: 9658530
    Abstract: The invention provides a process for forming a multi-layer film including the steps of: (1) forming an under layer film onto a substrate by coating an under layer film material containing a resin represented by the following general formula (1) in which a compound having a bisnaphthol group has been made a novolac resin, and curing the same by heat treatment at a temperature in a range of 300° C. or higher and 700° C. or lower for 10 seconds to 600 seconds, (2) forming a silicon film onto the under layer film, (3) forming a hydrocarbon film onto the silicon film by coating a hydrocarbon film material, and (4) forming a silicon-oxidized film onto the hydrocarbon film by coating a silicon-oxidized film material. There can be provided a process for forming a multi-layer film which can reduce reflectance, and useful for a patterning process with high dimensional accuracy of dry etching.
    Type: Grant
    Filed: June 17, 2015
    Date of Patent: May 23, 2017
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Jun Hatakeyama, Takeshi Nagata
  • Patent number: 9601660
    Abstract: A method of fabricating a flip-chip photonic-crystal light-emitting diode (LED) is disclosed. The method includes the steps of: providing an initial substrate including an epitaxial-growth surface and a light-output surface; performing a nanoimprint process on the epitaxial-growth surface of the initial substrate to form a nano-level patterned substrate; forming a flip-chip LED structure on the epitaxial-growth surface of the nano-level patterned substrate; and performing a nanoimprint process on the light-output surface of the nano-level patterned substrate to form the flip-chip photonic-crystal LED. The formation of the photonic-crystal structure on the light-output surface results in enhanced LED light extraction and emission efficiency.
    Type: Grant
    Filed: December 26, 2013
    Date of Patent: March 21, 2017
    Assignee: ENRAYTEK OPTOELECTRONICS CO., LTD.
    Inventor: Leke Wu
  • Patent number: 9564343
    Abstract: A substrate having an insulating layer including an oxide is loaded into a chamber, and at least a part of the insulating layer is removed by injecting a process gas including an etching source gas into the chamber. The removal process is performed in a pulse type in which a first period and a second period are repeated a plurality of times. The etching source gas is supplied at a first flow rate during the first period and is supplied at a second flow rate less than the first flow rate during the second period. A temperature of the inside of the chamber remains at 100° C. or more during the removal process.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: February 7, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Mongsup Lee, Yoonho Son, Sang-Jun Lee, Munkwon Kang, Kyunghyun Kim, Inseak Hwang
  • Patent number: 9548269
    Abstract: Self-aligned via and plug patterning using diagonal hardmasks for improved overlay in fabricating back end of line (BEOL) interconnects is described. In an example, a method of fabricating an interconnect structure for an integrated circuit involves forming a first hardmask layer above an interlayer dielectric layer disposed above a substrate. The first hardmask layer includes a plurality of first hardmask lines having a first grating in a first direction and comprising one or more sacrificial materials interleaved with the first grating. The method also involves forming a second hardmask layer above the first hardmask layer. The second hardmask layer includes a plurality of second hardmask lines having a second grating in a second direction, diagonal to the first direction. The method also involves, using the second hardmask layer as a mask, etching the first hardmask layer to form a patterned first hardmask layer. The etching involves removing a portion of the one or more sacrificial materials.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: January 17, 2017
    Assignee: Intel Corporation
    Inventors: Alan M. Myers, Kanwal Jit Singh, Robert L. Bristol, Jasmeet S. Chawla
  • Patent number: 9520299
    Abstract: A semiconductor device and method for forming a semiconductor device are presented. The method includes providing a patterned reticle having a pattern perimeter defined by active and dummy patterns. The dummy patterns include dummy structures modified according to a density equation. The patterned reticle is used to pattern a resist layer on a substrate with a device layer. An etch is performed to pattern the device layer using the patterned resist layer. Additional processing is performed to complete formation of the device.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: December 13, 2016
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Wanbing Yi, Chin Chuan Neo, Hai Cong, Kin Wai Tang, Weining Li, Juan Boon Tan
  • Patent number: 9405313
    Abstract: The semiconductor device includes a command generator, an information signal storage unit, a termination signal generator and a code generator. The command generator generates a mode register write command signal, a start command signal and a termination command signal from external command signals. The information signal storage unit extracts information signals from the external command signals to store the information signals and output the information signals. The termination signal generator generates a termination signal in response to the information signals. The code generator generates code signals to control a timing of a control signal.
    Type: Grant
    Filed: May 21, 2014
    Date of Patent: August 2, 2016
    Assignee: SK hynix Inc.
    Inventor: Bok Rim Ko
  • Patent number: 9082625
    Abstract: Embodiments of present invention provide a method of forming device pattern. The method includes defining a device pattern to be created in a device layer; forming a sacrificial layer on top of the device layer; identifying an imprinting mold that, at a position along a height thereof, has a horizontal cross-sectional shape that represents the device pattern; pushing the imprinting mold uniformly into the sacrificial layer until at least the position of the imprinting mold reaches a level inside the sacrificial layer that is being pushed by the imprinting mold; removing the imprinting mold away from the sacrificial layer; forming a hard mask in recesses created by the imprinting mold in the sacrificial layer, the hard mask has a pattern representing the device pattern; and transferring the pattern of the hard mask into underneath the device layer.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: July 14, 2015
    Assignees: International Business Machines Corporation, STMICROELECTRONICS, Inc.
    Inventors: Lawrence A. Clevenger, Carl J. Radens, Richard S. Wise, Yiheng Xu, John Zhang
  • Patent number: 9070633
    Abstract: Embodiments of the present disclosure relate to method and apparatus for providing processing gases to a process chamber with improved plasma dissociation efficiency. One embodiment of the present disclosure provides a baffle nozzle assembly comprising an outer body defining an extension volume connected to a processing chamber. A processing gas is flown to the processing chamber through the extension volume which is exposed to power source for plasma generation.
    Type: Grant
    Filed: May 21, 2014
    Date of Patent: June 30, 2015
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Roy C. Nangoy, Saravjeet Singh, Jon C. Farr, Sharma V. Pamarthy, Ajay Kumar
  • Patent number: 9023733
    Abstract: The present disclosure relates to a method (10) for block-copolymer lithography. This method comprises the step of obtaining (12) a self-organizing block-copolymer layer comprising at least two polymer components having mutually different etching resistances, and the steps of applying at least once each of first plasma etching (14) of said self-organizing block-copolymer layer using a plasma formed from a substantially ashing gas, and second plasma etching (16) of said self-organizing block-copolymer layer using plasma formed from a pure inert gas or mixture of inert gases in order to selectively remove a first polymer phase. A corresponding intermediate product also is described.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: May 5, 2015
    Assignees: IMEC, Tokyo Electron Limited
    Inventors: Boon Teik Chan, Shigeru Tahara
  • Patent number: 8999777
    Abstract: The present disclosure discloses a method of fabricating a semiconductor device. A first layer is formed over a substrate. A patterned second layer is then formed over the first layer. The patterned second layer includes an opening. A spacer material is then deposited in the opening, thereby reducing the opening in a plurality of directions. A direction-specific trimming process is performed to the spacer material and the second layer. Thereafter, the first layer is patterned with the second layer.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: April 7, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming Chyi Liu, Shih-Chang Liu, Chia-Shiung Tsai
  • Patent number: 8999854
    Abstract: On a substrate, a silicon carbide layer provided with a main surface is formed. A mask is formed to cover a portion of the main surface of the silicon carbide layer. The main surface of the silicon carbide layer on which the mask is formed is thermally etched using chlorine-based gas so as to provide the silicon carbide layer with a side surface inclined relative to the main surface. The step of thermally etching is performed in an atmosphere in which the chlorine-based gas has a partial pressure of 50% or smaller.
    Type: Grant
    Filed: October 23, 2012
    Date of Patent: April 7, 2015
    Assignees: Sumitomo Electric Industries, Ltd., National University Corporation Nara Institute of Science and Technology
    Inventors: Takeyoshi Masuda, Tomoaki Hatayama
  • Patent number: 8993445
    Abstract: Methods are provided for facilitating fabricating a semiconductor device by selectively etching a gate structure sidewall(s) to facilitate subsequent sidewall spacer isolation. The method includes, for instance: providing a gate structure with a protective layer(s) over the gate structure, the gate structure including one or more sidewalls; selectively removing a portion of the gate structure along at least one sidewall to partially undercut the protective layer(s); and forming a sidewall spacer(s) over the sidewall(s) of the gate structure, with a portion of the sidewall spacer at least partially filling the partial undercut of the protective layer(s), and residing below the protective layer(s). In certain embodiments, the selectively removing includes implanting the sidewall(s) with a dopant to produce a doped region(s) of the gate structure, and subsequently, at least partially removing the doped region(s) of the gate structure selective to an undoped region of the gate structure.
    Type: Grant
    Filed: January 14, 2013
    Date of Patent: March 31, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Dae-Han Choi, Dae Geun Yang, Chang Ho Maeng, Wontae Hwang
  • Patent number: 8980756
    Abstract: Embodiments of a method for device fabrication by reverse pitch reduction flow include forming a first pattern of features above a substrate and forming a second pattern of pitch-multiplied spacers subsequent to forming the first pattern of features. In embodiments of the invention the first pattern of features may be formed by photolithography and the second pattern of pitch-multiplied spacers may be formed by pitch multiplication. Other methods for device fabrication are provided.
    Type: Grant
    Filed: July 30, 2007
    Date of Patent: March 17, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Luan C. Tran, Raghupathy Giridhar
  • Patent number: 8969215
    Abstract: Methods of fabricating semiconductor devices and semiconductor devices fabricated thereby are provided. Two photolithography processes and two spacer processes are performed to provide final patterns that have a pitch that is smaller than a limitation of photolithography process. Furthermore, since initial patterns are formed to have line and pad portions simultaneously by performing a first photolithography process, there is no necessity to perform an additional photolithography process for forming the pad portion.
    Type: Grant
    Filed: November 13, 2013
    Date of Patent: March 3, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Hwang Sim, Jinhyun Shin
  • Patent number: 8928011
    Abstract: A highly reliable light-emitting device or lighting device is provided. Further, a light-emitting device or lighting device with a high manufacturing yield is provided. Provided is a light-emitting device having a contact structure which includes a separation layer having a shape typified by a reverse tapered shape in which an outline of the bottom portion is inside an outline of an upper portion and which utilizes the difference between an amount of a light-emitting layer extending inside the outline and that of an upper electrode extending inside the outline. Further, when the outline of the separation layer which forms the contact portion has a depression and a projection, the length of the contact portion can be increased, and thus, contact resistance can be reduced.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: January 6, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshifumi Tanada, Hidenori Mori
  • Patent number: 8921136
    Abstract: The present disclosure relates to methods of forming a self-aligned contact and related apparatus. In some embodiments, the method forms a plurality of gate lines interspersed between a plurality of dielectric lines, wherein the gate lines and the dielectric lines extend in a first direction over an active area. One or more of the plurality of gate lines are into a plurality of gate line sections aligned in the first direction. One or more of the plurality of dielectric lines are cut into a plurality of dielectric lines sections aligned in the first direction. A dummy isolation material is deposited between adjacent dielectric sections in the first direction and between adjacent gate line sections in the first direction. One or more self-aligned metal contacts are then formed by replacing a part of one or more of the plurality of dielectric lines over the active area with a contact metal.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: December 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Neng-Kuo Chen, Shao-Ming Yu, Gin-Chen Huang, Chia-Jung Hsu, Sey-Ping Sun, Clement Hsingjen Wann
  • Patent number: 8916477
    Abstract: Provided are methods and systems for removing polysilicon on a wafer. A wafer can include a polysilicon layer and an exposed nitride and/or oxide structure. An etchant with a hydrogen-based species, such as hydrogen gas, and a fluorine-based species, such as nitrogen trifluoride, can be introduced. The hydrogen-based species and the fluorine-based species can be activated with a remote plasma source. The layer of polysilicon on the wafer can be removed at a selectivity over the exposed nitride and/or oxide structure that is greater than about 500:1.
    Type: Grant
    Filed: June 12, 2013
    Date of Patent: December 23, 2014
    Assignee: Novellus Systems, Inc.
    Inventors: Bayu Thedjoisworo, Jack Kuo, David Cheung, Joon Park
  • Patent number: 8883651
    Abstract: A method of manufacturing a transistor of a semiconductor device, the method including forming a gate pattern on a semiconductor substrate, forming a spacer on a sidewall of the gate pattern, wet etching the semiconductor substrate to form a first recess in the semiconductor substrate, wherein the first recess is adjacent to the spacer, and wet etching the first recess to form a second recess in the semiconductor substrate.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: November 11, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seokhoon Kim, Sangsu Kim, Chung Geun Koh, Byeongchan Lee, Sunghil Lee, Jinyeong Joe
  • Patent number: 8871652
    Abstract: A method for manufacturing a semiconductor template balanced between strains and defects is provided, the method including steps of: preparing a substrate, dividing the substrate into a plurality of first patterned zones and a plurality of second patterned zones, the second patterned zones applied to separate the first patterned zones; selecting a semiconductor with an ideal lattice of a semiconductor buffer layer to be deposited on the substrate; etching a plurality of first microstructures in the first patterned zones according to the semiconductor with the ideal lattice, the first microstructures and the semiconductor with the ideal lattice following a lattice-structure matching relationship, discovered by strain-traction experiments, making the substrate a multi-patterned substrate; and depositing the semiconductor buffer layer having the semiconductor with the ideal lattice on the multi-patterned substrate to manufacture a semiconductor template which is balanced between strains and defects.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: October 28, 2014
    Assignee: Kingwave Corporation
    Inventors: Chieh-Hsiung Kuan, Wen-Sheng Su
  • Patent number: 8828882
    Abstract: A trench is formed in a semiconductor substrate by depositing an etch mask on the substrate having an opening, etching of the trench through the opening, and doping the walls of the trench. The etching step includes a first phase having an etch power set to etch the substrate under the etch mask, and a second phase having an etch power set smaller than the power of the first phase. Further, the doping of the walls of the trench is applied through the opening of the etch mask.
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: September 9, 2014
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Arnaud Tournier, Françcois Leverd
  • Patent number: 8828884
    Abstract: A method of making multi-level contacts. The method includes providing an in-process multilevel device including at least one device region and at least one contact region. The contact region includes a plurality of electrically conductive layers configured in a step pattern. The method also includes forming a conformal etch stop layer over the plurality of electrically conductive layers, forming a first electrically insulating layer over the etch stop layer, forming a conformal sacrificial layer over the first electrically insulating layer and forming a second electrically insulating layer over the sacrificial layer. The method also includes etching a plurality of contact openings through the etch stop layer, the first electrically insulating layer, the sacrificial layer and the second electrically insulating layer in the contact region to the plurality of electrically conductive layers.
    Type: Grant
    Filed: May 23, 2012
    Date of Patent: September 9, 2014
    Assignee: Sandisk Technologies Inc.
    Inventors: Yao-Sheng Lee, Zhen Chen, Syo Fukata
  • Patent number: 8828832
    Abstract: The present disclosure provides a semiconductor device that includes a semiconductor substrate, a gate structure disposed on a surface of the substrate, and strained structures disposed in the substrate at either side of the gate structure and formed of a semiconductor material different from the semiconductor substrate. Each strained structure has a cross-sectional profile that includes a first portion that extends from the surface of substrate and a second portion that tapers from the first portion at an angle ranging from about 50° to about 70°. The angle is measured with respect to an axis parallel to the surface of the substrate.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: September 9, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Huan Tsai, Han-Ting Tsai
  • Patent number: 8815674
    Abstract: One method disclosed includes forming a sidewall spacer proximate a gate structure, forming a sacrificial layer of material above a protective cap layer, the sidewall spacer and a substrate, forming a sacrificial protection layer above the sacrificial layer, reducing a thickness of the sacrificial protection layer such that its upper surface is positioned at a level that is below the upper surface of the protective cap layer, performing a first etching process to remove a portion of the sacrificial layer and thereby expose the protective cap layer for further processing, performing a wet acid etching process that includes diluted HF acid in the etch chemistry to remove the protective cap layer and performing at least one process operation to remove at least one of the reduced-thickness sacrificial protection layer or the sacrificial layer from above the surface of the substrate.
    Type: Grant
    Filed: February 4, 2014
    Date of Patent: August 26, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Berthold Reimer, Markus Lenski, Bastian Haussdoerfer, Ardechir Pakfar
  • Patent number: 8791027
    Abstract: A problem of a resist mask collapse due to a plasma process is solved. In a method of manufacturing a semiconductor device including steps of a plasma process to a sample having a mask made of an organic material, the plasma process includes a first step of a plasma process under a gas containing any of fluorine, oxygen, or nitrogen, or containing all of them, and a second step of the plasma process under a gas containing a rare gas without containing any of fluorine, oxygen, and nitrogen, and the first step and the second step are repeated.
    Type: Grant
    Filed: June 4, 2010
    Date of Patent: July 29, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Naoyuki Kofuji, Hideo Miura
  • Patent number: 8778804
    Abstract: A method and apparatus for selective etching a substrate using a focused beam. For example, multiple gases may be used that are involved in competing beam-induced and spontaneous reactions, with the result depending on the materials on the substrate. The gases may include, for example, an etchant gas and an auxiliary gas that inhibits etching.
    Type: Grant
    Filed: January 30, 2009
    Date of Patent: July 15, 2014
    Assignee: FEI Company
    Inventors: Steven Randolph, Clive D. Chandler
  • Patent number: 8778201
    Abstract: A pattern forming material contains a block copolymer or graft copolymer and forms a structure having micro polymer phases, in which, with respect to at least two polymer chains among polymer chains constituting the block copolymer or graft copolymer, the ratio between N/(Nc?No) values of monomer units constituting respective polymer chains is 1.4 or more, where N represents total number of atoms in the monomer unit, Nc represents the number of carbon atoms in the monomer unit, No represents the number of oxygen atoms in the monomer unit.
    Type: Grant
    Filed: October 21, 2011
    Date of Patent: July 15, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koji Asakawa, Toshiro Hiraoka, Yoshihiro Akasaka, Yasuyuki Hotta
  • Publication number: 20140191371
    Abstract: A material can be locally etched with arbitrary changes in the direction of the etch. A ferromagnetic-material-including catalytic particle is employed to etch the material. A wet etch chemical or a plasma condition can be employed in conjunction with the ferromagnetic-material-including catalytic particle to etch a material through a catalytic reaction between the catalytic particle and the material. During a catalytic etch process, a magnetic field is applied to the ferromagnetic-material-including catalytic particle to direct the movement of the particle to any direction, which is chosen so as to form a contiguous cavity having at least two cavity portions having different directions. The direction of the magnetic field can be controlled so as to form the contiguous cavity in a preplanned pattern, and each segment of the contiguous cavity can extend along an arbitrary direction.
    Type: Application
    Filed: January 7, 2013
    Publication date: July 10, 2014
    Applicant: International Business Machines Corporation
    Inventors: Eric A. Joseph, David W. Abraham, Roger W. Cheek, Alejandro G. Schroit, Ying Zhang
  • Patent number: 8765542
    Abstract: One method disclosed includes forming a gate structure of a transistor above a surface of a semiconducting substrate, forming a sidewall spacer proximate the gate structure, forming a sacrificial layer of material above the protective cap layer, sidewall spacer and substrate, forming an OPL layer above the sacrificial layer, reducing a thickness of the OPL layer such that, after the reduction, an upper surface of the OPL layer is positioned at a level that is below a level of an upper surface of the protective cap layer, performing a first etching process to remove the sacrificial layer from above the protective cap layer to expose the protective cap layer for further processing, performing a second etching process to remove the protective cap layer and performing at least one process operation to remove at least one of the OPL layer or the sacrificial layer from above the surface of the substrate.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: July 1, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Joachim Patzer, Frank Seliger, Markus Lenski, Stephan Kronholz
  • Patent number: 8759228
    Abstract: In the manufacture of integrated circuits, reactive compositions that include a reactive etchant species and an oxygen-containing species can provide selective removal of target material and can reduce contamination of gas delivery lines.
    Type: Grant
    Filed: October 9, 2007
    Date of Patent: June 24, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Aaron Wilson, Mark Kiehlbauch
  • Patent number: 8741161
    Abstract: According to one embodiment, a method of manufacturing a semiconductor device, the method includes forming a pillar on a base layer, forming a insulating layer on the base layer to cover the pillar by using GCIB method, where a lowermost portion of an upper surface of the insulating layer is lower than an upper surface of the pillar, and polishing the insulating layer and the pillar to expose a head of the pillar by using CMP method, where an end point of the polishing is the lowermost portion of the upper surface of the insulating layer.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: June 3, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuyuki Sonoda, Kyoichi Suguro, Masatoshi Yoshikawa, Koji Yamakawa, Katsuaki Natori, Daisuke Ikeno
  • Patent number: 8735300
    Abstract: A method of forming contact hole is disclosed, including the steps of: providing a semiconductor substrate having a first dielectric layer, a second dielectric layer and a third dielectric layer formed thereon in this order; forming a first contact hole through the third dielectric layer, the second dielectric layer and the first dielectric layer by using an etching process to expose the semiconductor substrate; removing the third dielectric layer; forming a fourth dielectric layer over the second dielectric layer, the fourth dielectric layer filling the first contact hole; forming a second contact hole through the fourth dielectric layer, the second dielectric layer and the first dielectric layer to expose the semiconductor substrate; and removing the fourth dielectric layer. The method is capable of improving the stability of the contact-hole formation process.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: May 27, 2014
    Assignee: Shanghai Huali Microelectronics Corporation
    Inventors: Yu Zhang, Jun Huang, Chenguang Gai
  • Patent number: 8716144
    Abstract: A method for manufacturing a semiconductor device for forming a deep hole in a substrate by using a photoresist film formed on the substrate includes a positioning step of positioning a substrate inside an etching chamber, the substrate having a photoresist film including an opening part formed thereon, a first etching step of performing plasma etching on the substrate positioned inside the etching chamber by using a first mixed gas including at least SiF4 and O2 with the photoresist film as a mask, and a second etching step of forming a hole in the substrate by performing plasma etching on the substrate by using a second mixed gas including at least SF6, O2, and HBr after the first etching step.
    Type: Grant
    Filed: November 17, 2010
    Date of Patent: May 6, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Shuichiro Uda, Koji Maruyama, Yusuke Hirayama
  • Patent number: 8709267
    Abstract: Methods for patterning material layers, which may be implemented in forming integrated circuit device features, are disclosed. In an example, a method includes forming a first resist layer over a material layer; forming a second resist layer over the first resist layer; forming an opening that extends through the second resist layer and the first resist layer to expose the material layer, wherein the opening has a substantially constant width in the second resist layer and a tapered width in the first resist layer; and performing a tilt-angle deposition process to form a feature over the exposed material layer.
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: April 29, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chwen Yu, Fei-Gwo Tsai, Kai-Wen Cheng
  • Patent number: 8703619
    Abstract: A method of taper-etching a layer to be etched that is made of a dielectric material and has a top surface. The method includes the steps of: forming an etching mask with an opening on the top surface of the layer to be etched; and taper-etching a portion of the layer to be etched, the portion being exposed from the opening, by reactive ion etching so that a groove having two wall faces intersecting at a predetermined angle is formed in the layer to be etched. The step of taper-etching employs an etching gas containing a first gas contributing to the etching of the layer to be etched and a second gas contributing to the deposition of a sidewall protective film, and changes, during the step, the ratio of the flow rate of the second gas to the flow rate of the first gas so that the ratio increases.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: April 22, 2014
    Assignee: Headway Technologies, Inc.
    Inventors: Hironori Araki, Yoshitaka Sasaki, Hiroyuki Ito, Shigeki Tanemura
  • Publication number: 20140103497
    Abstract: A production process for a micromechanical component includes at least partially structuring at least one structure from at least one monocrystalline silicon layer by at least performing a crystal-orientation-dependent etching step on an upper side of the silicon layer with a given (110) surface orientation of the silicon layer. For the at least partial structuring of the at least one structure, at least one crystal-orientation-independent etching step is additionally performed on the upper side of the silicon layer with the given (110) surface orientation of the silicon layer.
    Type: Application
    Filed: October 14, 2013
    Publication date: April 17, 2014
    Applicant: Robert Bosch GmbH
    Inventors: Friedjof Heuck, Christoph Schelling, Mirko Hattass, Benjamin Schmidt
  • Patent number: 8697528
    Abstract: Disclosed is a transistor that incorporates epitaxially deposited source/drain semiconductor films and a method for forming the transistor. A crystallographic etch is used to form recesses between a channel region and trench isolation regions in a silicon substrate. Each recess has a first side, having a first profile, adjacent to the channel region and a second side, having a second profile, adjacent to a trench isolation region. The crystallographic etch ensures that the second profile is angled so that all of the exposed recess surfaces comprise silicon. Thus, the recesses can be filled by epitaxial deposition without divot formation. Additional process steps can be used to ensure that the first side of the recess is formed with a different profile that enhances the desired stress in the channel region.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: April 15, 2014
    Assignee: International Business Machines Corporation
    Inventor: Thomas W. Dyer
  • Patent number: 8697455
    Abstract: Disclosed is a monitoring TEG for an etching process in a semiconductor device. The TEG includes an etch stopping layer on a substrate and a target layer to be etched provided on the etch stopping layer. The target layer to be etched includes a first opening portion formed by etching a portion of the target layer to be etched and a second opening portion formed by etching another portion of the target layer to be etched. The second opening portion has a smaller depth than the first opening portion. A depth of a partial contact hole formed by a first partial etching process may be measured.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: April 15, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyoung-Woo Lee, Hong-Jae Shin, Woo-Jin Jang
  • Patent number: 8692339
    Abstract: In a method for manufacturing a micromechanical component, a cavity is produced in the substrate from an opening at the rear of a monocrystalline semiconductor substrate. The etching process used for this purpose and the monocrystalline semiconductor substrate used are controlled in such a way that a largely rectangular cavity is formed.
    Type: Grant
    Filed: June 3, 2009
    Date of Patent: April 8, 2014
    Assignee: Robert Bosch GmbH
    Inventors: Jochen Reinmuth, Michael Saettler, Stefan Weiss, Arnim Hoechst
  • Patent number: 8679985
    Abstract: A dry etching method for a silicon nitride film capable of improving throughput is provided. A dry etching method for dry-etching a silicon nitride film 103 includes dry-etching the silicon nitride film 103 without generating plasma by using a processing gas containing at least a hydrogen fluoride gas (HF gas) and a fluorine gas (F2 gas), with respect to a processing target object 100 including the silicon nitride film 103.
    Type: Grant
    Filed: February 2, 2010
    Date of Patent: March 25, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Eiichi Nishimura, Yusuke Shimizu
  • Patent number: 8664699
    Abstract: The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: March 4, 2014
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: Ralph G. Nuzzo, John A. Rogers, Etienne Menard, Keon Jae Lee, Dahl-Young Khang, Yugang Sun, Matthew Meitl, Zhengtao Zhu
  • Patent number: 8658537
    Abstract: According to one embodiment, a mask manufacturing method includes acquiring positional deviation information between an actual position of a pattern formed on a mask substrate and a design position decided at the time of designing the pattern; calculating an irradiating amount and an irradiating position of radiation to be irradiated to a predetermined area of a square on the mask substrate according to the calculated positional deviation information; and irradiating the radiation based on the calculated irradiating amount and the calculated irradiating position to form in a part of the mask substrate a heterogeneous layer of which volume is expanded more greatly than that of the surrounding mask substrate region.
    Type: Grant
    Filed: February 15, 2013
    Date of Patent: February 25, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masamitsu Itoh