Abstract: A field effect semiconductor device comprising a high permittivity hafnium (or hafnium-zirconium) nitride gate dielectric and a method of forming the same are disclosed herein. The device comprises a silicon substrate 20 having a semiconducting channel region 24 formed therein. A hafnium (or hafnium-zirconium) nitride gate dielectric layer 36 is formed over this substrate, followed by a conductive gate 38. Hafnium (or hafnium-zirconium) nitride gate dielectric layer 36 has a dielectric constant is significantly higher than the dielectric constant of silicon dioxide.

Abstract: An embodiment of the present invention is a method of forming an ultra-thin dielectric layer, the method comprising the steps of: providing a substrate having a semiconductor surface; forming an oxygen-containing layer on the semiconductor surface; exposing the oxygen-containing layer to a nitrogen-containing plasma to create a uniform nitrogen distribution throughout the oxygen-containing layer; and re-oxidizing and annealing the layer to stabilize the nitrogen distribution, heal plasma-induced damage, and reduce interfacial defect density.

Abstract: A treated substrate produced by a process for treating a dielectric layer on a substrate, which comprises applying a sufficient amount of a liquid dielectric composition onto an upper surface of a semiconductor substrate to thereby form a dielectric layer on the upper surface of the substrate, the dielectric layer having a thickness of from about 2,000 to about 50,000 angstroms; heating a surface of the dielectric layer and exposing the dielectric layer to an electron beam radiation, in which the electron beam radiation is concentrated at a distance within about 1,000 angstroms from the surface of the dielectric layer, under vacuum conditions to remove substantially all moisture and/or contaminants from the surface of the dielectric layer at a depth of up to about 1,000 angstroms from the surface of the dielectric layer; and chemical vapor depositing a chemical vapor deposit material onto the surface of the treated dielectric layer while maintaining the vacuum conditions.

Abstract: The present invention fabricates an oxide-nitride-oxide (ONO) layer of an NROM. A first oxide layer is formed on the surface of the substrate of a semiconductor wafer. Then two CVD processes are performed to respectively form a first nitride layer and a second nitride layer on the surface of the first oxide layer, and the boundary between the second nitride layer and the first nitride layer is so forming an interface. Thereafter, a second oxide layer is formed on the surface of the second nitride layer completing the process of manufacturing the ONO layer. The second nitride layer and the first nitride layer are used as a floating gate of the NROM, and the interface is used as a deep charge trapping center to improve the charge trapping efficiency, and furthermore, to improve the endurance and reliability of the NROM.

Abstract: A method for the production of anisotropic, three dimensional thin films is disclosed. Instead of fabricating away from the routine tendency of vacuum sputter deposited thin films to form discontinuous islands which then accrete into the third dimension, the present method encourages this anisotropic formation. By precisely controlling gun voltage and deposition time, together with spectral control over the plasma forming gas and any reactive gas, with accurate substrate temperature control, and real-time feed-back and control over deposition parameters, two or more materials are sequentially grown on a substrate as distinct discontinuous islands. The resultant film maintains the optimum characteristics of each one of the film's components. Other novel structures made possible by the method of the invention include unique single component and post method deposited component anisotropic thin films.

Abstract: Methods for forming dielectric layers over polysilicon substrates, useful in the construction of capacitors and other semiconductor circuit components are provided. A self-limiting nitric oxide (NO) anneal of a polysilicon layer such as an HSG polysilicon capacitor electrode, at less than 800° C., is utilized to grow a thin oxide (oxynitride) layer of about 40 angstroms or less over the polysilicon layer. The NO anneal provides a nitrogen layer at the polysilicon-oxide interface that limits further oxidation of the polysilicon layer and growth of the oxide layer. The oxide layer is exposed to a nitrogen-containing gas to nitridize the surface of the oxide layer and reduce the effective dielectric constant of the oxide layer. The process is particularly useful in forming high K dielectric insulating layers such as tantalum pentoxide over polysilicon.

Abstract: A method for fabricating a silicon dioxide/silicon nitride/silicon dioxide (ONO) stacked composite having a thin silicon nitride layer for providing a high capacitance interpoly dielectric structure. In the formation of the ONO composite, a bottom silicon dioxide layer is formed on a substrate such as polysilicon. A silicon nitride layer is formed on the silicon dioxide layer and is thinned by oxidation. The oxidation of the silicon nitride film consumes some of the silicon nitride by a reaction that produces a silicon dioxide layer. This silicon dioxide layer is removed with a hydrofluoric acid dilution. The silicon nitride layer is again thinned by re-oxidization as a top silicon dioxide layer is formed on the silicon nitride layer. A second layer of polysilicon is deposited over the silicon nitride, forming an interpoly dielectric.

Abstract: A dielectric structure is disclosed for silicon carbide-based semiconductor devices. In gated devices, the structure includes a layer of silicon carbide, a layer of silicon dioxide on the silicon carbide layer, a layer of another insulating material on the silicon dioxide layer, with the insulating material having a dielectric constant higher than the dielectric constant of silicon dioxide, and a gate contact to the insulating material. In other devices the dielectric structure forms an enhanced passivation layer or field insulator.

Abstract: The reliability of integrated circuits fabricated with trench isolation is improved by forming a trench isolation structure with a void-free trench plug (36). In one embodiment, a polysilicon layer (28) is formed within a trench (22) and then subsequently oxidized to form a first dielectric layer (30). The first dielectric layer (30) is then etched and a second dielectric layer (34) is subsequently formed over the etched dielectric layer (32). A portion of the second dielectric layer (34) is then removed using chemical-mechanical polishing to form a void-free trench plug (36) within the trench (22). In addition, reliability is also improved by minimizing subsequent etching of trench plug (36) after it has been formed.

Abstract: The present invention provides a passivation film on a semiconductor wafer. The semiconductor wafer comprises a dielectric layer and a patterned conductive layer on the dielectric layer. The passivation film comprises a high density plasma (HDP) oxide layer positioned on the surface of the conductive layer and on the surface of the dielectric layer that is not covered by the conductive layer, a silicon nitride layer positioned on the HDP oxide layer, and a water-resistant layer positioned on the silicon nitride layer. The HDP oxide layer possesses good gap filling abilities to fill the spaces inside the conductive layer.

Abstract: A process for forming silicate glass layers on substrates is disclosed. A silicate glass layer is first deposited onto a substrate, such as a semiconductor wafer. The wafer is then placed in a thermal processing chamber and heated in the presence of a reactive gas. The object is heated to a temperature sufficient for reflow of the silicate glass. In one embodiment, the atmosphere contained within the processing chamber comprises steam in combination with a reactive gas. The reactive gas can be, for instance, hydrogen, oxygen, nitrogen, dinitrogen oxide, ozone, hydrogen peroxide, atomic and/or molecular hydrogen, or radicals or mixtures thereof.

Abstract: A method for manufacturing a semiconductor device of the present invention includes, forming a first silicon oxide film by HDP-CVD so as to bury a recess portion in a three-dimensional portion formed in a surface region of a semiconductor workpiece to a position lower than an upper surface of the recess portion, and forming a second silicon oxide film by SOG on the first silicon oxide film so as to fill the recess portion.

Abstract: The present invention is described in several embodiments depicting structures and methods to form these structures. A first embodiment is a structure having a silicon dioxide film bonded to a metal film comprising: a metal nitride film bonded to the metal film; and the silicon dioxide film bonded to the metal nitride film. A second embodiment is a structure having a silicon dioxide film bonded to a metal film comprising: a metal oxide film bonded to the metal film; and the silicon dioxide film bonded to the metal oxide film. A third embodiment is a structure having a silicon dioxide film is bonded to a metal film comprising: a metal/oxide/nitride film bonded to the metal film; and the silicon dioxide film bonded to the metal/oxide/nitride film.

Abstract: A fluorine-containing organic film having a relative dielectric constant of 4 or less is deposited on a semiconductor substrate using a material gas containing fluorocarbon as a main component in a reactor chamber of a plasma processing apparatus. During the deposition of the fluorine-containing organic film, a scavenger gas for scavenging fluorine constituting the fluorocarbon is mixed in the material gas. The proportion of the mixed scavenger gas in the material gas is changed to adjust the mechanical strength and relative dielectric constant of the fluorine-containing organic film.

Abstract: A method for protecting the surface of a semiconductor material from damage and dopant passivation is described. A barrier layer of dense or reactive material is deposited on the semiconductor material shortly after growth in a growth reactor such as a MOCVD reactor, using the MOCVD source gasses. The barrier layer blocks the diffusion of hydrogen into the material. The reactor can then be cooled in a reactive or non-reactive gas ambience. The semiconductor material can then be removed from the reactor with little or no passivation of the dopant species. The barrier layer can be removed using a variety of etching processes, including wet chemical etching or can be left at the semiconductor material for surface protection. The barrier layer can also be a gettering layer that chemically binds hydrogen trapped in the semiconductor material and/or blocks hydrogen diffusion into the material.

Abstract: To suppress the deposition of thin films on exposed positions inside the process chamber and facilitate the selective deposition of good quality thin films with high productivity, disilane gas is introduced to a substrate 9 heated by a heater 4 inside a process chamber 1, and a silicon film is deposited only on the silicon surfaces of substrate 9 by thermal CVD. A heat-reflecting plate 6, which is provided inside process chamber 1 to reflect the heat radiated from substrate 9 back to the substrate, is made of silicon with a silicon oxide film 61 formed on its surface. Silicon atoms separate out and adhere to the surface of silicon oxide layer 61 through the decomposition of disilane, but a reforming operation in which oxygen gas is introduced is performed between the film deposition processing of each substrate 9, whereby the Si atoms which exist in an isolated state with no Si—Si bonds between them are converted to silicon oxide.

Abstract: A method for protecting the surface of a semiconductor material from damage and dopant passivation is described. A barrier layer of dense or reactive material is deposited on the semiconductor material shortly after growth in a growth reactor such as a MOCVD reactor, using the MOCVD source gasses. The barrier layer blocks the diffusion of hydrogen into the material. The reactor can then be cooled in a reactive or non-reactive gas ambience. The semiconductor material can then be removed from the reactor with little or no passivation of the dopant species. The barrier layer can be removed using a variety of etching processes, including wet chemical etching or can be left at the semiconductor material for surface protection. The barrier layer can also be a gettering layer that chemically binds hydrogen trapped in the semiconductor material and/or blocks hydrogen diffusion into the material.

Abstract: A method for depositing a first metal layer such as tantalum or copper on a patterned semiconductor wafer using a metal sputtering tool that typically includes an electrically biased wafer chuck is disclosed. Initially, a first test wafer is placed on the wafer chuck and a first test layer of materials is deposited on the first test wafer. During the deposition of the first test layer on the first test wafer, the wafer receives the electrical bias at a first level. A second test wafer is then placed on the wafer chuck and a second test layer of material is deposited with the second wafer receiving a second level of electrical bias. The difference in thickness between the first layer and the second layer is then determined. If the difference in thickness is within a predetermined range, the metal sputtering chamber is qualified to deposit a production layer on a production semiconductor wafer.

Abstract: Silicon oxide films which are good as gate insulation films are formed by subjecting a silicon oxide film which has been formed on an active layer comprising a silicon film by means of a PVD method or CVD method to a heat treatment at 300-700° C. in a dinitrogen monoxide atmosphere, or in an NH3 or N2H4 atmosphere, while irradiating with ultraviolet light, reducing the hydrogen and carbon contents in the silicon oxide film and introducing nitrogen into the boundary with the silicon film in particular. Furthermore, silicon oxide films which are good as gate insulating films have been formed by subjecting silicon oxide films which have been formed on an active layer comprising a silicon film by means of a PVD method or CVD method to a heat treatment at 300-700° C. in an N2O atmosphere (or hydrogen nitride atmosphere) while irradiating with ultraviolet light, and then carrying out a heat treatment at 300-700° C.

Abstract: In accordance with the present invention, a method for forming a crystalline silicon nitride layer, includes the steps of providing a crystalline silicon substrate with an exposed surface, precleaning the exposed surface by employing a hydrogen prebake and exposing the exposed surface to nitrogen to form a crystalline silicon nitride layer. Also, a trench capacitor, in accordance with the present invention, includes a crystalline silicon substrate including deep trenches having surface substantially free of native oxide. A dielectric stack, including a crystalline silicon nitride layer, is formed on the sidewalls of the trenches. The dielectric stack forms a node dielectric between electrodes of the trench capacitor.

Abstract: Highe quality silicon oxide having a plurality of monolayers is grown at a high temperature on a silicon substrate. A monolayer of silicon oxide is a single layer of silicon atoms and two oxygen atoms per silicon atom bonded thereto. The silicon oxide is etched one monolayer at a time until a desired thickness of the silicon layer is obtained. Each monolayer is removed by introducing a first gas to form a reaction layer on the silicon oxide. The gas is then purged. Then the reaction layer is activated by either another gas or heat. The reaction layer then acts to remove a single monolayer. This process is repeated until a desired amount of silicon oxide layer remains. Because this removal process is limited to removing one monolayer at a time, the removal of silicon oxide is well controlled. This allows for a precise amount of silicon oxide to remain.

Abstract: According to a disclosed embodiment, the surface of a semiconductor wafer is covered by an etch stop layer. For example, the etch stop layer can be composed of silicon dioxide. A cap layer is then fabricated over the etch stop layer. For example, the cap layer can be a polycrystalline silicon layer fabricated over the etch stop layer. The cap layer is then selectively etched down to the etch stop layer creating an opening in the cap layer according to a pattern. The pattern can be formed, for example, by covering the cap layer with photoresist and selective etching. Selective etching can be accomplished by using a dry etch process which etches the cap layer without substantially etching the etch stop layer. The etch stop layer is then removed using, for example, a hydrogen-fluoride cleaning process. A semiconductor crystal is then grown by epitaxial deposition in the opening. For example, the semiconductor crystal can be silicon-germanium. Moreover, a single crystal semiconductor structure of high quality, i.

Abstract: The present invention relates to a method of reducing Si consumption during a self-aligned silicide process which employs a M—Si or M—Si—Ge alloy, where M is Co, Ni or CoNi, and a blanket layer of Si. The present invention is particularly useful in minimizing Si consumption in shallow junction and thin silicon-on-insulator (SOI) electronic devices.

Abstract: Disclosed is a semiconductor structure and manufacturing process for making an integrated FET and photodetector optical receiver on a semiconductor substrate. A FET is formed by forming at least one p region in a p-well of the substrate and forming at least one n region in the p-well of the substrate. A p-i-n photodetector is formed in the substrate by forming at least one p region in an absorption region of the substrate when forming the at least one p region in the p well of the FET and forming at least one n region in the absorption region of the substrate when forming the at least one n region in the p-well of the FET.

Abstract: A process for forming a storage capacitor for a semiconductor assembly, by forming a first storage electrode having a top surface consisting of titanium nitride; forming a barrier layer directly on the titanium nitride, the barrier layer (a material containing any one of amorphous silicon, tantalum, titanium, or strontium) being of sufficient thickness to substantially limit the oxidation of the titanium nitride when the semiconductor assembly is subjected to an oxidizing agent (either an oxidizing agent or an nitridizing agent); converting a portion of the barrier layer to a dielectric compound; depositing a storage cell dielectric directly on the dielectric compound, the storage cell dielectric being of the same chemical makeup as the dielectric compound and thereby using the dielectric compound as a nucleation surface; and forming a second capacitor electrode on the storage cell dielectric.

Abstract: A method of using dichloroethene and ammonia to provide chlorine and nitrogen during the growth of an in-situ hardened gate dielectric. The method provides a gaseous source of gettering agent and a gaseous source of dielectric strengthening agent that are compatible with each other and can be used during the formation of in-situ hardened dielectric or the strengthening of an already formed dielectric.

Abstract: A method for filling a trench within a silicon substrate. There is first provided a silicon substrate having a trench formed therein. There is then formed upon the substrate and within the trench a gap filling silicon oxide trench fill layer employing an ozone assisted thermal chemical vapor deposition (SACVD) method. There is then carried out a densification of the gap filling silicon oxide trench fill layer by annealing in an oxidizing atmosphere at an elevated temperature. Finally, the gap filling silicon oxide trench fill layer is planarized by chemical mechanical polish (CMP) planarization to form the silicon oxide trench filling layer with attenuated surface sensitivity and with an enhanced bulk quality and reduced trench recess at corners.

Abstract: A method of enriching the surface of a substrate with a solute material that was originally dissolved in the substrate material, to yield a uniform dispersion of the solute material at the substrate surface. The method generally entails the use of a solvent material that is more reactive than the solute material to a chosen reactive agent. The surface of the substrate is reacted with the reactive agent to preferentially form a reaction compound of the solvent material at the surface of the substrate. As the compound layer develops, the solute material segregates or diffuses out of the compound layer and into the underlying substrate, such that the region of the substrate nearest the compound layer becomes enriched with the solute material. At least a portion of the compound layer is then removed without removing the underlying enriched region of the substrate.

Abstract: A film of fluorine-doped silicon glass (“FSG”) is exposed to a nitrogen-containing plasma to nitride a portion of the FSG film. In one embodiment, the FSG film is chemically-mechanically polished prior to nitriding. The nitriding process is believed to scavenge moisture and free fluorine from the FSG film. The plasma can heat the FSG film to about 400° C. for about one minute to incorporate about 0.4 atomic percent nitrogen to a depth of nearly a micron. Thus, the nitriding process can passivate the FSG film deeper than a via depth.

Abstract: The present invention is directed to a method for fabricating a capacitor in a semiconductor device. The capacitor uses a Ta2O5 film as a dielectric film. The method for fabrication can include forming a nitride film on a capacitor lower electrode by a rapid thermal nitration process, and depositing the Ta2O5 film on the nitride film and heat treating using a rapid thermal process including N2O gas to form an SiON film at an interface between the capacitor lower electrode and the Ta2O5 film. A capacitor upper electrode is then formed on the Ta2O5 film. The method according to the present invention can reduce a device deterioration, improve leakage current characteristics and increase a device reliability.

Abstract: An apparatus for planarizing or patterning a dielectric film on a substrate is provided. The apparatus includes a press for applying contact pressure to an operably connected compression tool. The compression tool has a working face that is planar or patterned. A controller for regulating the position, timing and force applied by the compression tool to the dielectric film is also provided. There is also provided a support, with an optional workpiece holder for supporting the substrate and dielectric film during contact with the compression tool. Methods of using the apparatus, as well as planarized and/or patterned dielectric films are also provided.

Abstract: A polycrystalline or polysilicon film having large grain size, such as 1 &mgr;m to 2 &mgr;m in diameter or greater, is obtained over the methods of the prior art by initially forming a silicon film, which may be comprised of amorphous silicon or micro-crystalline silicon or contains micro-crystal regions in the amorphous phase, at a low temperature via a chemical vapor deposition (CVD) method, such as by plasma chemical vapor deposition (PCVD) with silane gas diluted with, for example, hydrogen, argon or helium at a temperature, for example, in the range of room temperature to 600° C. This is followed by solid phase recrystallization of the film to form a polycrystalline film which is conducted at a relatively low temperature in the range of about 550° C. to 650° C. in an inert atmosphere, e.g., N or Ar, for a period of about several hours to 40 or more hours wherein the temperature is gradually increased, e.g., at a temperature rise rate below 20° C./min, preferably about 5° C.

Abstract: A method for fabricating a semiconductor device including a silicon substrate includes forming a thin Nitrogen Oxide base film on a substrate, and then annealing the substrate in ammonia. An ultra-thin nitride film is deposited on the base film. The semiconductor device is then oxidized in Nitrogen Oxide. FET gates are then conventionally formed over the gate insulator. The resultant gate insulator is electrically insulative without degrading performance with respect to a conventional gate oxide insulator.

Abstract: A method is provided for pre-treating reactor parts, comprising quartz or silicon, in use in chemical vapor deposition reactors. Applying the pre-treatment prior to deposition increases the cumulative deposited film thickness that can be received by the reactor parts before contamination of wafers processed in said reactors exceeds acceptable limits. The pre-treatment comprises nitridation of the surface of the reactor part, such as by heating the reactor part to a temperature of at least 800° C. and exposing the reactor part to a nitrogen-containing gas.

Abstract: A finished structure (100) includes a semiconductive region (102), a first oxide layer (106), a second oxide layer (108), and a conductive layer (110). The first oxide layer (106) lies between the semiconductive region (102) and the second oxide layer (108); and the second oxide layer (108) lies between the first oxide layer (106) and the conductive layer (110). The first oxide layer (106) includes at least a portion that is amorphous or includes a first element, a second element, and a third element. In the latter, the first element is a metallic element, and each of the first, second, and third elements are different from each other. A process for forming a structure (100) includes forming a first layer (106) near a semiconductive region (102), forming a second layer (108) after forming the first layer (106), and forming a third layer (110) after forming the second layer (108). The first oxide layer (106) includes a metallic element and oxygen. The third layer (110) is a non-insulating layer.

Abstract: According to one aspect of the invention, a method of processing a wafer is provided. The wafer is located in a wafer processing chamber of a system for processing a wafer. A silicon layer is then formed on the wafer while the wafer is located in the wafer processing chamber. The wafer is then transferred from the wafer processing chamber to a loadlock chamber of the system. Communication between the processing chamber and the loadlock chamber is closed off. The wafer is then exposed to ozone gas while located in the loadlock chamber, whereafter the wafer is removed from the loadlock chamber out of the system.

Abstract: A dielectric insulating composite for insulating a floating gate from a control gate in a non-volatile memory is described. A material, such as an undoped polysilicon, amorphous silicon, or amorphous polysilicon or a silicon rich nitride, is inserted in the gate structure. The oxide film that results from the oxidation of these films is relatively free from impurities. As a result, charge leakage between the floating gate and control gate is reduced.

Abstract: The present invention is described in several embodiments depicting structures and methods to form these structures. A first embodiment is a structure having a silicon dioxide film bonded to a metal film comprising: a metal nitride film bonded to the metal film; and the silicon dioxide film bonded to the metal nitride film. A second embodiment is a structure having a silicon dioxide film bonded to a metal film comprising: a metal oxide film bonded to the metal film; and the silicon dioxide film bonded to the metal oxide film. A third embodiment is a structure having a silicon dioxide film bonded to a metal film comprising: a metal/oxide/nitride film bonded to the metal film; and the silicon dioxide film bonded to the metal/oxide/nitride film.

Abstract: A first p-type silicon layer (3) is formed as a buried layer in a p-type single crystal silicon substrate (2), and an n-type silicon layer (4) is formed on the upper side of the silicon substrate (2). A second p-type silicon layer (5) for forming an opening is defined in the n-type silicon layer (4), and a metal protecting film (14) is formed on the upper side of the n-type silicon layer (4). An electrode layer (18) is formed on the rear side of the silicon substrate (2) via an oxide film (17). The electrode layer (18) and the silicon substrate (2) are electrically connected to each other via a connecting opening (17a) at portions aligned with the first p-type silicon layer (3). After a positive terminal and a negative terminal of a DC power source (V) are connected to the electrode layer (18) and to a counter electrode (11) respectively, a voltage is applied between the electrode layer (18) and the counter electrode (11) to carry out anodization.

Abstract: A gate structure for an ONO flash memory device includes a first layer of silicon oxide on top of a semiconductor substrate, a second layer of silicon oxide, a layer of silicon nitride sandwiched between the two silicon oxide layers, and a control gate on top of the second layer of silicon oxide. Nitrogen is implanted into the first layer of silicon oxide at less than normal energy levels to reduce the amount of damage to the underlying semiconductor substrate. After low energy nitrogen implantation, the semiconductor structure is heated to anneal out the implant damage and to diffuse the implanted nitrogen to the substrate and silicon oxide interface to cause SiN bonds to be formed at that interface. The SiN bonds is desirable because they improve the bonding strength at the interface and the nitrogen remaining in the silicon oxide layer increases the oxide bulk reliability.

Abstract: The present invention relates to a film forming method of forming an interlayer insulating film having a low dielectric constant to cover a wiring. In construction, an insulating film for covering a wiring is formed on the substrate by plasmanizing a film forming gas, that consists of any one selected from a group consisting of alkoxy compound having Si—H bonds and siloxane having Si—H bonds and any one oxygen-containing gas selected from a group consisting of O2, N2O, NO2, CO, CO2, and H2O, to react.

Abstract: A method of passivating an integrated circuit (IC) is provided. An insulating layer is formed onto the IC. An adhesion layer is formed onto a surface of the insulating layer by treating the surface of the insulating layer with a gas and gas plasma. A first passivation layer is formed upon the adhesion layer, the first passivation layer and the gas and gas plasma including at least one common chemical element.

Abstract: A silicon nitride deposition method includes providing a substrate surface. Silicon is predeposited on at least a portion of the surface. After predeposition of the silicon, silicon nitride is deposited. The substrate surface may include one or more component surfaces and when at least a monolayer of silicon is predeposited thereon silicon nitride nucleation at the substrate surface is performed at a substantially equivalent rate independent of the different component surfaces.

Abstract: The present invention provides a method of fabricating capacitor dielectric layer. A bottom electrode covered by a native oxide layer on a chip is provided. The chip is disposed into a low pressure furnace. A mixture of dichlorosilane and ammonia is introduced into the low pressure furnace to form a nitride layer on the native oxide layer. In the same low pressure furnace, nitrogen monoxide or nitric oxygen is infused to form an oxynitride layer on the nitride layer.

Abstract: A dielectric insulating composite for insulating a floating gate from a control gate in a non-volatile memory is described. A material, such as an undoped polysilicon, amorphous silicon, or amorphous polysilicon or a silicon rich nitride, is inserted in the gate structure. The oxide film that results from the oxidation of these films is relatively free from impurities. As a result, charge leakage between the floating gate and control gate is reduced.

Abstract: A method is described for filling a high-aspect-ratio feature, in which compatible deposition and etching steps are performed in a sequence. The feature is formed as an opening in a substrate having a surface; a fill material is deposited at the bottom of the feature and on the surface of the substrate; deposition on the surface adjacent the feature causes formation of an overhang structure partially blocking the opening. The fill material is then reacted with a reactant to form a solid reaction product having a greater specific volume than the fill material. The overhang structure is thus converted into a reaction product structure blocking the opening. The reaction product (including the reaction product structure) is then desorbed, thereby exposing unreacted fill material at the bottom of the feature. The depositing and reacting steps may be repeated, with a final depositing step to fill the feature. Each sequence of depositing, reacting and desorbing reduces the aspect ratio of the feature.

Abstract: A method is disclosed for making gate oxides on a silicon wafer surface for multiple voltage applications comprising the steps of growing an oxide layer (12) on a wafer (10) surface, exposing the surface of the oxide layer (12) to a nitrogen ion containing plasma to form a nitrided layer (22). Next, a photoresist layer (14) is deposited over a portion of the oxide layer (12) and the isolation (30), followed by etching of the exposed nitrided layer 22 and a portion of the oxide layer (12) to create a thinner silicon dioxide layer (32). The photoresist layer (14) is removed, the wafer (10) is cleaned and then the thinner silicon dioxide layer (32) is removed prior to a final oxidation step to form a thinner silicon dioxide layer (34) having a different thickness than the silicon dioxide layer (12).

Abstract: The present invention provides a method for forming a dielectric 1; 7, 8 on a semiconductor substrate 2 having the following steps: implantation of ions into a surface layer of the semiconductor substrate 2, the ions forming a first dielectric layer 7; and performance of a thermal oxidation process for forming a second dielectric layer 8 on the first dielectric layer 7. Consequently, e.g. by the implantation of nitrogen ions into a surface layer of a silicon substrate, the imperfection density of the dielectric formed can be reduced approximately by a factor of 10.

Abstract: A method for making an improved ultra-thin silicon nitride-oxide gate insulating layer for field effect transistors (FETs) is achieved. After forming a field oxide to electrically isolate device areas on a silicon substrate, an ultra-thin silicon nitride-oxide insulating layer is formed in two process steps. In the first process step a silicon nitride layer is formed on the device areas on the substrate using a low-pressure rapid thermal process (LP-RTP) and a reactant gas of ammonia (NH3) while insuring that the RTP tool is free of oxygen. Then a second process step is carried out sequentially in the same LP-RTP at an elevated temperature and using an oxygen-rich ambient (dinitrogen oxide N2O) as a reoxidation gas. The non-self-limiting characteristic of the ultra-thin-silicon nitride layer results in the controllable diffusion of the dissociated oxygen (O) and nitrous oxide (NO) through the silicon nitride layer to form a thin good quality silicon oxide layer on and in the substrate surface.

Abstract: A method for forming a quaternary alloy film of Co—W—P—Au for use as a diffusion barrier layer on a copper interconnect in a semiconductor structure and devices formed incorporating such film are disclosed. In the method, a substrate that has copper conductive regions on top is first pre-treated by two separate pre-treatment steps. In the first step, the substrate is immersed in a H2SO4 rinsing solution and next in a solution containing palladium ions for a length of time sufficient for the ions to deposit on the surface of the copper conductive regions. The substrate is then immersed in a solution that contains at least 15 gr/l sodium citrate or EDTA for removing excess palladium ions from the surface of the copper conductive regions.