Abstract: Provided are a method of manufacturing a transparent N-doped p-type ZnO semiconductor layer using a surface chemical reaction between precursors containing elements constituting thin layers, and a thin film transistor (TFT) including the p-type ZnO semiconductor layer. The method includes the steps of: preparing a substrate and loading the substrate into a chamber; injecting a Zn precursor and an oxygen precursor into the chamber, and causing a surface chemical reaction between the Zn precursor and the oxygen precursor using an atomic layer deposition (ALD) technique to form a ZnO thin layer on the substrate; and injecting a Zn precursor and an nitrogen precursor into the chamber, and causing a surface chemical reaction between the Zn precursor and the nitrogen precursor to form a doping layer on the ZnO thin layer.

Abstract: An apparatus and method for forming an integrated barrier layer on a substrate is described. The integrated barrier layer comprises at least a first refractory metal layer and a second refractory metal layer. The integrated barrier layer is formed using a dual-mode deposition process comprising a chemical vapor deposition (CVD) step and a cyclical deposition step. The dual-mode deposition process may be performed in a single process chamber.

Abstract: A method for manufacturing an insulating film, which is used as an insulating film used for a semiconductor integrated circuit, whose reliability can be ensured even though it has small thickness, is provided. In particular, a method for manufacturing a high-quality insulating film over a substrate having an insulating surface, which can be enlarged, at low substrate temperature, is provided. A monosilane gas (SiH4), nitrous oxide (N2O), and a rare gas are introduced into a chamber to generate high-density plasma at a pressure higher than or equal to 10 Pa and lower than or equal to 30 Pa so that an insulating film is formed over a substrate having an insulating surface. After that, the supply of a monosilane gas is stopped, and nitrous oxide (N2O) and a rare gas are introduced without exposure to the air to perform plasma treatment on a surface of the insulating film.

Abstract: Methods and apparatus for processing a substrate are provided herein. In some embodiments, a method of processing a substrate may include providing a substrate having at least one of a defect or a contaminant disposed on or near a surface of the substrate; and selectively annealing a portion of the substrate with a laser beam in the presence of a process gas comprising hydrogen. The laser beam may be moved over the substrate or continuously, or in a stepwise fashion. The laser beam may be applied in a continuous wave or pulsed mode. The process gas may further comprise an inert gas, such as, at least one of helium, argon, or nitrogen. A layer of material may be subsequently deposited atop the annealed substrate.

Abstract: An in-situ hybrid film deposition method for forming a high-k dielectric film on a plurality of substrates in a batch processing system. The method includes loading the plurality of substrates into a process chamber of the batch processing system, depositing by atomic layer deposition (ALD) a first portion of a high-k dielectric film on the plurality of substrates, after depositing the first portion, and without removing the plurality of substrates from the process chamber, depositing by chemical vapor deposition (CVD) a second portion of the high-k dielectric film on the first portion, and removing the plurality of substrates from the process chamber. The method can further include alternatingly repeating the deposition of the first and second portions until the high-k dielectric film has a desired thickness. The method can still further include pre-treating the substrates and post-treating the high-k dielectric film in-situ prior to the removing.

Abstract: A number of methods are provided for semiconductor processing. One such method includes depositing a first precursor material on a surface at a particular temperature to form an undoped polysilicon. The method also includes depositing a second precursor material on a surface of the undoped polysilicon at substantially the same temperature, wherein the undoped polysilicon serves as a seed to accelerate forming a doped polysilicon.

Abstract: The invention includes methods of forming layers comprising epitaxial silicon. In one implementation, an opening is formed within a first material received over a monocrystalline material. Opposing walls, of a second material, are formed within the opening which are laterally displaced inwardly of the opposing sidewalls, a space being received between the opposing walls and the opposing sidewalls, with monocrystalline material being exposed between the opposing walls within the opening. A silicon-comprising layer is epitaxially grown from the exposed monocrystalline material within the second material-lined opening. Other aspects and implementations are contemplated.

Abstract: An image sensor and a method for manufacturing the same are provided. The image sensor can comprise a substrate, a metal pad, and a sulfur layer. The substrate can include a pixel region and a pad region. The metal pad can be formed of a material containing sulfur and can be disposed in the pad region of the substrate. The sulfur layer can be formed from the sulfur of the metal pad and provided on a top surface of the metal pad.

Abstract: A method of forming a semiconductor device includes providing a substrate for the semiconductor device. A base oxide layer is formed overlying the substrate by applying a rapid thermal oxidation (RTO) of the substrate in the presence of oxygen. A nitrogen-rich region is formed within and at a surface of the base oxide layer. The nitrogen-rich region overlies an oxide region in the base oxide layer. Afterwards, the semiconductor device is annealed in a dilute oxygen and hydrogen-free ambient of below 1 Torr partial pressure of the oxygen. The annealing heals bond damage in both the oxide region and the nitrogen-rich region in the base oxide layer. After annealing the semiconductor device in the dilute oxygen ambient, in-situ steam generation (ISSG) is used to grow and density the oxide region in the base oxide layer at an interface between the substrate and base oxide layer.

Abstract: Some embodiments include methods of forming dielectric materials associated with semiconductor constructions. A semiconductor substrate surface having two different compositions may be exposed to a first silanol, then to organoaluminum to form a monolayer, and finally to a second silanol to form a dielectric material containing aluminum from the organoaluminum together with silicon and oxygen from the second silanol. Alternatively, or additionally, an organoaluminum monolayer may be formed across a semiconductor substrate, and then exposed to silanol within a deposition chamber, with the silanol being provided in two doses. Initially, a first dose of the silanol is injected the chamber, and then the first dose is flushed from the chamber to remove substantially all unreacted silanol from within the chamber. Subsequently, the second dose of silanol is injected into the chamber. Some embodiments include semiconductor constructions.

Abstract: A semiconductor device and method for making such that provides improved mechanical strength is disclosed. The semiconductor device comprises a semiconductor substrate; an adhesion layer disposed over the semiconductor substrate; and a porous low-k film disposed over the semiconductor substrate, wherein the porous low-k film comprises a porogen and a composite bonding structure including at least one Si—O—Si bonding group and at least one bridging organic functional group.

Abstract: A method of fabricating silicon-on-insulators (SOIs) having a thin, but uniform buried oxide region beneath a Si-containing over-layer is provided. The SOI structures are fabricated by first modifying a surface of a Si-containing substrate to contain a large concentration of vacancies or voids. Next, a Si-containing layer is typically, but not always, formed atop the substrate and then oxygen ions are implanted into the structure utilizing a low-oxygen dose. The structure is then annealed to convert the implanted oxygen ions into a thin, but uniform thermal buried oxide region.

Abstract: A process for forming an oxide-containing film from silicon is provided that includes heating the silicon substrates to a process temperature of between 250° C. and 1100° C. with admission into the process chamber of diatomic reductant source gas Z-Z? where Z and Z? are each H, D and T and a stable source of oxide ion. Multiple exhaust ports exist along the vertical extent of the process chamber to create reactant across flow. A batch of silicon substrates is provided having multiple silicon base layers, each of the silicon base layers having exposed <110> and <100> planes and a film residual stress associated with the film being formed at a temperature of less than 600° C. and having a <110> film thickness that exceeds a <100> film thickness on the <100> crystallographic plane by less than 20%, or a film characterized by thickness anisotropy less than 18% and an electrical breakdown field of greater than 10.5 MV/cm.

Abstract: The present invention provides atomic layer deposition systems and methods that include metal compounds with at least one ?-diketiminate ligand. Such systems and methods can be useful for depositing metal-containing layers on substrates.

Abstract: A method of fabricating a device is described. A substrate having at least two isolation structures is provided. A first oxide layer and a first conductive layer are sequentially formed on the substrate between the isolation structures. A first nitridation process is performed to form a first nitride layer on the surface of the first conductive layer and a first oxynitride layer on the surface of the isolation structures. A second oxide layer is formed on the first nitride layer and first oxynitride layer. A densification process is performed to oxidize the first oxynitride layer on the surface of the isolation structures. A second nitride layer and a third oxide layer are sequentially formed on the second oxide layer. A second nitridation process is performed to form a third nitride layer on the surface of the third oxide layer. A second conductive layer is formed on the third nitride layer.

Abstract: A method for fabricating a nonvolatile charge trap memory device is described. The method includes first forming a tunnel dielectric layer on a substrate in a first process chamber of a single-wafer cluster tool. A charge-trapping layer is then formed on the tunnel dielectric layer in a second process chamber of the single-wafer cluster tool. A top dielectric layer is then formed on the charge-trapping layer in the second or in a third process chamber of the single-wafer cluster tool.

Abstract: A memory device includes a composite dielectric layer overlying a substrate. The composite dielectric layer includes a first dielectric layer, a bonding interface, and a second dielectric layer. The first and the second dielectric layers are bonded together at the bonding interface. A first plurality of conductive lines overlies the combined dielectric layer. One or more semiconductor switching devices formed in a single-crystalline semiconductor layer overlie and are coupled with one of the first plurality of conductive lines. The memory device also has one or more two-terminal memory elements, each of which overlies and is coupled to a corresponding one of the single-crystalline switching device. A second plurality of conductive lines overlies the memory elements. In the memory device, each of the memory elements is coupled to one of the first plurality of conductive lines and one of the second plurality of conductive lines.

Abstract: A method of forming a tunnel insulating layer in a flash memory device, comprising: forming an oxide layer on a semiconductor substrate, forming a nitrogen-containing layer to a surface of the oxide layer, and forming a nitrogen-accumulating layer on an interface defined between the semiconductor substrate and the oxide layer.

Abstract: A cap layer for a copper interconnect structure formed in a first dielectric layer is provided. In an embodiment, the cap layer may be formed by an in-situ deposition process in which a process gas comprising germanium, arsenic, tungsten, or gallium is introduced, thereby forming a copper-metal cap layer. In another embodiment, a copper-metal silicide cap is provided. In this embodiment, silane is introduced before, during, or after a process gas is introduced, the process gas comprising germanium, arsenic, tungsten, or gallium. Thereafter, an optional etch stop layer may be formed, and a second dielectric layer may be formed over the etch stop layer or the first dielectric layer.

Abstract: A method of forming a dielectric layer is provided. A first dielectric layer is formed on a substrate having metal layers formed thereon. The first dielectric layer includes overhangs in the spaces between two neighboring metal layers and voids under the overhangs. The first dielectric layer is partially removed to cut off the overhangs and expose the voids and therefore openings are formed. A second dielectric layer is formed on the dielectric layer to fill up the opening.

Abstract: A peripheral processing method includes: by at least one of locally heating the periphery of a workpiece including a silicon-based substrate and selectively supplying reacting activation species to the periphery, allowing oxidation rate on the periphery to be higher than oxidation rate of native oxide film on a surface of the silicon-based substrate, thereby forming a first oxide film along the periphery, the first oxide film being thicker than the native oxide film.

Abstract: There is provided a method for modifying a high-k dielectric thin film provided on the surface of an object using a metal organic compound material. The method includes a preparation process for providing the object with the high-k dielectric thin film formed on the surface thereof, and a modification process for applying UV rays to the highly dielectric thin film in an inert gas atmosphere while maintaining the object at a predetermined temperature to modify the high-k dielectric thin film. According to the above constitution, the carbon component can be eliminated from the high-k dielectric thin film, and the whole material can be thermally shrunk to improve the density, whereby the occurrence of defects can be prevented and the film density can be improved to enhance the specific permittivity and thus to provide a high level of electric properties.

Abstract: The present invention relates to a method for forming self-aligned metal silicide contacts over at least two silicon-containing semiconductor regions that are spaced apart from each other by an exposed dielectric region. Preferably, each of the self-aligned metal silicide contacts so formed comprises at least nickel silicide and platinum silicide with a substantially smooth surface, and the exposed dielectric region is essentially free of metal and metal silicide. More preferably, the method comprises the steps of nickel or nickel alloy deposition, low-temperature annealing, nickel etching, high-temperature annealing, and aqua regia etching.

Abstract: Substrate having a first partial substrate with a carrier layer and a second partial substrate, which is bonded to the first partial substrate. The second partial substrate has an insulator layer, which is applied on the carrier layer and has at least two regions each having a different thickness, thereby forming a stepped surface of the insulator layer, and a semiconductor layer, which is applied to the stepped surface of the insulator layer and is formed at least partially epitaxially, wherein the semiconductor layer has a planar surface which is opposite to the stepped surface of the insulator layer. Transistors are formed on the semiconductor layer.

Abstract: A corrosion resistant component of a plasma chamber includes a liquid crystalline polymer. In a preferred embodiment, the liquid crystalline polymer (LCP) is provided on an aluminum component having an anodized or non-anodized surface. The liquid crystalline polymer can also be provided on an alumina component. The liquid crystalline polymer can be deposited by a method such as plasma spraying. The liquid crystalline polymer may also be provided as a preformed sheet or other shape adapted to cover the exposed surfaces of the reaction chamber. Additionally, the reactor components may be made entirely from liquid crystalline polymer by machining the component from a solid block of liquid crystalline polymer or molding the component from the polymer. The liquid crystalline polymer may contain reinforcing fillers such as glass or mineral fillers.

Abstract: A manufacturing method for semiconductor devices having MOSFET gate insulation films The method includes forming a silicon oxide film, forming a silicon nitride film, nitriding the silicon nitride film, and first and second heat treatments.

Abstract: A method of fabricating a thin film transistor substrate includes forming a gate wiring on an insulating substrate and forming a gate insulating layer on the gate wiring; performing a first hydrogen plasma treatment with respect to the gate insulating layer; forming a first active layer with a first thickness at a first deposition rate on the gate insulating layer; performing a second hydrogen plasma treatment with respect to the first active layer; and forming a second active layer with a second thickness greater than the first thickness at a second deposition rate greater than the first deposition rate, on the first active layer.

Abstract: Deposition and anneal operations are iterated to break a deposition into a number of sequential deposition-anneal operations to reach a desired annealed dielectric layer thickness. In one particular embodiment, a two step anneal is performed including an NH3 or ND3 ambient followed by an N2O or NO ambient. In one embodiment, such a method is employed to form a dielectric layer having a stoichiometry attainable with only a deposition process but with a uniform material quality uncharacteristically high of a deposition process. In particular embodiments, sequential deposition-anneal operations provide an annealed first dielectric layer upon which a second dielectric layer may be left substantially non-annealed.

Abstract: This invention provides a method for manufacturing a semiconductor silicon substrate by use of carbon dioxide in a supercritical state, which method is capable of making the semiconductor silicon substrate highly reliable one. Specifically, this invention provides a method for manufacturing a semiconductor silicon substrate including at least two of: a cleaning step of cleaning a substrate to be treated in a presence of carbon dioxide in a supercritical state; a film forming step of forming at least one of a conducting film, an insulating film and barrier film on the substrate to be treated in the presence of carbon dioxide in the supercritical state; an etching step of etching the substrate to be treated in the presence of carbon dioxide in the supercritical state; and a resist removing step of removing a resist on the substrate to be treated in the presence of carbon dioxide in the supercritical state.

Abstract: An objective of this invention is to solve the problem that in ALD film deposition using a vertical batch processing machine advantageous for improving a throughput, reliability in a dielectric body formed on the bottom of a hole such as a capacitor formed on a semiconductor substrate is reduced as the hole is finer and deeper. A dielectric body is formed by an ALD film deposition process comprising a gas flow sequence where a purging step after supplying a source and a reactant gases is a two-stage purging of vacuum purging and gas purging and the step of supplying a reactant gas is further divided. The process allows a highly reliable dielectric body to be formed in the bottom of a deep hole, contributing to improvement in reliability of a capacitor and a semiconductor device.

Abstract: A metal oxide layer on a substrate is converted at least partly to a metal layer. At least part of the metal layer is covered by an oxidation resistant cover. The covered layer and underlying metal may be removed, for example, using acid.

Abstract: An apparatus for forming a multicomponent thin film, such as a superconducting thin film, on a substrate includes a holder for holding at least one substrate and a deposition/reaction vessel. The deposition/reaction vessel has at least three zones, each zone being separated from adjacent zones by a wall. The zones include at least two deposition zones, where each deposition zone is configured and arranged to deposit a deposition material on the at least one substrate, and at least one reaction zone for reacting the deposition material with a reactant. The apparatus is configured and arranged to rotate the at least one substrate sequentially through the plurality of zones to form a thin film on the substrate. In some embodiments of the apparatus, the deposition/reaction vessel includes a same number of deposition zones and reaction zones which may be alternating deposition and reaction zones.

Abstract: A semiconductor device is formed by forming a gate region, including a gate oxide layer, and impurity diffusion regions on a semiconductor substrate, forming a barrier metal layer on the gate region and the impurity diffusion regions of the semiconductor substrate, forming a passivation layer at an interface between the semiconductor substrate and the gate oxide layer to remove defects of the gate oxide layer, and then performing a nitridation process to remove impurities from the semiconductor substrate.

Abstract: A method for epitaxially forming a silicon-containing material on a substrate surface utilizes a halogen containing gas as both an etching gas as well as a carrier gas through adjustments of the process chamber temperature and pressure. It is beneficial to utilize HCl as the halogen containing gas because converting HCl from a carrier gas to an etching gas can easily be performed by adjusting the chamber pressure.

Abstract: The method for fabricating the semiconductor device includes the steps of: forming an insulating film 20, a conductive film 22 and an insulating film 24 over a semiconductor substrate 10 having a first to a third region; removing an insulating film 24, the conductive film 22 and an insulating film 20 formed in the second region and the third region; forming an insulating film 38 in the second region and the third region; removing the insulating film 24 in the first region and the insulating film 38 in the third region; forming an insulating film 44 in the third region; after a conductive film 52 has been formed, patterning the conductive films 22, 52 in the first region to form a gate electrode 58; and patterning the conductive film 52 to form gate electrodes 62 in the second region and the third region while removing the conductive film 52 over the gate electrode 58.

Abstract: The present invention provides a method for coating a group 4 semiconductor surface composed mainly of a group 4 semiconductor elements and a process for producing group 4 semiconductor particles having a luminescent capability and semiconductor particles and a semiconductor element produced thereby.

Abstract: An antifuse element (102, 152, 252, 302, 352, 402, 602, 652, 702) and method of fabricating the antifuse element, including a substrate material (101) having an active area (106) formed in an upper surface, a gate electrode (104) having at least a portion positioned above the active area (106), and a gate oxide layer (110) disposed between the gate electrode (104) and the active area (106). The gate oxide layer (110) including the fabrication of one of a gate oxide dip (128) or a gate oxide undercut (614). During operation a voltage applied between the gate electrode (104) and the active area (106) creates a current path through the gate oxide layer (110) and a rupture of the gate oxide layer (110) in a rupture region (130). The rupture region (130) defined by the oxide structure and the gate oxide dip (128) or the gate oxide undercut (614).

Abstract: A technology is provided which allows, in a coupling portion obtained by burying a conductive material within a coupling hole bored in an insulating film, the removal of a natural oxide film on the surface of a silicide layer which is present at the bottom portion of the coupling hole. A coupling hole is bored in an interlayer insulating film (first and second insulating films) to expose the surface of a nickel silicide layer at the bottom portion of the coupling hole. Then, reduction gases including a HF gas and a NH3 gas is supplied to the principal surface of a semiconductor wafer to form a product by a reduction reaction, and remove the natural oxide film on the surface of the nickel silicide layer. At this time, the flow rate ratio (HF/NH3 gas flow rate ratio) between the NF gas and the NH3 gas is adjusted to be more than 1 and not more than 5. Preferably, the temperature of the semiconductor wafer is adjusted to be not more than 30° C. Thereafter, a heating process is performed at 400° C.

Abstract: To provide a manufacturing method of a semiconductor device and a substrate processing apparatus capable of easily controlling a nitrogen concentration distribution in a film containing a metal atom and a silicon atom, and manufacturing a high quality semiconductor device. The method comprises a step of forming a film containing the metal atom and the silicon atom on a substrate 30 in a reaction chamber 4, and performing a nitriding process for the film, wherein the film is formed by changing a silicon concentration at least in two stages in the step of forming a film.

Abstract: In a method for fabricating gate dielectrics of metal-oxide-semiconductor transistors, rapid thermal processing (RTP) of a gate dielectric material is performed at a temperature from 1000-1200° C. in a low-concentration oxidizing gas. The method regrows an oxide layer having a thickness of more than 0.05 nm between the gate dielectric layer and the channel region that reduces gate leakage current by 2-5 orders of magnitude and improves hot-electron reliability due to phonon-energy-coupling enhancement (PECE) effect.

Abstract: A method of fabricating a flash memory device is disclosed. The method comprises forming a first insulating layer on a semiconductor substrate; accumulating nitrogen at an interface between the semiconductor substrate and the first insulating layer to form a second insulating layer at the interface; and implanting oxygen into the second insulating layer to convert the second insulating layer to a third insulating layer.

Abstract: A substrate with hermetically sealed vias extending from one side of the substrate to another and a method for fabricating same. The vias may be filled with a conductive material such as, for example, a fritless ink. The conductive path formed by the conductive material aids in sealing one side of the substrate from another. One side of the substrate may include a sensing element and another side of the substrate may include sensing electronics.

Abstract: By selectively providing a buffer layer having an appropriate thickness, height differences occurring during the deposition of an SACVD silicon dioxide may be reduced during the formation of an interlayer dielectric stack of advanced semiconductor devices. The buffer material may be selectively provided after the deposition of contact etch stop layers of both types of internal stress or may be provided after the deposition of one type of dielectric material and may be used during the subsequent patterning of the other type of dielectric stop material as an efficient etch stop layer.

Abstract: Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic properties. By allowing the MOSFET channel to be either at the surface or buried, one can create high-speed digital and/or analog circuits. The planarization before the device epitaxial layers are deposited ensures a flat surface for state-of-the-art lithography.

Abstract: A method for fabricating a semiconductor device includes the steps of forming a nitrogen-containing layer in an exposed portion of a copper interconnect formed in an insulating film provided on a substrate; and forming an interlayer insulating film on the nitrogen-containing layer through plasma CVD performed by using, as a material, an organic silicon compound having a siloxane (Si—O—Si) bond.

Abstract: A semiconductor device fabrication method by which a desired pattern can be formed. After a conductive layer which is a material for a gate electrode is formed, a SiN layer to be used as a hard mask is formed. Then a photoresist layer is formed as a second mask. Then patterning is performed on the photoresist layer. Then patterning is performed on the SiN layer with the photoresist layer as a mask. After the photoresist layer is removed, surface portions of the SiN layer are transmuted and are selectively removed. The conductive layer under the SiN layer is etched with the reduced SiN layer as the hard mask. By doing so, the photoresist layer does not, for example, deform during the process and a minute gate electrode pattern can be formed stably.

Abstract: A method of fabricating an integrated device on a substrate with an exposed surface region is disclosed. One embodiment provides introducing a first component into the exposed surface region of the substrate. A material is provided on the exposed surface region. The material on the exposed surface region is cured and the first component release from the exposed surface region of the substrate.

Abstract: A method of fabricating a semiconductor device including depositing a first silicon oxide film on a silicon substrate, depositing a silicon-containing film on the first silicon oxide film, applying a coating solution for silica film formation over the silicon-containing film, and heat-treating the coating solution, thereby forming a second silicon oxide film.

Abstract: A method of processing semiconductor wafers is provided, comprising loading a batch of semiconductor wafers into a processing chamber; depositing titanium nitride (TiN) onto the wafers in the processing chamber; and depositing silicon onto the wafers in the processing chamber, without removing the wafers from the processing chamber between said depositing steps. In preferred embodiments, the TiN and silicon depositing steps are both conducted at temperatures within about 400-550° C., and at temperatures within 100° C. of one another.

Abstract: The present invention provides atomic layer deposition systems and methods that include metal compounds with at least one ?-diketiminate ligand. Such systems and methods can be useful for depositing metal-containing layers on substrates.