Multiple Layers Patents (Class 438/761)
  • Patent number: 11307113
    Abstract: A method is used for determining a status of an encapsulation and/or a passivation layer of the encapsulation. The encapsulation forms a multi-layer system from multiple passivation layers arranged on top of one another and electrically contacted intermediate layers arranged between the passivation layers. The multi-layer system protects an implant surrounded by the encapsulation. In the method, an electrical measurement is carried out between a reference potential and at least one electrically contacted intermediate layer, and at least one current flowing between the reference potential and the at least one electrically contacted intermediate layer is detected. The at least one detected current is compared with at least one pre-determined threshold value. If the detected current falls below or exceeds the at least one threshold value, this indicates a functional state of a passivation layer adjacent to the at least one electrically contacted intermediate layer.
    Type: Grant
    Filed: August 16, 2018
    Date of Patent: April 19, 2022
    Assignees: AESCULAP AG, EBERHARD KARLS UNIVERSITÄT TÜBINGEN
    Inventors: Boris Hofmann, Markus Westerhausen
  • Patent number: 11276668
    Abstract: The technology relates to an integrated circuit (IC) package. The IC package may include a packaging substrate, an IC die, and an integrated voltage regulator die. The IC die may include a metal layer and a silicon layer. The metal layer may be connected to the packaging substrate. The integrated voltage regulator die may be positioned adjacent to the silicon layer and connected to the packaging substrate via one or more through mold vias or through dielectric vias. The IC die may be an application specific integrated circuit (ASIC) die.
    Type: Grant
    Filed: February 12, 2020
    Date of Patent: March 15, 2022
    Assignee: Google LLC
    Inventors: Nam Hoon Kim, Woon Seong Kwon, Houle Gan, Yujeong Shim, Mikhail Popovich, Teckgyu Kang
  • Patent number: 11251038
    Abstract: A film where a first layer and a second layer are laminated is formed on a substrate by performing: forming the first layer by performing a first cycle a predetermined number of times, the first cycle including non-simultaneously performing: supplying a source to the substrate, and supplying a reactant to the substrate, under a first temperature at which neither the source nor the reactant is thermally decomposed when the source and the reactant are present alone, respectively; and forming the second layer by performing a second cycle a predetermined number of times, the second cycle including non-simultaneously performing: supplying the source to the substrate, and supplying the reactant to the substrate, under a second temperature at which neither the source nor the reactant is thermally decomposed when the source and the reactant are present alone, respectively, the second temperature being different from the first temperature.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: February 15, 2022
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventors: Tsukasa Kamakura, Takaaki Noda, Yoshiro Hirose
  • Patent number: 11152464
    Abstract: Embodiments of the present invention are directed to methods and resulting structures for nanosheet devices having self-aligned isolations. In a non-limiting embodiment of the invention, a first gate stack is formed over channel regions of a first nanosheet stack. A second gate stack is formed over channel regions of a second nanosheet stack adjacent to the first nanosheet stack. An isolation pillar is positioned between the first gate stack and the second gate stack. The isolation pillar includes a top portion having a first width and a bottom portion having a second width less than the first width.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: October 19, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Balasubramanian S. Pranatharthi Haran, Ruilong Xie, Veeraraghavan S. Basker, Robert Robison
  • Patent number: 11133189
    Abstract: The present disclosure relates to methods and apparatuses related to the deposition of a protective layer selective to an interlayer dielectric layer so that the protective layer is formed onto a top portion associated with the interlayer dielectric layer. In some embodiments, a method comprises: forming an interlayer dielectric layer on a substrate; covering a trench region with a metal liner, wherein the trench region is situated above the substrate and formed within the interlayer dielectric layer; and depositing a protective layer selective to the interlayer dielectric layer so that the protective layer is formed onto a top portion associated with the interlayer dielectric layer. In various embodiments, the depositing the protective layer comprises: repeatedly depositing the protective layer via a multi-deposition sequence; or depositing a self-assembled monolayer onto the top portion.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: September 28, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kisup Chung, Ekmini Anuja De Silva, Andrew Greene, Siva Kanakasabapathy, Indira Seshadri
  • Patent number: 11118264
    Abstract: A plasma processing method is provided. In the plasma processing method, a plurality of types of mixed gases is supplied to a plurality of areas on a film deposited on a surface of a substrate. The plurality of types of mixed gases contains a plurality types of noble gases. The plurality of types of mixed gases has different mix proportions of the plurality types of noble gases from each other. The plurality of types of mixed gases is converted to plasma. A plasma process is performed by using the mixed gases converted to the plasma on the film.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: September 14, 2021
    Assignee: Tokyo Electron Limited
    Inventor: Shigehiro Miura
  • Patent number: 11069568
    Abstract: In one embodiment, a method of forming a barrier layer is provided. The method includes positioning a substrate in a processing chamber, forming a barrier layer over the substrate and in contact with the underlayer, and annealing the substrate. The substrate comprises at least one underlayer having cobalt, tungsten, or copper. The barrier layer has a thickness of less than 70 angstroms.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: July 20, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Susmit Singha Roy, Yihong Chen, Abhijit Basu Mallick, Srinivas Gandikota
  • Patent number: 11004676
    Abstract: A method for improving a film formation rate and forming a film having a high dry etching resistance is disclosed. The method includes forming a metal nitride layer containing the metal element and the nitrogen element by performing a predetermined number of times in a time division manner supplying a halogen-based source gas containing the metal element to the substrate and supplying a reaction gas containing the nitrogen element and reacting with the metal element to the substrate; and forming a metal carbonitride layer containing the metal element, the carbon element, and the nitrogen element by performing a predetermined number of times in a time division manner supplying an organic-based source gas containing the metal element and the carbon element to the substrate and supplying the reaction gas to the substrate.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: May 11, 2021
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventors: Arito Ogawa, Yukinao Kaga, Kazuhiro Harada, Motomu Degai
  • Patent number: 10957697
    Abstract: A manufacture includes a substrate comprising a first portion and a second portion. The manufacture further includes a first polysilicon structure over the first portion of the substrate. The manufacture further includes a second polysilicon structure over the second portion of the substrate. The manufacture further includes two spacers on opposite sidewalls of the second polysilicon structure, wherein each spacer of the two spacers has a concave corner region between an upper portion and a lower portion. The manufacture further includes a protective layer covering the first portion of the substrate and the first polysilicon structure, the protective layer exposing the second portion of the substrate, the second polysilicon structure, and partially exposing the two spacers.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: March 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Shao Cheng, Shin-Yeu Tsai, Chui-Ya Peng, Kung-Wei Lee
  • Patent number: 10867850
    Abstract: A method for forming a semiconductor structure is provided. A substrate including a metal portion and a low-k dielectric portion formed thereon is provided. The metal portion adjoins the low-k dielectric portion. A SAM solution is prepared. The SAM solution includes at least one blocking compound and a multi-solvent system. The multi-solvent system includes an alcohol and an ester. The SAM solution is applied over surfaces of the metal portion and the low-k dielectric portion. The substrate is heated to remove the multi-solvent system of the SAM solution to form a blocking layer on one of the metal portion and the low-k dielectric portion. A material layer is selectively deposited on the other one of the metal portion and the low-k dielectric portion using the blocking layer as a stencil. The blocking layer is removed from the substrate.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Chin Lee, Shao-Kuan Lee, Hsin-Yen Huang, Hai-Ching Chen, Shau-Lin Shue
  • Patent number: 10622266
    Abstract: The disclosure is directed to methods of identifying a space within an integrated circuit structure as a mandrel space or a non-mandrel space. One method may include: identifying a space between freestanding spacers as being one of: a former mandrel space created by removal of a mandrel from between the freestanding spacers or a non-mandrel space between adjacent mandrels prior to removal of the mandrel, based on a line width roughness of the space, wherein the line width roughness represents a deviation of a width of the space from a centerline axis along a length of the space.
    Type: Grant
    Filed: April 4, 2017
    Date of Patent: April 14, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Erik A. Verduijn, Genevieve Beique, Nicholas V. LiCausi, Lei Sun, Francis G. Goodwin
  • Patent number: 10566496
    Abstract: An optoelectronic semiconductor chip (10) is specified, comprising a p-type semiconductor region (4), an n-type semiconductor region (6), and an active layer arranged between the p-type semiconductor region (4) and the n-type semiconductor region (6), said active layer being designed as a multiple quantum well structure (5), wherein the multiple quantum well structure (5) comprises quantum well layers (53) and barrier layers (51), wherein the barrier layers (51) are doped, and wherein undoped intermediate layers (52, 54) are arranged between the quantum well layers (53) and the barrier layers (51). Furthermore, a method for producing the optoelectronic semiconductor chip (10) is specified.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: February 18, 2020
    Assignee: OSRAM OPTO SEMICONDUCTORS GMBH
    Inventor: Andreas Rudolph
  • Patent number: 10490416
    Abstract: Described herein are structures and methods for preparing photobuckets for lithography, e.g. photolithography or electron-beam lithography. One method includes arranging photobuckets on a material to be etched using lithography and providing a layer of a first material at least on inner side walls of the photobuckets, followed by filling the photobuckets with a second material. The second material is more lithosensitive than the first material and the first material could be not lithosensitive at all. Layering each photobucket from the inner side wall(s) of the photobucket towards the center of the photobucket with materials that are increasingly more lithosensitive results in an improved control of lithographic patterning by reducing or eliminating edge placement errors of accidentally exposing photobuckets that should not have been exposed.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: November 26, 2019
    Assignee: Intel Corporation
    Inventors: Robert L. Bristol, James M. Blackwell
  • Patent number: 10418243
    Abstract: Implementations of the present disclosure generally relate to the fabrication of integrated circuits. More particularly, the implementations described herein provide techniques for deposition of boron-carbon films on a substrate. In one implementation, a method of processing a substrate is provided. The method comprises flowing a hydrocarbon-containing gas mixture into a processing volume of a processing chamber having a substrate positioned therein, wherein the substrate is heated to a substrate temperature from about 400 degrees Celsius to about 700 degrees Celsius, flowing a boron-containing gas mixture into the processing volume and generating an RF plasma in the processing volume to deposit a boron-carbon film on the heated substrate, wherein the boron-carbon film has an elastic modulus of from about 200 to about 400 GPa and a stress from about ?100 MPa to about 100 MPa.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: September 17, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Prashant Kumar Kulshreshtha, Ziqing Duan, Karthik Thimmavajjula Narasimha, Kwangduk Douglas Lee, Bok Hoen Kim
  • Patent number: 10374144
    Abstract: Methods of etching metal by depositing a material reactive with a metal to be etched and a halogen to form a volatile species and exposing the substrate to a halogen-containing gas and activation gas to etch the substrate are provided. Deposited materials may include silicon, germanium, titanium, carbon, tin, and combinations thereof. Methods are suitable for fabricating MRAM structures and may involve integrating ALD and ALE processes without breaking vacuum.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: August 6, 2019
    Assignee: Lam Research Corporation
    Inventors: Samantha Tan, Taeseung Kim, Wenbing Yang, Jeffrey Marks, Thorsten Lill
  • Patent number: 10192743
    Abstract: A method of preparing a self-aligned block (SAB) structure is described. The method includes providing a substrate having raised features defined by a first material containing silicon nitride and a second material containing silicon oxide formed on side walls of the first material, and a third material containing an organic material covering some of the raised features and exposing some raised features according to a block pattern formed in the third material. The method further includes forming a first chemical mixture by plasma-excitation of a first process gas, and exposing the first material on the substrate to the first chemical mixture. Thereafter, the method includes forming a second chemical mixture by plasma-excitation of a second process gas, and exposing the first material on the substrate to the second plasma-excited process gas to selectively etch the first material relative to the second and third material.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: January 29, 2019
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Sonam D. Sherpa, Alok Ranjan
  • Patent number: 10090149
    Abstract: A method of manufacturing a semiconductor device includes: forming a base film containing a first element and carbon on a substrate by supplying a film forming gas to the substrate; and oxidizing the base film by supplying an oxidizing gas to the substrate to modify the base film into a C-free oxide film containing the first element.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: October 2, 2018
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Yoshitomo Hashimoto, Yoshiro Hirose
  • Patent number: 10073342
    Abstract: A substrate having a target material layer is provided. A first hard mask layer, a second hard mask layer, and a photoresist layer are formed on the target material layer. The photoresist layer is transferred into first patterns on the second hard mask layer. Regions of the second hard mask layer not protected by the first patterns are etched away, thereby forming second patterns. The first patterns are trimmed to form trimmed features. A conformal spacer material layer is deposited on the trimmed features, the second patterns, and the first hard mask. The spacer material layer is etched to form first spacers on sidewalls of the trimmed features, and second spacers on sidewalls of the second patterns. The trimmed features are removed. Regions of the second patterns not protected by the first spacers are removed, thereby forming patterns with a reduced, fine pitch.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: September 11, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Kuo-Yao Chou
  • Patent number: 10014437
    Abstract: An optical semiconductor device comprises, on a substrate, a fin of diamond-cubic semiconductor material and, at the base of the fin, a slab of that semiconductor material, in a diamond-hexagonal structure, that extends over the full width of the fin, the slab being configured as an optically active material. This semiconductor material can contain silicon. A method for manufacturing the optical semiconductor device comprises annealing the sidewalls of the fin, thereby inducing a stress gradient along the width of the fin.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: July 3, 2018
    Assignees: IMEC VZW, Katholieke Universiteit Leuven, KU Leuven R&D
    Inventors: Hugo Bender, Yang Qiu
  • Patent number: 10002317
    Abstract: A label adapted to be attached to an item and a system for validating a label are provided. The label contains an identifying portion of a circuit path extending between at least a pair of contact points in which the identifying portion of the circuit path includes a segment containing graphene. The system can include this label and a validating device. The validating device includes a testing portion of the circuit path adapted to contact the at least the pair of contact points of the identifying portion of the circuit path in the label to thereby complete the circuit path. The testing portion of the validation device is configured to internally process and validate the label in the validating device.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: June 19, 2018
    Assignee: Brady Worldwide, Inc.
    Inventor: J. Michael Nauman
  • Patent number: 9957165
    Abstract: Provided are methods of depositing silicon-containing films utilizing certain precursors at temperatures of 400° C. or higher. Certain methods comprise exposing a substrate surface to a silicon precursor and another precursor to achieve various films. Examples of silicon-containing films which can be deposited include SiN, SiC, SiO2, SiCN, etc.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: May 1, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventor: Mark Saly
  • Patent number: 9745656
    Abstract: A method of manufacturing a semiconductor device, includes: alternately performing (i) a first step of alternately supplying a first raw material containing a first metal element and a halogen element and a second raw material containing a second metal element and carbon to a substrate by a first predetermined number of times, and (ii) a second step of supplying a nitridation raw material to the substrate, by a second predetermined number of times, wherein alternating the first and second steps forms a metal carbonitride film containing the first metal element having a predetermined thickness on the substrate.
    Type: Grant
    Filed: June 23, 2016
    Date of Patent: August 29, 2017
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Arito Ogawa, Tsuyoshi Takeda
  • Patent number: 9646846
    Abstract: A method for producing a multilevel microelectronic structure includes formation of a first layer, production of at least one second layer at least partially covering the first layer, and production of at least one microelectronic pattern on or in the second layer. The second layer is formed so as to generate a mechanical stress in it, the first layer forms, for the second layer, a support preventing relaxation of the stress. After the production of at least one microelectronic pattern, the method includes at least elimination of at least part of the first layer, thus making it possible to relax at least part of the mechanical stress on the second layer so that at least a portion of the second layer covering the eliminated part of the first layer moves, and fixing the moved portion of the second layer to a structure part that has remained fixed.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: May 9, 2017
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Philippe Coronel, Claire Fenouillet-Beranger
  • Patent number: 9570394
    Abstract: Embodiments of the present disclosure may provide methods of forming an IC structure with a pair of metal fins. An IC structure with a pair of metal fins can include two unitary metal fins positioned on a substrate and each including an elongated wire positioned on the substrate and a via positioned directly on a portion of the elongated wire, the elongated wire and the via of each unitary metal fin defining an inverted T-shape, wherein each unitary metal fin includes the elongated wire with a pair of opposing sidewalls substantially coplanar with a pair of opposing sidewalls of the via, and wherein the each unitary metal fin includes a single crystallographic orientation. An insulating layer can be positioned directly laterally between the two unitary metal fins.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: February 14, 2017
    Assignee: Globalfoundries Inc.
    Inventors: Xunyuan Zhang, Nicholas V. LiCausi, Errol Todd Ryan
  • Patent number: 9425038
    Abstract: A method for forming a silicon oxycarbonitride film includes supplying a gas containing a silicon precursor having an oxygen-containing group onto a process surface of a workpiece, supplying a gas containing a carbon precursor onto the process surface, and supplying a nitriding gas onto the process surface subjected to the supplying a gas containing a silicon precursor and the supplying a gas containing a carbon precursor. The silicon oxycarbonitride film is formed on the process surface by the supplying the gas containing the silicon precursor, the supplying gas containing the carbon precursor and the supplying a nitriding gas without performing an oxidation process.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: August 23, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Akira Shimizu
  • Patent number: 9425071
    Abstract: A film forming method for obtaining a thin film by laminating molecular layers of oxide on a surface of a substrate in a vacuum atmosphere includes performing a cycle a plurality of times. The cycle includes: supplying a source gas containing a source to the substrate in a vacuum vessel to adsorb the source onto the substrate; forming an ozone atmosphere containing ozone having a concentration not less than that where a chain decomposition reaction is caused in the vacuum vessel; and forcibly decomposing the ozone by supplying energy to the ozone atmosphere to generate active species of oxygen, and oxidizing the source adsorbed onto the surface of the substrate by the active species to obtain the oxide.
    Type: Grant
    Filed: April 28, 2015
    Date of Patent: August 23, 2016
    Assignees: TOKYO ELECTRON LIMITED, IWATANI CORPORATION
    Inventors: Kazuo Yabe, Akira Shimizu, Koichi Izumi, Masahiro Furutani
  • Patent number: 9384961
    Abstract: A method for manufacturing a semiconductor device includes forming a thin film containing a specific element and having a prescribed composition on a substrate by alternately performing the following steps prescribed number of times: forming a first layer containing the specific element, nitrogen, and carbon on the substrate by alternately performing prescribed number of times: supplying a first source gas containing the specific element and a halogen-group to the substrate, and supplying a second source gas containing the specific element and an amino-group to the substrate, and forming a second layer by modifying the first layer by supplying a reactive gas different from each of the source gases, to the substrate.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: July 5, 2016
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Yoshiro Hirose, Ryuji Yamamoto
  • Patent number: 9185805
    Abstract: A thin circuit substrate and a circuit module are arranged such that the circuit module includes an IC mounted on a circuit substrate, the IC includes an IC body and an solder bump located on a mounting surface of the IC body, and the circuit substrate includes a substrate including a recess formed by recessing a portion of a mounting surface of the substrate on which the IC is to be mounted, and a terminal protruding from the mounting surface of the substrate. The terminal is to be electrically connected to the solder bump.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: November 10, 2015
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Yutaka Fukuda
  • Patent number: 9165761
    Abstract: There is provided a method for manufacturing a semiconductor device, including forming a thin film containing a specific element and having a prescribed composition on a substrate by alternately performing the following steps prescribed number of times: forming a first layer containing the specific element, nitrogen, and carbon on the substrate by alternately performing prescribed number of times: supplying a first source gas containing the specific element and a halogen-group to the substrate, and supplying a second source gas containing the specific element and an amino-group to the substrate, and forming a second layer by modifying the first layer by supplying a reactive gas different from each of the source gases, to the substrate.
    Type: Grant
    Filed: August 1, 2012
    Date of Patent: October 20, 2015
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Yoshiro Hirose, Ryuji Yamamoto
  • Patent number: 9140978
    Abstract: The embodiment provides a semiconductor MP wafer process including processing a plurality of MP wafers in a lot or batch with a first process step. The plurality of the MP wafers is split into an MP wafer group-1 and an MP wafer group-2. At least one of the MP wafers of the MP wafer group-1 is processed with a second process step-1 and at least one of the MP wafers of the MP wafer group-2 is processed with a second process step-2 to form different device components on the MP wafers of the MP wafer group-1 and group-2, respectively. At least one of the MP wafers of the MP wafer group-1 is processed with a third process step-3 and at least one of the MP wafers of the MP wafer group-2 is processed with a third process step-4 to form a substantially same device component on the MP wafers.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: September 22, 2015
    Inventor: Weng-Dah Ken
  • Patent number: 9130014
    Abstract: A method for fabricating shallow trench isolation structure is disclosed. The method includes the steps of: (a) providing a substrate; (b) forming a trench in the substrate; (c) forming a silicon layer in the trench; and (d) performing an oxidation process to partially transform a surface of the silicon layer into an oxide layer.
    Type: Grant
    Filed: November 21, 2013
    Date of Patent: September 8, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Keng-Jen Lin, Yu-Ren Wang, Chien-Liang Lin, Tsuo-Wen Lu, Wei-Jen Chen, Chih-Chung Chen
  • Patent number: 9040433
    Abstract: One or more techniques or systems for forming a line end space structure are provided herein. In some embodiments, a first patterned second hard mask (HM) region is formed above a first HM region. Additionally, at least some of the first patterned second HM region is removed. In some embodiments, a first sacrificial HM region and a second sacrificial HM region are formed above at least one of the first patterned second HM region or the first HM region. Photo resist (PR) is patterned above the second sacrificial HM region, and a spacer region is deposited above the patterned PR and second sacrificial HM region. In some embodiments, at least some of at least one of the spacer region, the PR, or the respective sacrificial HMs is removed. In this way, a line end space structure associated with an end-to-end space is formed.
    Type: Grant
    Filed: September 8, 2014
    Date of Patent: May 26, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chia-Ying Lee, Jyu-Horng Shieh, Ming-Feng Shieh, Shih-Ming Chang, Chih-Ming Lai, Ken-Hsien Hsieh, Ru-Gun Liu
  • Patent number: 9040410
    Abstract: A fabrication method for semiconductor devices is provided. The method comprises: depositing a dielectric layer that includes a plurality of functional layers, and forming a contact hole, or through hole, and a metal layer. The forming of the contact hole, or through hole, and the metal layer comprises performing photolithography on regions corresponding to a marking label for the photolithography of the dielectric layer and the metal layer. On at least one of the functional layers, the performing photolithography on regions corresponding to a marking label for the photolithography comprises limiting the photolithography to the metal layer thereof. A semiconductor device thus fabricated is also provided. The method and device do not affect the reading of the marking label, and also can avoid the problem of defocusing in the vicinity of the marking label.
    Type: Grant
    Filed: May 10, 2013
    Date of Patent: May 26, 2015
    Assignee: CSMC Technologies Fab2 Co., Ltd.
    Inventor: Xin Yang
  • Publication number: 20150140832
    Abstract: Sources, devices, and techniques for deposition of organic layers, such as for use in an OLED, are provided. A vaporizer may vaporize a material between cooled side walls and toward a mask having an adjustable mask opening. The mask opening may be adjusted to control the pattern of deposition of the material on a substrate, such as to correct for material buildup that occurs during deposition. Material may be collected from the cooled side walls for reuse.
    Type: Application
    Filed: November 15, 2013
    Publication date: May 21, 2015
    Applicant: Universal Display Corporation
    Inventors: William E. Quinn, Siddharth Harikrishna Mohan, Gregory McGraw
  • Patent number: 9034740
    Abstract: The deposition rate of a porous insulation film is increased, and the film strength of the porous insulation film is improved. Two or more organic siloxane raw materials each having a cyclic SiO structure as a main skeleton thereof, and having mutually different structures, are vaporized, and transported with a carrier gas to a reactor (chamber), and an oxidant gas including an oxygen atom is added thereto. Thus, a porous insulation film is formed by a plasma CVD (Chemical Vapor Deposition) method or a plasma polymerization method in the reactor (chamber). In the step, the ratio of the flow rate of the added oxidant gas to the flow rate of the carrier gas is more than 0 and 0.08 or less.
    Type: Grant
    Filed: May 6, 2013
    Date of Patent: May 19, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hironori Yamamoto, Fuminori Ito, Yoshihiro Hayashi
  • Patent number: 9035277
    Abstract: The present disclosure provides a method for fabricating an integrated circuit (IC) device. The method includes providing a precursor including a substrate having first and second metal-oxide-semiconductor (MOS) regions. The first and second MOS regions include first and second gate regions, semiconductor layer stacks, source/drain regions and isolation regions. The method includes exposing and oxidizing the first semiconductor layer stack to form a first outer oxide layer and a first inner nanowire, and removing the first outer oxide layer to expose the first inner nanowire in the first gate region. A first high-k/metal gate (HK/MG) stack wraps around the first inner nanowire. The method includes exposing and oxidizing the second semiconductor layer stack to form second outer oxide layer and inner nanowire, and removing the second outer oxide layer to expose the second inner nanowire in the second gate region. A second HK/MG stack wraps around the second inner nanowire.
    Type: Grant
    Filed: August 1, 2013
    Date of Patent: May 19, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Ting-Hung Hsu
  • Publication number: 20150132949
    Abstract: A chip package and a fabrication method thereof are provided. The chip package includes a semiconductor substrate, having a first surface and an opposing second surface. A spacer is disposed under the second surface of the semiconductor substrate and a cover plate is disposed under the spacer. A recessed portion is formed adjacent to a sidewall of the semiconductor substrate, extending from the first surface of the semiconductor substrate to at least the spacer. Then, a protection layer is disposed over the first surface of the semiconductor substrate and in the recessed portion.
    Type: Application
    Filed: January 8, 2015
    Publication date: May 14, 2015
    Inventors: Chia-Sheng LIN, Po-Han LEE
  • Publication number: 20150126042
    Abstract: Methods for depositing nanolaminate protective layers over a core layer to enable deposition of high quality conformal films over the core layer for use in advanced multiple patterning schemes are provided. In certain embodiments, the methods involve depositing a thin silicon oxide or titanium oxide film using plasma-based atomic layer deposition techniques with a low high frequency radio frequency (HFRF) plasma power, followed by depositing a conformal titanium oxide film or spacer with a high HFRF plasma power.
    Type: Application
    Filed: February 28, 2014
    Publication date: May 7, 2015
    Inventors: Frank L. Pasquale, Shankar Swaminathan, Adrien LaVoie, Nader Shamma, Girish Dixit
  • Publication number: 20150118850
    Abstract: A method embodiment for patterning a semiconductor device includes forming a plurality of mandrels over a substrate, and forming a multilayer spacer layer over the plurality of mandrels. The multilayer spacer layer is formed by conformably depositing a spacer layer over the plurality of mandrels and treating the spacer layer with plasma. The plurality of mandrels is exposed by etching a top portion of the multilayer spacer layer, thereby forming a multilayer spacer.
    Type: Application
    Filed: October 25, 2013
    Publication date: April 30, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chao-Hsien Peng, Hsiang-Huan Lee, Shau-Lin Shue
  • Patent number: 9012328
    Abstract: Embodiments of the present invention generally relate to methods of forming epitaxial layers and devices having epitaxial layers. The methods generally include forming a first epitaxial layer including phosphorus and carbon on a substrate, and then forming a second epitaxial layer including phosphorus and carbon on the first epitaxial layer. The second epitaxial layer has a lower phosphorus concentration than the first epitaxial layer, which allows for selective etching of the second epitaxial layer and undesired amorphous silicon or polysilicon deposited during the depositions. The substrate is then exposed to an etchant to remove the second epitaxial layer and undesired amorphous silicon or polysilicon. The carbon present in the first and second epitaxial layers reduces phosphorus diffusion, which allows for higher phosphorus doping concentrations. The increased phosphorus concentrations reduce the resistivity of the final device.
    Type: Grant
    Filed: July 28, 2011
    Date of Patent: April 21, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Zhiyuan Ye, Xuebin Li, Saurabh Chopra, Yihwan Kim
  • Patent number: 9012261
    Abstract: Methods for HPC techniques are applied to the processing of site-isolated regions (SIR) on a substrate to form at least a portion of a TFT device used in display applications. The processing may be applied to at least one of gate electrode deposition, gate electrode patterning, gate dielectric deposition, gate dielectric patterning, metal-based semiconductor material (e.g. IGZO) deposition, metal-based semiconductor material (e.g. IGZO) patterning, etch stop deposition, etch stop patterning, source/drain deposition, source/drain patterning, passivation deposition, or passivation patterning. The SIRs may be defined during the deposition process with uniform deposition within each SIR or the SIRs may be defined subsequent to the deposition of layers wherein the layers are deposited with a gradient in one or more properties across the substrate.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: April 21, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Jeroen Van Duren, Sang Lee, Minh Huu Le, Sandeep Nijhawan, Teresa B. Sapirman
  • Publication number: 20150099372
    Abstract: Disclosed herein are methods of depositing layers of material on multiple semiconductor substrates at multiple processing stations within one or more reaction chambers. The methods may include dosing a first substrate with film precursor at a first processing station and dosing a second substrate with film precursor at a second processing station with precursor flowing from a common source, wherein the timing of said dosing is staggered such that the first substrate is dosed during a first dosing phase during which the second substrate is not substantially dosed, and the second substrate is dosed during a second dosing phase during which the first substrate is not substantially dosed. Also disclosed herein are apparatuses having a plurality of processing stations contained within one or more reaction chambers and a controller with machine-readable instructions for staggering the dosing of first and second substrates at first and second processing stations.
    Type: Application
    Filed: December 15, 2014
    Publication date: April 9, 2015
    Inventors: Ramesh Chandrasekharan, Adrien LaVoie, Damien Slevin, Karl Leeser
  • Patent number: 8999787
    Abstract: A semiconductor device includes a plurality of conductive layers and a plurality of insulating layers formed alternately with each other, at least one channel layer passing through the plurality of conductive layers and the plurality of insulating layers, and at least one first charge blocking layer surrounding the at least one channel layer, wherein a plurality of first regions, interposed between the at least one channel layer and the plurality of conductive layers, and a plurality of second regions, interposed between the at least one channel layer and the plurality of insulating layers, are alternately defined on the at least one first charge blocking layer, and each of the plurality of first regions has a greater thickness than each of the plurality of second regions.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: April 7, 2015
    Assignee: SK Hynix Inc.
    Inventors: Ki Hong Lee, Seung Ho Pyi, Seok Min Jeon
  • Patent number: 8999858
    Abstract: The substrate processing apparatus includes a reaction chamber configured to accommodate a substrate; a first gas supply unit configured to supply a first process gas containing a silicon element to the substrate; a second gas supply unit configured to supply a second process gas containing a silicon element and a chlorine element to the substrate; an exhaust unit configured to exhaust the first process gas and the second process gas; a cleaning gas bypass supply unit configured to supply a cleaning gas to the exhaust unit; a cleaning monitoring unit installed in the exhaust unit; a gas flow rate control unit configured to adjust an amount of the cleaning gas supplied; and a main control unit configured to control the gas flow rate control unit in response to a signal received from the cleaning gas monitoring unit.
    Type: Grant
    Filed: December 26, 2012
    Date of Patent: April 7, 2015
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Yasunobu Koshi, Kenichi Suzaki, Akihito Yoshino
  • Publication number: 20150093911
    Abstract: A method of manufacturing a semiconductor device includes: (a) forming a first film containing a metal element on a substrate by performing a cycle a predetermined number of times, the cycle including: (a-1) supplying a first precursor gas being a fluorine-free inorganic gas containing the metal element to the substrate; and (a-2) supplying a first reactant gas having reducibility to the substrate; (b) forming a second film containing the metal element on the first film by performing a cycle a predetermined number of times, the cycle including: (b-1) supplying a second precursor gas containing the metal element and fluorine to the substrate; and (b-2) supplying a second reactant gas having reducibility to the substrate; and (c) forming a film containing the metal element and obtained by the first film and the second film being laminated on the substrate by performing the (a) and (b).
    Type: Application
    Filed: September 29, 2014
    Publication date: April 2, 2015
    Applicant: Hitachi Kokusai Electric Inc.
    Inventors: Kimihiko NAKATANI, Kazuhiro HARADA, Hiroshi ASHIHARA, Ryuji YAMAMOTO
  • Publication number: 20150093910
    Abstract: Methods for converting planar designs to FinFET designs in the design and fabrication of integrated circuits are provided. In one embodiment, a method for converting a planar integrated circuit design to a non-planar integrated circuit design includes identifying a rectangular silicon active area in the planar integrated circuit design, superimposing a FinFET design grid comprising a plurality of equidistantly-spaced parallel grid lines over the rectangular silicon active area such that two sides of the rectangular silicon active area are parallel to the grid lines, and generating a rectangular active silicon marker area encompassing the silicon active area. Furthermore, the method includes generating fin mandrels longitudinally along every other grid line of the plurality of grid lines and within the active silicon marker area and the silicon active area, and removing the fin mandrels from areas of the design grid outside of the active silicon marker area.
    Type: Application
    Filed: September 27, 2013
    Publication date: April 2, 2015
    Applicant: GLOBALFOUNDERIES Singapore Pte. Ltd.
    Inventors: Soon Yoeng Tan, Srinidhi Ramamoorthy, Angeline Ho Chye Ee, Andreas Knorr, Frank Scott Johnson
  • Patent number: 8993454
    Abstract: Embodiments of the present invention generally relate to the fabrication of integrated circuits and particularly to the deposition of a boron containing amorphous carbon layer on a semiconductor substrate. In one embodiment, a boron-containing amorphous carbon film is disclosed. The boron-containing amorphous carbon film comprises from about 10 to 60 atomic percentage of boron, from about 20 to about 50 atomic percentage of carbon, and from about 10 to about 30 atomic percentage of hydrogen.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: March 31, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Martin Jay Seamons, Sudha Rathi, Kwangduk Douglas Lee, Deenesh Padhi, Bok Hoen Kim, Chiu Chan
  • Publication number: 20150087158
    Abstract: A method for depositing a film is provided. In the method, an object to be processed is accommodated in a process chamber, and an insulating film made of a polymer thin film is deposited on a surface of the object to be processed by supplying a first source gas composed of an acid anhydride and a second source gas composed of a diamine into the process chamber that is evacuated. Next, the insulating film is modified so as to have a barrier function by stopping the supply of the second source gas into the process chamber and continuously supplying the first source gas into the process chamber.
    Type: Application
    Filed: April 22, 2013
    Publication date: March 26, 2015
    Inventors: Kippei Sugita, Hiroyuki Hashimoto, Muneo Harada
  • Patent number: 8987147
    Abstract: A method of depositing a film on substrates using an apparatus including a turntable mounting substrates, first and second process areas above the upper surface of the turntable provided with gas supplying portions, a separation gas supplying portion between the first and second process areas, and a separation area including depositing a first oxide film by rotating the turntable first turns while supplying a first reaction gas, the oxidation gas from the second gas supplying portion, and the separation gas; rotating at least one turn while supplying the separation gas from the first gas supplying portion and the separation gas supplying portion, and the oxidation gas from the second gas supplying portion; and rotating at least second turns to deposit a second oxide film while supplying a second reaction gas from the first gas supplying portion, the oxidation gas from the second gas supplying portion, and the separation gas.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: March 24, 2015
    Assignee: Tokyo Electron Limited
    Inventors: Hiroaki Ikegawa, Masahiko Kaminishi, Kosuke Takahashi, Masato Koakutsu, Jun Ogawa
  • Publication number: 20150076705
    Abstract: Interlayer fabrication methods and interlayer structure are provided having reduced dielectric constants. The methods include, for example: providing a first uncured insulating layer with an evaporable material; and disposing a second uncured insulating layer having porogens above the first uncured insulating layer. The interlayer structure includes both the first and second insulating layers, and the methods further include curing the interlayer structure, leaving air gaps in the first insulating layer, and pores in the second insulating layer, where the air gaps are larger than the pores, and where the air gaps and pores reduce the dielectric constant of the interlayer structure.
    Type: Application
    Filed: September 16, 2013
    Publication date: March 19, 2015
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Sunil Kumar SINGH, Matthew HERRICK, Teck Jung TANG, Dewei XU