Reaction With Conductive Region Patents (Class 438/768)
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Publication number: 20020182823Abstract: A wafer stage having a built-in heater therein mounts a heat conductive disk which mounts thereon an object wafer having an AlAs layer therein. The heat conductive disk has a thermal conductivity equal to or higher than 100 watts/K/meter. The Al-oxidized area in the AlAs layer has excellent in-plane uniformity for the width thereof due to desirable heat distribution of the wafer caused by the heat conductive disk.Type: ApplicationFiled: December 3, 2001Publication date: December 5, 2002Inventors: Noriyuki Yokouchi, Natsumi Ueda, Yasumasa Sasaki, Fumio Koyama, Kenichi Iga
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Publication number: 20020168847Abstract: A method of providing a stable interface between a metallic layer and a dielectric layer in a semiconductor device is provided. The method includes generating a remote nitrogen containing plasma and flowing activated nitrogen species, from the remote site to the location of the metallic layer. The activated nitrogen species are flowed over at least the surface of the metallic layer, where they react with the metallic surface to form a metal nitride. The treated layer can be used to provide a stable bottom electrode in a capacitor stack formation.Type: ApplicationFiled: May 9, 2001Publication date: November 14, 2002Applicant: Applied Materials, Inc.Inventors: Pravin Narwankar, Ravi Rajagopalan, Turgut Sahin
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Publication number: 20020146913Abstract: A method of manufacturing a semiconductor device having a metal layer is provided in which variation of surface morphology resulting from thermal oxidation is suppressed. The metal layer is pretreated at a first temperature so that an upper surface of the metal layer is changed into a mixed phase of metal and oxygen and becomes substantially resistant to further oxidation during a subsequent heating at a higher temperature in an oxygen atmosphere.Type: ApplicationFiled: March 19, 2002Publication date: October 10, 2002Inventors: Eun-ae Chung, Doo-sup Hwang, Cha-young Yoo
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Publication number: 20020142622Abstract: A metal wiring buried in an insulating layer is subjected to a reducing treatment prior to formation of a second insulating layer on the insulating layer under the condition that the total partial pressure of oxygen and water vapor is sufficiently low.Type: ApplicationFiled: March 28, 2002Publication date: October 3, 2002Applicant: Kabushiki Kaisha ToshibaInventors: Tadashi Iijima, Tadayoshi Watanabe
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Patent number: 6440852Abstract: An integrated circuit includes a substrate, and at least one copper interconnection layer adjacent the substrate. The interconnection layer further comprises copper lines, each comprising at least an upper surface portion including at least one copper fluoride compound. The copper fluoride compound preferably comprises at least one of cuprous fluoride and cupric fluoride. The compounds of copper and fluoride are relatively stable and provide a reliable and long term passivation for the underlying copper. In accordance with one particularly advantageous embodiment of the invention, the dielectric layer may comprise a fluorosilicate glass (FSG) layer. Accordingly, during formation of the FSG layer, the upper surface of the copper reacts with the fluorine to form the copper fluoride compound which then acts as the passivation layer for the underlying copper. In other embodiments, the dielectric layer may comprise an oxide or air, for example.Type: GrantFiled: July 30, 1999Date of Patent: August 27, 2002Assignee: Agere Systems Guardian Corp.Inventors: Martin G. Meder, Sailesh Mansinh Merchant, Michael Louis Steigerwald, Yiu-Huen Wong
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Publication number: 20020111021Abstract: Nickel salicide processing is implemented by forming a non-stoicheiometric mediating layer, such as ozonated SiOx, to control the reaction of Ni and Si during annealing to form a NiSi layer on the polysilicon gate electrodes and source/drain regions without conductive bridging between the metal silicide layer on the gate electrode and the metal silicide layers on associated source/drain regions. Embodiments of the present invention comprise forming silicon nitride sidewall spacers on the side surfaces of the gate electrode.Type: ApplicationFiled: February 13, 2001Publication date: August 15, 2002Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Eric N. Paton, Terri J. Kitson, Jeffrey S. Glick, John C. Foster
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Publication number: 20020076940Abstract: An aluminium film is formed by sputtering on a ferromagnetic layer made of, e.g., Ni—Fe alloy. The aluminum film is oxidized while an alumina film is deposited on the aluminum film by reactive sputtering, to form a tunneling barrier film. Assuming that the aluminum film has a thickness of 1 nm and the alumina film deposited has a thickness of 0.2 nm, an alumina film having a thickness of about 1.5 nm is formed on the ferromagnetic layer, this alumina film being a lamination of an alumina film which is the oxidized aluminum film and the deposited alumina film. The surface of the ferromagnetic layer is prevented from being oxidized because of the presence of the aluminum film. A thin oxide film such as alumina can be formed in a short time without oxidizing an underlying layer.Type: ApplicationFiled: December 17, 2001Publication date: June 20, 2002Applicant: Yamaha CorporationInventor: Satoshi Hibino
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Patent number: 6348373Abstract: A method of improving the electrical properties of high dielectric constant films by depositing an initial film and implanting oxygen ions to modify the film by decreasing the oxygen deficiency of the film while reducing or eliminating formation of an interfacial silicon dioxide layer. An initial high dielectric constant material is deposited over a silicon substrate by means of CVD, reactive sputtering or evaporation. Oxygen ions are preferably implanted using plasma ion immersion (PIII), although other methods are also provided. Following implantation the substrate is annealed to condition the high dielectric constant film.Type: GrantFiled: March 29, 2000Date of Patent: February 19, 2002Assignee: Sharp Laboratories of America, Inc.Inventors: Yanjun Ma, Yoshi Ono
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Patent number: 6331486Abstract: A method of reducing contact resistance of metal silicides to a silicon-containing substrate is provided. The method includes first forming a metal germanium layer over a silicon-containing substrate. An optionally oxygen barrier layer may be formed over the metal germanium layer. Next, the structure containing the metal germanium layer is annealed at a temperature effective in converting at least a portion of the metal germanium layer into a substantially non-etchable metal silicide layer, while forming a Si-Ge interlayer between the substrate and the silicide layer. After annealing, the optional oxygen barrier layer and any remaining metal germanium layer is removed from the substrate.Type: GrantFiled: March 6, 2000Date of Patent: December 18, 2001Assignee: International Business Machines CorporationInventors: Cyril Cabral, Jr., Roy Arthur Carruthers, James McKell Edwin Harper, Christian Lavoie, Ronnen Andrew Roy, Yun Yu Wang
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Patent number: 6323128Abstract: A method for forming a quaternary alloy film of Co—W—P—Au for use as a diffusion barrier layer on a copper interconnect in a semiconductor structure and devices formed incorporating such film are disclosed. In the method, a substrate that has copper conductive regions on top is first pre-treated by two separate pre-treatment steps. In the first step, the substrate is immersed in a H2SO4 rinsing solution and next in a solution containing palladium ions for a length of time sufficient for the ions to deposit on the surface of the copper conductive regions. The substrate is then immersed in a solution that contains at least 15 gr/l sodium citrate or EDTA for removing excess palladium ions from the surface of the copper conductive regions.Type: GrantFiled: May 26, 1999Date of Patent: November 27, 2001Assignee: International Business Machines CorporationInventors: Carlos Juan Sambucetti, Judith Marie Rubino, Daniel Charles Edelstein, Cyryl Cabral, Jr., George Frederick Walker, John G Gaudiello, Horatio Seymour Wildman
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Patent number: 6309970Abstract: There is presented a semiconductor device including multiple levels of copper interconnects; wherein the surface of a copper interconnect corresponding to at least one underlying layer of another copper interconnect layer is turned into copper oxide to a thickness of 30 nm or more by oxidation conducted at the oxidation rate of 20 nm/minor less, and thereby the reflection of the exposure light from the lower-level copper interconnect is prevented, in forming by means of photolithography a trench to form a copper interconnect through damascening.Type: GrantFiled: August 30, 1999Date of Patent: October 30, 2001Assignee: NEC CorporationInventors: Nobukazu Ito, Yoshihisa Matsubara
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Patent number: 6300147Abstract: An SOI substrate having a silicon layer formed on an embedded oxide layer is prepared at a step ST11. An exposed surface of the silicon layer is thermally oxidized for forming a thermal oxide film at a step ST12. The thermal oxide film, enclosing a defect in the silicon layer, is formed in a shape on or to which the defect is reflected or transferred. At this time, thermal oxidation is so executed that the transferred part of the thermal oxide film is in contact with the embedded oxide layer. The SOI substrate is dipped in a hydrofluoric acid solution at a step ST13. Thus, the thermal oxide film is removed while the embedded oxide layer is eroded through the part in contact with the thermal oxide film. According to this inspection method ST10, the defect is reliably transferred to the embedded oxide layer through the thermal oxidation step ST12, whereby it is possible to evaluate an inner defect undetectable/unevaluative by a conventional inspection method.Type: GrantFiled: June 26, 2000Date of Patent: October 9, 2001Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Hideki Naruoka
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Patent number: 6284600Abstract: A predetermined species such as nitrogen is placed at an interface between a bit line junction and a dielectric layer of a control dielectric structure of a flash memory device to minimize degradation of such an interface by minimizing formation of interface defects during program or erase operations of the flash memory device. The predetermined species such as nitrogen is implanted into a bit line junction of the flash memory device. A thermal process is performed that heats up the semiconductor wafer such that the predetermined species such as nitrogen implanted within the semiconductor wafer thermally drifts to the interface between the bit line junction and the control dielectric structure during the thermal process. The predetermined species such as nitrogen at the interface minimizes formation of interface defects and thus degradation of the interface with time during the program or erase operations of the flash memory device.Type: GrantFiled: July 3, 2000Date of Patent: September 4, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Yider Wu, Mark T. Ramsbey, Chi Chang, Yu Sun, Tuan Duc Pham, Jean Y. Yang
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Patent number: 6190994Abstract: There is provided a method for forming a capacitor of a semiconductor device capable of preventing a dielectric layer from being damaged in forming a tungsten upper electrode on a dielectic layer, and preventing tungsten siliside from being formed on a tungsten film in the following processes. In the present invention, for protecting a dielectric layer, a polisilicon layer is formed on a dielectric layer as a sacrifical reduction layer. Then, a tungsten seed layer is formed on the dielectric layer by reducing WF6 with the polysilicon layer. After that, a tungsten film to be an upper electrode is formed by subsequently carrying out a deposition process using the reaction of WF6 and H2 or SiH4 Then, for preventing tungsten silicide film from being formed in following thermal process, a thermal process is performed in ammonia(NH3) cointaining ambient, or a plasma process using a nitrogen gas or an ammonia gas is performed to nitrize the surface of the tungsten film.Type: GrantFiled: June 28, 1999Date of Patent: February 20, 2001Assignee: Hyundai Electronics Industries Co., Ltd.Inventor: Hwan Seok Seo
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Patent number: 6177311Abstract: A floating memory device utilizing a composite oxide/oxynitride or oxide/oxynitride/oxide interpoly dielectric.Type: GrantFiled: November 25, 1997Date of Patent: January 23, 2001Assignee: Micron Technology, Inc.Inventors: Ralph Kauffman, Roger Lee
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Patent number: 6156619Abstract: A capacitor in a semiconductor device is constituted by a lower electrode having a laminated layer including an adhesive layer formed on an insulating film, a barrier layer formed so as to cover the upper surface of the insulating layer, a nitride side formed so as to cover the side face of the adhesive layer, and an electrode layer formed so as to cover the upper surface of the barrier layer, a capacitor insulating film formed so as to cover the upper surface and side surface of the lower electrode, and an upper electrode formed so as to cover the surface of the capacitor insulating film.Type: GrantFiled: June 29, 1998Date of Patent: December 5, 2000Assignee: Oki Electric Industry Co., Ltd.Inventor: Shih-Chang Chen
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Patent number: 6127270Abstract: Methods of forming refractory metal silicide components are described. In accordance with one implementation, a refractory metal layer is formed over a substrate. A silicon-containing structure is formed over the refractory metal layer and a silicon diffusion restricting layer is formed over at least some of the silicon-containing structure. The substrate is subsequently annealed at a temperature which is sufficient to cause a reaction between at least some of the refractory metal layer and at least some of the silicon-containing structure to at least partially form a refractory metal silicide component. In accordance with one aspect of the invention, a silicon diffusion restricting layer is formed over or within the refractory metal layer in a step which is common with the forming of the silicon diffusion restricting layer over the silicon-containing structure.Type: GrantFiled: August 13, 1997Date of Patent: October 3, 2000Assignee: Micron Technology, Inc.Inventors: Yongjun Hu, Jigish D. Trivedi
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Patent number: 6063692Abstract: A method of fabricating an oxidation barrier for a thin film is provided. The method may include forming a thin film (10) outwardly from a semiconductor substrate (12) and separated from the semiconductor substrate (12) by a primary insulator layer (14). A reactive layer (16) may be formed in-situ adjacent to the thin film (10). An oxidation barrier (20) may be formed by a chemical reaction between the thin film (10) and the reactive layer (16). The oxidation barrier (20) may comprise a silicide alloy that operates to reduce oxidation of the thin film (10).Type: GrantFiled: December 14, 1998Date of Patent: May 16, 2000Assignee: Texas Instruments IncorporatedInventors: Wei William Lee, Joseph D. Luttmer, Hong Yang
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Patent number: 6057223Abstract: A copper conductor is formed which is included as a component in microelectronic devices. The conductor is formed by forming a metal layer on the surface of a microelectronic substrate, forming a copper layer on the metal layer, and annealing the metal and copper layers. The annealing step diffuses at least some of the metal layer through the copper layer to the surface thereof where the diffused metal forms a protective metal oxide at the surface of the copper layer. As a result, the metal oxide layer passivates the copper layer.Type: GrantFiled: February 10, 1998Date of Patent: May 2, 2000Assignee: The Research Foundation of State University of New YorkInventors: William A. Lanford, Wei Wang, Peijun Ding
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Patent number: 5994218Abstract: A silicon film is deposited using low pressure chemical vapor deposition (LPCVD) to fill in openings formed in a substrate such as an insulating film. An aluminum film and a metal film are then formed on the silicon film. A thermal process is then carried out. This thermal process causes the deposited aluminum to replace the silicon in the openings because the silicon migrates to the metal and forms a metal silicide film. The aluminum which replaces the silicon in the openings has few or no voids. The metal silicide film any remaining portion of the aluminum film are then removed using CMP, for example.Type: GrantFiled: September 30, 1996Date of Patent: November 30, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Shigeki Sugimoto, Katsuya Okumura
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Patent number: 5963828Abstract: A method in a semiconductor process for forming a layer of a selected compound on a substrate of a semiconductor device. A layer of titanium is formed on the substrate as a sacrificial layer. The layer of titanium is reduced using a gaseous form of a fluorine containing compound in which the fluorine containing compound includes the selected compound that is to be formed on the substrate of the semiconductor device.Type: GrantFiled: December 23, 1996Date of Patent: October 5, 1999Assignee: LSI Logic CorporationInventors: Derryl D.J. Allman, Verne C. Hornback, Ramanath Ganapathiraman, Leslie H. Allen
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Patent number: 5908316Abstract: A method of passivating a semiconductor substrate includes singulating (13) a semiconductor substrate (23) from a semiconductor wafer, coupling (14) a heatsink (21) to the semiconductor substrate (23), etching (15) the semiconductor substrate (23) in a chamber of an etch tool, and passivating (17) the semiconductor substrate (23) with an oxide layer (31). The semiconductor substrate (23) is kept in the chamber of the etch tool from the etching (15) step through the passivating (17) step. The etching (15) of the semiconductor substrate (23) does not substantially etch the heatsink (21), and the passivating (17) of the semiconductor substrate (23) does not substantially passivate the heatsink (21).Type: GrantFiled: December 18, 1995Date of Patent: June 1, 1999Assignee: Motorola, Inc.Inventors: Hiep M. Le, Lonne L. Mays, Albert E. Tavares
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Patent number: 5879969Abstract: In a thin-film insulated gate type field effect transistor having a metal gate in which the surface of the gate electrode is subjected to anodic oxidation, a silicon nitride film is provided so as to be interposed between the gate electrode and the gate insulating film to prevent invasion of movable ions into a channel, and also to prevent the breakdown of the gate insulating film due to a potential difference between the gate electrode and the channel region. By coating a specific portion of the gate electrode with metal material such as chrome or the like for the anodic oxidation, and then removing only the metal material such as chrome or the like together with the anodic oxide of the metal material such as chrome or the like, an exposed portion of metal gate (e.g. aluminum) is formed, and an upper wiring is connected to the exposed portion.Type: GrantFiled: April 30, 1997Date of Patent: March 9, 1999Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hongyong Zhang, Yasuhiko Takemura
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Patent number: 5866444Abstract: An integrated circuit using conductive interconnects made of aluminum or a material consisting chiefly of aluminum. Defects due to hillocks and whiskers are prevented. The integrated circuit is composed of TFTs. Gate interconnects are made of aluminum. Before a metallization film for forming the gate interconnects is patterned, slits are formed in locations where crosstalks and shorts are likely to occur by generation of hillocks and whiskers. The surfaces inside the slits are anodized. The conductive interconnects are formed, using the locations provided with the slits. In this way, during the anodization, unwanted stress is prevented. Furthermore, it is unlikely that a required electric current cannot be supplied for the anodization because of excessive complexity of the interconnection pattern.Type: GrantFiled: March 18, 1996Date of Patent: February 2, 1999Assignee: Semiconductor Energy Laboratory Co.Inventors: Shunpei Yamazaki, Jun Koyama, Toshimitsu Konuma, Satoshi Teramoto
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Patent number: 5861332Abstract: A method for fabricating a capacitor of a semiconductor device, which is capable improving the chemical and thermal stability of lower electrodes.Type: GrantFiled: June 26, 1997Date of Patent: January 19, 1999Assignee: Hyundai Electronics Industries Co., Ltd.Inventors: Yong Sik Yu, Kwon Hong
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Patent number: 5861346Abstract: Silicon carbide films and microcomponents are grown on silicon substrates at surface temperatures between 900 K and 1700 K via C.sub.60 precursors in a hydrogen-free environment. Selective crystalline silicon carbide growth can be achieved on patterned silicon-silicon oxide samples. Patterned SiC films are produced by making use of the high reaction probability of C.sub.60 with silicon at surface temperatures greater than 900 K and the negligible reaction probability for C.sub.60 on silicon dioxide at surface temperatures less than 1250 K.Type: GrantFiled: July 27, 1995Date of Patent: January 19, 1999Assignee: Regents of the University of CaliforniaInventors: Alex V. Hamza, Mehdi Balooch, Mehran Moalem
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Patent number: 5849611Abstract: A wiring formed on a substrate is oxidized and the oxide is used as a mask for forming source and drain impurity regions of a transistor, or as a material for insulating wirings from each other, or as a dielectric of a capacitor. Thickness of the oxide is determined depending on purpose of the oxide.In a transistor adapted to be used in an active-matrix liquid-crystal display, the channel length, or the distance between the source region and the drain region, is made larger than the length of the gate electrode taken in the longitudinal direction of the channel. Offset regions are formed in the channel region on the sides of the source and drain regions. No or very weak electric field is applied to these offset regions from the gate electrode.Type: GrantFiled: May 31, 1995Date of Patent: December 15, 1998Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Akira Mase, Masaaki Hiroki, Yasuhiko Takemura, Hongyong Zhang, Hideki Uochi
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Patent number: 5830786Abstract: A process for fabricating an electronic circuit by oxidizing the surroundings of a metallic interconnection such as of aluminum, tantalum, and titanium, wherein anodic oxidation is effected at a temperature not higher than room temperature, preferably, at 10.degree. C. or lower, and more preferably, at 0.degree. C. or lower. The surface oxidation rate of a metallic interconnection can be maintained constant to provide a surface free of irregularities.Type: GrantFiled: May 28, 1996Date of Patent: November 3, 1998Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hongyong Zhang, Hideki Uochi, Shunpei Yamazaki, Yasuhiko Takemura, Minoru Miyazaki, Akane Murakami, Toshimitsu Konuma, Akira Sugawara, Yukiko Uehara
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Patent number: 5733817Abstract: A method of forming isolated metal contacts during fabrication of semiconductor devices including blanket forming contact metal on a semiconductor device having a mesa structure with a first layer overlying an upper surface, a second layer overlying a lower surface and a third, substantially thinner layer overlying the sidewall therebetween. The contact metal is blanket oxidized using deep ultra violet light until the third layer is substantially completely oxidized thereby electrically isolating the first layer from the second layer.Type: GrantFiled: June 20, 1997Date of Patent: March 31, 1998Assignee: Motorola, Inc.Inventor: Kumar Shiralagi
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Patent number: 5658819Abstract: An antifuse may include one or more interfacial oxide film layers surrounding an antifuse dielectric layer to provide narrowing of the antifuse programming voltage distribution and to improve the antifuse yield and long term reliability.Type: GrantFiled: November 1, 1995Date of Patent: August 19, 1997Assignee: United Technologies CorporationInventors: Kurt D. Humphrey, Bradley S. Holway, Craig Hafer
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Patent number: 5624874Abstract: The properties of a diffusion barrier material layer over a semiconductor substrate are enhanced in a simple and time-effective manner by immersing the substrate in an oxidizing liquid. For a titanium-tungsten barrier metal, a dip in nitric acid for 1-60 minutes provides the metal with an oxide layer of the right thickness of 10-20 .ANG..Type: GrantFiled: October 18, 1995Date of Patent: April 29, 1997Assignee: North America Philips CorporationInventors: Sheldon C. P. Lim, Stanley C. Chu
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Patent number: 5622608Abstract: A process for preparing an oxidation resistant, electrically conductive copper layer on a substrate, and copper layers so formed, are disclosed. A copper layer is deposited onto the surface of a substrate, and subsequently annealed. The copper layer includes magnesium in an amount sufficient to form an inert magnesium oxide layer at the surface of the copper layer upon annealing.Type: GrantFiled: May 5, 1994Date of Patent: April 22, 1997Assignee: Research Foundation of State University of New YorkInventors: William A. Lanford, Peijun Ding