By Reaction With Substrate Patents (Class 438/765)
  • Patent number: 10157741
    Abstract: A method of manufacturing a semiconductor structure includes providing a first lot including a plurality of first wafers and a second lot including a plurality of second wafers; deriving a first processing time for processing the first lot; deriving a second processing time for processing the second lot; deriving a processing time difference between the first processing time and the second processing time; loading a first mask on a mask stage; processing the first lot on a wafer stage; removing the first mask from the mask stage; loading a second mask on the mask stage; and processing the second lot on the wafer stage, wherein a time interval between accomplishment of the processing of the first lot and beginning of the processing of the second lot is substantially greater than or equal to the processing time difference.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: December 18, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yung-Yao Lee, En-Chao Shen
  • Patent number: 9606138
    Abstract: Provided are a motion recognition apparatus, a motion recognition system and a motion recognition method that enable ‘event motions’ to be recognized with a small number of calculations. The motion recognition system, which recognizes user motions by using sensor data, is configured to be provided with: a cyclical loss detection means for detecting cyclical losses of sensor data when a user is moving; and a recognition processing means for setting data intervals to be used for recognizing motions in accordance with the cyclical losses of sensor data that were detected, and for recognizing user motions on the basis of sensor data for the data intervals that have been set.
    Type: Grant
    Filed: January 21, 2013
    Date of Patent: March 28, 2017
    Assignee: NEC CORPORATION
    Inventors: Yuki Chiba, Yoji Miyazaki
  • Patent number: 9472412
    Abstract: Methods of conditioning interior processing chamber walls of an etch chamber are described. A fluorine-containing precursor may be remotely or locally excited in a plasma to treat the interior chamber walls periodically on a preventative maintenance schedule. The treated walls promote an even etch rate when used to perform gas-phase etching of silicon regions following conditioning. Alternatively, a hydrogen-containing precursor may be remotely or locally excited in a plasma to treat the interior chamber walls in embodiments. Regions of exposed silicon may then be etched with more reproducible etch rates from wafer-to-wafer. The silicon etch may be performed using plasma effluents formed from a remotely excited fluorine-containing precursor.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: October 18, 2016
    Assignee: Applied Materials, Inc.
    Inventors: Jingchun Zhang, Hanshen Zhang
  • Patent number: 9409769
    Abstract: A biosensing FET device, comprising a plurality of nanostructured SOI channels, that is adapted to operate in solutions having a high ionic strength and provides improves sensitivity and detection. Generally, the biosensing device comprises an underlying substrate layer, an insulator and a semiconductor layer and a plurality of channels in the semiconductor layer comprising a plurality of whole or partially formed nanopores in the channels.
    Type: Grant
    Filed: November 30, 2007
    Date of Patent: August 9, 2016
    Assignee: GENERAL ELECTRIC COMPANY
    Inventors: An-Ping Zhang, Anthony John Murray, Rui Chen
  • Patent number: 9337017
    Abstract: A method for repairing damages to sidewalls of an ultra-low dielectric constant film is disclosed by the present invention comprises the following steps: depositing an ultra-low dielectric constant film on an semiconductor substrate; dry-etching the ultra-low dielectric constant film to form a sidewall structure thereof; performing wet cleaning by using a chemical agent containing an unsaturated hydrocarbon having —O—C(Re)x; and performing ultraviolet curing. The present invention can restore pores size and porosity of the ultra-low dielectric constant film, and to keep effective dielectric constant to a minimum.
    Type: Grant
    Filed: August 11, 2014
    Date of Patent: May 10, 2016
    Assignee: SHANGHAI IC R&D CENTER CO., LTD
    Inventors: Shaohai Zeng, Qingyun Zuo, Ming Li
  • Patent number: 9305833
    Abstract: A method is provided for fabricating a semiconductor structure. The method includes providing a substrate; and forming a conductive layer in one surface of the substrate. The method also includes forming a dielectric layer on the surface of the substrate; and forming an opening exposing a portion of the conductive layer in the dielectric layer. Further, the method includes forming a passivation layer for protecting the portion of the conductive layer on a surface of the portion of the conductive layer on the bottom of the opening using a passivation solution; and cleaning inner surface of the opening using a cleaning solution not reacting with the passivation layer. Further, the method also includes removing the passivation layer; and forming a metal layer connecting with the conductive layer in the opening.
    Type: Grant
    Filed: July 7, 2014
    Date of Patent: April 5, 2016
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Chunzhou Hu
  • Patent number: 9269652
    Abstract: A method including forming a dielectric material including a surface porosity on a circuit substrate including a plurality of devices; chemically modifying a portion of the surface of the dielectric material with a first reactant; reacting the chemically modified portion of the surface with a molecule that, once reacted, will be thermally stable; and forming a film including the molecule. An apparatus including a circuit substrate including a plurality of devices; a plurality of interconnect lines disposed in a plurality of layers coupled to the plurality of devices; and a plurality of dielectric layers disposed between the plurality of interconnect lines, wherein at least one of the dielectric layers comprises a porous material surface relative to the plurality of devices and the surface comprises a pore obstructing material.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: February 23, 2016
    Assignee: Intel Corporation
    Inventors: David J. Michalak, James M. Blackwell, Jeffery D. Bielefeld, James S. Clarke
  • Patent number: 9238861
    Abstract: In one embodiment, a method includes depositing a CIGS precursor layer onto a substrate, introducing a source-material layer into proximity with the precursor layer, where the source-material layer includes one or more of Cu, In, or Ga, and one or more of S or Se, and annealing the precursor layer in proximity with of the source-material layer, where the annealing is performed in a constrained volume, and where the presence of the source-material layer reduces decomposition of volatile species from the precursor layer during annealing.
    Type: Grant
    Filed: May 9, 2012
    Date of Patent: January 19, 2016
    Assignee: ZETTA RESEARCH AND DEVELOPMENT LLC—AQT SERIES
    Inventors: Mariana Rodica Munteanu, Amith Kumar Murali, Brian Josef Bartholomeusz, Vardaan Chawla
  • Patent number: 9207689
    Abstract: Provided are a substrate temperature control method and a plasma processing apparatus using the method. The method includes: disposing a substrate on a placing table provided in a vacuum processing chamber; supplying a heat conduction gas between a rear surface of the substrate and the placing table; detecting a pressure of the heat conduction gas; comparing the detected pressure value with a set pressure value; controlling the supply of the heat conduction gas so that the detected pressure value becomes the set pressure value; and alternately repeating a first period where the set pressure value is set to be a first set pressure value that is higher than a low pressure value and equal to or higher than the lowest limit pressure value and a second period where the set pressure value is set to be a second set pressure value that is lower than the low pressure value.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: December 8, 2015
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Chishio Koshimizu
  • Patent number: 9209513
    Abstract: A housing for an electronic device, including an aluminum layer enclosing a volume that includes a radio-frequency (RF) antenna is provided. The housing includes a window aligned with the RF antenna; the window including a non-conductive material filling a cavity in the aluminum layer; and a thin aluminum oxide layer adjacent to the aluminum layer and to the non-conductive material; wherein the non-conductive material and the thin aluminum oxide layer form an RF-transparent path through the window. A housing for an electronic device including an integrated RF-antenna is also provided. A method of manufacturing a housing for an electronic device as described above is provided.
    Type: Grant
    Filed: August 22, 2013
    Date of Patent: December 8, 2015
    Assignee: Apple Inc.
    Inventors: Colin M. Ely, Christopher D. Prest, Lucy E. Browning, Stephen B. Lynch, Eric S. Laakmann, Paul L. Nangeroni
  • Patent number: 9176509
    Abstract: Provided are a substrate temperature control method and a plasma processing apparatus using the method. The method includes: disposing a substrate on a placing table provided in a vacuum processing chamber; supplying a heat conduction gas between a rear surface of the substrate and the placing table; detecting a pressure of the heat conduction gas; comparing the detected pressure value with a set pressure value; controlling the supply of the heat conduction gas so that the detected pressure value becomes the set pressure value; and alternately repeating a first period where the set pressure value is set to be a first set pressure value that is higher than a low pressure value and equal to or higher than the lowest limit pressure value and a second period where the set pressure value is set to be a second set pressure value that is lower than the low pressure value.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: November 3, 2015
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Chishio Koshimizu
  • Patent number: 9142647
    Abstract: A method of producing a vertical transistor includes providing a conductive gate structure having a reentrant profile on a substrate. A conformal insulating material layer is formed on the conductive gate structure. A conformal semiconductor material layer is formed on the insulating material layer. A deposition inhibiting material is deposited over a portion of the substrate and the conductive gate structure including filling the reentrant profile. A portion of the deposition inhibiting material is removed without removing all of the deposition inhibiting material from the reentrant profile. A plurality of electrodes is formed by depositing an electrically conductive material layer on portions of the semiconductor material layer using a selective area deposition process in which the electrically conductive material layer is not deposited on the deposition inhibiting material remaining in the reentrant profile.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: September 22, 2015
    Assignee: EASTMAN KODAK COMPANY
    Inventors: Shelby Forrester Nelson, Carolyn Rae Ellinger
  • Patent number: 9064908
    Abstract: There is provided a liquid processing apparatus capable of efficiently processing a pattern formation surface of a wafer, while preventing diffusion of a chemical-liquid atmosphere which might possibly occurs during a chemical-liquid process.
    Type: Grant
    Filed: June 7, 2012
    Date of Patent: June 23, 2015
    Assignee: Tokyo Electron Limited
    Inventors: Norihiro Itoh, Kazuhiro Aiura
  • Publication number: 20150140834
    Abstract: Methods and apparatus for processing using a plasma source for the treatment of semiconductor surfaces are disclosed. The apparatus includes an outer vacuum chamber enclosing a substrate support, a plasma source (either a direct plasma or a remote plasma), and an optional showerhead. Other gas distribution and gas dispersal hardware may also be used. The plasma source may be used to generate activated species operable to alter the surface of the semiconductor materials. Further, the plasma source may be used to generate activated species operable to enhance the nucleation of deposition precursors on the semiconductor surface.
    Type: Application
    Filed: November 18, 2013
    Publication date: May 21, 2015
    Applicant: Intermolecular Inc.
    Inventors: Kevin Kashefi, Frank Greer
  • Patent number: 8999860
    Abstract: The process for the production of at least one silicon-based nanoelement (4), in particular a nanowire, comprises the following stages: providing a substrate comprising, at the surface, a first layer (1) comprising electrically doped silicon; forming, on the first layer (1), a second layer (2) based on silicon oxide with carbon atoms (3) dispersed in the said second layer (2); and exposing the first and second layers (1, 2) to an oxidizing atmosphere, so as to oxidize at least a first section (1a) of the first layer (1) at the interface of the said first layer (1) with the second layer (2) and to form the said at least one nanoelement (4) at the said first section (1a).
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: April 7, 2015
    Assignee: Commissariat a l'energie Atomique et aux Energies Alternatives
    Inventors: Vincent Larrey, Laurent Vandroux, Audrey Berthelot, Marie-Helene Vaudaine
  • Patent number: 8999858
    Abstract: The substrate processing apparatus includes a reaction chamber configured to accommodate a substrate; a first gas supply unit configured to supply a first process gas containing a silicon element to the substrate; a second gas supply unit configured to supply a second process gas containing a silicon element and a chlorine element to the substrate; an exhaust unit configured to exhaust the first process gas and the second process gas; a cleaning gas bypass supply unit configured to supply a cleaning gas to the exhaust unit; a cleaning monitoring unit installed in the exhaust unit; a gas flow rate control unit configured to adjust an amount of the cleaning gas supplied; and a main control unit configured to control the gas flow rate control unit in response to a signal received from the cleaning gas monitoring unit.
    Type: Grant
    Filed: December 26, 2012
    Date of Patent: April 7, 2015
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Yasunobu Koshi, Kenichi Suzaki, Akihito Yoshino
  • Patent number: 8999475
    Abstract: A component of a substrate processing apparatus that performs plasma processing on a substrate includes a base mainly formed of an aluminum alloy containing silicon. A film is formed on the surface of the base by an anodic oxidation process which includes connecting the component to an anode of a power supply and immersing the component in a solution mainly formed of an organic acid. The film is impregnated with ethyl silicate.
    Type: Grant
    Filed: January 16, 2009
    Date of Patent: April 7, 2015
    Assignee: Tokyo Electron Limited
    Inventor: Koji Mitsuhashi
  • Publication number: 20150087159
    Abstract: Provided is a technique of efficiently purging source gases remaining on a substrate and improving in-plane uniformity of a substrate. A method of processing a substrate includes forming a thin film on a substrate accommodated in a process chamber by (a) supplying a source gas into the process chamber, and (b) supplying an inert gas into the process chamber while alternately increasing and decreasing a flow rate of the inert gas supplied into the process chamber and exhausting the source gas and the inert gas from the process chamber.
    Type: Application
    Filed: September 24, 2014
    Publication date: March 26, 2015
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Koei KURIBAYASHI, Shinya EBATA
  • Patent number: 8975194
    Abstract: Disclosed a method for manufacturing an oxide layer, applicable to a manufacture procedure of a field oxide layer of a CMOS transistor in the field of semiconductor manufacturing, the method includes: injecting a first gas satisfying a first predetermined condition into a processing furnace in which a first CMOS transistor semi-finished product formed with an N-well and a P-well is placed, and dry-oxidizing the first CMOS transistor semi-finished product into a second CMOS transistor semi-finished product; and injecting a second gas satisfying a second predetermined condition different from the first predetermined condition into the processing furnace, and wet-oxidizing the second CMOS transistor semi-finished product into a third CMOS transistor semi-finished product.
    Type: Grant
    Filed: November 13, 2013
    Date of Patent: March 10, 2015
    Assignees: Peking University Founder Group Co., Ltd., Founder Microelectronics International Co., Ltd.
    Inventor: Jinyuan Chen
  • Patent number: 8956937
    Abstract: The present invention discloses to a method of depositing the metal barrier layer comprising silicon dioxide. It is applied in the transistor device comprising a silicon substrate, a gate and a gate side wall. The method comprises the following steps: ions are implanted into the silicon substrate to form an active region in the said silicon substrate; a first dense silicon dioxide film is deposited; a second normal silicon dioxide film is deposited; the said transistor device is high temperature annealed. The present invention ensures that the implanted ion is not separated out of the substrate during the annealing. And it prevents the warping and fragment of the silicon surface.
    Type: Grant
    Filed: November 1, 2013
    Date of Patent: February 17, 2015
    Assignee: Shanghai Huali Microelectronics Corporation
    Inventors: GuoFang Xuan, Fei Luo
  • Patent number: 8945302
    Abstract: Method for crystal growth from a surfactant of a metal-nonmetal (MN) compound, including the procedures of providing a seed crystal, introducing atoms of a first metal to the seed crystal thus forming a thin liquid metal wetting layer on a surface of the seed crystal, setting a temperature of the seed crystal below a minimal temperature required for dissolving MN molecules in the wetting layer and above a melting point of the first metal, each one of the MN molecules being formed from an atom of a second metal and an atom of a first nonmetal, introducing the MN molecules which form an MN surfactant monolayer, thereby facilitating a formation of the wetting layer between the MN surfactant monolayer and the surface of the seed crystal, and regulating a thickness of the wetting layer, thereby growing an epitaxial layer of the MN compound on the seed crystal.
    Type: Grant
    Filed: March 4, 2012
    Date of Patent: February 3, 2015
    Assignee: Mosaic Crystals Ltd.
    Inventor: Moshe Einav
  • Patent number: 8945979
    Abstract: An organic layer deposition apparatus, a method of manufacturing an organic light-emitting display apparatus by using the same, and an organic light-emitting display apparatus manufactured by the method, and more particularly, an organic layer deposition apparatus that is suitable for use in the mass production of a large substrate, that enables high-definition patterning, and that is capable of controlling a distance between a patterning slit sheet and a substrate that moves, a method of manufacturing an organic light-emitting display apparatus by using the organic layer deposition apparatus, and an organic light-emitting display apparatus manufactured by the method.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: February 3, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventor: Yun-Ho Chang
  • Patent number: 8937016
    Abstract: A method of producing a patterned inorganic thin film element includes providing a substrate having a patterned thin layer of polymeric inhibitor on the surface. The substrate and the patterned thin layer of polymeric inhibitor are exposed to a highly reactive oxygen process. An inorganic thin film layer is deposited on the substrate in areas without inhibitor using an atomic layer deposition process.
    Type: Grant
    Filed: June 21, 2013
    Date of Patent: January 20, 2015
    Assignee: Eastman Kodak Company
    Inventors: Carolyn R. Ellinger, Shelby F. Nelson, Kurt D. Sieber
  • Publication number: 20150008393
    Abstract: Networks of semiconductor structures with fused insulator coatings and methods of fabricating networks of semiconductor structures with fused insulator coatings are described. In an example, a semiconductor structure includes an insulator network. A plurality of discrete semiconductor nanocrystals is disposed in the insulator network. Each of the plurality of discrete semiconductor nanocrystals is spaced apart from one another by the insulator network.
    Type: Application
    Filed: August 21, 2013
    Publication date: January 8, 2015
    Inventors: Benjamin Daniel Mangum, Weiwen Zhao, Kari N. Haley, Juanita N. Kurtin
  • Patent number: 8921176
    Abstract: A semiconductor fabrication method includes forming a gate dielectric stack on a semiconductor substrate and annealing the gate dielectric stack. Forming the stack may include depositing a first layer of a metal-oxide dielectric on the substrate, forming a refractory metal silicon nitride on the first layer, and depositing a second layer of the metal-oxide dielectric on the refractory metal silicon nitride. Depositing the first layer may include depositing a metal-oxide dielectric, such as HfO2, using atomic layer deposition. Forming the refractory metal silicon nitride film may include forming a film of tantalum silicon nitride using a physical vapor deposition process. Annealing the gate dielectric stack may include annealing the gate dielectric stack in an oxygen-bearing ambient at approximately 750 C for 10 minutes or less. In one embodiment, annealing the dielectric stack includes annealing the dielectric stack for approximately 60 seconds at a temperature of approximately 500 C.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: December 30, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Rama I. Hegde
  • Patent number: 8921236
    Abstract: A method of producing a patterned inorganic thin film element includes providing a substrate. A thin layer of polymeric inhibitor is uniformly depositing on the substrate. A patterned mask having open areas is provided on the thin layer of polymeric inhibitor. The thin layer of polymeric inhibitor is patterned by removing inhibitor from areas exposed by the open areas of the patterned mask using a highly reactive oxygen process. An inorganic thin film layer is deposited on the substrate in the areas exposed by the removal of the thin layer of polymeric inhibitor using an atomic layer deposition process.
    Type: Grant
    Filed: June 21, 2013
    Date of Patent: December 30, 2014
    Assignee: Eastman Kodak Company
    Inventors: Carolyn R. Ellinger, Shelby F. Nelson, Kurt D. Sieber
  • Patent number: 8912611
    Abstract: A method of fabricating a semiconductor device includes forming a lower interfacial layer on a semiconductor layer, the lower interfacial layer being a nitride layer, forming an intermediate interfacial layer on the lower interfacial layer, the intermediate interfacial layer being an oxide layer, and forming a high-k dielectric layer on the intermediate interfacial layer. The high-k dielectric layer has a dielectric constant that is higher than dielectric constants of the lower interfacial layer and the intermediate interfacial layer.
    Type: Grant
    Filed: February 26, 2014
    Date of Patent: December 16, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: WeonHong Kim, Dae-Kwon Joo, Hajin Lim, Jinho Do, Kyungil Hong, Moonkyun Song
  • Publication number: 20140322546
    Abstract: A thermally oxidized heterogeneous composite substrate provided with a single crystal silicon film on a handle substrate, said heterogeneous composite substrate being obtained by, prior to a thermal oxidization treatment at a temperature exceeding 850° C., conducting an intermediate heat: treatment at 650-850° C. and then conducting the thermal oxidization treatment at a temperature exceeding 850° C. According to the present invention, a thermally oxidized heterogeneous composite substrate with a reduced number of defects after thermal oxidization can be obtained.
    Type: Application
    Filed: January 11, 2013
    Publication date: October 30, 2014
    Applicant: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Shoji Akiyama, Yuji Tobisaka, Kazutoshi Nagata
  • Patent number: 8859440
    Abstract: The method for forming wavelike coherent nanostructures by irradiating a surface of a material by a homogeneous flow of ions is disclosed. The rate of coherency is increased by applying preliminary preprocessing steps.
    Type: Grant
    Filed: April 9, 2013
    Date of Patent: October 14, 2014
    Assignee: Wostec, Inc.
    Inventors: Valery K. Smirnov, Dmitry S. Kibalov
  • Patent number: 8853098
    Abstract: Embodiments disclosed herein generally relate to an apparatus and a method for placing a substrate substantially flush against a substrate support in a processing chamber. When a large area substrate is placed onto a substrate support, the substrate may not be perfectly flush against the substrate support due to gas pockets that may be present between the substrate and the substrate support. The gas pockets can lead to uneven deposition on the substrate. Therefore, pulling the gas from between the substrate and the support may pull the substrate substantially flush against the support. During deposition, an electrostatic charge can build up and cause the substrate to stick to the substrate support. By introducing a gas between the substrate and the substrate support, the electrostatic forces may be overcome so that the substrate can be separated from the susceptor with less or no plasma support which takes extra time and gas.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: October 7, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Sam H. Kim, John M. White, Soo Young Choi, Carl A. Sorensen, Robin L. Tiner, Beom Soo Park
  • Patent number: 8841221
    Abstract: The invention relates to a device for depositing semiconductor layers, comprising a process chamber (1) arranged substantially rotationally symmetrically about a center (11), a susceptor (2), a process chamber ceiling (3), a gas inlet element (4) having gas inlet chambers (8, 9, 10) that are arranged vertically on top of each other, and a heater (27) arranged below the susceptor (2), wherein the topmost (8) of the gas inlet chambers is directly adjacent to the process chamber ceiling (3) and is connected to a feed line (14) for feeding a hydride together with a carrier gas into the process chamber (1), wherein the lowest (10) of the gas inlet chambers is directly adjacent to the susceptor (2) and is connected to a feed line (16) for feeding a hydride together with a carrier gas into the process chamber (1), wherein at least one center gas inlet chamber (9) arranged between the lowest (10) and the topmost (8) gas inlet chamber is connected to a feed line (15) for feeding an organometallic compound into the pro
    Type: Grant
    Filed: December 18, 2009
    Date of Patent: September 23, 2014
    Assignee: Aixtron SE
    Inventors: Daniel Brien, Oliver Schön
  • Publication number: 20140273517
    Abstract: Methods and apparatus for forming nitrogen-containing layers are provided herein. In some embodiments, a method includes placing a substrate having a first layer disposed thereon on a substrate support of a process chamber; heating the substrate to a first temperature; and exposing the first layer to an RF plasma formed from a process gas comprising ammonia (NH3) to transform the first layer into a nitrogen-containing layer, wherein the plasma has an ion energy of less than about 8 eV.
    Type: Application
    Filed: March 3, 2014
    Publication date: September 18, 2014
    Applicant: APPLIED MATERIALS, INC.
    Inventors: THERESA KRAMER GUARINI, WEI LIU
  • Publication number: 20140273516
    Abstract: Methods for the repair of damaged low k films are provided. In one embodiment, the method comprises providing a substrate having a low k dielectric film deposited thereon, and exposing a surface of the low k dielectric film to an activated carbon-containing precursor gas to form a conformal carbon-containing film on the surface of the low k dielectric film, wherein the carbon-containing precursor gas has at least one or more Si—N—Si linkages in the molecular structure.
    Type: Application
    Filed: February 5, 2014
    Publication date: September 18, 2014
    Inventors: Li-Qun XIA, Weifeng YE, Xiaojun ZHANG, Mei-yee SHEK, Mihaela BALSEANU, Victor NGUYEN, Derek R. WITTY
  • Publication number: 20140264774
    Abstract: The present disclosure provides a wafer that can be used in coating films. The wafer includes a front surface, a back surface opposite to the front surface, and a plurality of trenches. The back surface further includes a central region and a surrounding region. The trenches are disposed on the back surface. The spacing between any two adjacent trenches in surrounding region is less than the spacing between any two adjacent trenches in the central region.
    Type: Application
    Filed: March 6, 2014
    Publication date: September 18, 2014
    Applicant: INOTERA MEMORIES, INC.
    Inventors: ERIC LAHAUG, CHIA-MING YANG, REGAN STANLEY TSUI
  • Patent number: 8835331
    Abstract: According to one embodiment, a vapor-phase growing apparatus, includes: a reactor containing a plurality of gas introduction portions and a gas reaction portion located below the gas introduction portions; a susceptor, of which a surface is exposed in an interior space of the gas reaction portion of the reactor, for disposing and fixing a substrate on the surface thereof; a gas distributor provided between the gas introduction portions and the gas reaction portion of the reactor; a plurality of gas inlet conduits which are connected with the gas introduction portions, respectively; and a switching device, which is provided in an outside of the reactor, for switching gases to be supplied to the gas inlet conduits, respectively.
    Type: Grant
    Filed: August 29, 2011
    Date of Patent: September 16, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yuusuke Sato
  • Patent number: 8835923
    Abstract: The semiconductor wafer for a silicon-on-insulator integrated circuit comprises an insulating region located between a first semiconductor substrate intended to receive the integrated circuit and a second semiconductor substrate containing at least one buried layer comprising at least one metal silicide.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: September 16, 2014
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Pascal Fornara
  • Patent number: 8822350
    Abstract: An oxide film is formed, having a specific film thickness on a substrate by alternately repeating: forming a specific element-containing layer on the substrate by supplying a source gas containing a specific element, to the substrate housed in a processing chamber and heated to a first temperature; and changing the specific element-containing layer formed on the substrate, to an oxide layer by supplying a reactive species containing oxygen to the substrate heated to the first temperature in the processing chamber under a pressure of less than atmospheric pressure, the reactive species being generated by causing a reaction between an oxygen-containing gas and a hydrogen-containing gas in a pre-reaction chamber under a pressure of less than atmospheric pressure and heated to a second temperature higher than the first temperature.
    Type: Grant
    Filed: November 8, 2011
    Date of Patent: September 2, 2014
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Kazuhiro Yuasa, Ryuji Yamamoto
  • Patent number: 8815753
    Abstract: Methods for sealing a porous dielectric are presented including: receiving a substrate, the substrate including the porous dielectric; exposing the substrate to an organosilane, where the organosilane includes a hydrolysable group for facilitating attachment with the porous dielectric, and where the organosilane does not include an alkyl group; and forming a layer as a result of the exposing to seal the porous dielectric. In some embodiments, methods are presented where the organosilane includes: alkynyl groups, aryl groups, fluoroalkyl groups, heteroaryl groups, alcohol groups, thiol groups, amine groups, thiocarbamate groups, ester groups, ether groups, sulfide groups, and nitrile groups. In some embodiments, method further include: removing contamination from the porous dielectric and a conductive region of the substrate prior to the exposing; and removing contamination from the conductive region after the forming.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: August 26, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Tony P. Chiang, Majid Keshavarz, David E. Lazovsky
  • Patent number: 8809201
    Abstract: The present invention provides; a method for forming a metal oxide film which has both a surface irregularity and a predetermined pattern or either and has few unevenness of surface specific resistance, light transmittance and the like, and such the metal oxide film. The method for forming a metal oxide film having both a surface irregularity and a predetermined pattern or either on a substrate, wherein, the method comprises a first process in which a liquid material containing a metal salt is applied on the substrate to form a metal salt film, a second process in which a surface irregularity or a predetermined pattern is formed to the metal salt film, and a third process in which the metal salt film is converted to a metal oxide film by thermal oxidation treatment or plasma oxidation treatment.
    Type: Grant
    Filed: March 23, 2010
    Date of Patent: August 19, 2014
    Assignee: Lintec Corporation
    Inventors: Satoshi Naganawa, Takeshi Kondo
  • Patent number: 8803314
    Abstract: A method for forming an integrated circuit includes transforming at least a portion of a first substrate layer to form a conductive region within the first substrate layer. An integrated circuit device is provided proximate an outer surface of the first substrate layer. The integrated circuit device transmits or receives electrical signals through the conductive region. A second substrate layer is disposed proximate to the outer surface of the first substrate layer to enclose the integrated circuit device in a hermetic environment.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: August 12, 2014
    Assignee: Raytheon Company
    Inventors: Premjeet Chahal, Francis J. Morris
  • Publication number: 20140213068
    Abstract: A film deposition apparatus includes a separation member that extends to cover a rotation center of the turntable and two different points on a circumference of the turntable above the turntable, thereby separating the inside of the chamber into a first area and a second area; a first reaction gas supplying portion that supplies a first reaction gas toward the turntable in the first area; a second reaction gas supplying portion that supplies a second reaction gas toward the turntable in the second area; a first evacuation port that evacuates the first reaction gas and the first separation gas that converges with the first reaction gas; and a second evacuation port that evacuates the second reaction gas and the first separation gas that converges with the second reaction gas. The separation member has a bent portion that substantially fills in a gap between the turntable and the chamber.
    Type: Application
    Filed: April 3, 2014
    Publication date: July 31, 2014
    Applicant: Tokyo Electron Limited
    Inventors: Hitoshi Kato, Manabu Honma, Yasushi Takeuchi
  • Patent number: 8772146
    Abstract: A method of fabricating a semiconductor device includes forming a first gate pattern and a dummy gate pattern on a first active area and a second active area of a substrate, respectively, the first gate pattern including a first gate insulating layer and a silicon gate electrode, removing the dummy gate pattern to expose a surface of the substrate in the second active area, forming a second gate pattern including a second gate insulating layer and a metal gate electrode on the exposed surface of the substrate, the first gate insulating layer having a thickness larger than a thickness of the second gate insulating layer, and forming a gate silicide on the silicon gate electrode after forming the second gate pattern.
    Type: Grant
    Filed: August 28, 2012
    Date of Patent: July 8, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ju-Youn Kim, Hyun-Min Choi, Sung-Kee Han, Je-Don Kim
  • Patent number: 8772160
    Abstract: An object of the present invention is to provide an apparatus for successive deposition used for manufacturing a semiconductor element including an oxide semiconductor in which impurities are not included. By using the deposition apparatus capable of successive deposition of the present invention that keeps its inside in high vacuum state, and thus allows films to be deposited without being exposed to the air, the entry of impurities such as hydrogen into the oxide semiconductor layer and the layer being in contact with the oxide semiconductor layer can be prevented; as a result, a semiconductor element including a high-purity oxide semiconductor layer in which hydrogen concentration is sufficiently reduced can be manufactured. In such a semiconductor element, off-state current is low, and a semiconductor device with low power consumption can be realized.
    Type: Grant
    Filed: February 17, 2011
    Date of Patent: July 8, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Natsuko Takase
  • Patent number: 8766341
    Abstract: The embodiments disclosed herein relate to growth of magnesium-oxide on a single crystalline substrate of germanium. The embodiments further describes a method of manufacturing and crystalline structure of a FM/MgO/Ge(001) heterostructure. The embodiments further related to method of manufacturing and a crystalline structure for a high-k dielectric//MgO [100](001)//Ge[110](001) heterostructure.
    Type: Grant
    Filed: October 15, 2010
    Date of Patent: July 1, 2014
    Assignee: The Regents of the University of California
    Inventors: Wei Han, Yi Zhou, Kang-Lung Wang, Roland K. Kawakami
  • Patent number: 8753984
    Abstract: A method of forming a silicon nitride film on the surface of an object to be processed, the method including forming a seed layer functioning as a seed of the silicon nitride film on the surface of the object to be processed by using at least an aminosilane-based gas, prior to forming the silicon nitride film on the surface of the object to be processed.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: June 17, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Hiroki Murakami, Yosuke Watanabe, Kazuhide Hasebe
  • Patent number: 8728955
    Abstract: A method of depositing a film on a substrate surface includes providing a substrate in a reaction chamber; selecting a silicon-containing reactant from a precursor group consisting of di-tert-butyl diazidosilane, bis(ethylmethylamido)silane, bis(diisopropylamino)silane, bis(tert-butylhydrazido)diethylsilane, tris(dimethylamido)silylazide, tris(dimethylamido)silylamide, ethylsilicon triazide, diisopropylaminosilane, and hexakis(dimethylamido)disilazane; introducing the silicon-containing reactant in vapor phase into the reaction chamber under conditions allowing the silicon-containing reactant to adsorb onto the substrate surface; introducing a second reactant in vapor phase into the reaction chamber while the silicon-containing reactant is adsorbed on the substrate surface, and wherein the second reactant is introduced without first sweeping the silicon-containing reactant out of the reaction chamber; and exposing the substrate surface to plasma to drive a reaction between the silicon-containing reactant and
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: May 20, 2014
    Assignee: Novellus Systems, Inc.
    Inventors: Adrien LaVoie, Mark J. Saly, Daniel Moser, Rajesh Odedra, Ravi Konjolia
  • Publication number: 20140134850
    Abstract: Disclosed a method for manufacturing an oxide layer, applicable to a manufacture procedure of a field oxide layer of a CMOS transistor in the field of semiconductor manufacturing, the method includes: injecting a first gas satisfying a first predetermined condition into a processing furnace in which a first CMOS transistor semi-finished product formed with an N-well and a P-well is placed, and dry-oxidizing the first CMOS transistor semi-finished product into a second CMOS transistor semi-finished product; and injecting a second gas satisfying a second predetermined condition different from the first predetermined condition into the processing furnace, and wet-oxidizing the second CMOS transistor semi-finished product into a third CMOS transistor semi-finished product.
    Type: Application
    Filed: November 13, 2013
    Publication date: May 15, 2014
    Applicants: Founder Microelectronics International Co., Ltd., Peking University Founder Group Co., Ltd.
    Inventor: Jinyuan CHEN
  • Patent number: 8716775
    Abstract: A semiconductor integrated circuit including a large capacity reservoir capacitor to provide suitable power is provided. The semiconductor integrated circuit includes a semiconductor substrate in which a cell area and a peripheral circuit area are defined, a MOS capacitor formed on the semiconductor substrate corresponding to the peripheral circuit area, and a dummy capacitor group formed on the peripheral circuit area to overlap the MOS capacitor. One electrode of the MOS capacitor and one electrode of the dummy capacitor group are connected to each other and the other electrode of the MOS capacitor and the other electrode of the dummy capacitor group are connected to difference voltage sources from each other.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: May 6, 2014
    Assignee: SK Hynix Inc.
    Inventor: Jong Su Kim
  • Publication number: 20140120737
    Abstract: Methods and apparatus for depositing continuous thin films using plasma-activated sub-saturated atomic layer deposition are provided herein. According to various embodiments, pin-hole free continuous films may be deposited at thicknesses thinner than achievable with conventional methods. The methods and apparatus also provide high degree of thickness control, with films a per-cycle thickness tunable to as low as 0.1 ? in some embodiments. Further, the methods and apparatus may be used to provide films having improved properties, such as lower wet etch rate, in some embodiments.
    Type: Application
    Filed: October 23, 2013
    Publication date: May 1, 2014
    Applicant: Lam Research Corporation
    Inventors: Shankar Swaminathan, Hu Kang, Adrien Lavoie
  • Patent number: RE45106
    Abstract: In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a method to manufacture a semiconductor structure includes forming a cavity in a substrate. A portion of the substrate is doped, or a doped material is deposited over a portion of the substrate. At least a portion of the doped substrate or at least a portion of the doped material is converted to a dielectric material to enclose the cavity. The forming of the cavity may occur before or after the doping of the substrate or the depositing of the doped material. Other embodiments are described and claimed.
    Type: Grant
    Filed: October 11, 2012
    Date of Patent: September 2, 2014
    Assignee: Estivation Properties LLC
    Inventor: Bishnu Prasanna Gogoi