Abstract: A method for generating an optical marker for image processing/photogrammetry/motion detection using an output unit and/or a control and/or regulation unit. The optical marker is output/generated in such a way that the represented optical marker is formed by a regular pattern of angular structures and by substructures, each of which is situated completely within one of the structures. In each case, at least two directly adjacent structures, viewed in at least two mutually perpendicularly oriented directions along a projection plane of the optical marker, have different colors, and a color sequence of the plurality of structures periodically repeats along the two directions. The optical marker is formed from unique minimum recognition areas within the optical marker. The optical marker is output/generated in such a way that the substructures each include an imaging surface that corresponds to at least 15% of a maximum projection surface spanned by one of the structures.

Abstract: A method includes forming a conductive pad over an interconnect structure of a wafer, forming a capping layer over the conductive pad, forming a dielectric layer covering the capping layer, and etching the dielectric layer to form an opening in the dielectric layer. The capping layer is exposed to the opening. A wet-cleaning process is then performed on the wafer. During the wet-cleaning process, a top surface of the capping layer is exposed to a chemical solution used for performing the wet-cleaning process. The method further includes depositing a conductive diffusion barrier extending into the opening, and depositing a conductive material over the conductive diffusion barrier.

Abstract: The invention provides a structure of an emitter layer and a base layer that reduces the influence of a conduction band energy barrier generated at an interface between the emitter layer and the base layer on power amplifier characteristics for a GaAs HBT using InGaAs grown by pseudomorphic growth in the base layer. In the first invention, InGaP having a CuPt-type ordering is used in the emitter layer. In the second invention, a p-type impurity concentration of an InGaAs base layer grown by pseudomorphic growth is less in an emitter layer side portion than in a collector layer side portion.

Abstract: Disclosed herein is an SiC substrate separating method for separating an SiC substrate into at least two parts in a planar manner. The SiC substrate separating method includes an adhesive tape attaching step of attaching a transparent adhesive tape to a first surface of the SiC substrate, a support member attaching step of attaching a support member to a second, opposite surface of the SiC substrate, and a separation start point forming step of setting the focal point of a laser beam at a predetermined depth from the adhesive tape and next applying the laser beam to the adhesive tape while relatively moving the focal point and the SiC substrate to thereby form a modified layer parallel to the first surface of the SiC substrate and cracks propagating from the modified layer, thus forming a separation start point.

Abstract: A wafer processing method for dividing a wafer along a plurality of division lines to obtain a plurality of individual chips. The wafer processing method includes a filament forming step of applying a pulsed laser beam having a transmission wavelength to the wafer along each division line in the condition where the focal point of the pulsed laser beam is set inside the wafer in a subject area to be divided, thereby forming a plurality of amorphous filaments inside the wafer along each division line, and an etching step of etching the amorphous filaments formed inside the wafer along each division line by using an etching agent to thereby divide the wafer into the individual chips along the division lines.

Abstract: A method and apparatus for forming a crystalline semiconductor layer on a substrate are provided. A semiconductor layer is formed by vapor deposition. A pulsed laser melt/recrystallization process is performed to convert the semiconductor layer to a crystalline layer. Laser, or other electromagnetic radiation, pulses are formed into a pulse train and uniformly distributed over a treatment zone, and successive neighboring treatment zones are exposed to the pulse train to progressively convert the deposited material to crystalline material.

Abstract: The first flash irradiation is performed on a semiconductor wafer preheated to 500° C. to heat a front surface of the semiconductor wafer. Thereafter, the second flash irradiation is performed to reheat the front surface of the semiconductor wafer before the temperature of the front surface of the semiconductor wafer becomes equal to the temperature of a back surface of the semiconductor wafer. Thus, the second flash irradiation is performed before the temperature of the front surface of the semiconductor wafer falls. Even if less energy is consumable by the second flash irradiation, the efficiency of heating of the front surface of the semiconductor wafer resulting from each iteration of the flash irradiation is improved.

Abstract: A method and apparatus for forming a crystalline semiconductor layer on a substrate are provided. A semiconductor layer is formed by vapor deposition. A pulsed laser melt/recrystallization process is performed to convert the semiconductor layer to a crystalline layer. Laser, or other electromagnetic radiation, pulses are formed into a pulse train and uniformly distributed over a treatment zone, and successive neighboring treatment zones are exposed to the pulse train to progressively convert the deposited material to crystalline material.

Abstract: Disclosed are a method for fabricating a quantum dot. The method includes the steps of (a) preparing a compound semiconductor layer including a quantum well structure formed by sequentially stacking a first barrier layer, a well layer and a second barrier layer; (b) forming a dielectric thin film pattern including a first dielectric thin film having a thermal expansion coefficient higher than a thermal expansion coefficient of the second barrier layer and a second dielectric thin film having a thermal expansion coefficient lower than the thermal expansion coefficient of the second barrier layer on the second barrier layer; and (c) heat-treating the compound semiconductor layer formed thereon with the dielectric thin film pattern to cause an intermixing between elements of the well layer and elements of the barrier layers at a region of the compound semiconductor layer under the second dielectric thin film.

Abstract: A method for fabricating high efficiency CIGS solar cells including the deposition of Ga concentrations (Ga/(Ga+In)=0.25?0.66) from sputtering targets containing Ga concentrations between about 25 atomic % and about 66 atomic %. Further, the method includes a high temperature selenization process integrated with a high temperature anneal process that results in high efficiency.

Abstract: New methods for improving thermoelectric properties of bismuth telluride based materials are described. Constrained deformation, such as by canned/sandwich, or encapsulated, rolling and plane strain channel die compression, particularly at temperatures above 80% of the melting point of the material on an absolute temperature scale, changes the crystallographic texture and grain size to desirably increase the values of both the thermoelectric power factor and the thermoelectric figure of merit ZT for the material.

Abstract: The present disclosure relates to laser processing and a laser processing apparatus for processing materials using laser. Processing performed after loading a wafer on a work stage and a laser processing apparatus for implementing such processing, among others, are disclosed. The laser processing includes loading a wafer on a work stage; determining the number of chips formed on the wafer loaded on the work stage, performing chip defect inspection and aligning the wafer while moving the work stage; measuring a height of a surface of the wafer loaded on the work stage using a displacement sensor; monitoring output power of a processing laser using a power meter; and shifting the work stage while irradiating a laser beam on the wafer to process the wafer.

Abstract: In one example embodiment, a method includes depositing one or more thin-film layers onto a substrate. More particularly, at least one of the thin-film layers comprises at least one electropositive material and at least one of the thin-film layers comprises at least one chalcogen material suitable for forming a chalcogenide material with the electropositive material. The method further includes annealing the one or more deposited thin-film layers at an average heating rate of or exceeding 1 degree Celsius per second. The method may also include cooling the annealed one or more thin-film layers at an average cooling rate of or exceeding 0.1 degrees Celsius per second.

Abstract: A method for increasing the Seebeck coefficient of a semiconductor involves creating a reaction cell including a semiconductor in a pressure-transmitting medium, exposing the reaction cell to elevated pressure and elevated temperature for a time sufficient to increase the Seebeck coefficient of the semiconductor, and recovering the semiconductor with an increased Seebeck coefficient.

Abstract: A method, system and scan lens for use therein are provided for high-speed, laser-based, precise laser trimming at least one electrical element along a trim path. The method includes generating a pulsed laser output with a laser, the output having one or more laser pulses at a repetition rate. A fast rise/fall time, pulse-shaped q-switched laser or an ultra-fast laser may be used. Beam shaping optics may be used to generate a flat-top beam profile. Each laser pulse has a pulse energy, a laser wavelength within a range of laser wavelengths, and a pulse duration. The wavelength is short enough to produce desired short-wavelength benefits of small spot size, tight tolerance, high absorption and reduced or eliminated heat-affected zone (HAZ) along the trim path, but not so short so as to cause microcracking. In this way, resistance drift after the trimming process is reduced.

Abstract: A method and apparatus for forming a crystalline semiconductor layer on a substrate are provided. A semiconductor layer is formed by vapor deposition. A pulsed laser melt/recrystallization process is performed to convert the semiconductor layer to a crystalline layer. Laser, or other electromagnetic radiation, pulses are formed into a pulse train and uniformly distributed over a treatment zone, and successive neighboring treatment zones are exposed to the pulse train to progressively convert the deposited material to crystalline material.

Abstract: Structures include a tunneling device disposed over first and second lattice-mismatched semiconductor materials. Process embodiments include forming tunneling devices over lattice-mismatched materials.

Abstract: Stability of an underlying dielectric diffusion barrier during deposition and ultraviolet (UV) processing of an overlying dielectric layer is critical for successful integration. UV-resistant diffusion barrier layers are formed by depositing the layer in a hydrogen-starved environment. Diffusion barrier layers can be made more resistant to UV radiation by thermal, plasma, or UV treatment during or after deposition. Lowering the modulus of the diffusion barrier layer can also improve the resistance to UV radiation.

Abstract: In one example embodiment, a method includes depositing one or more thin-film layers onto a substrate. More particularly, at least one of the thin-film layers comprises at least one electropositive material and at least one of the thin-film layers comprises at least one chalcogen material suitable for forming a chalcogenide material with the electropositive material. The method further includes annealing the one or more deposited thin-film layers at an average heating rate of or exceeding 1 degree Celsius per second. The method may also include cooling the annealed one or more thin-film layers at an average cooling rate of or exceeding 0.1 degrees Celsius per second.

Abstract: A laser processing method is provided, which, when cutting a substrate formed with a multilayer part including a plurality of functional devices, makes it possible to cut the multilayer part with a high precision in particular. In a state where a protective tape 22 is attached to the front face 16a of a multilayer part 16, a substrate 4 is irradiated with laser light L while using its rear face 4b as a laser light entrance surface, so as to form a modified region 7 within the substrate 4 along a line to cut, thereby generating a fracture 24 reaching the front face 4a of the substrate 4 from a front-side end part 7a of the modified region 7. Attaching an expandable tape to the rear face 4b of the substrate 4 and expanding it in the state where such a fracture 24 is generated can cut not only the substrate 4 but also the multilayer part 16 on the line to cut, i.e., interlayer insulating films 17a, 17b, with a favorable precision along the line to cut.

Abstract: Provided are methods of stabilizing an underlying dielectric diffusion barrier during deposition and ultraviolet (UV) processing of an overlying dielectric layer. Methods include modulating the optical properties reduces the effects of UV radiation on the dielectric diffusion barrier layer. The dielectric diffusion barrier can be made to absorb less UV radiation. A dielectric layer with UV absorbing properties may also be added on top of the diffusion barrier layer so less UV is transmitted. Both methods result in reduced interaction between UV radiation and the dielectric diffusion barrier.

Abstract: Apparatus and methods that minimize surface defect development in silicon wafers during thermal processing at relatively high temperatures at which silicon wafers are annealed and at less extreme temperature, or for other purposes. The apparatus and methods have utility to horizontally-disposed furnaces for silicon wafers and to vertically-oriented furnaces in which larger wafers can be thermally processed. A selectively-sealable process tube encloses silicon wafers during heating of the silicon wafers to a predetermined temperature, and a heating atmosphere supply system induces through the process tube a positive flow of a process gas, such as hydrogen or argon, that is non-reactive with solid silicon at the predetermined temperature. A process tube outlet vents gas from the process tube, and an impurity sensor in the process tube outlet detects oxygen and moisture in the vented gas to verify the purity of the atmosphere surrounding the wafers during thermal processing.

Abstract: An array substrate includes a base substrate, a switching element, and a pixel electrode. The switching element is on the base substrate. The switching element includes a poly silicon pattern having at least one block. Grains are formed in each of the at least one block that are extended in a plurality of directions. The pixel electrode is electrically connected to the switching element. Therefore, current mobility and design margin of the switching element are improved.

Abstract: Provided are a biosensor with a silicon nanowire and a method of manufacturing the same, and more particularly, a biosensor with a silicon nanowire including a defect region formed by irradiation of an electron beam, and a method of manufacturing the same. The biosensor includes: a silicon substrate; a source region disposed on the silicon substrate; a drain region disposed on the silicon substrate; and a silicon nanowire disposed on the source region and the drain region, and having a defect region formed by irradiation of an electron beam. Therefore, by irradiating a certain region of a high-concentration doped silicon nanowire with an electron beam to lower electron mobility in the certain region, it is possible to maintain a low contact resistance between the silicon nanowire and a metal electrode and to lower operation current of a biomaterial detection part, thereby improving sensitivity of the biosensor.

Abstract: An impurity-activating thermal process is performed after a target is subjected to an impurity introduction step. In this thermal process, while a spike RTA process including a holding period for holding a temperature at a predetermined temperature is performed, at least one iteration of millisecond annealing at a temperature higher than the predetermined temperature is performed during the holding period of the spike RTA process.

Abstract: A thin film transistor disposed on a substrate is provided. The thin film transistor includes a gate, a gate insulating layer, a silicon-rich channel layer, a source, and a drain. The gate is disposed on the substrate. The gate insulator is disposed over the gate. The silicon-rich channel layer is disposed above the gate, wherein the material of the silicon-rich channel layer is selected from a group consisting of silicon-rich silicon oxide (Si-rich SiOx), silicon-rich silicon nitride (Si-rich SiNx), silicon-rich silicon oxynitride (Si-rich SiOxNy), silicon-rich silicon carbide (Si-rich SiC) and silicon-rich silicon oxycarbide (Si-rich SiOC). The content (concentration) of silicon of the silicon-rich channel layer within a film depth between 10 nm to 170 nm ranges from about 1E23 atoms/cm3 to about 4E23 atoms/cm3. The source and the drain are connected with the silicon-rich channel layer.

Abstract: A laser processing method is provided, which, when cutting an object to be processed comprising a substrate and a multilayer part, formed on a front face of the substrate, including a functional device, can cut the multilayer part with a high precision in particular. In a state where a protective tape 22 is attached to the front face 16a of a multilayer part 16, a substrate 4 is irradiated with laser light L while using its rear face 4b as a laser light entrance surface, so as to form a modified region 7 within the substrate 4 along a line to cut, thereby generating a fracture 24 reaching the front face 4a of the substrate 4 from a front-side end part 7a of the modified region 7. Attaching an expandable tape to the rear face 4b of the substrate 4 and expanding it in the state where such a fracture 24 is generated can cut not only the substrate 4 but also the multilayer part 16 on the line to cut, i.e., interlayer insulating films 17a, 17b, with a favorable precision along the line to cut.

Abstract: A magnetic memory device including a Magnetic Tunnel Junction (MTJ) device comprises a substrate and Front End of Line (FEOL) circuitry. A Via level (VA) InterLayer Dielectric (ILD) layer, a bottom conductor layer, and an MTJ device formed over the top surface of the VA ILD layer are formed over a portion of the substrate. An alignment region including alignment marks extends through the bottom conductor layer and extends down into the device below the top surface of the VA ILD layers is juxtaposed with the MJT device.

Abstract: Crystalline silicon particles of nanometer order usable as a semiconductor element are provided by a method for producing SiOx particles, comprising irradiating SiOx (X is 0.5 or more and less than 2.0) particles each including therein an amorphous silicon particle having a particle diameter of 0.5 to 5 nm with light, and preferably a laser beam, to produce SiOx (X is 0.5 or more and less than 2.0) particles each including therein a crystalline silicon particle having a particle diameter of 1 to 10 nm.

Abstract: Methods, systems, and apparatuses for annealing semiconductor nanowires and for fabricating electrical devices are provided. Nanowires are deposited on a substrate. A plurality of electrodes is formed. The nanowires are in electrical contact with the plurality of electrodes. The nanowires are doped. A polarized laser beam is applied to the nanowires to anneal at least a portion of the nanowires. The nanowires may be aligned substantially parallel to an axis. The laser beam may be polarized in various ways to modify absorption of radiation of the applied laser beam by the nanowires. For example, the laser beam may be polarized in a direction substantially parallel to the axis or substantially perpendicular to the axis to enable different nanowire absorption profiles.

Abstract: A method of manufacturing a nitride semiconductor device includes the steps of; forming a stripping layer including In on a substrate; forming a nitride semiconductor layer on the stripping layer; causing a decomposition of the stripping layer by increasing a temperature of the stripping layer; irradiating the stripping layer with laser light; and separating the nitride semiconductor layer from the substrate.

Abstract: A laser processing method is provided, which, even when a substrate formed with a laminate part including a plurality of functional devices is thick, can cut the substrate and laminate part with a high precision. This laser processing method irradiates a substrate 4 with laser light L while using a rear face 21 as a laser light entrance surface and locating a light-converging point P within the substrate 4, so as to form modified regions 71, 72, 73 within the substrate 4. Here, the quality modified region 71 is formed at a position where the distance between the front face 3 of the substrate 4 and the end part of the quality modified region 71 on the front face side is 5 ?m to 15 ?m. When the quality modified region 71 is formed at such a position, a laminate part 16 (constituted by interlayer insulating films 17a, 17b here) formed on the front face 3 of the substrate 4 is also cut along a line to cut with a high precision together with the substrate 4.

Abstract: A laser beam machining method and a laser beam machining device capable of cutting a work without producing a fusing and a cracking out of a predetermined cutting line on the surface of the work, wherein a pulse laser beam is radiated on the predetermined cut line on the surface of the work under the conditions causing a multiple photon absorption and with a condensed point aligned to the inside of the work, and a modified area is formed inside the work along the predetermined determined cut line by moving the condensed point along the predetermined cut line, whereby the work can be cut with a rather small force by cracking the work along the predetermined cut line starting from the modified area and, because the pulse laser beam radiated is not almost absorbed onto the surface of the work, the surface is not fused even if the modified area is formed.

Abstract: According to one embodiment of the invention, a method of modifying a mechanical, physical and/or electrical property of a dielectric layer comprises exposing the dielectric layer to a first dose of electron beam radiation at a first energy level; and thereafter, exposing the dielectric layer to a second dose of electron beam radiation at a second energy level that is different from the first energy level.

Abstract: A laser activated phase change device for use in an integrated circuit comprises a chalcogenide fuse configured to connect a first patterned metal line and a second patterned metal line and positioned between an inter layer dielectric and an over fuse dielectric. The fuse interconnects active semiconductor elements manufactured on a substrate. A method for activating the laser activated phase change device includes selecting a laser condition of a laser based on characteristics of the fuse and programming a phase-change of the fuse with the laser by direct photon absorption until a threshold transition temperature is met.

Abstract: A linear laser light which has an energy and is to be scanned is irradiated to a semiconductor device formed on a substrate, and then the substrate is rotated to irradiate to the semiconductor device a linear laser light which has a higher energy than that of the irradiated linear laser light and is to be scanned. Also, in a semiconductor device having an analog circuit region and a remaining circuit region wherein the analog circuit region is smaller than the remaining circuit region, a linear laser light having an irradiation area is irradiated to the analog circuit region without moving the irradiation area so as not to overlap the laser lights by scanning. On the other hand, the linear laser light to be scanned is irradiated to the remaining circuit region.

Abstract: Objects of the present invention is to reduce a number of scanning a linear laser, to shorten the amount of time for laser annealing, and to reduce a manufacturing process, a manufacturing time, and manufacturing cost of a semiconductor device. In this invention, a gas at high temperature is locally blown so as to overlap at an irradiation surface of linear laser light. The linear laser light can be obtained by injecting laser light radiated from a laser oscillator into a lens. The gas at high temperature can be obtained by heating a gas which is compressed using a gas compressor, by a nozzle type heater. The heated has is sprayed so as to overlap with the irradiation surface of the linear laser light.

Abstract: An embodiment of a multilayer wafer according to the invention includes a base substrate, a first layer associated with the base substrate, and a second layer on the first layer on side opposite from the base substrate in an axial direction and having a lateral edge. The first layer includes a ridge that protrudes axially and is disposed laterally adjacent the second layer measured in a direction normal to the axial direction for protecting the lateral edge. This ridge can surround portion the lateral edge in an axial cross-section for preventing edge falls. Also, the ridge can have an axial height greater than the axial thickness of the second layer. In one embodiment, the second layer includes an oxydizable semiconductor and the first layer includes an oxidized insulator.

Abstract: A laser splitting method for splitting off a segment from an object to be split using a laser beam, includes a surface processing step of processing the object by forming a linear recessed portion in a surface of the object, the linear recessed portion being effective to cause a stress concentration at the surface of the object; an internal processed-region forming step of forming an internal processed-regions at a depth of the object in a line along which a laser beam scans the surface of the object by a relative motion therebetween, the laser beam being converged adjacent the depth, wherein the thus formed internal processed-regions extend in a direction substantially perpendicular to the surface of the object; and an external force applying step of applying an external force to the object to form cracks between the recessed portion and the internal processed-regions.

Abstract: A method of controlling the degree of IFVEI for post-growth tuning of an optical bandgap of a semiconductor heterostructure. The resultant layer structure may contain a semi-conductor heterostructure with one or more regions with selectively modified bandgap. According to one aspect of the invention, a metal interlayer is deposited between the heterostructure and a dielectric layer such as silica. According to another aspect of the invention, an oxidized surface is provided between a dielectric layer and the heterostructure. The presence of the oxide layer improves stability and reproducibility in the post-annealing process. In a further aspect, the oxide layer may be provided between the interlayer and the heterostructure. In one embodiment of the invention, a photoresist mask with a specific pattern is deposited on the surface of the heterostructure so that the interlayer is deposited in an unmasked region whereon post-growth tuning results.

Abstract: A method of reducing propagation of threading dislocations into active areas of an optoelectronic device having a III–V material system includes growing a metamorphic buffer region in the presence of an isoelectronic surfactant. A first buffer layer may be lattice matched to an adjacent substrate and a second buffer layer may be lattice matched to device layers disposed upon the second buffer layer. Moreover, multiple metamorphic buffer layers fabricated in this manner may be used in a single given device allowing multiple layers to have their band gaps and lattice constants independently selected from those of the rest of the device.

Abstract: The method for forming a flowable dielectric layer without micro-voids therein in a semiconductor device is employed to utilize a ultra-violet (UV) bake process. The method includes steps of: forming a plurality of patterns on a semiconductor substrate, wherein narrow and deep gaps are formed therebetween; forming a flowable dielectric layer so as to fill the gaps between the patterns; carrying out a baking process for densifying the flowable dielectric layer from a bottom face thereof; forming a plurality of contact holes by selectively etching the flowable dielectric layer; carrying out a pre-cleaning process in order to remove native oxide and impurity substances on the contact holes; and forming a plurality of contact plugs by filling a conductive material into the contact holes.

Abstract: A laser beam machining method and a laser beam machining device capable of cutting a work without producing a fusing and a cracking out of a predetermined cutting line on the surface of the work, wherein a pulse laser beam is radiated on the predetermined cut line on the surface of the work under the conditions causing a multiple photon absorption and with a condensed point aligned to the inside of the work, and a modified area is formed inside the work along the predetermined determined cut line by moving the condensed point along the predetermined cut line, whereby the work can be cut with a rather small force by cracking the work along the predetermined cut line starting from the modified area and, because the pulse laser beam radiated is not almost absorbed onto the surface of the work, the surface is not fused even if the modified area is formed.

Abstract: A nitride compound semiconductor light-emitting device having a stack of layers including an active layer for a light emitting device and a method of manufacturing the device is disclosed. The method includes the steps of growing a first layer on a substrate at a first temperature to obtain an incomplete crystalline structure including both indium and aluminum and having the composition expressed as InXAlYGa1-X-YN(0?X?1, 0?Y?1). The method grows a cap layer on the first layer to cover the first layer, with growth of the cap layer proceeding at a second temperature substantially equal to or below the first temperature. The first layer is heat treated at a third temperature above the first temperature to cause the incomplete crystalline structure to crystallize and to create areas of differing compositions, thus changing the first layer to an active layer. The material of the cap layer is selected to be heat stable during the heat-treating step.

Abstract: A method for preparing a semiconductor die for analysis comprises providing a semiconductor die having a connector on one side and an opposite, backside surface to be analyzed, providing a polishing pad for polishing the backside surface of a semiconductor die, providing a rotatable spindle for securing the polishing pad, and providing a constant force actuator on the spindle, the constant force actuator being adapted to provide constant force between the polishing pad and the backside surface of the die. The method then includes contacting the backside die surface with the polishing pad, rotating the spindle and polishing pad, and polishing the backside surface of the die while maintaining the substantially constant force of the polishing pad on the die backside surface with the constant force actuator.

Abstract: A method of fabricating relaxed SiGe buffer layers with low threading dislocation densities on silicon-on-insulator (SOI) substrates is provided. The relaxed SiGe buffer layers are fabricated by the epitaxial deposition of a defect-free Stranski-Krastanov Ge or SiGe islands on a surface of the SOI substrate; the capping and planarizing of the islands with a Si or Si-rich SiGe layer, and the annealing of the structure at elevated temperatures until intermixing and thereby formation of a relaxed SiGe layer on the insulating layer (i.e., buried oxide layer) of the initial SOI wafer is achieved. The present invention is also directed to semiconductor structures, devices and integrated circuits which include at least the relaxed SiGe buffer layer mentioned above.

Abstract: To provide a laser apparatus and a laser annealing method with which a crystalline semiconductor film with a larger crystal grain size is obtained and which are low in their running cost. A solid state laser easy to maintenance and high in durability is used as a laser, and laser light emitted therefrom is linearized to increase the throughput and to reduce the production cost as a whole. Further, both the front side and the back side of an amorphous semiconductor film is irradiated with such laser light to obtain the crystalline semiconductor film with a larger crystal grain size.

Abstract: A first semiconductor layer is formed on a mother substrate, and the mother substrate is irradiated with irradiation light from a surface opposite to the first semiconductor layer, so that a thermally decomposed layer formed by thermally decomposing the first semiconductor layer between the first semiconductor layer and the mother substrate. Then, a second semiconductor layer including an active layer is formed on the first semiconductor layer in which the thermally decomposed layer is formed.

Abstract: An apparatus for rapid thermal processing is described and includes a cylindrical lamp array structure (13) surrounding a cylindrical process tube (16). The cylindrical process tube (16) has a lengthwise central axis (22). The cylindrical lamp array structure (13) includes heat sources or lamps (26). The lamps (26) are positioned with respect to the cylindrical process tube (16) so that the sides of the lamps (26) focus light energy in the direction of the lengthwise central axis (22). Substrates (12) are oriented within the cylindrical process tube (16) so that the major surfaces (14) of the substrates (12) are substantially normal to the lengthwise central axis (22). In an alternative embodiment, a magnetic field source (19) is included for processing storage devices such as non-volatile memory devices.

Abstract: To provide a laser apparatus and a laser annealing method with which a crystalline semiconductor film with a larger crystal grain size is obtained and which are low in their running cost. A solid state laser easy to maintenance and high in durability is used as a laser, and laser light emitted therefrom is linearized to increase the throughput and to reduce the production cost as a whole. Further, both the front side and the back side of an amorphous semiconductor film is irradiated with such laser light to obtain the crystalline semiconductor film with a larger crystal grain size.