Compound Semiconductor Patents (Class 438/796)
  • Patent number: 10636677
    Abstract: Embodiments of the disclosure relate to an apparatus and method for annealing semiconductor substrates. In one embodiment, a batch processing chamber is disclosed. The batch processing chamber includes a chamber body enclosing a processing region, a gas panel configured to provide a processing fluid into the processing region, a condenser fluidly connected to the processing region and a temperature-controlled fluid circuit configured to maintain the processing fluid at a temperature above a condensation point of the processing fluid. The processing region is configured to retain a plurality of substrates during processing. The condenser is configured to condense the processing fluid into a liquid phase.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: April 28, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Jean Delmas, Steven Verhaverbeke, Kurtis Leschkies
  • Patent number: 10381444
    Abstract: To improve the performance of a semiconductor device, there is provided with a manufacturing method of a semiconductor device including a step of removing an oxide film formed on the surface of a silicon carbide substrate including the inner wall of a trench, before forming the hydrogen annealing.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: August 13, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Youichi Yamamoto
  • Patent number: 9905432
    Abstract: The method for manufacturing comprises an ion implantation process of implanting a p-type impurity into a semiconductor layer mainly made of a group III nitride by ion implantation; a first heating process of heating the semiconductor layer at a first temperature in a first atmospheric gas including ammonia (NH3) after the ion implantation process; and a second heating process of heating the semiconductor layer, after the first heating process, at a second temperature that is lower than the first temperature in a second atmospheric gas including oxygen (O2).
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: February 27, 2018
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Takaki Niwa, Tohru Oka, Masayoshi Kosaki, Takahiro Fujii, Yukihisa Ueno
  • Patent number: 9647151
    Abstract: The invention relates to manufacturing a I-III-VI compound in the form of a thin film for use in photovoltaics, including the steps of: a) electrodepositing a thin-film structure, consisting of I and/or III elements, onto the surface of an electrode that forms a substrate (SUB); and b) incorporating at least one VI element into the structure so as to obtain the I-III-VI compound. According to the invention, the electrodeposition step comprises checking that the uniformity of the thickness of the thin film varies by no more than 3% over the entire surface of the substrate receiving the deposition.
    Type: Grant
    Filed: October 10, 2011
    Date of Patent: May 9, 2017
    Assignee: NEXCIS
    Inventors: Pierre-Philippe Grand, Salvador Jaime, Philippe De Gasquet, Hariklia Deligianni, Lubomyr T. Romankiw, Raman Vaidyanathan, Qiang Huang, Shafaat Ahmed
  • Patent number: 9419170
    Abstract: Methods for treating a semiconductor material are provided. According to an aspect of the invention, the method includes annealing the semiconductor material in the presence of a compound that includes a first element and a second element. The first element provides an overpressure to achieve a desired stoichiometry of the semiconductor material, and the second element provides a dopant to the semiconductor material.
    Type: Grant
    Filed: February 5, 2015
    Date of Patent: August 16, 2016
    Assignee: Alliance for Sustainable Energy, LLC
    Inventors: David Albin, James Burst, Wyatt Metzger, Joel Duenow, Stuart Farrell, Eric Colegrove
  • Patent number: 9157153
    Abstract: In one embodiment, a method includes depositing a chalcogenide precursor layer onto a substrate, introducing a cover into proximity with the precursor layer, and annealing the precursor layer in proximity with of the cover, where the annealing is performed in a constrained volume, and where the presence of the cover reduces decomposition of volatile species from the precursor layer during annealing.
    Type: Grant
    Filed: May 9, 2012
    Date of Patent: October 13, 2015
    Assignee: ZETTA RESEARCH AND DEVELOPMENT LLC—AQT SERIES
    Inventors: Mariana Rodica Munteanu, Amith Kumar Murali, Brian Josef Bartholomeusz, Vardaan Chawla
  • Patent number: 9048093
    Abstract: A single crystal substrate made of silicon carbide and a first support substrate having a size greater than a size of each of the single crystal substrates are prepared. The single crystal substrate is bonded onto the first support substrate. Process on the single crystal substrate bonded to the first support substrate is performed. The first support substrate is removed. The single crystal substrate is subjected to heat treatment. The single crystal substrate is bonded onto a second support substrate having a size greater than the size of the single crystal substrate. Process on the single crystal substrate bonded to the second support substrate is performed.
    Type: Grant
    Filed: February 14, 2013
    Date of Patent: June 2, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Taku Horii
  • Patent number: 8962379
    Abstract: A CIGS film production method is provided which ensures that a CIGS film having a higher conversion efficiency can be produced at lower costs at higher reproducibility even for production of a large-area device. A CIGS solar cell production method is also provided for producing a CIGS solar cell including the CIGS film. The CIGS film production method includes: a stacking step of stacking a layer (A) containing indium, gallium and selenium and a layer (B) containing copper and selenium in a solid phase in this order over a substrate; and a heating step of heating a stacked structure including the layer (A) and the layer (B) to melt a compound of copper and selenium of the layer (B) into a liquid phase to thereby diffuse copper from the layer (B) into the layer (A) to permit crystal growth to provide a CIGS film.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: February 24, 2015
    Assignee: Nitto Denko Corporation
    Inventors: Hiroto Nishii, Shigenori Morita, Seiki Teraji, Kazuhito Hosokawa, Takashi Minemoto
  • Patent number: 8962496
    Abstract: The process for smoothing a rough surface of a first substrate made of a semiconductor alloy based on at least two elements chosen from Ga, As, Al, In, P and N is implemented by placing a second substrate facing the first substrate so that the rough surface is placed facing a surface of the second substrate. The first and second substrates are separated by a distance d of at least 10 ?m, the facing portions of the two substrates defining a confinement space. The first substrate is then heated so as to partially desorb one of the elements of said alloy and to reach the saturated vapor pressure of this element in the confinement space and to obtain a surface atom mobility that is sufficient to reduce the roughness of the rough surface.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: February 24, 2015
    Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventors: Thomas Jouanneau, Yann Bogumilowicz
  • Patent number: 8946098
    Abstract: A device is intended for a laser lift-off method to sever at least one layer from a carrier. The device includes a laser that generates pulsed laser radiation and at least one beam splitter. The laser radiation is divided into at least two partial beams by the at least one beam splitter. The partial beams are superimposed in an irradiation plane, the irradiation plane being provided such that a major side of the carrier remote from the layer is arranged therein. At the irradiation plane, an angle (?) between the at least two partial beams is at least 1.0°.
    Type: Grant
    Filed: October 21, 2010
    Date of Patent: February 3, 2015
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventor: Ralph Wagner
  • Patent number: 8937023
    Abstract: A method includes forming an insulating film over a substrate by introducing a cyclic siloxane compound having a cyclic siloxane as a skeleton and having at least one volatile hydrocarbon group bonded to a side chain, and a silicon-containing compound into a plasma, and converting the insulating film to a porous insulating film by adding energy to the insulating film. The silicon-containing compound is decomposed using less energy as compared with the skeleton of the cyclic siloxane compound, the volatile hydrocarbon group, and the bond between the cyclic siloxane compound and the volatile hydrocarbon group.
    Type: Grant
    Filed: February 1, 2012
    Date of Patent: January 20, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Fuminori Ito, Yoshihiro Hayashi
  • Patent number: 8936963
    Abstract: If an oxide semiconductor layer is crystallized by heat treatment without being covered with an inorganic insulating film, surface unevenness and the like are formed due to the crystallization, which may cause variation in electrical characteristics. Steps are performed in the following order: a second insulating film is formed on an oxide semiconductor layer over a substrate and then heat treatment is performed, instead of performing heat treatment during a period immediately after formation of the oxide semiconductor layer and immediately before formation of an inorganic insulating film including silicon oxide on the oxide semiconductor layer. The density of hydrogen included in the inorganic insulating film including silicon oxide is 5×1020/cm3 or more, and the density of nitrogen is 1×1019/cm3 or more.
    Type: Grant
    Filed: March 9, 2010
    Date of Patent: January 20, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiroki Ohara, Toshinari Sasaki
  • Patent number: 8932944
    Abstract: In the manufacture of a silicon carbide semiconductor device having a termination region being a JTE region or FLR, the margin of the amount of etching for removing a damage layer formed in the surface of the termination region is enlarged. A silicon carbide semiconductor device has a termination region being a JTE (Junction Termination Extension) region or an FLR (Field Limiting Ring) at a termination of the semiconductor elements. The termination region is formed by one step of ion implantation in which the kind of impurity and the implant energy are fixed. In the impurity concentration profile of the termination region in the depth direction, the concentration peak in the shallowest position is in a position deeper than 0.35 ?m from the surface, and the concentration in the surface portion is not more than one-tenth of the shallowest concentration peak.
    Type: Grant
    Filed: July 24, 2013
    Date of Patent: January 13, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yoichiro Tarui, Naoto Kaguchi, Takuyo Nakamura
  • Publication number: 20140370716
    Abstract: There is disclosed a method of preserving the integrity of a growth substrate in a epitaxial lift-off method, the method comprising providing a structure comprising a growth substrate, one or more protective layers, a sacrificial layer, and at least one epilayer, wherein the sacrificial layer and the one or more protective layers are positioned between the growth substrate and the at least one epilayer; releasing the at least one epilayer by etching the sacrificial layer with an etchant; and heat treating the growth substrate and/or at least one of the protective layers.
    Type: Application
    Filed: February 7, 2013
    Publication date: December 18, 2014
    Inventors: Kyusang Lee, Jeramy Zimmerman, Stephen R. Forrest
  • Publication number: 20140360566
    Abstract: The present invention provides methods of making photovoltaic devices incorporating improved pnictide semiconductor films. In particular, the principles of the present invention are used to improve the surface quality of pnictide films. Photovoltaic devices incorporating these films demonstrate improved electronic performance. As an overview, the present invention involves a methodology that metalizes the pnictide film, anneals the metalized film under conditions that tend to form an alloy between the pnictide film and the alloy, and then removes the excess metal and at least a portion of the alloy. In one mode of practice, the pnictide semiconductor is Zinc phosphide and the metal is Magnesium.
    Type: Application
    Filed: January 30, 2013
    Publication date: December 11, 2014
    Inventors: Gregory M. Kimball, Marty W. DeGroot, Harry A. Atwater, Nathan S. Lewis, Rebekah K. Feist, Jeffrey P. Bosco
  • Publication number: 20140315394
    Abstract: The process for smoothing a rough surface of a first substrate made of a semiconductor alloy based on at least two elements chosen from Ga, As, Al, In, P and N is implemented by placing a second substrate facing the first substrate so that the rough surface is placed facing a surface of the second substrate. The first and second substrates are separated by a distance d of at least 10 ?m, the facing portions of the two substrates defining a confinement space. The first substrate is then heated so as to partially desorb one of the elements of said alloy and to reach the saturated vapor pressure of this element in the confinement space and to obtain a surface atom mobility that is sufficient to reduce the roughness of the rough surface.
    Type: Application
    Filed: October 26, 2012
    Publication date: October 23, 2014
    Applicant: COMMISSARIAT Á L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Thomas Jouanneau, Yann Bogumilowicz
  • Patent number: 8859443
    Abstract: The first flash irradiation is performed on a semiconductor wafer preheated to 500° C. to heat a front surface of the semiconductor wafer. Thereafter, the second flash irradiation is performed to reheat the front surface of the semiconductor wafer before the temperature of the front surface of the semiconductor wafer becomes equal to the temperature of a back surface of the semiconductor wafer. Thus, the second flash irradiation is performed before the temperature of the front surface of the semiconductor wafer falls. Even if less energy is consumable by the second flash irradiation, the efficiency of heating of the front surface of the semiconductor wafer resulting from each iteration of the flash irradiation is improved.
    Type: Grant
    Filed: February 6, 2012
    Date of Patent: October 14, 2014
    Assignee: Dainippon Screen Mfg. Co., Ltd.
    Inventor: Kenichi Yokouchi
  • Patent number: 8847280
    Abstract: An improved insulated gate field effect device is obtained by providing a substrate desirably comprising a III-V semiconductor, having a further semiconductor layer on the substrate adapted to contain the channel of the device between spaced apart source-drain electrodes formed on the semiconductor layer. A dielectric layer is formed on the semiconductor layer. A sealing layer is formed on the dielectric layer and exposed to an oxygen plasma. A gate electrode is formed on the dielectric layer between the source-drain electrodes. The dielectric layer preferably comprises gallium-oxide and/or gadolinium-gallium oxide, and the oxygen plasma is preferably an inductively coupled plasma. A further sealing layer of, for example, silicon nitride is desirably provided above the sealing layer. Surface states and gate dielectric traps that otherwise adversely affect leakage and channel sheet resistance are much reduced.
    Type: Grant
    Filed: November 10, 2011
    Date of Patent: September 30, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jonathan K. Abrokwah, Ravindranath Droopad, Matthias Passlack
  • Patent number: 8784699
    Abstract: An oxide including indium (In), gallium (Ga) and zinc (Zn), wherein diffraction peaks are observed at positions corresponding to incident angles (2?) of 7.0° to 8.4°, 30.6° to 32.0°, 33.8° to 35.8°, 53.5° to 56.5° and 56.5° to 59.5° in an X-ray diffraction measurement (CuK? rays), and one of diffraction peaks observed at positions corresponding to incident angles (2?) of 30.6° to 32.0° and 33.8° to 35.8° is a main peak and the other is a sub peak.
    Type: Grant
    Filed: November 17, 2010
    Date of Patent: July 22, 2014
    Assignee: Idemitsu Kosan Co., Ltd.
    Inventors: Koki Yano, Masayuki Itose, Hirokazu Kawashima
  • Patent number: 8765494
    Abstract: An organic EL device (OELD) having a defective portion is irradiated with a laser beam; first luminance of light emitted from the OELD is measured after the OELD is irradiated with the laser beam, while supplying, to the OELD, a first amount of current with which the OELD in a normal state would emit light having luminance corresponding to a first grayscale level smaller than a reference level; the OELD is re-irradiated with the laser beam when the first luminance is smaller than a threshold; and second luminance of light emitted from the OELD is measured when the first luminance is greater than or equal to the threshold, while supplying, to the OELD, a second amount of current with which the OELD in the normal state would emit light having luminance corresponding to a second grayscale level greater than or equal to the reference level.
    Type: Grant
    Filed: December 4, 2012
    Date of Patent: July 1, 2014
    Assignee: Panasonic Corporation
    Inventors: Tomomi Hiraoka, Yasuo Segawa
  • Patent number: 8764903
    Abstract: The present invention in one preferred embodiment discloses a new design of HVPE reactor, which can grow gallium nitride for more than one day without interruption. To avoid clogging in the exhaust system, a second reactor chamber is added after a main reactor where GaN is produced. The second reactor chamber may be configured to enhance ammonium chloride formation, and the powder may be collected efficiently in it. To avoid ammonium chloride formation in the main reactor, the connection between the main reactor and the second reaction chamber can be maintained at elevated temperature. In addition, the second reactor chamber may have two or more exhaust lines. If one exhaust line becomes clogged with powder, the valve for an alternative exhaust line may open and the valve for the clogged line may be closed to avoid overpressuring the system. The quartz-made main reactor may have e.g. a pyrolytic boron nitride liner to collect polycrystalline gallium nitride efficiently.
    Type: Grant
    Filed: May 5, 2010
    Date of Patent: July 1, 2014
    Assignee: Sixpoint Materials, Inc.
    Inventors: Tadao Hashimoto, Edward Letts
  • Publication number: 20140162443
    Abstract: A method for producing a semiconductor device includes: an arranging process of arranging a plurality of silicon carbide wafers having opposed first and surfaces so that the first surface and the second surface of adjacent silicon carbide wafers face each other and are separated in parallel; and a heat treatment process of heating the arranged plurality of silicon carbide wafers so that the first surface of each silicon carbide wafer becomes higher in temperature than the second surface thereof, and, in the adjacent silicon carbide wafers, the second surface of one silicon carbide wafer becomes higher in temperature than the first surface of the other silicon carbide wafer that faces the second surface.
    Type: Application
    Filed: November 26, 2013
    Publication date: June 12, 2014
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Masatoshi TSUJIMURA, Hirokazu FUJIWARA, Tomoo MORINO, Narumasa SOEJIMA
  • Patent number: 8729561
    Abstract: In one implementation, a method of forming a P type III-nitride material includes forming a getter material over a III-nitride material, the III-nitride material having residual complexes formed from P type dopants and carrier gas impurities. The method further includes gettering at least some of the carrier gas impurities, from at least some of the residual complexes, into the getter material to form the P type III-nitride material. In some implementations, the carrier gas impurities include hydrogen and the getter material includes at least partially titanium. An overlying material can be formed on the getter material prior to gettering at least some of the carrier gas impurities.
    Type: Grant
    Filed: April 24, 2012
    Date of Patent: May 20, 2014
    Assignee: International Rectifier Corporation
    Inventor: Michael A. Briere
  • Publication number: 20140113459
    Abstract: A method for in-situ dry cleaning of a Ge containing semiconductor surface, other than SiGe. The method is conducted in a vacuum chamber. An oxygen monolayer(s) is formed and promotes removal of essentially all carbon from the surface, and serves to both clean and functionalize the surface. The Ge semiconductor surface is then annealed at a temperature below that which would induce dopant diffusion.
    Type: Application
    Filed: October 24, 2013
    Publication date: April 24, 2014
    Applicant: The Regents of the University of California
    Inventors: Tobin Kaufman-Osborn, Andrew C. Kummel, Kiarash Kiantaj
  • Patent number: 8686417
    Abstract: An object is to manufacture a semiconductor device including an oxide semiconductor at low cost with high productivity in such a manner that a photolithography process is simplified by reducing the number of light-exposure masks. In a method for manufacturing a semiconductor device including a channel-etched inverted-staggered thin film transistor, an oxide semiconductor film and a conductive film are etched using a mask layer formed with the use of a multi-tone mask which is a light-exposure mask through which light is transmitted so as to have a plurality of intensities. In etching steps, a first etching step is performed by wet etching in which an etchant is used, and a second etching step is performed by dry etching in which an etching gas is used.
    Type: Grant
    Filed: July 23, 2012
    Date of Patent: April 1, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideomi Suzawa, Shinya Sasagawa, Taiga Muraoka, Shunichi Ito, Miyuki Hosoba
  • Patent number: 8673745
    Abstract: A method of cutting an object which can accurately cut the object is provided. An object to be processed 1 such as a silicon wafer is irradiated with laser light L while a light-converging point P is positioned therewithin, so as to form a modified region 7 due to multiphoton absorption within the object 1, and cause the modified region 7 to form a starting point region for cutting 8 shifted from the center line CL of the thickness of the object 1 toward the front face 3 of the object 1 along a line along which the object should be cut. Subsequently, the object 1 is pressed from the rear face 21 side thereof. This can generate a fracture from the starting point region for cutting 8 acting as a start point, thereby accurately cutting the object 1 along the line along which the object should be cut.
    Type: Grant
    Filed: August 26, 2013
    Date of Patent: March 18, 2014
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Fumitsugu Fukuyo, Kenshi Fukumitsu
  • Patent number: 8674351
    Abstract: A data retention period of a memory circuit is lengthened, power consumption is reduced, and a circuit area is reduced. Further, the number of times written data can be read to one data writing operation is increased. A memory circuit has a first field-effect transistor, a second field-effect transistor, and a third field-effect transistor. A data signal is input to one of a source and a drain of the first field-effect transistor. A gate of the second field-effect transistor is electrically connected to the other of the source and the drain of the first field-effect transistor. One of a source and a drain of the third field-effect transistor is electrically connected to a source or a drain of the second field-effect transistor.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: March 18, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Jun Koyama, Shunpei Yamazaki
  • Publication number: 20140054680
    Abstract: A method of forming a group III nitride semiconductor comprises: preparing a group III nitride semiconductor which contains a p-type dopant or an n-type dopant; and performing a treatment of the group III nitride semiconductor by using a reducing gas and a nitrogen source gas to form a conductive group III nitride semiconductor. The treatment includes performing a first treatment of the group III nitride semiconductor by using a first treatment gas including the reducing gas and the nitrogen source gas, which are supplied to a treatment apparatus at a first flow rate and a second flow rate, respectively, and after the first treatment is performed, performing a second treatment of the group III nitride semiconductor by using a second treatment gas including the reducing gas and the nitrogen source gas, which are supplied to the treatment apparatus at a third flow rate and a fourth flow rate, respectively.
    Type: Application
    Filed: August 21, 2013
    Publication date: February 27, 2014
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Shin HASHIMOTO, Takao NAKAMURA, Hiroshi AMANO
  • Publication number: 20140057461
    Abstract: A method for manufacturing a silicon carbide semiconductor device includes the following steps. A silicon carbide substrate is heated in an atmosphere containing oxygen, so as to form a gate insulating film on and in contact with the silicon carbide substrate. The silicon carbide substrate having the gate insulating film is heated at 1250° C. or more in an atmosphere containing nitrogen and nitrogen monoxide. A value obtained by dividing partial pressure of the nitrogen monoxide by a total of partial pressure of the nitrogen and the partial pressure of the nitrogen monoxide in the second heating step is more than 3% and less than 10%. Accordingly, there can be provided a method for manufacturing a silicon carbide semiconductor device having high mobility.
    Type: Application
    Filed: July 17, 2013
    Publication date: February 27, 2014
    Inventor: Hiromu Shiomi
  • Publication number: 20140051191
    Abstract: An extremely non-degenerate two photon absorption (END-2PA) method and apparatus provide for irradiating a semiconductor material substrate simultaneously with two photons each of different energy less than a bandgap energy of the semiconductor material substrate but in an aggregate greater than the bandgap energy of the semiconductor material substrate. A ratio of a higher energy photon energy to a lower energy photon energy is at least about 3.0. Alternatively, or as an adjunct, the higher energy photon has an energy at least about 75% of the bandgap energy and the lower energy photon has an energy no greater than about 25% of the bandgap energy.
    Type: Application
    Filed: November 19, 2012
    Publication date: February 20, 2014
    Applicant: UNIVERSITY OF CENTRAL FLORIDA RESEARCH FOUNDATION INC.
    Inventor: University of Central Florida Research Foudation I
  • Publication number: 20140042453
    Abstract: A method for manufacturing a silicon carbide semiconductor device includes the following steps. A silicon carbide substrate is prepared. A first heating step of heating the silicon carbide substrate in an atmosphere of oxygen is performed. A second heating step of heating the silicon carbide substrate to a temperature of 1300° C. or more and 1500° C. or less in an atmosphere of gas containing nitrogen atoms or phosphorus atoms is performed after the first heating step. A third heating step of heating the silicon carbide substrate in an atmosphere of a first inert gas is performed after the second heating step. Thus, the silicon carbide semiconductor device in which threshold voltage variation is small, and a method for manufacturing the same can be provided.
    Type: Application
    Filed: June 24, 2013
    Publication date: February 13, 2014
    Inventors: Toru Hiyoshi, Kosuke Uchida, Takeyoshi Masuda
  • Patent number: 8623728
    Abstract: A method for producing a SiGe stressor with high Ge concentration is provided. The method includes providing a semiconductor substrate with a source area, a drain area, and a channel in between; depositing the first SiGe film layer on the source area and/or the drain area; performing a low temperature thermal oxidation, e.g., a high water vapor pressure wet oxidation, to form an oxide layer at the top of the first SiGe layer and to form the second SiGe film layer with high Ge percentage at the bottom of the first SiGe film layer without Ge diffusion into the semiconductor substrate; performing a thermal diffusion to form the SiGe stressor from the second SiGe film layer, wherein the SiGe stressor provides uniaxial compressive strain on the channel; and removing the oxide layer. A Si cap layer can be deposited on the first SiGe film layer prior to performing oxidation.
    Type: Grant
    Filed: July 7, 2010
    Date of Patent: January 7, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Chang, Jeff J. Xu, Chien-Hsun Wang, Chih Chieh Yeh, Chih-Hsiang Chang
  • Patent number: 8617915
    Abstract: In an annealing process, a Kesterite film is provided on a substrate. The Kesterite film and the substrate are generally planar, have an interface, and have a substrate exterior side and a Kesterite exterior side. An additional step includes locating the cap adjacent the Kesterite exterior side. A further step includes applying sufficient heat to the Kesterite film and the substrate for a sufficient time to anneal the Kesterite film. The annealing is carried out with the cap adjacent the Kesterite exterior side. In another aspect, the film is not limited to Kesterite, and the cap is employed without any precursor layer thereon. Solar cell manufacturing techniques employing the annealing techniques are also disclosed.
    Type: Grant
    Filed: June 3, 2011
    Date of Patent: December 31, 2013
    Assignee: International Business Machines Corporation
    Inventors: Supratik Guha, David B. Mitzi, Teodor K. Todorov, Kejia Wang
  • Patent number: 8557719
    Abstract: A method for fabricating a semiconductor device, according to the present invention includes the steps of: preparing an SOI substrate, which comprises a semiconductor supporting layer, an oxide layer formed on the semiconductor supporting layer and an SOI layer formed on the oxide layer; forming a semiconductor device on the SOI layer; forming a passivation layer over the SOI substrate, the passivation layer allowing a UV light to pass through it; and applying a UV light to the SOI substrate after the step of forming the semiconductor device is completed.
    Type: Grant
    Filed: February 13, 2009
    Date of Patent: October 15, 2013
    Assignee: Lapis Semiconductor Co., Ltd.
    Inventors: Wataru Shimizu, Ikuo Kurachi
  • Patent number: 8551865
    Abstract: A method of cutting an object which can accurately cut the object is provided. An object to be processed 1 such as a silicon wafer is irradiated with laser light L while a light-converging point P is positioned therewithin, so as to form a modified region 7 due to multiphoton absorption within the object 1, and cause the modified region 7 to form a starting point region for cutting 8 shifted from the center line CL of the thickness of the object 1 toward the front face 3 of the object 1 along a line along which the object should be cut. Subsequently, the object 1 is pressed from the rear face 21 side thereof. This can generate a fracture from the starting point region for cutting 8 acting as a start point, thereby accurately cutting the object 1 along the line along which the object should be cut.
    Type: Grant
    Filed: April 20, 2012
    Date of Patent: October 8, 2013
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Fumitsugu Fukuyo, Kenshi Fukumitsu
  • Patent number: 8507367
    Abstract: A method of fabricating semiconductor devices is disclosed. The method comprises providing a substrate with a plurality of epitaxial layers mounted on the substrate and separating the substrate from the plurality of epitaxial layers while the plurality of epitaxial layers is intact. This preserves the electrical, optical, and mechanical properties of the plurality of epitaxial layers.
    Type: Grant
    Filed: July 3, 2008
    Date of Patent: August 13, 2013
    Assignee: Tinggi Technologies Pte Ltd.
    Inventors: Xuejun Kang, Shu Yuan, Jenny Lam, Shiming Lin
  • Publication number: 20130168826
    Abstract: Novel laser processed semiconductor materials, systems, and methods associated with the manufacture and use of such materials are provided. In one aspect, for example, a method of processing a semiconductor material can include providing a semiconductor material and irradiating a target region of the semiconductor material with a beam of laser radiation to form a laser treated region. The laser radiation is irradiated at an angle of incidence relative to the semiconductor material surface normal of from about 5° to about 89°, and the laser radiation can be at least substantially p-polarized.
    Type: Application
    Filed: October 1, 2012
    Publication date: July 4, 2013
    Applicant: SiOnyx, Inc.
    Inventor: SiOnyx, Inc.
  • Publication number: 20130168797
    Abstract: A thin film photovoltaic device includes a substrate and a first conductive layer coupled to the substrate. The first conductive layer includes at least one first groove extending through a first portion of the first conductive layer to a portion of the substrate. The device also includes at least one semiconductor layer coupled to a remaining portion of the first conductive layer and the portion of the substrate. The at least one semiconductor layer includes a plurality of non-overlapping vias, each via extending through a portion of the at least one semiconductor layer to a portion of the first conductive layer. The device further includes a second conductive layer coupled to a remaining portion of the at least one semiconductor layer and portions of the first conductive layer. The second conductive layer includes at least one second groove extending through a portion of the second conductive layer to a portion of the at least one semiconductor layer.
    Type: Application
    Filed: January 4, 2012
    Publication date: July 4, 2013
    Applicant: ESI-PyroPhotonics Lasers, Inc.
    Inventor: Matthew Rekow
  • Patent number: 8476171
    Abstract: The present invention is to provide a heat treatment method for effectively eliminating Te deposits in a ZnTe single crystal substrate, and a ZnTe single crystal substrate having an optical characteristic suitable for use of a light modulation element and having a thickness of 1 mm or more. A heat treatment method of a ZnTe single crystal substrate, includes: a first step of increasing a temperature the ZnTe single crystal substrate to a first heat treatment temperature T1, and retaining the temperature of the substrate for a predetermined time; and a second step of gradually reducing the temperature of the substrate from the first heat treatment temperature T1 to a second heat treatment temperature T2 lower than the heat treatment temperature T1 with a predetermined rate, wherein the first heat treatment temperature T1 is set in a range of 700° C.?T1?1250° C. and the second heat treatment temperature T2 is set in a range of T2?T1?50.
    Type: Grant
    Filed: July 18, 2006
    Date of Patent: July 2, 2013
    Assignee: Nippon Mining & Metals Co., Ltd.
    Inventors: Toshiaki Asahi, Kenji Sato, Takayuki Shimizu
  • Patent number: 8450704
    Abstract: A system for modifying dislocation distributions in semiconductor materials is provided. The system includes one or more vibrational sources for producing at least one excitation of vibrational mode having phonon frequencies so as to enhance dislocation motion through a crystal lattice.
    Type: Grant
    Filed: December 3, 2010
    Date of Patent: May 28, 2013
    Assignee: Massachusetts Institute of Technology
    Inventors: Anthony Buonassisi, Mariana Bertoni, Bonna Newman
  • Patent number: 8420551
    Abstract: Example methods and example embodiments include methods of fabricating semiconductor devices and semiconductor devices fabricated by the same. Example fabricating methods include forming a first nanowire, oxidizing the first nanowire to form a first nanostructure including a first insulator and a second nanowire, and oxidizing the second nanowire to form a second nanostructure including a second insulator and nanodots. Example semiconductor devices include nanostructures including nanodots and nanostructures providing storage nodes in memory devices.
    Type: Grant
    Filed: December 6, 2010
    Date of Patent: April 16, 2013
    Assignees: Samsung Electronics Co., Ltd., Industry-Academic Cooperation Foundation
    Inventors: Myung-Jong Kim, In-Seok Yeo, Dae-Hong Ko, Hyun-Chul Sohn, Mann-Ho Cho, Sang-Yeon Kim
  • Publication number: 20130082279
    Abstract: A substrate including a body comprising a Group III-V material and having an upper surface, the body comprising an offcut angle defined between the upper surface and a crystallographic reference plane, and the body further having an offcut angle variation of not greater than about 0.6 degrees.
    Type: Application
    Filed: September 28, 2012
    Publication date: April 4, 2013
    Inventors: Jean-Pierre Faurie, Bernard Beaumont
  • Patent number: 8399367
    Abstract: The disclosure provides a process to anneal group III-V metal nitride crystals, wafers, epitaxial layers, and epitaxial films to reduce nitrogen vacancies. In particular, the disclosure provides a process to perform slow annealing of the group III-V metal nitrides in a high temperature and high pressure environment.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: March 19, 2013
    Assignee: Nitride Solutions, Inc.
    Inventor: Jason Schmitt
  • Publication number: 20130052838
    Abstract: An annealing method to reduce defects of epitaxial films and epitaxial films formed therewith. The annealing method includes features as follows: apply a pressure ranged from 10 MPa to 6,000 MPa to an epitaxial film grown on a substrate through a vapor phase deposition process and heat the epitaxial film at a temperature lower than the melting temperature of the epitaxial film. Through applying pressure to the epitaxial film, the lattice strain of the epitaxial film is alleviated, and therefore the defect density of the epitaxial film also decreases.
    Type: Application
    Filed: December 23, 2011
    Publication date: February 28, 2013
    Inventors: I-Chiao Lin, Chien-Min Sung
  • Patent number: 8377743
    Abstract: A method of annealing a metal oxide on a temperature sensitive substrate formation includes the steps of providing a temperature sensitive substrate formation and forming a spacer layer on a surface of the substrate formation. A metal oxide semiconductor device is formed on the spacer layer, the device includes at least a layer of amorphous metal oxide semiconductor material, an interface of the amorphous metal oxide layer with a dielectric layer, and a gate metal layer adjacent the layer of amorphous metal oxide semiconductor material and the interface. The method then includes the step of at least partially annealing the layer of metal oxide semiconductor material by heating the adjacent gate metal layer with pulses of infra red radiation to improve the mobility and operating stability of the amorphous metal oxide semiconductor material while retaining at least the amorphous metal oxide semiconductor material adjacent the gate metal layer amorphous.
    Type: Grant
    Filed: September 1, 2010
    Date of Patent: February 19, 2013
    Assignee: CBRITE Inc.
    Inventors: Chan-Long Shieh, Hsing-Chung Lee
  • Publication number: 20130040466
    Abstract: In a modified region forming step, an element-group formation substrate (20) having plural semiconductor light emitting elements (21) formed on a substrate front surface (11a) of a wafer substrate (11) is irradiated with laser light (64) from the substrate back surface (11b) of the substrate, thereby forming the following inside the substrate: first and third modified regions (L1) and (L3) oriented in a y-direction (corresponding to a first direction) that is parallel to the surfaces of the substrate; and second and fourth modified regions (L2) and (L4) oriented in an x-direction (corresponding to a second direction) that is parallel to the surfaces of the substrate and differs from the y-direction. In the step, the first modified region (L1), the second modified region (L2), the third modified region (L3) and the fourth modified region (L4) are formed at different depths from the substrate back surface of the substrate.
    Type: Application
    Filed: June 3, 2011
    Publication date: February 14, 2013
    Applicant: SHOWA DENKO K.K.
    Inventor: Yoshinori Abe
  • Patent number: 8372683
    Abstract: An RTP heating system and an RTP heating method, which can heat a photovoltaic-device intermediate product having a glass substrate, a Mo layer, and a light absorption layer in formation. The RTP heating system is composed of a chamber; a support member located in the chamber; a heating element mounted in the chamber for emitting infrared rays for heating; and a plurality of temperature sensors and a temperature control device for sensing and controlling thermal sources from the heating element and the support member. The infrared rays can be mostly reflected off the Mo layer to apply less direct heating to the glass substrate. Accordingly, the upper and lower surfaces of the photovoltaic-device intermediate product can be heated under different temperatures separately to prevent the glass substrate below the photovoltaic-device intermediate product from softening and deformation and to allow production of the light absorption layer on the Mo layer.
    Type: Grant
    Filed: January 11, 2011
    Date of Patent: February 12, 2013
    Assignee: ADPV Technology Limited
    Inventor: Shiezen Steven Huang
  • Patent number: 8334532
    Abstract: The invention provides an IGZO-based oxide material and a method of producing the same, the IGZO-based oxide material being represented by a composition formula of In2-xGaxZnO4-?, where 0.75<x<1.10 and 0<??1.29161×exp(?x/0.11802)+0.00153, and being formed from a single phase of IGZO having a crystal structure of YbFe2O4.
    Type: Grant
    Filed: June 15, 2010
    Date of Patent: December 18, 2012
    Assignee: FUJIFILM Corporation
    Inventors: Kenichi Umeda, Masayuki Suzuki, Atsushi Tanaka
  • Patent number: 8278128
    Abstract: An off-axis cut of a nonpolar III-nitride wafer towards a polar (?c) orientation results in higher polarization ratios for light emission than wafers without such off-axis cuts. A 5° angle for an off-axis cut has been confirmed to provide the highest polarization ratio (0.9) than any other examined angles for off-axis cuts between 0° and 27°.
    Type: Grant
    Filed: February 2, 2009
    Date of Patent: October 2, 2012
    Assignee: The Regents of the University of California
    Inventors: Hisashi Masui, Hisashi Yamada, Kenji Iso, Asako Hirai, Makoto Saito, James S. Speck, Shuji Nakamura, Steven P. DenBaars
  • Patent number: 8247289
    Abstract: A capacitor having a high quality and a manufacturing method of the same are provided. A capacitor has a lower electrode formed on an oxide film, a dielectric layer formed on the lower electrode, an upper electrode formed so as to face the lower electrode with the dielectric layer between, and an upper electrode formed so as to cover the upper electrode, an opening portion of the upper electrode and an opening portion of the dielectric layer. By forming the upper electrode on the dielectric layer, it is possible to pattern the dielectric layer by using the upper electrode as a mask, and provide a capacitor having a high-quality dielectric layer by preventing impurity diffusion into the dielectric layer. By forming the upper electrode on the dielectric layer, it is possible to prevent the dielectric layer from being exposed to etching liquid, liquid developer, etc.
    Type: Grant
    Filed: August 23, 2006
    Date of Patent: August 21, 2012
    Assignee: Ibiden Co., Ltd.
    Inventors: Yoshiki Yamanishi, Muneo Harada, Takahiro Kitano, Tatsuzo Kawaguchi, Yoshihiro Hirota, Kinji Yamada, Tomotaka Shinoda, Katsuya Okumura, Shuichi Kawano