Abstract: A process for heat treating a silicon wafer to dissolve B-type agglomerated interstitial defects present therein. The process includes heating the silicon wafer at a temperature for a time sufficient to dissolve B-defects, the wafer being heated to said temperature at a rate sufficient to prevent B-defects from becoming stabilized such that these defects are rendered incapable of being dissolved.

Abstract: The present invention provides a method for thermal processing a semiconductor wafer wherein the semiconductor wafer is heat-treated by means of flash radiation means constituted by a flash discharge lamp after preheating the semiconductor wafer to a predetermined temperature by means of preheating means, the preheating is performed at a preheating temperature capable of controlling that the maximum tension of the semiconductor wafer when heated by the flash radiation means is to be less than the tense strength of the semiconductor wafer itself.

Abstract: According to the present invention, there are provided a method for heat treatment of silicon wafers wherein a silicon wafer is subjected to a heat treatment at a temperature of from 1000° C. to the melting point of silicon in an inert gas atmosphere, and temperature decreasing in the heat treatment is performed in an atmosphere containing 1-60% by volume of hydrogen, a method for heat treatment of silicon wafers under a reducing atmosphere containing hydrogen by using a rapid heating and rapid cooling apparatus, wherein temperature decreasing rate from the maximum temperature in the heat treatment to 700° C. is controlled to be 20° C./sec or less, and a silicon wafer which has a crystal defect density of 1.0×104 defects/cm3 or more in a wafer bulk portion, a crystal defect density of 1.0×104 defects/cm3 or less in a wafer surface layer of a depth of 0.5 &mgr;m from the surface, a crystal defect density of 0.15 defects/cm2 or less on a wafer surface and surface roughness of 1.

Abstract: OBJECT OF THE INVENTION

Abstract: The present invention is related to a method of crystallizing an amorphous silicon layer and a crystallizing apparatus thereof which crystallize an amorphous silicon layer using of electric fields and plasma. The present invention includes the steps of depositing an inducing substance for silicon crystallization on an amorphous silicon layer by plasma exposure, and carrying out annealing on the amorphous silicon layer while applying an electric field to the amorphous silicon layer. The present invention includes a chamber having an inner space, a substrate support in the chamber wherein the substrate support supports a substrate, a plasma generating means in the chamber wherein the plasma generating means produces plasma inside the chamber, an electric field generating means in the chamber wherein the electric field generating means applies electric field to the substrate, and a heater at the substrate support wherein the heater supplies the substrate with heat.

Abstract: A method of heat-treating a nitride compound semiconductor layer, comprising heating a nitride compound semiconductor layer doped with a p-type impurity at a temperature that is at least 200° C. but less than 400° C. for at least 100 minutes.

Abstract: It is possible to prevent lowering in productivity of thin-film transistors with no decrease in performance of the transistors. Provided are depositing an amorphous semiconductor film on a substrate, a first irradiating the amorphous semiconductor film with an energy-rich beam in an atmosphere of a gas containing an inert gas as a major component with a specific amount of oxygen, to change the amorphous semiconductor film into a polycrystalline semiconductor film, and a second irradiating the polycrystalline semiconductor film with an energy-rich beam in an atmosphere of a gas containing an inert gas as major component with oxygen of an amount less than the specific amount.

Abstract: A gallium nitride layer is pendeoepitaxially grown on weak posts on a substrate that are configured to crack due to a thermal expansion coefficient mismatch between the substrate and the gallium nitride layer on the weak posts. Thus, upon cooling, at least some of the weak posts crack, to thereby relieve stress in the gallium nitride semiconductor layer. Accordingly, low defect density gallium nitride semiconductor layers may be produced. Moreover, the weak posts can allow relatively easy separation of the substrate from the gallium nitride semiconductor layer to provide a freestanding gallium nitride layer. The weak posts may be formed by forming an array of posts in spaced apart staggered relation on the substrate. By staggering the posts, later fracturing may be promoted compared to long unstaggered posts. Alternatively, the posts may have a height to width ratio in excess of 0.5, so that the relatively narrow posts promote cracking upon reduction of the temperature.

Abstract: A method of making a vertical diode is provided, the vertical dioxide having associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer covers the interior surface of the diode opening and contacts the active region. The diode opening is initially filled with an amorphous silicon plug that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug has a top portion that is heavily doped with a first type dopant and a bottom portion that is lightly doped with a second type dopant. The top portion is bounded by the bottom portion so as not to contact the titanium silicide layer. For one embodiment of the vertical diode, a programmable resistor contacts the top portion of the silicon plug and a metal line contacts the programmable resistor.

Abstract: The present invention provides a method of manufacturing a low resistivity p-type compound semiconductor material over a substrate. The method of the present invention comprises the steps of forming a p-type impurity doped compound semiconductor layer on the substrate by either HVPE, OMVPE or MBE and applying a microwave treatment over the p-type impurity doped compound semiconductor layer for a period of time. The high resistivity p-type impurity doped compound semiconductor layer is converted into a low resistivity p-type compound semiconductor material according to the present invention.

Abstract: A method for growing high-quality gallium nitride over a substrate is disclosed. The method comprises growing first layer with a high dislocation density over the substrate, a second layer having a high number of point defects and a reduced dislocation density as compared to the dislocation density of the first layer over the first layer, and a third layer having a reduced number of point defects as compared to the second layer over the second layer. The resulting gallium nitride is semi-insulating, which inhibits parasitic current flow and parasitic capacitive effects, yet it not so insulating that electron flow in adjacent transistor channels is inhibited.

Abstract: The nickel element is provided selectively, i.e., adjacent to part of the surface of an amorphous silicon film in a long and narrow opening. The amorphous silicon film is irradiated with linear infrared light beams emitted from respective linear infrared lamps while scanned with the linear beams perpendicularly to the longitudinal direction of the opening. The longitudinal direction of the linear beams are set coincident with that of the opening. The infrared light beams are absorbed by the silicon film mainly as thermal energy, whereby a negative temperature gradient is formed in the silicon film. The temperature gradient moves as the lamps are moved for the scanning. The direction of the negative temperature gradient is set coincident with the lamp movement direction and an intended crystal growth direction, which enables crystal growth to proceed parallel with a substrate uniformly over a long distance.

Abstract: An improved gallium arsenide anneal boat and method for annealing comprises a slot structure for holding a wafer-stack of first and second GaAs wafers and a silicon wafer in the slot structure prior to annealing. The silicon wafer is tightly held in a central slot to maintain a vertical position and the GaAs wafers are loosely held in outside slots to avoid the formation of slip lines. The GaAs wafers slightly adhere to the silicon wafer to maintain a vertical position to avoid bending. Additionally, the wafer-stacks are separated by more than about 1.25 inches and processed in arsine gas at about 1 atm. pressure to avoid hazing.

Abstract: In a method of forming a polycrystalline silicon film in a process of manufacturing an LCD, a hydrogenated amorphous silicon film is formed on a glass substrate by plasam CVD throughout areas serving as the pixel portion and driver unit of the LCD. A laser beam is radiated on a selected region of the film on the area serving as the driver unit. The energy of the laser beam is set such that hydrogen in the film is discharged without crystallizing the film and damaging the film. The energy of the laser beam is gradually increased to gradually discharge hydrogen from the film. The energy of the laser beam is finally set such that the film is transformed into a polycrystalline silicon film. The amorphous silicon film can be poly-crystallized without damaging the film by the discharge of hydrogen.