Abstract: A process uses pressure changes and a pressure compensation factor to estimate the rate at which neutral atoms are implanted. While implanting a first wafer using a first pressure compensation factor, the rate at which ions are implanted is determined. The first wafer is moved radially with respect to an ion beam while implanting ions into the first wafer so as to achieve a uniform total dose based on the rate at which ions are implanted and the estimated rate at which neutral atoms are implanted. The pressure is determined while implanting the first wafer, determining the pressure. A second pressure compensation factor is selected, that would have achieved a uniform rate of implanted ions plus implanted neutral atoms across a surface of the first wafer. The second pressure compensation factor is different from the first pressure compensation factor. The second pressure compensation factor is used to implant a second wafer. The second wafer is tested by forming a sheet resistance contour map.

Abstract: This invention relates to the field of nanotechnology. Specifically the invention describes a method for cutting a multiplicity of nano-structures to uniform dimensions of length, length and width, or area, or to a specific distribution of lengths or area using various cutting techniques.

Abstract: A method of making byte erasable devices having elements made with nanotubes. Under one aspect of the invention, a device is made having nanotube memory elements. A structure is provided having a plurality of transistors, each with a drain and a source with a defined channel region therebetween, each transistor further including a gate over said channel. For a predefined set of transistors, a corresponding trench is formed between gates of adjacent transistors. For each trench, a defined pattern of nanotube fabric is provided over at least a horizontal portion of the structure and extending into the trench. An electrode is provided in each trench. Each defined pattern of nanotube fabric is suspended so that at least a portion is vertically suspended in spaced relation to the vertical walls of the trench and positioned so that the vertically suspended defined pattern of nanotube fabric is electromechanically deflectable into electrical communication with one of the drain and source of a transistor.

Abstract: A reticle assembly includes a reticle with a reticle plate. A radio frequency device is positioned on the reticle for providing information regarding the reticle to a reader by radio frequency.

Abstract: A technique is disclosed that allows alignment of substrates on a run-to-run basis by using the position data of one or more previously aligned substrates to determine a setpoint of a pre-alignment process for one or more subsequent substrates. The setpoint may also be determined on the basis of a predefined characteristic of the substrates to be aligned.

Abstract: This invention relates to the field of nanotechnology. Specifically the invention describes a method for cutting a multiplicity of nano-structures to uniform dimensions of length, length and width, or area, or to a specific distribution of lengths or area using various cutting techniques.

Abstract: The present invention is directed to a method of forming a clamping plate for a multi-polar electrostatic chuck. The method comprises forming a first electrically conductive layer over a semiconductor platform and defining a plurality of portions of the first electrically conductive layer which are electrically isolated from one another. A first electrically insulative layer is formed over the first electrically conductive layer, the first electrically insulative layer comprising a top surface having a plurality of MEMS protrusions extending a first distance therefrom. A plurality of poles are furthermore electrically connected to the respective plurality of portions of the first electrically conductive layer, wherein a voltage applied between the plurality of poles is operable to induce an electrostatic force in the clamping plate.

Abstract: A manufacturing method of an integrated chip. The integrated chip includes at least two devices with different functions. The method uses a first production line to form a first device on a semiconductor wafer and then uses a second production line to form a second device on the semiconductor wafer so as to complete the integrated chip.

Abstract: The present invention provides a vacuum processing system for creating processed substrates having a domed lid on at least the transfer chamber. The lid may be provided either convex to the chamber, thus decreasing the volume of the chamber and the amount of microparticulate matter present in the chamber, or concave to the chamber. The invention also provides features to enhance the use of the domed lid, e.g., structural features that decrease lifting of the edges of the lid upon introduction of a vacuum to the chamber.

Abstract: An optical element holding device includes a ring body for accommodating an optical element and a drive mechanism for driving the optical element. The ring body has an inner ring portion, which engages with a peripheral edge of the optical element, and an outer ring portion integral with the inner ring portion. The drive mechanism includes an actuator, a displacement increasing mechanism and a guide mechanism. The guide mechanism transfers displacement of the actuator to the inner ring and moves the inner ring axially.

Abstract: A process for providing regions of substantially lower fluorine content in a fluorine-containing dielectric comprises exposing the fluorine-containing dielectric to a reactive species to form volatile byproducts.

Abstract: In an alignment or overlay measurement of patterns on a semiconductor wafer an error that occurs during the measurement in one of a predefined number of alignment structures in an exposure field of a corresponding predefined set of exposure fields can be handled by selecting an alignment structure in a substitute exposure field. The latter exposure field need not be part of the predefined set of exposure fields, that is, an inter-field change may be effected. The number of alignment measurements on a wafer remains constant and the quality is increased. Alternatively, when using another alignment structure in the same exposure field—by effecting an intra-field change—the method becomes particularly advantageous when different minimum structure sizes are considered for the substitute targets. Due to the different selectivity in, say, a previous CMP process, such targets might not erode and do not cause an error in a measurement, thus providing an increased alignment or overlay quality.

Abstract: In a method of manufacturing a compound semiconductor device, individual chip patterns are projected onto a (1 0 0) surface of a GaAs wafer so that the columns and rows of the chip patterns are aligned in a direction slanting by 45 degrees with respect to a [0 1 1] direction of the GaAs wafer. The wafer is diced along this slanting direction and chipping along the edges of the individual separated chips is greatly reduced.

Abstract: An integrated circuit including a power ring and an embedded low drop-off voltage regulator is disclosed herein. The regulator is located within an inner side of the power ring. An input of the regulator is coupled to the power ring. An output of the regulator is coupled to a circuit also included in the integrated circuit. The regulator is configured to fit within a bond pad frame.

Abstract: Methods are provided for adjusting and controlling the stress between layers of material in a multilayer structure. A first stress is configured in a region of stress on the substrate material. A second material is then deposited over the substrate. A second stress results between the substrate and the second material such that a net stress results where the net stress is a function of said first and second stresses. As such, the first stress can be configured to achieve a predetermined, desired net stress. For example, the first stress can be configured to cancel out the second stress such that the net stress is substantially zero.

Abstract: Disclosed are layered groupings and methods for constructing digital circuitry, such as memory known as Permanent Inexpensive Rugged Memory (PIRM) cross point arrays which can be produced on flexible substrates by patterning and curing through the use of a transparent embossing tool.

Abstract: The present invention relates to a low nitrogen concentration carbonaceous material with a nitrogen concentration according to glow discharge mass spectrometry of 100 ppm or less, as well as a manufacturing method thereof are provided. A carbonaceous material subjected to a high purification treatment in a halogen gas atmosphere is heat treated under a pressure of 100 Pa or less and at a temperature of 1800° C. or higher, releasing nitrogen in the carbonaceous material and then cooling the material under a pressure of 100 Pa or less or in a rare gas atmosphere.

Abstract: An air-supply machine cleans outside air. The cleaned outside air is dehumidified by cooling by performing heat exchange between the cleaned outside air and an exhaust air from a lithography apparatus by a first heat-pipe. The dehumidified outside air is heated by performing heat treatment between the dehumidified outside air and an exhaust air from a vertical heat treatment apparatus by a second heat-pipe. The heated outside air is supplied to inside the housing of the vertical heat treatment apparatus. Thereby, the consumption of air in the clean room is reduced and the running cost of the clean room is reduced.

Abstract: An improved and novel method of selectively aligning and positioning nanometer-scale components using AC fields. The method provides for more precise manipulation of the nanometer-scale components in bridging test electrodes including the steps of: providing an alternating current (AC) field at a single electrode or between a plurality of electrodes to create an electric field in an environment containing nanometer-scale components. The electric field thereby providing for the aligning and positioning of the nanometer-scale components to the desired location.

Abstract: An object of the present invention is to provide a quartz glass jig, which, when employed in a processing apparatus using plasma, is less in generation of abnormal etching and particles and low in contamination with impurities. This object is obtained by a quartz glass jig for a processing apparatus using plasma, wherein a surface of the jig is subjected to grinding or a sandblast processing and has a surface roughness Ra in the range of from 2 ?m to 0.05 ?m, and microcracks of grinding marks formed during the grinding or sandblast processing have a depth of 50 ?m or less.

Abstract: A nano-scale system is provided, and a method of manufacture therefor, including a support material, a nanotube embedded in the support material and an electrical connection to the nanotube.

Abstract: A FOUP having semiconductor wafers received therein is transferred to a loading port and then the door of the FOUP is fixed and removed by a FIMS door and then the semiconductor wafers are taken out of the shell of the FOUP and then a predetermined manufacturing processing is performed to the semiconductor wafers. After performing the manufacturing processing, the semiconductor wafers are returned into the shell and the FIMS door is returned to a closed position and the shell is retracted about 50 mm to 65 mm to form a gap between the FIMS door and the shell. Then, purge gas is introduced from a gas introduction pipe arranged above the loading port on the left and right sides in a slanting forward direction of the FIMS door into the shell to replace the atmosphere in the shell with the purge gas.

Abstract: A method of fabricating a multilayer ceramic substrate includes stacking one or a plurality of unfired ceramic greensheets on one or both sides of a previously fired ceramic substrate, thereby forming a stack, each unfired ceramic greensheet having a firing temperature substantially equal to or lower than a firing temperature of the previously fired ceramic substrate, stacking a restricting greensheet on the unfired ceramic greensheet composing an outermost layer of the stack, the restricting greensheet having a higher firing temperature than each unfired ceramic greensheet, firing the stack at the firing temperature of the unfired ceramic green sheets with or without pressure applied via the restricting greensheet while the stack is under restriction by the restricting greensheet, thereby integrating the stack, and eliminating remainders of the restricting greensheet after the firing step.

Abstract: A low-capacitance one-resistor/one-diode (1R1D) R-RAM array with a floating p-well is provided. The fabrication method comprises: forming an integrated circuit (IC) substrate; forming an n-doped buried layer (buried n layer) of silicon overlying the substrate; forming n-doped silicon sidewalls overlying the buried n layer; forming a p-doped well of silicon (p-well) overlying the buried n layer; and, forming a 1R1D R-RAM array overlying the p-well. Typically, the combination of the buried n layer and the n-doped sidewalls form an n-doped well (n-well) of silicon. Then, the p-well is formed inside the n-well. In other aspects, the p-well has sidewalls, and the method further comprises: forming an oxide insulator overlying the p-well sidewalls, between the n-well and the R-RAM array.

Abstract: A substrate holder holds a substrate while hermetically sealing an outer circumferential edge and a reverse side of the substrate and exposing a surface of the substrate. The substrate holder has a base and a cover having an opening defined therein and positioned to place the substrate between the base and the cover. An attracting mechanism couples the base and the cover to each other to hold the substrate between the base and the cover, with the surface of the substrate being exposed through the opening.

Abstract: A process tool for electrochemically treating a substrate is configured to reduce the oxygen concentration and/or the sulfur dioxide concentration in the vicinity of the substrate so that corrosion of copper may be reduced. In one embodiment, a substantially inert atmosphere is established within the process tool including a plating reactor by providing a continuous inert gas flow and/or by providing a cover that reduces a gas exchange with the ambient atmosphere. The substantially inert gas atmosphere may also be maintained during further process steps involved in electrochemically treating the substrate including required transportation steps between the individual process steps.

Abstract: A device for transferring an object between manufacturing steps includes a transfer surface for receiving an object having an initial temperature from a first manufacturing step, for transporting the object from the first manufacturing step to another manufacturing step, and for transferring the object having a final temperature from the transfer surface to the other manufacturing step; and at least one Peltier unit coupled to the transfer surface for effecting a temperature change of the object from the initial temperature to the final temperature at a controlled rate.

Abstract: a method and apparatus for preventing N2O from becoming super critical during a high pressure oxidation stage within a high pressure oxidation furnace are disclosed. The method and apparatus utilize a catalyst to catalytically disassociate N2O as it enters the high pressure oxidation furnace. This catalyst is used in an environment of between five (5) atmospheres to twenty-five (25) atmospheres N2O and a temperature range of 600° to 750° C., which are the conditions that lead to the N2O going super critical. By preventing the N2O from becoming super critical, the reaction is controlled that prevents both temperature and pressure spikes. The catalyst can be selected from the group of noble transition metals and their oxides. This group can comprise palladium, platinum, rhodium, nickel, silver, and gold.

Abstract: A system for processing a workpiece includes a process head assembly and a base assembly. The process head assembly has a process head and an upper rotor. The base assembly has a base and a lower rotor. The base and lower rotor have magnets wherein the upper rotor is engageable with the lower rotor via a magnetic force created by the magnets. The engaged upper and lower rotors form a process chamber where a semiconductor wafer is positioned for processing. Process fluids for treating the workpiece are introduced into the process chamber, optionally while the processing head spins the workpiece. Additionally, air flow around and through the process chamber is managed to reduce particle adders on the workpiece.

Abstract: An exemplary embodiment of the present invention includes a method for forming a programmable cell by forming an opening in a dielectric material to expose a portion of an underlying first conductive electrode, forming a recessed chalcogenide-metal ion material in said opening and forming a second conductive electrode overlying the dielectric material and the chalcogenide-metal ion material. A method for forming the recessed chalcogenide-metal ion material comprises forming a metal material being recessed approximately 10-90%, in the opening in the dielectric material, forming a glass material on the metal material within the opening and diffusing metal ions from the metal material into the glass material by using ultraviolet light or ultraviolet light in combination with a heat treatment, to cause a resultant metal ion concentration in the glass material.

Abstract: Bioelectronic components are formed using nanoparticles surrounded by attached shells of at least one biological material. The nanoparticles are deposited (e.g., using a printing process) onto a surface, and by associating the deposited nanoparticles with one or more electrical contacts, electrical measurement across the nanoparticles (and, consequently, across the biological material) may be made. A finished component may include multiple layers formed by nanoparticle deposition.

Abstract: An arrangement for transferring information/structures to wafers uses a stamp on which the information/structures to be transferred have been applied as elevated structures. The wafer is fixed on a chuck and is provided with a plastically deformable auxiliary patterning layer. In various implementations, the dimensions of the stamp approximately correspond to those of the wafer, the stamp is provided with the elevated structures essentially over the whole area, and/or the stamp and the wafer are in each case provided with mutually assigned pairs of alignment marks in such a way that the stamp can be positioned in a predetermined position on the wafer by means of an infrared positioning system and can be pressed into the plastically deformable auxiliary patterning layer.

Abstract: A thermoplastic molding composition having improved impact strength at low temperatures is disclosed. The composition contains A) polycarbonate and/or polyester carbonate B) a graft polymer based on ethylene-&agr;-olefin rubber as graft base, C) wollastonite having carbon content greater than 0.1% relative to the weight of the wollastonite and D) at least one of triglyceride, aliphatic saturated hydrocarbon and aliphatic unsaturated hydrocarbon.

Abstract: A new technique for fabricating two-dimensional and three-dimensional fluid microchannels for molecular studies includes fabricating a monolithic unit using planar processing techniques adapted from semiconductor electronics fabrication. A fluid gap between a floor layer (12) and a ceiling layer (20) is provided by an intermediate patterned sacrificial layer (14) which is removed by a wet chemical etch. The process may be used to produce a structure such as a filter or artificial gel by using Electron beam lithography to define a square array of 100 nm holes (30) in the sacrificial layer. CVD silicon nitride (54) is applied over the sacrificial layer and enters the array of holes to produce closely spaced pillars. The sacrificial layer can be removed with a wet chemical etch through access holes in the ceiling layer, after which the access holes are sealed with VLTO silicon dioxide (64).

Abstract: An electronic device having an interconnected network of carbon nanotubes on the surface of a substrate, and two or more electrical leads. The network forms an electrical connection between the leads.

Abstract: A method for marking a wafer that is cut from a boule. A surface of the boule is marked with an encoded marking that extends completely along a distance of the boule that is used for cutting wafers. The encoded marking is disposed substantially parallel to a length axis of the boule. The wafer is cut from the boule from within the distance, such that the encoded marking along the surface of the boule is disposed at a peripheral edge of the wafer. The encoded marking contains information in regard to the wafer.

Abstract: A reticle assembly includes a reticle with a reticle plate. A radio frequency device is positioned on the reticle for providing information regarding the reticle to a reader by radio frequency.

Abstract: A technique for forming a film of material (12) from a donor substrate (10). The technique has a step of forming a stressed region in a selected manner at a selected depth (20) underneath the surface. An energy source such as pressurized fluid is directed to a selected region of the donor substrate to initiate a controlled cleaving action of the substrate (10) at the selected depth (20), whereupon the cleaving action provides an expanding cleave front to free the donor material from a remaining portion of the donor substrate.

Abstract: A rigid pellicle, used to protect a patterned reticle from contamination in a lithographic process in the manufacture of integrated circuits, is attached to a mounting frame by fusing the pellicle and frame together. In one embodiment, an infrared laser beam is used to produce the fusion along the seam between the pellicle and the frame. The frame may also be attached to the reticle through a similar fusion process. In one embodiment, the pellicle, frame, and reticle are all comprised of fused silica.

Abstract: Production of an electronic device by solution processing by depositing fluid including a device material or a precursor thereto onto a zone of a substrate surface between at least two opposed barriers for together controlling the spread of said fluid on the substrate surface, wherein at least one of the two opposed barriers is structured so as to facilitate controlled spillage of excess fluid out of the zone to one or more selected locations. Also, production of an electronic device by solution processing by longitudinally depositing fluid containing a device material or a precursor thereto on a patterned substrate to form a plurality of spaced longitudinal channels of said device material of controlled lateral width, wherein the substrate is patterned such that at least one lateral connection between at least one pair of adjacent channels is formed at at least one selected location without the need to carry out any lateral deposition of said fluid.

Abstract: The conveyance of wafers in bays (equipment groups) of a clean room is performed by RGVs (Rail Guided Vehicles) that linearly travel on conveying rails (3) laid on the floor of the clean room at high speed. A structure is adopted wherein a conveying area over which the RGV travels, is separated from a human working area by a compartment (partition) (4), and a human does not enter the conveying area upon operation of a line.

Abstract: Components of semiconductor processing apparatus are formed at least partially of erosion, corrosion and/or corrosion-erosion resistant ceramic materials. Exemplary ceramic materials can include at least one oxide, nitride, boride, carbide and/or fluoride of hafnium, strontium, lanthanum oxide and/or dysprosium. The ceramic materials can be applied as coatings over substrates to form composite components, or formed into monolithic bodies. The coatings can protect substrates from physical and/or chemical attack. The ceramic materials can be used to form plasma exposed components of semiconductor processing apparatus to provide extended service lives.

Abstract: Device nanotechnology based on silicon wafers and other substrates is described. Methods for preparing such devices are discussed. The teachings allow integration of current semiconductor device, sensor device and other device fabrication methods with nanotechnology. Integration of nanotubes and nanowires to wafers is discussed. Sensors, electronics, biomedical and other devices are presented.

Abstract: A manufacturing apparatus for a semiconductor device comprises: a clean room for installing a plurality of semiconductor manufacturing and processing apparatuses; an external air cleaning device connected to a supply port of the clean room for supplying a cleaned-up outside air into the clean room; a common air duct section installed in the clean room; a first air cleaning and ventilating means connected to said common air duct section for cleaning and ventilating a part of the cleaned-up outside air to the common air duct section; individual air duct section branched off from the common air duct section and connected to each of said semiconductor manufacturing and processing apparatuses; and a second air cleaning and ventilating means interposed between the individual air duct section and each of the semiconductor manufacturing and processing apparatuses for cleaning and ventilating the air to be supplied to each of the semiconductor manufacturing and processing apparatuses.

Abstract: An in-line system having an overlay measurement function and a method thereof capable of reducing overlay measurement time and simplifying related jobs are disclosed. The system for performing wafer processing comprises an in-line system comprising a stepper for performing alignment and photo-exposure of a wafer and a spinner, in-line connected to the stepper, for performing coating and development of the wafer, and an overlay measurement device, in-line connected to the spinner, for automatically measuring an overlay accuracy of the wafer after wafer development is completed by the spinner.

Abstract: A method of securing a substrate in a semiconductor processing machine. The method includes moving latch bodies between latched and unlatched positions while permitting contact between a clamping member of each latch body and the substrate only if the latch bodies are substantially in the latched position. In the latched position, the clamping members apply a clamping force effective to secure the substrate. Generally, contact is prevented by engagement between a support member and an ramp that is inclined such that the clamping member descends toward the substrate as the latch body moves from the unlatched position to the latched position and only contacts the substrate as the latched position is established.

Abstract: A nano-scale system is provided, and a method of manufacture therefor, including a support material, a nanotube embedded in the support material and an electrical connection to the nanotube.

Abstract: A new technique for fabricating two-dimensional and three-dimensional fluid microchannels for molecular studies includes fabricating a monolithic unit using planar processing techniques adapted from semiconductor electronics fabrication. A fluid gap between a floor layer (12) and a ceiling layer (20) is provided by an intermediate patterned sacrificial layer (14) which is removed by a wet chemical etch. The process may be used to produce a structure such as a filter or artificial gel by using Electron beam lithography to define a square array of 100 nm holes (30) in the sacrificial layer. CVD silicon nitride (54) is applied over the sacrificial layer and enters the array of holes to produce closely spaced pillars. The sacrificial layer can be removed with a wet chemical etch trough access holes in the ceiling layer, after which the access holes are sealed with VLTO silicon dioxide (64).

Abstract: An apparatus to prevent oxidation of an electronic device, such as a semiconductor substrate during a semiconductor packaging process, comprises a substantially-enclosed conduit having at least one movable support defining a path through which the electronic device may travel and a plurality of gas outlets to introduce a relatively inert gas into the conduit. Conveying means adapted to engage and move the electronic device along the conduit is provided, and an opening along a portion of the conduit allows engagement between the conveying means and the electronic device. Actuating means are adapted to shift the movable support whereby the size of the path is adjustable to suit different electronic devices.

Abstract: A manufacturing apparatus for a semiconductor device comprises: a clean room for installing a plurality of semiconductor manufacturing and processing apparatuses; an external air cleaning device connected to a supply port of the clean room for supplying a cleaned-up outside air into the clean room; a common air duct section installed in the clean room; a first air cleaning and ventilating means connected to said common air duct section for cleaning and ventilating a part of the cleaned-up outside air to the common air duct section; individual air duct section branched off from the common air duct section and connected to each of said semiconductor manufacturing and processing apparatuses; and a second air cleaning and ventilating means interposed between the individual air duct section and each of the semiconductor manufacturing and processing apparatuses for cleaning and ventilating the air to be supplied to each of the semiconductor manufacturing and processing apparatuses.