Forming Point Contact Patents (Class 438/83)
-
Patent number: 12098069Abstract: A method of manufacturing a plurality of neural probes from a silicon wafer in which after neural probes are formed on one side of a silicon wafer, the other side of the silicon wafter is subject to a dicing process that separates and adjusts the thickness of the neural probes.Type: GrantFiled: December 2, 2021Date of Patent: September 24, 2024Inventor: Sangwoo Lee
-
Patent number: 11437528Abstract: Contact holes of solar cells are formed by laser ablation to accommodate various solar cell designs. Use of a laser to form the contact holes is facilitated by replacing films formed on the diffusion regions with a film that has substantially uniform thickness. Contact holes may be formed to deep diffusion regions to increase the laser ablation process margins. The laser configuration may be tailored to form contact holes through dielectric films of varying thicknesses.Type: GrantFiled: February 18, 2020Date of Patent: September 6, 2022Assignee: SunPower CorporationInventors: Gabriel Harley, David D. Smith, Tim Dennis, Ann Waldhauer, Taeseok Kim, Peter John Cousins
-
Patent number: 9263602Abstract: Contact holes of solar cells are formed by laser ablation to accommodate various solar cell designs. Use of a laser to form the contact holes is facilitated by replacing films formed on the diffusion regions with a film that has substantially uniform thickness. Contact holes may be formed to deep diffusion regions to increase the laser ablation process margins. The laser configuration may be tailored to form contact holes through dielectric films of varying thicknesses.Type: GrantFiled: October 23, 2013Date of Patent: February 16, 2016Assignee: SunPower CorporationInventors: Gabriel Harley, David D. Smith, Tim Dennis, Ann Waldhauer, Taeseok Kim, Peter John Cousins
-
Patent number: 8980663Abstract: An organic light emitting diode (OLED) display device and a method of fabricating the same are disclosed.Type: GrantFiled: July 18, 2013Date of Patent: March 17, 2015Assignee: Samsung Display Co., Ltd.Inventors: Won-Kyu Lee, Kyu-Sik Cho, Tae-Hoon Yang, Byoung-Kwon Choo, Sang-Ho Moon, Bo-Kyung Choi, Yong-Hwan Park, Joon-Hoo Choi, Min-Chul Shin, Yun-Gyu Lee
-
Patent number: 8956908Abstract: In image sensors and methods of manufacturing the same, a substrate has a photoelectric conversion area, a floating diffusion area and a recess between the photoelectric conversion area and the floating diffusion area. A plurality of photodiodes is vertically arranged inside the substrate in the photoelectric conversion area. A transfer transistor is arranged along a surface profile of the substrate having the recess and configured to transfer electric charges generated from the plurality of photodiodes to the floating diffusion area. The transfer transistor includes a gate insulation pattern on a sidewall and a bottom of the recess and on a surface of the substrate around the recess, and a gate conductive pattern including polysilicon doped with impurities and positioned on the gate insulation pattern along the surface profile of the substrate having the recess, wherein a cavity is in an upper surface of the gate conductive pattern.Type: GrantFiled: August 11, 2014Date of Patent: February 17, 2015Assignee: Samsung Electronics Co., Ltd.Inventor: Ihara Hisanori
-
Patent number: 8927324Abstract: A method for the production of a wafer-based, back-contacted heterojunction solar cell includes providing at least one absorber wafer. Metallic contacts are deposited as at least one of point contacts and strip contacts in a predetermined distribution on a back side of the at least one absorber wafer. The contacts have steep flanks that are higher than a cumulative layer thickness of an emitter layer and an emitter contact layer and are sheathed with an insulating sheath. The emitter layer is deposited over an entire surface of the back side of the at least one absorber wafer. The emitter contact layer is deposited over an entire surface of the emitter layer so as to form an emitter contact system. At least one of the emitter layer and the emitter contact layer is selectively removed so as to expose the steep flanks of the contacts that are covered with the insulating sheath.Type: GrantFiled: October 10, 2009Date of Patent: January 6, 2015Assignee: Helmholtz-Zentrum Berlin Fuer Materialien und Energie GmbHInventor: Rolf Stangl
-
Patent number: 8901555Abstract: A light sensing device is disclosed. The light sensing device includes a first light sensor and a second light sensor. The first light sensor formed on a substrate includes a first metal oxide semiconductor layer for absorbing a first light having a first waveband. The second light sensor formed on the substrate includes a second metal oxide semiconductor layer and an organic light-sensitive layer on the second metal oxide semiconductor layer for absorbing a second light having a second waveband.Type: GrantFiled: July 17, 2012Date of Patent: December 2, 2014Assignee: E Ink Holdings Inc.Inventors: Chia-Chun Yeh, Henry Wang, Wei-Chou Lan, Ted-Hong Shinn
-
Patent number: 8852991Abstract: Provided is a method of manufacturing a solar cell. The method includes: preparing a substrate with a rear electrode; and forming a copper indium gallium selenide (CIGS) based light absorbing layer on the rear electrode at a substrate temperature of room temperature to about 350° C., wherein the forming of the CIGS based light absorbing layer includes projecting an electron beam on the CIGS based light absorbing layer.Type: GrantFiled: December 30, 2011Date of Patent: October 7, 2014Assignee: Electronics and Telecommunications Research InstituteInventor: Yong-Duck Chung
-
Patent number: 8815631Abstract: A silicon solar cell has doped amorphous silicon contacts formed on a tunnel silicon oxide layer on a surface of a silicon substrate. High temperature processing is unnecessary in fabricating the solar cell.Type: GrantFiled: May 25, 2010Date of Patent: August 26, 2014Assignee: SunPower CorporationInventor: Peter John Cousins
-
Patent number: 8803126Abstract: A solid-state imaging device includes a first electrode, a second electrode disposed opposing to the first electrode, and a photoelectric conversion layer, which is disposed between the first electrode and the second electrode and in which narrow gap semiconductor quantum dots are dispersed in a conductive layer, wherein one electrode of the first electrode and the second electrode is formed from a transparent electrode and the other electrode is formed from a metal electrode or a transparent electrode.Type: GrantFiled: August 22, 2013Date of Patent: August 12, 2014Assignee: Sony CorporationInventor: Atsushi Toda
-
Publication number: 20140196776Abstract: Disclosed are a solar cell apparatus and a method of fabricating the same. The solar cell apparatus includes a substrate, a first electrode layer on the substrate, a plurality of light absorbing columns on the first electrode layer, and a second electrode layer on the light absorbing columns.Type: ApplicationFiled: May 30, 2012Publication date: July 17, 2014Applicant: LG INNOTEK CO., LTD.Inventor: Kyung Eun Park
-
Patent number: 8748210Abstract: A semiconductor device comprises a semiconductor substrate, and a multilayer wiring structure arranged on the semiconductor substrate, the multilayer wiring structure including a plurality of first electrically conductive lines, an insulating film covering the plurality of first electrically conductive lines, and a second electrically conductive line arranged on the insulating film so as to intersect the plurality of first electrically conductive lines, wherein the insulating film has gaps in at least some of a plurality of regions where the plurality of first electrically conductive lines and the second electrically conductive line intersect each other, and a width of the gap in a direction along the second electrically conductive line is not larger than a width of the first electrically conductive line.Type: GrantFiled: December 7, 2012Date of Patent: June 10, 2014Assignee: Canon Kabushiki KaishaInventor: Takeshi Aoki
-
Patent number: 8742436Abstract: The present invention relates to an organic light emitting display device which can prevent a light compensation layer from cracking and a method for fabricating the same.Type: GrantFiled: September 25, 2012Date of Patent: June 3, 2014Assignee: LG Display Co., Ltd.Inventors: Jun-Jung Kim, Hee-Suk Pang
-
Patent number: 8728922Abstract: A method for producing monocrystalline n-silicon solar cells having a rear-side passivated p+ emitter and rear-side, spatially separate heavily doped n++-base regions near the surface, as well as an interdigitated rear-side contact finger structure, which is in conductive connection with the p+-emitter regions and the n++-base regions. An aluminum thin layer or an aluminum-containing thin layer is first deposited on the rear side of the n-silicon wafer, and the thin layer is subsequently structured so that openings are obtained in the region of the future base contacts. In a further process step, the aluminum is then diffused into the n-silicon wafer in order to form a structured emitter layer.Type: GrantFiled: February 11, 2009Date of Patent: May 20, 2014Assignee: SolarWorld Industries-Thueringen GmbHInventors: Hans-Joachim Krokoszinski, Jan Lossen
-
Patent number: 8722453Abstract: The method includes: steps of forming an n-type diffusion layer having an n-type impurity diffused thereon at a first surface side of a p-type silicon substrate; forming a reflection prevention film on the n-type diffusion layer; forming a back-surface passivation film made of an SiONH film on a second surface of the silicon substrate; forming a paste material containing silver in a front-surface electrode shape on the reflection prevention film; forming a front surface electrode that is contacted to the n-type diffusion layer by sintering the silicon substrate; forming a paste material containing a metal in a back-surface electrode shape on the back-surface passivation film; and forming a back surface electrode by melting a metal in the paste material by irradiating laser light onto a forming position of the back surface electrode and by solidifying the molten metal.Type: GrantFiled: April 14, 2009Date of Patent: May 13, 2014Assignee: Mitsubishi Electric CorporationInventor: Mitsunori Nakatani
-
Patent number: 8716596Abstract: A silicon solar cell having a silicon substrate includes p-type and n-type emitters on a surface of the substrate, the emitters being doped nano-particles of silicon. To reduce high interface recombination at the substrate surface, the nano-particle emitters are preferably formed over a thin interfacial tunnel oxide layer on the surface of the substrate.Type: GrantFiled: February 3, 2010Date of Patent: May 6, 2014Assignee: SunPower CorporationInventor: Richard M. Swanson
-
Publication number: 20140020746Abstract: A method of forming point metal electrical contacts to a semiconductor surface of a semiconductor device is provided. In a first step a first metal layer is formed over the semiconductor surface. The first metal layer is then anodised to create a porous metal-oxide layer formed over the semiconductor surface. The pores in the porous metal-oxide layer will thus form an array of openings in the porous metal-oxide layer. A contact metal layer is then formed over the porous metal-oxide layer such that parts of the contact metal layer extend into openings of the array of openings. The contact metal layer electrically contacts the semiconductor surface through the array of openings in the porous metal-oxide layer. A dielectric layer may optionally be formed over the semiconductor surface and the porous metal-oxide layer the formed over the dielectric layer and the contact metal then contacts the semiconductor surface through the dielectric layer.Type: ApplicationFiled: May 17, 2011Publication date: January 23, 2014Applicant: NewSouth Innovations Pty LimitedInventors: Alison Joan Lennon, Pei Hsuan Lu, Yang Chen
-
Patent number: 8507789Abstract: A solar cell and a method of manufacturing the same are disclosed. The solar cell includes a substrate of a first conductive type having at least one via hole; an emitter layer only on at least a portion of the via hole and at least one selected from a group consisting of an incident surface and side surfaces of the substrate, the emitter layer having a second conductive type opposite the first conductive type; at least one first electrode on the incident surface, the first electrode being electrically connected to the emitter layer; a second electrode connected to an opposite surface to the incident surface; and at least one first electrode current collector on the opposite surface, the at least one first electrode current collector being insulated from the second electrode and being electrically connected to the at least one first electrode through the via hole.Type: GrantFiled: May 18, 2012Date of Patent: August 13, 2013Assignee: LG Electronics Inc.Inventors: Jihoon Ko, Juwan Kang, Jonghwan Kim, Daehee Jang
-
Patent number: 8481847Abstract: A solar cell and a method of manufacturing the same are disclosed. The solar cell includes a substrate of a first conductive type having at least one via hole; an emitter layer only on at least a portion of the via hole and at least one selected from a group consisting of an incident surface and side surfaces of the substrate, the emitter layer having a second conductive type opposite the first conductive type; at least one first electrode on the incident surface, the first electrode being electrically connected to the emitter layer; a second electrode connected to an opposite surface to the incident surface; and at least one first electrode current collector on the opposite surface, the at least one first electrode current collector being insulated from the second electrode and being electrically connected to the at least one first electrode through the via hole.Type: GrantFiled: May 18, 2012Date of Patent: July 9, 2013Assignee: LG Electronics Inc.Inventors: Jihoon Ko, Juwan Kang, Jonghwan Kim, Daehee Jang
-
Patent number: 8394650Abstract: A laminated module or panel of solar cells and a laminating method for making same comprise a top layer of melt flowable optically transparent molecularly flexible thermoplastic and a rear sheet of melt flowable insulating molecularly flexible thermoplastic both melt flowing at a temperature between about 80° C. and 250° C. and having a low glass transition temperature. Solar cells are encapsulated by melt flowing the top layer and rear sheet, and electrical connections are provided between front and back contacts thereof. Light passing through the transparent top layer impinges upon the solar cells and the laminated module exhibits sufficient flexural modulus without cross-linking chemical curing. Electrical connections may be provided by melt flowable electrically conductive molecularly flexible thermoplastic adhesive or by metal strips or by both.Type: GrantFiled: June 7, 2011Date of Patent: March 12, 2013Assignee: Amerasia International Technology, Inc.Inventor: Kevin Kwong-Tai Chung
-
Patent number: 8395043Abstract: A solar cell includes a photoactive, semiconductive absorber layer configured to generate excess charge carriers of opposed polarity by light incident on a front of the absorber layer during operation. The absorber layer is configured to separate and move, via at least one electric field formed in the absorber layer, the photogenerated excess charge carriers of opposed polarity over a minimal effective diffusion length Leff,min. The absorber layer has a thickness Lx of 0<Lx?Leff,min. First contact elements are configured to remove the excess charge carriers of a first polarity on a rear of the absorber layer. Second contact elements are configured remove the excess charge carriers of a second polarity on the rear of the absorber layer. At least one undoped, electrically insulating second passivation region is disposed in an alternating, neighboring arrangement with a first passivation region on the rear of the absorber layer.Type: GrantFiled: June 1, 2010Date of Patent: March 12, 2013Assignee: Helmholtz-Zentrum Berlin fuer Materialien und Energie GmbHInventors: Rolf Stangl, Bernd Rech
-
Patent number: 8367924Abstract: The present invention relates to methods and apparatuses for providing a buried insulator isolation for solar cell contacts. According to certain aspects, the invention places a buried oxide under the emitter of a polysilicon emitter solar cell. The oxide provides an excellent passivation layer over most of the surface. Holes in the oxide provide contact areas, increasing the current density to enhance efficiency. The oxide isolates the contacts from the substrate, achieving the advantage of a selective emitter structure without requiring deep diffusions. The oxide further enables use of screen printing on advanced shallow emitter cells. Positioning of the grid lines close to the openings also enables use of a very thin emitter to maximize blue response.Type: GrantFiled: January 27, 2009Date of Patent: February 5, 2013Assignee: Applied Materials, Inc.Inventors: Peter Borden, Li Xu
-
Patent number: 8361836Abstract: A method for manufacturing a photoelectric conversion element and a photoelectric conversion element manufactured by the manufacturing method. The method includes the steps of forming a p-type impurity diffusion layer by diffusing boron into a silicon substrate, forming an oxidation control mask on a surface of the p-type impurity diffusion layer in an area corresponding to an area where an electrode for p-type is to be formed, forming a thermal silicon oxide film on the surface of the p-type impurity diffusion layer, exposing part of the surface of the p-type impurity diffusion layer by removing the oxidation control mask formed on the surface of the p-type impurity diffusion layer in the area corresponding to the area where the electrode for p-type is to be formed, and forming the electrode for p-type on the part of the surface of the p-type impurity diffusion layer exposed by the removal of the oxidation control mask.Type: GrantFiled: March 15, 2010Date of Patent: January 29, 2013Assignee: Sharp Kabushiki KaishaInventor: Tsutomu Yamazaki
-
Patent number: 8361826Abstract: A method of manufacturing a thin film solar cell includes steps of preparing a substrate on which unit cells are defined, forming transparent conducive layers on the substrate and corresponding to the unit cells, respectively, the transparent conductive layers spaced apart from each other with a first separation line therebetween, forming light-absorbing layers on the transparent conductive layers and corresponding to the unit cells, respectively, the light-absorbing layers spaced apart from each other with a second separation line therebetween, forming a third separation line in each of the light-absorbing layers, the third separation line spaced apart from the second separation line, forming a reflection material layer by disposing a silk screen over the third separation line and applying a conductive paste, and forming reflection electrodes corresponding to the unit cells, respectively, by sintering the reflection material layer.Type: GrantFiled: December 4, 2009Date of Patent: January 29, 2013Assignee: LG Display Co., Ltd.Inventors: Tae-Youn Kim, Won-Seo Park, Jeong-Woo Lee, Seong-Kee Park, Kyung-Jin Shim
-
Patent number: 8338220Abstract: Embodiments of the invention are directed to methods and apparatus for processing of a solar substrate for making a photovoltaic device. In particular, methods and apparatus for creating a negatively charged passivation layer by are provided.Type: GrantFiled: February 6, 2009Date of Patent: December 25, 2012Assignee: Applied Materials, Inc.Inventors: Peter G. Borden, Christopher Sean Olsen
-
Patent number: 8329495Abstract: A method of forming a PV module includes forming conductors on a top surface of a PV coated substrate; forming insulators on the top surface of the PV coated substrate; and cutting the PV coated substrate to form a plurality of individual PV cells. The PV coated substrate is cut so that each of the PV cells has some of the conductors and an insulator on its top surface. Multiple PV cells are then joined to form a PV module by attaching an edge of a first one of the PV cells under an edge of a second one of the PV cells so that at least a portion of the conductors on the first PV cell electrically contacts a bottom surface of the second PV cell.Type: GrantFiled: February 16, 2011Date of Patent: December 11, 2012Assignee: Preco, Inc.Inventor: Chris Walker
-
Patent number: 8294837Abstract: A sensor array substrate, a display device including the sensor array substrate, and a method of manufacturing the sensor array substrate are provided. The sensor array substrate includes a substrate, a first sensor formed on a first pixel area of the substrate and configured to detect light, an overcoat layer formed on the first sensor, and a shield layer formed over the overcoat layer, wherein the shield layer overlaps the first sensor.Type: GrantFiled: October 5, 2010Date of Patent: October 23, 2012Assignee: Samsung Display Co., Ltd.Inventors: Woong-Kwon Kim, Dae-Cheol Kim, Dong-Kwon Kim, Ki-Hun Jeong, Sung-Hoon Yang, Sang-Youn Han, Suk-Won Jung, Byeong-Hoon Cho, Kyung-Sook Jeon, Seung-Mi Seo, Jung-Suk Bang, Mi-Seon Seo
-
Patent number: 8273596Abstract: Process for producing strip-shaped and/or point-shaped electrically conducting contacts on a semiconductor component like a solar cell, includes the steps of applying a moist material forming the contacts in a desired striplike and/or point-like arrangement on at least one exterior surface of the semiconductor component; drying the moist material by heating the semiconductor component to a temperature T1 and keeping the semiconductor element at temperature T1 over a time t1; sintering the dried material by heating the semiconductor component to a temperature T2 and keeping the semiconductor component at temperature T2 over a time t2; cooling the semiconductor component to a temperature T3 that is equal or roughly equal to room temperature, and keeping the semiconductor component at temperature T3 over a time T3; cooling the semiconductor component to a temperature T4 with T4??35° C.Type: GrantFiled: May 17, 2010Date of Patent: September 25, 2012Assignee: Schott Solar AGInventors: Henning Nagel, Wilfried Schmidt, Ingo Schwirtlich, Dieter Franke
-
Patent number: 8216873Abstract: Light is illuminated from a back-surface side of a silicon substrate 4. A back-illuminated type imaging device 100 reads out, from a front-surface side of the silicon substrate 4, charges that are generated in the silicon substrate 4 in response to the illuminated light, so as to perform imaging. The back-illuminated type imaging device 100 includes pad portions 17 formed on the back surface of the semiconductor substrate 4, and a plurality of pillars 9 that are formed in the semiconductor substrate 4, are made of a conductive material and electrically connect wiring portions 12 formed on the front surface of the semiconductor substrate 4 and the pad portions 17 to each other.Type: GrantFiled: May 4, 2011Date of Patent: July 10, 2012Assignee: Fujifilm CorporationInventor: Shinji Uya
-
Patent number: 8207443Abstract: The present invention relates to electrical contacts in a semiconductor device, and more particularly to methods and apparatuses for providing point contacts in a polysilicon emitter or HIT type solar cell. According to certain aspects, the invention uses a dielectric layer interposed between the substrate and a conductive layer to provide a limited area over which junction current can flow. The benefit is that the metal grid conductors do not need to align to the contacts, and can be applied freely without registration. Another benefit of the invention is that it provides increased efficiency for poly emitter and HIT cells through use of point contacts to increase current density. A further benefit is that patterning can be accomplished using low cost methods such as inclusion masking, screen printing or laser ablation. A still further benefit is that final contacts do not need alignment to the point contacts, eliminating registration required for conventional point contact designs.Type: GrantFiled: January 27, 2009Date of Patent: June 26, 2012Assignee: Applied Materials, Inc.Inventor: Peter Borden
-
Publication number: 20110316427Abstract: A photodiode (10) according to the present invention is provided with a p-type semiconductor region (11), an i-type semiconductor region (12) and an n-type semiconductor region (13). A protection film (9) provided on the surface of the photodiode has been removed from at least a light receiving portion of the photodiode (10). Accordingly, the present invention provides the photodiode (10) that has less changes in its characteristics even with the prolonged use and a display device that uses the photodiode (10).Type: ApplicationFiled: February 3, 2010Publication date: December 29, 2011Applicant: SHARP KABUSHIKI KAISHAInventor: Nami Okajima
-
Patent number: 8003530Abstract: The present invention relates to a method for metallizing semiconductor components in which aluminium is used. In particular in the case of products in which the process costs play a big part, such as e.g. solar cells based on silicon, a cost advantage can be achieved with the invention. In addition, the present invention relates to the use of the method, for example in the production of solar cells.Type: GrantFiled: March 6, 2009Date of Patent: August 23, 2011Assignee: Fraunhofer-Gesellschaft zur Forderung der Angewandten Forschung E.V.Inventors: Andreas Grohe, Jan-Frederik Nekarda, Oliver Schultz-Wittmann
-
Patent number: 7943409Abstract: The present invention relates to a photodiode of an image sensor using a three-dimensional multi-layer substrate, and more particularly, to a method of implementing a buried type photodiode and a structure thereof, and a trench contact method for connecting a photodiode in a multi-layer substrate and a transistor for signal detection.Type: GrantFiled: August 31, 2010Date of Patent: May 17, 2011Assignees: Lumiense Photonics, Inc., Hanvision Co., Ltd.Inventor: Robert Steven Hannebauer
-
Publication number: 20110039367Abstract: An improved method of producing solar cells utilizes a mask which is fixed relative to an ion beam in an ion implanter. The ion beam is directed through a plurality of apertures in the mask toward a substrate. The substrate is moved at different speeds such that the substrate is exposed to an ion dose rate when the substrate is moved at a first scan rate and to a second ion dose rate when the substrate is moved at a second scan rate. By modifying the scan rate, various dose rates may be implanted on the substrate at corresponding substrate locations. This allows ion implantation to be used to provide precise doping profiles advantageous for manufacturing solar cells.Type: ApplicationFiled: August 10, 2010Publication date: February 17, 2011Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.Inventors: Nicholas P.T. Bateman, Steven M. Anella, Benjamin B. Riordon, Atul Gupta
-
Publication number: 20100297801Abstract: Process for producing strip-shaped and/or point-shaped electrically conducting contacts on a semiconductor component like a solar cell, includes the steps of applying a moist material forming the contacts in a desired striplike and/or point-like arrangement on at least one exterior surface of the semiconductor component; drying the moist material by heating the semiconductor component to a temperature T1 and keeping the semiconductor element at temperature T1 over a time t1; sintering the dried material by heating the semiconductor component to a temperature T2 and keeping the semiconductor component at temperature T2 over a time t2; cooling the semiconductor component to a temperature T3 that is equal or roughly equal to room temperature, and keeping the semiconductor component at temperature T3 over a time T3; cooling the semiconductor component to a temperature T4 with T4??35° C.Type: ApplicationFiled: May 17, 2010Publication date: November 25, 2010Applicant: SCHOTT SOLAR GMBHInventors: Henning NAGEL, Wilfried SCHMIDT, Ingo SCHWIRTLICH, Dieter FRANKE
-
Patent number: 7838318Abstract: The present invention relates to a photodiode of an image sensor using a three-dimensional multi-layer substrate, and more particularly, to a method of implementing a buried type photodiode and a structure thereof, and a trench contact method for connecting a photodiode in a multi-layer substrate and a transistor for signal detection.Type: GrantFiled: March 11, 2008Date of Patent: November 23, 2010Assignee: Lumiense Photonics, Inc.Inventor: Robert Steven Hannebauer
-
Patent number: 7790493Abstract: Disclosed herein is a method of fabricating a device having a microstructure. The method includes forming a connector on a semiconductor substrate, coating the connector with a polymer layer, and immersing the semiconductor substrate and the coated connector in an etchant solution to form the microstructure from the semiconductor substrate and to release the coated connector and the microstructure from the semiconductor substrate such that the microstructure remains coupled to a further element of the device via the coated connector. In some cases, the microstructure is defined by forming an etch stop in the semiconductor substrate, and the microstructure and the semiconductor substrate are coated with a polymer layer, which may then be selectively patterned. The microstructure may then be released from the semiconductor substrate in accordance with the etch stop.Type: GrantFiled: May 25, 2006Date of Patent: September 7, 2010Assignee: The Regents of the University of MichiganInventors: Kensall D. Wise, Mayurachat Ning Gulari, Ying Yao
-
Patent number: 7786545Abstract: Disclosed are an image sensor and a method for manufacturing the same. The image sensor includes a substrate provided with a transistor circuit, first and second interconnections separated from each other on the substrate, a first conductive-type conductive layer formed at side surfaces of the first interconnection, a second conductive-type conductive layer formed at side surfaces of the second interconnection, and an intrinsic layer formed between the first and second conductive-type conductive layers thereby forming a P-I-N structure.Type: GrantFiled: August 3, 2009Date of Patent: August 31, 2010Assignee: Dongbu Hitek Co., Ltd.Inventor: Seoung Hyun Kim
-
Patent number: 7767487Abstract: Embodiments of the invention are concerned with a method of manufacturing a radiation detector having one or more conductive contacts on a semiconductor substrate, and comprise the steps of: applying a first conductive layer to a first surface of the semiconductor substrate; applying a second conductive layer to form a plurality of contiguous layers of conductive materials, said plurality of contiguous layers including said first conductive layer; and selectively removing parts of said plurality of contiguous layers so as to form said conductive contacts, the conductive contacts defining one or more radiation detector cells in the semiconductor substrate.Type: GrantFiled: October 23, 2003Date of Patent: August 3, 2010Assignee: IPL Intellectual Property Licensing LimitedInventors: Kimmo Puhakka, Ian Benson
-
Publication number: 20090283141Abstract: This invention relates to a method for contacting solar wafers containing one or more layers of temperature sensitive passivation layers by first creating local openings in the passivation layer(s) and then fill the openings with an electric conducting material. In this way, it becomes possible to avoid the relatively high temperatures needed in the conventional method for contacting solar wafers containing one or more passivation layer(s), and thus maintain the excellent passivation properties of newly developed temperature sensitive passivation layer(s) during and after the contacting.Type: ApplicationFiled: April 12, 2007Publication date: November 19, 2009Applicant: Renewable Energy Corporation ASAInventors: Andreas Bentzen, Erik Sauar
-
Patent number: 7588951Abstract: A method of packaging a first device having a first major surface and a second major surface includes forming a first layer over a second major surface of the first device and around sides of the first device and leaving the first major surface of the first device exposed, wherein the first layer is selected from the group consisting of an encapsulant and a polymer; forming a first dielectric layer over the first major surface of the first device, forming a via in the first dielectric layer, forming a seed layer within the via and over a portion of the first dielectric layer, physically coupling a connector to the seed layer, and plating a conductive material over the seed layer to form a first interconnect in the first via and over a portion of the first dielectric layer.Type: GrantFiled: November 17, 2006Date of Patent: September 15, 2009Assignee: Freescale Semiconductor, Inc.Inventors: Marc A. Mangrum, Kenneth R. Burch
-
Patent number: 7585696Abstract: Disclosed are an image sensor and a method for manufacturing the same. The image sensor includes a substrate provided with a transistor circuit, first and second interconnections separated from each other on the substrate, a first conductive-type conductive layer formed at side surfaces of the first interconnection, a second conductive-type conductive layer formed at side surfaces of the second interconnection, and an intrinsic layer formed between the first and second conductive-type conductive layers thereby forming a P-I-N structure.Type: GrantFiled: August 21, 2007Date of Patent: September 8, 2009Assignee: Dongbu Hitek Co., Ltd.Inventor: Seoung Hyun Kim
-
Patent number: 7432125Abstract: A CMOS image sensor-manufacturing method includes forming a photodiode on a substrate, forming an insulating layer over the substrate, forming a contact hole in the insulating layer, and forming a gate terminal over the insulating layer. The gate terminal is connected to the photodiode through the contact hole.Type: GrantFiled: October 1, 2004Date of Patent: October 7, 2008Assignee: Dongbu Electronics Co., Ltd.Inventor: In-Gyun Jeon
-
Patent number: 7402736Abstract: A probe of a scanning probe microscope having a sharp tip and an increased electric characteristic by fabricating a planar type of field effect transistor and manufacturing a conductive carbon nanotube on the planar type field effect transistor. To achieve this, the present invention provides a method for fabricating a probe having a field effect transistor channel structure including fabricating a field effect transistor, making preparations for growing a carbon nanotube at a top portion of a gate electrode of the field effect transistor, and generating the carbon nanotube at the top portion of the gate electrode of the field effect transistor.Type: GrantFiled: December 23, 2005Date of Patent: July 22, 2008Assignee: POSTECH FoundationInventors: Wonkyu Moon, Geunbae Lim, Sang Hoon Lee
-
Patent number: 7364938Abstract: This invention relates to a process for making a semiconductor device comprising the following steps: a doped region with a first type of conductivity is made on a first principal face of a semiconductor substrate and at least one window is made, a first metallisation area is deposited on the doped region, a dielectric layer is deposited on at least the window and the first metallisation area, at least a first opening is etched in the dielectric layer at the window to accommodate a doped region with a second type of conductivity while arranging an undoped portion of the semiconductor substrate laterally between the doped regions, the substrate is doped to create the doped region with the second type of conductivity, a second metallisation area is deposited. Application particularly for solar cells in thin layer.Type: GrantFiled: April 27, 2004Date of Patent: April 29, 2008Assignee: Commissariat a l'Energie AtomiqueInventors: Pierre-Jean Ribeyron, Marc Pirot
-
Patent number: 7229676Abstract: Processes for effecting thermal transfer of electroactive organic material are disclosed wherein unwanted portions of a layer of electroactive organic material supported by a donor element are removed or transferred from the layer by thermal transfer, particularly laser-induced thermal transfer, leaving a desired pattern of the electroactive organic material on the donor element. The electroactive organic material may be an organic material exhibiting electroluminescence, charge transport, charge injection, electrical conductivity, semiconductivity and/or exciton blocking. The layer of electroactive organic material may comprise more than one layer of different types of electroactive organic material. The exposure pattern is a negative image of the desired pattern. The electroactive organic material of the desired pattern is not, therefore, exposed to the heat which can cause decomposition.Type: GrantFiled: September 8, 2004Date of Patent: June 12, 2007Assignee: E. I. du Pont de Nemours and CompanyInventor: Graciela B. Blanchet-Fincher
-
Patent number: 7217883Abstract: A solar cell involving a silicon wafer having a basic doping, a light-receiving front side and a backside, which is provided with an interdigital semiconductor pattern, which interdigital semiconductor pattern has a first pattern of at least one first diffusion zone having a first doping and a second pattern of at least one second diffusion zone, separated from the first diffusion zone(s) and having a second doping that differs from the first doping, wherein each second diffusion zone is arranged along the sides of at least one groove extending from the backside into the silicon wafer.Type: GrantFiled: November 26, 2002Date of Patent: May 15, 2007Assignee: Shell Solar GmbHInventor: Adolf Münzer
-
Patent number: 6988900Abstract: A surface mount connector assembly for mounting to a printed wiring board (PWB) in a low-profile manner. The height of the surface mount connector assembly is diminished because the connector assembly extends from one side of the PWB to the other through an opening in the PWB. The surface mount connector assembly includes an outer housing portion having a plurality of openings therethrough for receiving a plurality of electrical contacts. The surface mount connector also includes an inner housing portion to be nested within the outer housing portion. Each of the electrical contacts are configured to be received within one of the openings in the inner housing portion such that a portion of each contact extends into the interior of the inner housing portion and another portion of each contact extends to the exterior of the inner housing portion.Type: GrantFiled: December 17, 2004Date of Patent: January 24, 2006Assignee: Scinetific-Atlanta, Inc.Inventor: Douglas L. Meister
-
Patent number: 6872588Abstract: A structure and method of using microfluidic channels to form an array of semiconductor devices is described. The microfluidic channels have been found to be particularly useful when formed in a self aligned process and used to interconnect a series of thin film transistor (TFT) devices.Type: GrantFiled: November 22, 2002Date of Patent: March 29, 2005Assignee: Palo Alto Research Center Inc.Inventors: Michael L. Chabinyc, William S. Wong, Robert A. Street, Kateri E. Paul
-
Patent number: RE43948Abstract: Embodiments of the invention are concerned with a method of manufacturing a radiation detector having one or more conductive contacts on a semiconductor substrate, and comprise the steps of: applying a first conductive layer to a first surface of the semiconductor substrate; applying a second conductive layer to form a plurality of contiguous layers of conductive materials, said plurality of contiguous layers including said first conductive layer; and selectively removing parts of said plurality of contiguous layers so as to form said conductive contacts, the conductive contacts defining one or more radiation detector cells in the semiconductor substrate.Type: GrantFiled: October 23, 2003Date of Patent: January 29, 2013Assignee: Siemens AktiengesellschaftInventors: Kimmo Puhakka, Ian Benson