And Cadmium Sulfide Compound Semiconductive Component Patents (Class 438/86)
  • Patent number: 9147582
    Abstract: A method of manufacturing semiconductor assemblies is provided. The manufacturing method includes thermally processing a first semiconductor assembly comprising a first semiconductor layer disposed on a first support and thermally processing a second semiconductor assembly comprising a second semiconductor layer disposed on a second support. The first and second semiconductor assemblies are thermally processed simultaneously, and the first and second semiconductor assemblies are arranged such that the first semiconductor layer faces the second semiconductor layer during the thermal processing.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: September 29, 2015
    Assignee: First Solar, Inc.
    Inventors: Jinbo Cao, Bastiaan Arie Korevaar, George Theodore Dalakos, Aharon Yakimov, Scott D. Feldman-Peabody, Dalong Zhong, Juan Carlos Rojo
  • Patent number: 9013019
    Abstract: Avalanche diode-type semiconductor structure (1) intended to receive electromagnetic radiation in a given wavelength. The structure (1) comprises a semiconductor multiplication zone (310) including a majority carrier concentration, and delimitation means suitable for laterally delimiting the multiplication zone (310). The delimitation means comprise a semiconductor zone (410) surrounding the multiplication zone (310) and comprising a forbidden energy gap greater than the forbidden energy gap of the major part (320) of the multiplication zone (310), said zone (410) having a type of conductivity opposite that of the multiplication zone (310) with a majority carrier concentration at least 10 times greater than that of the multiplication zone (310). The invention also relates to a process for producing an avalanche photodiode-type semiconductor structure.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: April 21, 2015
    Assignee: Commissariat à l'Énergie atomique et aux Énergies Alternatives
    Inventor: Johan Rothman
  • Patent number: 8980682
    Abstract: Methods of forming absorber layers in a TFPV device are provided. Methods are described to provide the formation of metal oxide films and heating the metal oxide films in the presence of a chalcogen to form a metal-oxygen-chalcogen alloy. Methods are described to provide the formation of metal oxide films, forming a layer of elemental chalcogen on the metal oxide film, and heating the stack to form a metal-oxygen-chalcogen alloy. In some embodiments, the metal oxide film includes zinc oxide and the chalcogen includes selenium.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: March 17, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Haifan Liang, Jeroen Van Duren
  • Patent number: 8963149
    Abstract: A thin film transistor including an oxide semiconductor with favorable electrical characteristics is provided. The thin film transistor includes a gate electrode provided over a substrate, a gate insulating film provided over the gate electrode, an oxide semiconductor film provided over the gate electrode and on the gate insulating film, a metal oxide film provided on the oxide semiconductor film, and a metal film provided on the metal oxide film. The oxide semiconductor film is in contact with the metal oxide film, and includes a region whose concentration of metal is higher than that of any other region in the oxide semiconductor film (a high metal concentration region). In the high metal concentration region, the metal contained in the oxide semiconductor film may be present as a crystal grain or a microcrystal.
    Type: Grant
    Filed: June 6, 2014
    Date of Patent: February 24, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akiharu Miyanaga, Junichiro Sakata, Masayuki Sakakura, Masahiro Takahashi, Hideyuki Kishida, Shunpei Yamazaki
  • Patent number: 8952381
    Abstract: High field-effect mobility is provided for a semiconductor device including an oxide semiconductor. Further, a highly reliable semiconductor device including the transistor is provided. In a transistor in which a stack of oxide semiconductor layers is provided over a gate electrode layer with a gate insulating layer provided therebetween, an oxide semiconductor layer functioning as a current path (channel) of the transistor and containing an n-type impurity is sandwiched between oxide semiconductor layers having lower conductivity than the oxide semiconductor layer. In the oxide semiconductor layer functioning as the channel, a region on the gate insulating layer side contains the n-type impurity at a higher concentration than a region on the back channel side. With such a structure, the channel can be separated from the interface between the oxide semiconductor stack and the insulating layer in contact with the oxide semiconductor stack, so that a buried channel can be formed.
    Type: Grant
    Filed: June 18, 2013
    Date of Patent: February 10, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8927322
    Abstract: The present disclosure is directed to methods of forming different types of Cu2ZnSnS4 (CZTS) solar cells and Copper Indium Gallium DiSelenide (CIGS) solar cells that can be combinatorially varied and evaluated. These methodologies all incorporate the formation of site-isolated regions using a combinatorial processing tool and the use of these site-isolated regions to form the solar cell area. Therefore, multiple solar cells may be rapidly formed on a single substrate for use in combinatorial methodologies. Any of the individual processes of the methods described may be varied combinatorially to test varied process conditions or materials.
    Type: Grant
    Filed: May 3, 2011
    Date of Patent: January 6, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Upendra Avachat, Tony Chiang, Craig Hunter, Jian Li, Guizhen Zhang
  • Patent number: 8894826
    Abstract: A method and apparatus for forming a thin film of a copper indium gallium selenide (CIGS)-type material are disclosed. The method includes providing first and second targets in a common sputtering chamber. The first target includes a source of CIGS material, such as an approximately stoichiometric polycrystalline CIGS material, and the second target includes a chalcogen, such as selenium, sulfur, tellurium, or a combination of these elements. The second target provides an excess of chalcogen in the chamber. This can compensate, at least in part, for the loss of chalcogen from the CIGS-source in the first target, resulting in a thin film with a controlled stoichiometry which provides effective light absorption when used in a solar cell.
    Type: Grant
    Filed: September 17, 2010
    Date of Patent: November 25, 2014
    Inventors: Jesse A. Frantz, Jasbinder S. Sanghera, Robel Y. Bekele, Vinh Q Nguyen, Ishwar D. Aggarwal, Allan J. Bruce, Michael Cyrus, Sergey V. Frolov
  • Patent number: 8889468
    Abstract: A tandem photovoltaic cell. The tandem photovoltaic cell includes a bifacial top cell and a bottom cell. The top bifacial cell includes a top first transparent conductive oxide material. A top window material underlies the top first transparent conductive oxide material. A first interface region is disposed between the top window material and the top first transparent conductive oxide material. The first interface region is substantially free from one or more entities from the top first transparent conductive oxide material diffused into the top window material. A top absorber material comprising a copper species, an indium species, and a sulfur species underlies the top window material. A top second transparent conductive oxide material underlies the top absorber material. A second interface region is disposed between the top second transparent conductive oxide material and the top absorber material. The bottom cell includes a bottom first transparent conductive oxide material.
    Type: Grant
    Filed: February 18, 2011
    Date of Patent: November 18, 2014
    Assignee: Stion Corporation
    Inventor: Howard W. H. Lee
  • Patent number: 8889466
    Abstract: A method for forming a photovoltaic device includes forming an absorber layer with a granular structure on a conductive layer; conformally depositing an insulating protection layer over the absorber layer to fill in between grains of the absorber layer; and planarizing the protection layer and the absorber layer. A buffer layer is formed on the absorber layer, and a top transparent conductor layer is deposited over the buffer layer.
    Type: Grant
    Filed: April 12, 2013
    Date of Patent: November 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Talia S. Gershon, Supratik Guha, Jeehwan Kim, Mahadevaiyer Krishnan, Byungha Shin
  • Patent number: 8883549
    Abstract: Exemplary embodiments of the present disclosure are directed to improve p-type doping (p-doping) of cadmium telluride (CdTe) for CdTe-based solar cells, such as cadmium Sulfide (Cds)/CdTe solar cells. Embodiments can achieve improved p-doping of CdTe by creating a high density of cadmium (Cd) vacancies (VCd) and subsequently substituting a high density of substitutional defects and/or defect complexes for the Cd vacancies that were created. Formation of a high density of substitutional defects and defect complexes as a p-dopant can improve light-to-electricity conversion efficiency, doping levels or hole concentrations, junction band bending, and/or ohmic contact associated with p-type CdTe (p-CdTe) based solar cells.
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: November 11, 2014
    Assignee: New Jersey Institute of Technology
    Inventor: Ken K. Chin
  • Publication number: 20140261686
    Abstract: Photovoltaic devices with a zinc oxide layer replacing all or part of at least one of a window layer and a buffer layer, and methods of making the devices.
    Type: Application
    Filed: March 13, 2014
    Publication date: September 18, 2014
    Applicant: FIRST SOLAR, INC
    Inventors: Benyamin Buller, Daniel Damjanovic, Feng Liao, Rick C. Powell, Jigish Trivedi, Zhibo Zhao
  • Patent number: 8835212
    Abstract: Methods for developing and investigating materials and processes for various layers used in manufacturing CdTe, CIGS, and CZTS TFPV superstrate devices using high productivity combinatorial techniques is described. Typical layers subjected to the HPC techniques include the buffer layers, absorber layers, and the contact interface layers.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: September 16, 2014
    Assignee: Intermolecular, Inc.
    Inventor: Upendra Avachat
  • Patent number: 8829337
    Abstract: Novel structures of photovoltaic cells (also treated as solar cells) are provided. The cells are based on nanometer-scaled wires, tubes, and/or rods, which are made of electronic materials covering semiconductors, insulators or metallic in structure. These photovoltaic cells have large power generation capability per unit physical area over the conventional cells. These cells will have enormous applications in space, commercial, residential, and industrial applications.
    Type: Grant
    Filed: October 8, 2012
    Date of Patent: September 9, 2014
    Assignee: Banpil Photonics, Inc.
    Inventor: Achyut Kumar Dutta
  • Patent number: 8829517
    Abstract: A TFT substrate (20a) includes: an insulating substrate (10a); a plurality of source terminals (15) located on the insulating substrate (10a); and a first terminal cover (24) covering part of each of the source terminals (15) and made of an oxide semiconductor. The first terminal cover (24) is removed in a region R between adjacent ones of the source terminals (15).
    Type: Grant
    Filed: July 14, 2011
    Date of Patent: September 9, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshihito Hara, Yukinobu Nakata
  • Patent number: 8829512
    Abstract: A miniaturized semiconductor device including a transistor in which a channel formation region is formed using an oxide semiconductor film and variation in electric characteristics due to a short-channel effect is suppressed is provided. In addition, a semiconductor device whose on-state current is improved is provided. A semiconductor device is provided with an oxide semiconductor film including a pair of second oxide semiconductor regions which are amorphous regions and a first oxide semiconductor region located between the pair of second oxide semiconductor regions, a gate insulating film, and a gate electrode provided over the first oxide semiconductor region with the gate insulating film interposed therebetween. Hydrogen or a rare gas is added to the second oxide semiconductor regions.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: September 9, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8809678
    Abstract: CIGS absorber layers fabricated using coated semiconducting nanoparticles and/or quantum dots are disclosed. Core nanoparticles and/or quantum dots containing one or more elements from group 13 and/or IIIA and/or VIA may be coated with one or more layers containing elements group IB, IIIA or VIA. Using nanoparticles with a defined surface area, a layer thickness could be tuned to give the proper stoichiometric ratio, and/or crystal phase, and/or size, and/or shape. The coated nanoparticles could then be placed in a dispersant for use as an ink, paste, or paint. By appropriate coating of the core nanoparticles, the resulting coated nanoparticles can have the desired elements intermixed within the size scale of the nanoparticle, while the phase can be controlled by tuning the stoichiometry, and the stoichiometry of the coated nanoparticle may be tuned by controlling the thickness of the coating(s).
    Type: Grant
    Filed: May 7, 2012
    Date of Patent: August 19, 2014
    Assignee: aeris CAPITAL Sustainable IP Ltd.
    Inventors: Brian M. Sager, Dong Yu, Matthew R. Robinson
  • Patent number: 8809105
    Abstract: A method for processing a semiconductor assembly is presented. The method includes thermally processing a semiconductor assembly in a non-oxidizing atmosphere at a pressure greater than about 10 Torr. The semiconductor assembly includes a semiconductor layer disposed on a support, and the semiconductor layer includes cadmium and sulfur.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: August 19, 2014
    Assignee: First Solar, Inc.
    Inventors: Jinbo Cao, Bastiaan Arie Korevaar
  • Patent number: 8803144
    Abstract: The present disclosure relates to a thin film transistor substrate for flat panel display device including oxide semiconductor. The present disclosure suggests a thin film transistor substrate for flat panel display device comprising: a transparent substrate; a thin film transistor layer having an oxide semiconductor material disposed on the transparent substrate; a passivation layer disposed on the whole surface of the thin film transistor layer; a pixel electrode formed on the passivation layer and contact the thin film transistor layer through a contact hole formed at the passivation layer; and a first ultra violet light absorbing layer disposed on the whole surface of the pixel electrode. Absorbing all of ultra violet light and passing all of the visible light, the photo-thermal characteristic is enhanced and the transparency property is not degraded.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: August 12, 2014
    Assignee: LG Display Co., Ltd
    Inventors: Hoon Yim, Daehwan Kim, Byungkook Choi, Sul Lee
  • Patent number: 8791458
    Abstract: Disclosed is a semiconductor device which consumes low power and has high reliability and tolerance for electrostatic discharge. The semiconductor device includes, over a first substrate, a pixel portion and a driver circuit portion both of which have a thin film transistor having an oxide semiconductor layer. The semiconductor device further possesses a second substrate to which a first counter electrode layer and a second counter electrode layer are provided, and a liquid crystal layer is interposed between the first and second substrates. The first and second counter electrode layers are provided over the pixel portion and the driver circuit portion, respectively, and the second counter electrode layer has the same potential as the first counter electrode layer.
    Type: Grant
    Filed: November 21, 2013
    Date of Patent: July 29, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideaki Shishido
  • Patent number: 8791359
    Abstract: Novel structures of photovoltaic cells (also called as solar cells) are provided. The cells are based on nanoparticles or nanometer-scaled wires, tubes, and/or rods, which are made of electronic materials covering semiconductors, insulators, and may be metallic in structure. These photovoltaic cells have large power generation capability per unit physical area over the conventional cells. These cells will have enormous applications such as in space, commercial, residential and industrial applications.
    Type: Grant
    Filed: January 24, 2007
    Date of Patent: July 29, 2014
    Assignee: Banpil Photonics, Inc.
    Inventor: Achyut Kumar Dutta
  • Patent number: 8772768
    Abstract: A semiconductor device in which fluctuation in electric characteristics due to miniaturization is less likely to be caused is provided. The semiconductor device includes an oxide semiconductor film including a first region, a pair of second regions in contact with side surfaces of the first region, and a pair of third regions in contact with side surfaces of the pair of second regions; a gate insulating film provided over the oxide semiconductor film; and a first electrode that is over the gate insulating film and overlaps with the first region. The first region is a CAAC oxide semiconductor region. The pair of second regions and the pair of third regions are each an amorphous oxide semiconductor region containing a dopant. The dopant concentration of the pair of third regions is higher than the dopant concentration of the pair of second regions.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: July 8, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8766250
    Abstract: A thin film transistor including an oxide semiconductor with favorable electrical characteristics is provided. The thin film transistor includes a gate electrode provided over a substrate, a gate insulating film provided over the gate electrode, an oxide semiconductor film provided over the gate electrode and on the gate insulating film, a metal oxide film provided on the oxide semiconductor film, and a metal film provided on the metal oxide film. The oxide semiconductor film is in contact with the metal oxide film, and includes a region whose concentration of metal is higher than that of any other region in the oxide semiconductor film (a high metal concentration region). In the high metal concentration region, the metal contained in the oxide semiconductor film may be present as a crystal grain or a microcrystal.
    Type: Grant
    Filed: November 19, 2010
    Date of Patent: July 1, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akiharu Miyanaga, Junichiro Sakata, Masayuki Sakakura, Masahiro Takahashi, Hideyuki Kishida, Shunpei Yamazaki
  • Patent number: 8741687
    Abstract: A method for manufacturing a multilayered structure may include forming a transparent conductive oxide layer including cadmium stannate adjacent to a substrate and annealing the structure in an annealing environment including a reducing agent at a temperature greater than 500 degrees C. to crystallize the cadmium stannate.
    Type: Grant
    Filed: March 16, 2011
    Date of Patent: June 3, 2014
    Assignee: First Solar, Inc.
    Inventors: Zhibo Zhao, Dale Roberts, Yu Yang, Douglas Dauson
  • Patent number: 8726835
    Abstract: A chemical bath deposition apparatus is presented to prepare different thin films on plane substrates. In particular, it is useful to deposit CdS or ZnS buffer layers in manufacture of thin film solar cells. This deposition apparatus deposits thin films onto vertically travelling plane workpieces delivered by a conveyor belt. The thin films are deposited with continuously spraying the reaction solutions from their freshly mixed styles to gradually aged forms until the designed thickness is obtained. The substrates and the solutions are heated to a reaction temperature. During the deposition processes, the front surfaces of the substrates are totally covered with the sprayed solutions but the substrate backsides are remained dry. The reaction ambience inside the reactor can be isolated from the outside atmosphere. The apparatus is designed to generate a minimum amount of waste solutions for chemical treatments.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: May 20, 2014
    Inventor: Jiaxiong Wang
  • Patent number: 8685779
    Abstract: A method is provided for forming a Group VA-doped solution-processed metal chalcogenide. The method forms a first solution including a first material group, dissolved in solvent. A Group VA-containing material is added to the first solution. The Group VA-containing material may include arsenic (As), antimony (Sb), bismuth (Bi), or combinations thereof. The first solution is deposited on a conductive substrate, and a Group VA-doped first intermediate film is formed comprising metal precursors from corresponding members of the first material group. Thermal annealing is performed in an environment of selenium (Se), Se and hydrogen (H2), hydrogen selenide (H2Se), sulfur (S), S and H2, hydrogen sulfide (H2S), or combinations thereof. As a result, the metal precursors in the Group VA-doped first intermediate film are transformed, forming a Group VA-doped metal chalcogenide layer. In one aspect, an antimony-doped Cu—In—Ga—Se chalcogenide (CIGS) is formed.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: April 1, 2014
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Sean Vail, Alexey Koposov, Gary Foley
  • Patent number: 8674352
    Abstract: An apparatus is provided. In the apparatus, there is comprises a substrate with a first region of a first conductivity type, a second region of a second conductivity type that is substantially surrounded by the first region, and a third region of the second conductivity type that is substantially surrounded by the second region. A first dielectric layer is formed over the substrate, and a first conductive layer is formed over the first dielectric layer, which is configured to form a first electrode of a capacitor. A second dielectric layer is formed over the first conductive layer. A plate is formed over the second dielectric layer so as to form a second electrode of the capacitor. A cap is formed over the second dielectric layer, being spaced apart from the plate. A via is electrically coupled to the cap and the third region, extending through the first and second dielectric layers.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: March 18, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Kannan Soundarapandian, Benjamin Amey, Timothy P. Duryea
  • Publication number: 20140038344
    Abstract: Embodiments relate to a method including forming a layer of copper zinc tin sulfide (CZTS) on a first layer of molybdenum (Mo) and annealing the CZTS layer and the first Mo layer to form a layer of molybdenum disulfide (MoS2) between the layer of CZTS and the first layer of Mo. The method includes forming a back contact on a first surface of the CZTS layer opposite the first Mo layer and separating the first Mo layer and the MoS2 layer from the CZTS layer to expose a second surface of the CZTS layer opposite the first surface. The method further includes forming a buffer layer on the second surface of the CZTS layer.
    Type: Application
    Filed: August 1, 2012
    Publication date: February 6, 2014
    Applicant: International Business Machines Corporation
    Inventors: Nestor A. Bojarczuk, Keith E. Fogel, Supratik Guha, Byungha Shin
  • Patent number: 8629347
    Abstract: Novel structures of photovoltaic cells (also known as solar cells) are provided. The Cells are based on the nanometer-scaled wire, tubes, and/or rods, which are made of the electronics materials covering semiconductors, insulator or metallic in structure. These photovoltaic cells have large power generation capability per unit physical area over the conventional cells. These cells can have also high radiation tolerant capability. These cells will have enormous applications such as in space, in commercial, residential and industrial applications.
    Type: Grant
    Filed: September 30, 2012
    Date of Patent: January 14, 2014
    Assignee: Banpil Photonics, Inc.
    Inventors: Nobuhiko P. Kobayashi, Achyut K. Dutta
  • Patent number: 8624107
    Abstract: Novel structures of photovoltaic cells (also known as solar cells) are provided. The Cells are based on the nanometer-scaled wire, tubes, and/or rods, which are made of the electronics materials covering semiconductors, insulator or metallic in structure. These photovoltaic cells have large power generation capability per unit physical area over the conventional cells. These cells can have also high radiation tolerant capability. These cells will have enormous applications such as in space, in commercial, residential and industrial applications.
    Type: Grant
    Filed: September 30, 2012
    Date of Patent: January 7, 2014
    Assignee: Banpil Photonics, Inc.
    Inventors: Nobuhiko P. Kobayashi, Achyut K. Dutta
  • Patent number: 8624108
    Abstract: Novel structures of photovoltaic cells (also treated as solar cells) are provided. The cells are based on nanometer-scaled wires, tubes, and/or rods, which are made of electronic materials covering semiconductors, insulators or metallic in structure. These photovoltaic cells have large power generation capability per unit physical area over the conventional cells. These cells will have enormous applications in space, commercial, residential, and industrial applications.
    Type: Grant
    Filed: October 8, 2012
    Date of Patent: January 7, 2014
    Assignee: Banpil Photonics, Inc.
    Inventor: Achyut K. Dutta
  • Publication number: 20140000673
    Abstract: A photovoltaic device is presented. The device includes a first semiconductor layer disposed on a second semiconductor layer. The first semiconductor layer includes a compound having a metal species, sulfur, and oxygen. The metal species may include zinc, magnesium, tin, indium, or a combination thereof. Method for making a photovoltaic device is also presented.
    Type: Application
    Filed: June 29, 2012
    Publication date: January 2, 2014
    Applicant: GENERAL ELECTRIC COMPANY
    Inventors: Jinbo Cao, Bastiaan Arie Korevaar, Hongying Peng, Allan Robert Northrup
  • Patent number: 8618410
    Abstract: A method of manufacturing improved thin-film solar cells entirely by sputtering includes a high efficiency back contact/reflecting multi-layer containing at least one barrier layer consisting of a transition metal nitride. A copper indium gallium diselenide (Cu(InXGa1-X)Se2) absorber layer (X ranging from 1 to approximately 0.7) is co-sputtered from specially prepared electrically conductive targets using dual cylindrical rotary magnetron technology. The band gap of the absorber layer can be graded by varying the gallium content, and by replacing the gallium partially or totally with aluminum. Alternately the absorber layer is reactively sputtered from metal alloy targets in the presence of hydrogen selenide gas. RF sputtering is used to deposit a non-cadmium containing window layer of ZnS. The top transparent electrode is reactively sputtered aluminum doped ZnO. A unique modular vacuum roll-to-roll sputtering machine is described.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: December 31, 2013
    Assignee: MiaSole
    Inventor: Dennis R. Hollars
  • Patent number: 8617916
    Abstract: A chemical bath deposition method is presented to prepare different thin films on plane substrates. In particular, they are useful to deposit CdS or ZnS buffer layers in manufacture of thin film solar cells. This method and the deposition apparatus deposit thin films onto vertically travelling plane workpieces delivered by a conveyor belt. The thin films are deposited by continuously spraying the reaction solutions from their freshly mixed styles to gradually aged forms until the designed thickness is obtained. The substrates and the solutions are heated to a reaction temperature. During the deposition processes, the front surfaces of the substrates are totally covered with the sprayed solutions but the substrate backsides are remained dry. The reaction ambience inside the reactor can be isolated from the outside atmosphere. The method is designed to generate a minimum amount of waste solutions for chemical treatments.
    Type: Grant
    Filed: August 21, 2013
    Date of Patent: December 31, 2013
    Inventor: Jiaxiong Wang
  • Patent number: 8614393
    Abstract: A new photovoltaic (PV) cell structure, prepared on transparent substrate with transparent conductive oxide (TCO) layer and having nanorod zinc oxide layer. The cell has a thin conductive layer of doped zinc oxide deposited on the nanorod zinc oxide layer, an extremely thin blocking layer of titanium oxide or indium sulfide on the thin conductive layer, a buffer layer of indium sulfide on the extremely thin blocking layer, an absorber layer, comprising copper indium disulfide on said buffer layer and one electrode attached to the transparent conductive oxide layer and a second electrode attached to the absorber layer. Also, a method of preparing a zinc oxide nanorod PV cell entirely by chemical spray pyrolysis is disclosed. Efficiency up to 3.9% is achieved by simple continuous non-vacuum process.
    Type: Grant
    Filed: July 9, 2008
    Date of Patent: December 24, 2013
    Assignee: Tallinn University of Technology
    Inventors: Malle Krunks, Atanas Katerski, Tatjana Dedova, Arvo Mere, Ilona Oja Acik
  • Publication number: 20130337600
    Abstract: A method for processing a semiconductor assembly is presented. The method includes thermally processing a semiconductor assembly in a non-oxidizing atmosphere at a pressure greater than about 10 Torr. The semiconductor assembly includes a semiconductor layer disposed on a support, and the semiconductor layer includes cadmium and sulfur.
    Type: Application
    Filed: June 14, 2012
    Publication date: December 19, 2013
    Applicant: GENERAL ELECTRIC COMPANY
    Inventors: Jinbo Cao, Bastiaan Arie Korevaar
  • Patent number: 8609182
    Abstract: Improved methods and apparatus for forming thin-film layers of chalcogenide on a substrate web. Solutions containing the reactants for the chalcogenide layer may be contained substantially to the front surface of the web, controlling the boundaries of the reaction and avoiding undesired deposition of chalcogenide upon the back side of the web.
    Type: Grant
    Filed: March 4, 2009
    Date of Patent: December 17, 2013
    Assignee: Global Solar Energy, Inc.
    Inventors: Jeffrey S. Britt, Scot Albright, Urs Schoop
  • Publication number: 20130330874
    Abstract: A chemical bath deposition method is presented to prepare different thin films on plane substrates. In particular, they are useful to deposit CdS or ZnS buffer layers in manufacture of thin film solar cells. This method and the deposition apparatus deposit thin films onto vertically travelling plane workpieces delivered by a conveyor belt. The thin films are deposited by continuously spraying the reaction solutions from their freshly mixed styles to gradually aged forms until the designed thickness is obtained. The substrates and the solutions are heated to a reaction temperature. During the deposition processes, the front surfaces of the substrates are totally covered with the sprayed solutions but the substrate backsides are remained dry. The reaction ambience inside the reactor can be isolated from the outside atmosphere. The method is designed to generate a minimum amount of waste solutions for chemical treatments.
    Type: Application
    Filed: August 21, 2013
    Publication date: December 12, 2013
    Inventor: Jiaxiong Wang
  • Patent number: 8592246
    Abstract: Methods of manufacturing a solar cell module are provided. The method may include forming lower electrodes on a substrate, forming a light absorption layer on the lower electrodes and the substrate, patterning the light absorption layer to form a trench exposing the lower electrodes, and forming window electrodes using a conductive film. The conductive film extends from a top surface of the light absorption layer to a bottom of the trench along one-sidewall of the trench and is divided at another-sidewall of the trench.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: November 26, 2013
    Assignee: Electronics and Telecommunications Research Institute
    Inventor: Rae-Man Park
  • Patent number: 8563356
    Abstract: Provided are a thin film transistor in which an oxide semiconductor combined with a nitride containing boron or aluminum is applied to a channel layer and a method of fabricating the same. The thin film transistor in which an oxide semiconductor combined with a nitride containing boron or aluminum is applied to a channel layer exhibits significantly improved mobility and increased stability at a high temperature.
    Type: Grant
    Filed: September 21, 2010
    Date of Patent: October 22, 2013
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Woo Seok Cheong, Sung Mook Chung, Jun Yong Bak
  • Patent number: 8519435
    Abstract: A photovoltaic cell is fabricated onto a polyimide film using an unbalanced RF magnetron sputtering process. The sputtering process includes the addition of 0.05% to 0.5% oxygen to an inert gas stream. Portions of the photovoltaic cell are exposed to an elevated temperature CdCl2 treatment which is at or below the glass transition temperature of the polyimide film.
    Type: Grant
    Filed: June 8, 2010
    Date of Patent: August 27, 2013
    Assignee: The University of Toledo
    Inventors: Anthony Vasko, Kristopher Wieland, James Walker, Alvin Compaan
  • Patent number: 8476105
    Abstract: In one aspect of the present invention, a method is provided. The method includes disposing a substantially amorphous cadmium tin oxide layer on a support; and thermally processing the substantially amorphous cadmium tin oxide layer in an atmosphere substantially free of cadmium from an external source to form a transparent layer, wherein the transparent layer has an electrical resistivity less than about 2×10?4 Ohm-cm. Method of making a photovoltaic device is also provided.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: July 2, 2013
    Assignee: General Electric Company
    Inventors: Holly Ann Blaydes, George Theodore Dalakos, David William Vernooy, Allan Robert Northrup, Juan Carlos Rojo, Peter Joel Meschter, Hongying Peng, Hongbo Cao, Yangang Andrew Xi, Robert Dwayne Gossman, Anping Zhang
  • Patent number: 8440497
    Abstract: A Kesterite film is vacuum deposited and annealed on a substrate. Deposition is conducted at low temperature to provide good composition control and efficient use of metals. Annealing is conducted at a high temperature for a short period of time. Thermal evaporation, E-beam evaporation or sputtering in a high vacuum environment may be employed as part of a deposition process.
    Type: Grant
    Filed: October 26, 2010
    Date of Patent: May 14, 2013
    Assignee: International Business Machines Corporation
    Inventors: Supratik Guha, Kejia Wang
  • Patent number: 8426728
    Abstract: Solar cells and methods for manufacturing solar cells and/or components or layers thereof are disclosed. An example method for manufacturing a multi-bandgap quantum dot layer for use in a solar cell may include providing a first precursor compound, providing a second precursor compound, and combining a portion of the first precursor compound with a portion of the second precursor compound to form a multi-bandgap quantum dot layer that includes a plurality of quantum dots that differ in bandgap.
    Type: Grant
    Filed: June 12, 2009
    Date of Patent: April 23, 2013
    Assignee: Honeywell International Inc.
    Inventors: Linan Zhao, Zhi Zheng, Marilyn Wang, Xuanbin Liu, Huili Tang
  • Publication number: 20130089946
    Abstract: Described herein are wavelength conversion films that are easy-to-apply to solar cells, solar panels, or photovoltaic devices using an adhesive layer. The wavelength conversion films include a wavelength conversion layer with a photostable chromophore and are useful for improving the solar harvesting efficiency of solar cells, solar panels, and photovoltaic devices.
    Type: Application
    Filed: September 28, 2012
    Publication date: April 11, 2013
    Inventor: Nitto Denko Corporation
  • Patent number: 8383450
    Abstract: A method for forming a thin film photovoltaic material. The method includes providing a plurality of substrates. Each of the substrates has a surface region, an overlying first electrode material, an absorber material including at least a copper species, an indium species, and a selenium species. The method immerses the plurality of substrates in an aqueous solution including an ammonia species, a cadmium species, and a organosulfur (for example, thiourea) species in a bath to form a cadmium sulfide window material having a thickness of less than about 200 Angstroms overlying the absorber material. The aqueous solution is maintained at a temperature ranging from about 50 to about 60 Degrees Celsius. The plurality of substrates having at least the absorber material and the window layer are removed from the aqueous solution. The aqueous solution is further subjected to a filter process to substantially remove one or more particles greater than about 5 microns.
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: February 26, 2013
    Assignee: Stion Corporation
    Inventor: Robert D. Wieting
  • Patent number: 8378341
    Abstract: A semiconductor device of the present invention has a first interconnect layer formed over the semiconductor substrate, and a semiconductor element; the first interconnect layer has an insulating layer, and a first interconnect filled in a surficial portion of the insulating layer; the semiconductor element has a semiconductor layer, a gate insulating film, and a gate electrode; the semiconductor layer is positioned over the first interconnect layer; the gate insulating film is positioned over or below semiconductor layer; and the gate electrode is positioned on the opposite side of the semiconductor layer while placing the gate insulating film in between.
    Type: Grant
    Filed: December 14, 2009
    Date of Patent: February 19, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshihiro Hayashi, Naoya Inoue, Kishou Kaneko
  • Patent number: 8377737
    Abstract: Methods for isolating thin film photovoltaic cells on a superstrate are provided. The method includes focusing a laser beam onto a first surface of the superstrate to remove a thin film stack positioned on a second surface of the superstrate, and directing the laser beam across the first surface of the superstrate to form an isolation scribe that is substantially free from the thin film stack. The thin film stack can include a transparent conductive oxide layer on the second surface, an n-type window layer on the transparent conductive oxide layer, and an absorber layer on the n-type window layer. The laser beam can have a laser wavelength of about 370 nm or less, and/or can have a laser wavelength such that the transparent conductive oxide layer absorbs at least about 80% of the laser beam at the laser wavelength.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: February 19, 2013
    Assignee: Primestar Solar, Inc.
    Inventors: William J. Schaffer, Luke W. Jacobson, Scott L. French, Eric Boese, Robert A. Garber
  • Patent number: 8354586
    Abstract: Certain example embodiments relate to a transparent conductor film stack with cadmium stannate used as a front contact layer and/or a buffer layer in a photovoltaic device or the like. The cadmium stannate-based layers may be provided between the front glass substrate and the semiconductor absorber film in a photovoltaic device (e.g., a CdS and/or CdTe based photovoltaic device). In certain example embodiments, the buffer layer based on cadmium stannate may have a higher resistivity than the transparent conductive oxide layer based on cadmium stannate. In certain example embodiments, one or more index matching layer(s) may be provided between the glass substrate and the layer(s) comprising cadmium stannate, e.g., to help overcome the optical mismatch between the glass substrate and the CdSnOx.
    Type: Grant
    Filed: October 1, 2010
    Date of Patent: January 15, 2013
    Assignee: Guardian Industries Corp.
    Inventors: Scott V. Thomsen, Willem den Boer, Yiwei Lu
  • Publication number: 20130005073
    Abstract: A chemical bath deposition method and a system are presented to prepare different thin films on plane substrates. In particular, they are useful to deposit CdS or ZnS buffer layers in manufacture of thin film solar cells. This method and the deposition system deposit thin films onto vertically travelling plane workpieces delivered by a conveyor belt. The thin films are deposited with continuously spraying the reaction solutions from their freshly mixed styles to gradually aged forms until the designed thickness is obtained. The substrates and the solutions are heated to a reaction temperature. During the deposition processes, the front surfaces of the substrates are totally covered with the sprayed solutions but the substrate backsides are remained dry. The reaction ambience inside the reactor can be isolated from the outside atmosphere. The apparatus is designed to generate a minimum amount of waste solutions for chemical treatments.
    Type: Application
    Filed: June 30, 2011
    Publication date: January 3, 2013
    Inventor: Jiaxiong Wang
  • Patent number: 8343797
    Abstract: A process for preparing a solar cell comprising a support, a layer of cadmium sulfide (CdS), a layer of cadmium telluride (CdTe), a layer of a transparent conductive oxide (TCO), a conductive metallic layer and optionally a layer of buffer material, the CdS layer and the CdTe layer being deposited by means of a pulsed plasma deposition (PPD) method, a solar cell obtainable by means of the described process being also provided.
    Type: Grant
    Filed: September 17, 2008
    Date of Patent: January 1, 2013
    Inventors: Carlo Taliani, Petr Nozar