Graded Composition Patents (Class 438/87)
  • Patent number: 11682744
    Abstract: A solar cell, and methods of fabricating said solar cell, are disclosed. The solar cell can include a substrate having a light-receiving surface and a back surface. The solar cell can include a first semiconductor region of a first conductivity type disposed on a first dielectric layer, wherein the first dielectric layer is disposed on the substrate. The solar cell can also include a second semiconductor region of a second, different, conductivity type disposed on a second dielectric layer, where a portion of the second thin dielectric layer is disposed between the first and second semiconductor regions. The solar cell can include a third dielectric layer disposed on the second semiconductor region. The solar cell can include a first conductive contact disposed over the first semiconductor region but not the third dielectric layer.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: June 20, 2023
    Assignee: Maxeon Solar Pte. Ltd.
    Inventor: David D. Smith
  • Patent number: 11367805
    Abstract: Solar cells, absorber structures, back contact structures, and methods of making the same are described. The solar cells and absorber structures include a pseudomorphically strained electron reflector layer.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: June 21, 2022
    Assignee: First Solar, Inc.
    Inventors: Andrei Los, Roger Malik
  • Patent number: 10714652
    Abstract: Methods of forming interdigitated back contact (IBC) layers are provided. According to an aspect of the invention, a first layer having alternating regions of n-type amorphous hydrogenated silicon and p-type amorphous hydrogenated silicon is formed on a second layer of intrinsic amorphous hydrogenated silicon. The first layer and the second layer are then annealed, such that dopants from the first layer diffuse into the second layer, and the first layer and the second layer crystallize into polysilicon.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: July 14, 2020
    Assignee: Alliance for Sustainable Energy, LLC
    Inventors: William Michael Nemeth, Pauls Stradins, Vincenzo Anthony LaSalvia, Matthew Robert Page, David Levi Young
  • Patent number: 10658525
    Abstract: A method of fabricating a solar cell can include forming a dielectric region on a silicon substrate. The method can also include forming an emitter region over the dielectric region and forming a dopant region on a surface of the silicon substrate. In an embodiment, the method can include heating the silicon substrate at a temperature above 900 degrees Celsius to getter impurities to the emitter region and drive dopants from the dopant region to a portion of the silicon substrate.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: May 19, 2020
    Assignee: SunPower Corporation
    Inventors: David D. Smith, Tim Dennis, Russelle De Jesus Tabajonda
  • Patent number: 9865762
    Abstract: The thin-film photoelectric conversion device of the present invention includes: a transparent electroconductive film having zinc oxide as a main component; a contact layer; a photoelectric conversion unit having a p-type semiconductor layer, an i-type semiconductor layer and an n-type semiconductor layer in this order; and a back electrode layer, in this order, on one main surface of a substrate. The contact layer has an intrinsic crystalline semiconductor layer and a p-type crystalline semiconductor layer in this order from the substrate side, and the intrinsic crystalline semiconductor layer of the contact layer and the transparent electroconductive film are in contact with each other. The p-type crystalline semiconductor layer of the contact layer is preferably a layer having as a main component a silicon alloy selected from the group consisting of a silicon oxide; a silicon nitride; and silicon carbide.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: January 9, 2018
    Assignee: KANEKA CORPORATION
    Inventors: Tomomi Meguro, Kenji Yamamoto
  • Patent number: 9515201
    Abstract: Provided is a solar cell module comprising a crystalline silicon wafer, at least one amorphous silicon layer provided on at least one of a top and bottom of the crystalline silicon wafer, a transparent conductive film provided on a surface of the at least one amorphous silicon layer, electrodes provided on a surface of the transparent conductive film and a division unit to divide the transparent conductive film into a current-carrying region and a non-current-carrying region, wherein the current-carrying region is electrically connected to the electrodes and the non-current-carrying region is electrically disconnected from the electrodes.
    Type: Grant
    Filed: May 8, 2015
    Date of Patent: December 6, 2016
    Assignee: TES Co., Ltd.
    Inventor: Hong-Jae Lee
  • Patent number: 9431574
    Abstract: A light-emitting device includes a pixel having a transistor provided over a substrate, and a light-emitting element. The transistor includes a single-crystal semiconductor layer which forms a channel formation region, a silicon oxide layer is provided between the substrate and the single-crystal semiconductor layer, a source or a drain of the transistor is electrically connected to an electrode of the light-emitting element, and the transistor is operated in a saturation region when the light-emitting element emits light. Further, in the light-emitting device, a gray scale of the light-emitting element is displayed by changing a potential applied to the gate of the transistor.
    Type: Grant
    Filed: August 19, 2013
    Date of Patent: August 30, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 9276154
    Abstract: A photovoltaic device including a protective layer between a window layer and an absorber layer, the protective layer inhibiting dissolving/intermixing of the window layer into the absorber layer during a device activation step, and methods of forming such photovoltaic devices.
    Type: Grant
    Filed: February 3, 2014
    Date of Patent: March 1, 2016
    Assignee: FIRST SOLAR, INC.
    Inventors: Daniel Damjanovic, Jing Guo, Sreenivas Jayaraman, Oleh P. Karpenko, Feng Liao, Chong Lim, Rick C. Powell, Jigish Trivedi, Zhibo Zhao
  • Patent number: 9214594
    Abstract: The present disclosure provides a method of manufacturing a solar cell including: providing a first substrate and a second substrate; depositing on the first substrate a sequence of layers of semiconductor material forming a solar cell including a top subcell and a bottom subcell; forming a back metal contact over the bottom subcell; applying a conductive polyimide adhesive to the second substrate; attaching the second substrate on top of the back metal contact; and removing the first substrate to expose the surface of the top subcell.
    Type: Grant
    Filed: August 7, 2013
    Date of Patent: December 15, 2015
    Assignee: SolAero Technologies Corp.
    Inventors: Mark A. Stan, Chelsea Mackos, Jeff Steinfeldt
  • Patent number: 9024361
    Abstract: Provided is a solid-state imaging device including: a photodiode which converts an optical signal to signal charges; a transfer gate which transfers the signal charges from the photodiode; an impurity diffusion layer to which the signal charges are transferred by the transfer gate; and a MOS transistor of which a gate is connected to the impurity diffusion layer. The impurity diffusion layer has a first conduction type semiconductor layer and a second conduction type semiconductor layer which is formed in the first conduction type semiconductor layer and under an end portion of the transfer gate.
    Type: Grant
    Filed: July 19, 2010
    Date of Patent: May 5, 2015
    Assignee: Sony Corporation
    Inventors: Hiroyuki Ohri, Yasunori Sogoh
  • Patent number: 9023680
    Abstract: A method for producing a compound semiconductor layer comprises dissolving a metal feedstock comprising at least one of a group I-B element and a group III-B element, in a metal state, in a mixed solvent comprising an organic compound containing a chalcogen element and a Lewis base organic compound to produce a solution for forming a semiconductor; forming a coat using the solution for forming a semiconductor; and heat-treating the coat.
    Type: Grant
    Filed: July 27, 2010
    Date of Patent: May 5, 2015
    Assignee: KYOCERA Corporation
    Inventors: Seiichiro Inai, Yoshihide Okawa, Isamu Tanaka, Koichiro Yamada
  • Patent number: 9012256
    Abstract: A process for producing a photovoltaic device that can improve the power generation characteristics of a solar cell having a heterojunction composed of a p-type crystalline Ge (substrate), an i-type amorphous silicon semiconductor layer, and an n-type amorphous silicon semiconductor layer.
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: April 21, 2015
    Assignees: Mitsubishi Heavy Industries, Ltd., National Institute of Advanced Industrial Science and Technology
    Inventors: Shinya Nakano, Yoshiaki Takeuchi, Michio Kondo, Takuya Matsui
  • Publication number: 20150090322
    Abstract: Disclosed are a solar cell apparatus and a method of fabricating the same. The solar cell apparatus includes a substrate; a back electrode layer on the substrate; a light absorbing layer on the back electrode layer; and a front electrode layer on the light absorbing layer, wherein the light absorbing layer includes: a first region having a bandgap energy which is gradually increased in a direction of the front electrode; a second region on the first region, the second region having a bandgap energy which is gradually decreased in a direction of the front electrode layer; a third region on the second region, the third region having a bandgap energy which is gradually increased in a direction of the front electrode layer; and a fourth region on the first region, the fourth region having a bandgap energy which is gradually decreased in a direction of the front electrode layer.
    Type: Application
    Filed: December 17, 2012
    Publication date: April 2, 2015
    Inventor: Jin Woo Lee
  • Patent number: 8993423
    Abstract: A method of manufacturing a solar cell is disclosed. The method includes forming a dielectric film on a semiconductor substrate doped with a first conductive type impurity, exposing a high concentration doping region of a predetermined selective emitter by partially removing the dielectric film, and ion-implanting a second conductive type impurity into a front surface of the semiconductor substrate with the dielectric film formed thereon to form a high concentration doping layer in the semiconductor substrate to correspond to the high concentration doping region and to form a low concentration doping layer in the semiconductor substrate to correspond to a region in which the dielectric film is formed.
    Type: Grant
    Filed: July 1, 2013
    Date of Patent: March 31, 2015
    Assignee: Shinshung Solar Energy Co., Ltd.
    Inventors: Ji Soo Kim, Ho Sik Kim, Ji Sun Kim, Jong Youb Lim, Yeon Hee Hwang, Hoon Joo Choi, Jeong Jae Jo
  • Publication number: 20150083183
    Abstract: A solar cell includes: a semiconductor substrate of a first conductivity type that includes an impurity diffusion layer, in which an impurity element of a second conductivity type is diffused, on one surface side; a passivation film that is formed on the impurity diffusion layer and that is made of an oxide film of a material of the semiconductor substrate; an anti-reflective film that is made of a translucent material having a refractive index different from that of the oxide film and that is formed on the passivation film; a light-receiving-surface-side electrode that is electrically connected to the impurity diffusion layer and that is formed on one surface side of the semiconductor substrate; and a rear-surface-side electrode that is formed on another surface side of the semiconductor substrate.
    Type: Application
    Filed: April 25, 2012
    Publication date: March 26, 2015
    Applicant: Mitsubishi Electric Corporation
    Inventor: Yoichiro Nishimoto
  • Patent number: 8987042
    Abstract: A method of forming a multijunction solar cell including an upper subcell, a middle subcell, and a lower subcell by providing a substrate for the epitaxial growth of semiconductor material; forming a first solar subcell on the substrate having a first band gap; forming a second solar subcell over the first solar subcell having a second band gap smaller than the first band gap; forming a graded interlayer over the second subcell, the graded interlayer having a third band gap greater than the second band gap; forming a third solar subcell over the graded interlayer having a fourth band gap smaller than the second band gap such that the third subcell is lattice mismatched with respect to the second subcell; and forming a contact composed of a sequence of layers over the first subcell at a temperature of 280° C. or less and having a contact resistance of less than 5×10?4 ohms-cm2.
    Type: Grant
    Filed: May 22, 2014
    Date of Patent: March 24, 2015
    Assignee: SolAero Technologies Corp.
    Inventors: Tansen Varghese, Arthur Cornfeld
  • Patent number: 8987738
    Abstract: A photoelectric conversion device with improved electric characteristics is provided. The photoelectric conversion device has a structure in which a window layer is formed by a stack of a first silicon semiconductor layer and a second silicon semiconductor layer, and the second silicon semiconductor layer has high carrier concentration than the first silicon semiconductor layer and has an opening. Light irradiation is performed on the first silicon semiconductor layer through the opening without passing through the second silicon semiconductor layer; thus, light absorption loss in the window layer can be reduced.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: March 24, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takashi Hirose, Naoto Kusumoto
  • Publication number: 20150075595
    Abstract: A method for producing a photovoltaic cell with interdigitated contacts in the rear face, comprising: providing a doped silicon substrate; forming, on the rear face of said substrate, a doped semiconductor layer with a first dopant species; forming, on said layer, a dopant layer comprising a second dopant species, of an electric type opposite to that of the first species; forming, in the doped layer, at least one doped region of a type opposite to that of the first species, by irradiation of at least one region of the dopant layer with a luminous flux of fluence greater than a threshold above which the dopants of the irradiated region of the dopant layer diffuse into the region underlying the doped layer in such a way as to exceed the concentration of the first dopant species; and forming, in the doped layer, at least one electrically insulating region, by selective irradiation of at least one region of the dopant layer with a luminous flux of which the fluence is in a range lower than said threshold, at whic
    Type: Application
    Filed: April 3, 2013
    Publication date: March 19, 2015
    Applicant: Commissariat à I'Energie Atomique et aux Energies Alternatives
    Inventor: Samuel Gall
  • Patent number: 8975718
    Abstract: The invention relates to an avalanche photodiode-type semiconductor structure (1) intended to receive electromagnetic radiation in a given wavelength. The structure comprises a first semiconductor zone (210) with a first type of conductivity with a first longitudinal face (201), said first zone (210) being made of mercury-cadmium telluride of the CdxHg1-xTe type with a cadmium proportion x that is varied. The structure (1) also comprises at least one second semiconductor zone (310) in contact with the first zone (210), and a third semiconductor zone (410) in contact with the second zone (310). The first zone (210) comprises a doping element, such as arsenic, of which the concentration is varied alternately in a direction substantially perpendicular to the first longitudinal face (201) between a so-called low concentration and a so-called high concentration. The invention also relates to a process for producing a structure (1) according to the invention.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: March 10, 2015
    Assignee: Commissariat a l'energie atomique et aux energies alternatives
    Inventor: Johan Rothman
  • Patent number: 8969124
    Abstract: A method for fabricating a Cu—In—Ga—Se film solar cell is provided. The method comprises: a) fabricating a molybdenum back electrode on a substrate; b) fabricating a Cu—In—Ga—Se absorbing layer on the molybdenum back electrode; c) performing an annealing; d) fabricating an In2Se3 or ZnS buffer layer on the Cu—In—Ga—Se absorbing layer; e) fabricating an intrinsic zinc oxide high impedance layer; f) fabricating an indium tin oxide film low impedance layer on the intrinsic zinc oxide high impedance layer; g) fabricating an aluminum electrode on the indium tin oxide film low impedance layer.
    Type: Grant
    Filed: January 11, 2014
    Date of Patent: March 3, 2015
    Inventors: Liuyu Lin, Zhun Zhang
  • Patent number: 8951827
    Abstract: Manufacture of multi-junction solar cells, and devices thereof, are disclosed. The architectures are also adapted to provide for a more uniform and consistent fabrication of the solar cell structures, leading to improved yields and lower costs. Certain solar cells may further include one or more compositional gradients of one or more semiconductor elements in one or more semiconductor layers, resulting in a more optimal solar cell device.
    Type: Grant
    Filed: June 21, 2013
    Date of Patent: February 10, 2015
    Assignee: EpiWorks, Inc.
    Inventors: David Ahmari, Swee Lim, Shiva Rai, David Forbes
  • Patent number: 8951829
    Abstract: Methods, devices, and systems associated with oxide based memory can include a method of forming a resistive switching region of a memory cell. Forming a resistive switching region of a memory cell can include forming a metal oxide material on an electrode and forming a metal material on the metal oxide material, wherein the metal material formation causes a reaction that results in a graded metal oxide portion of the memory cell.
    Type: Grant
    Filed: April 1, 2011
    Date of Patent: February 10, 2015
    Assignee: Micron Technology, Inc.
    Inventors: D.V. Nirmal Ramaswamy, Gurtej S. Sandhu
  • Publication number: 20150008493
    Abstract: The invention relates to an active CMOS pixel structure comprising: at least one photoelectric conversion zone (NPD) defined by n-doping of the substrate, said zone accumulating an amount of charge during an exposure to light and comprising a p-doped surface zone (PIN); and at least one MOS transfer transistor (TX), the gate of said transfer transistor (TX) being electrically insulated from the substrate and being used to control transfer of said charge from said photoelectric conversion zone (NPD) to said floating diffusion node (FD), in which the gate of said transfer transistor (TX) partially covers said p-doped surface zone (PIN), and said photoelectric conversion zone (NPD) extends under said gate of said transfer transistor (TX) at least as far as the end of the p-doped surface zone (PIN).
    Type: Application
    Filed: February 13, 2013
    Publication date: January 8, 2015
    Inventor: Yang Ni
  • Patent number: 8927323
    Abstract: A photovoltaic device includes a crystalline substrate having a first dopant conductivity, an interdigitated back contact and a front surface field structure. The front surface field structure includes a crystalline layer formed on the substrate and a noncrystalline layer formed on the crystalline layer. The crystalline layer and the noncrystalline layer are doped with dopants having a same dopant conductivity as the substrate. Methods are also disclosed.
    Type: Grant
    Filed: August 14, 2013
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Tze-Chiang Chen, Bahman Hekmatshoartabari, Devendra K. Sadana, Davood Shahrjerdi
  • Publication number: 20150000730
    Abstract: A method for the low-temperature production of radial electronic junction semiconductor nanostructures on a substrate, includes: a) forming on the substrate, metal aggregates capable of electronically doping a first semiconductor material; b) growing, in the vapor phase, doped semiconductor nanowires in the presence of one or more non-dopant precursor gases of the first semiconductor material, the substrate being heated to a temperature at which the metal aggregates are in the liquid phase, the growth of the doped semiconductor nanowires in the vapor phase being catalyzed by the metal aggregates; c) rendering the residual metal aggregates inactive; and d) the chemical vapor deposition, in the presence of one or more precursor gases and a dopant gas, of at least one thin film of a second semiconductor material so as to form at least one radial electronic junction nanostructure between the nanowire and the at least one doped thin film.
    Type: Application
    Filed: January 3, 2013
    Publication date: January 1, 2015
    Applicants: TOTAL MARKETING SERVICES, ECOLE POLYTECHNIQUE, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE
    Inventors: Linwei Yu, Pere Roca I Cabarrocas
  • Publication number: 20140373896
    Abstract: A back contact heterojunction photoelectric conversion device, that obtain junctions that are nearly ohmic contacts by integrally forming a transparent conductive film including an electrode directly on a p-type amorphous silicon film and a transparent conductive oxide directly on an n-type amorphous silicon film. A method of manufacturing the device includes: integrally forming an oxide electrode layer on the n-type amorphous silicon film and the p-type amorphous silicon film; and applying plasma, under a condition that a mask is disposed on the transparent conductive film covering either the n-type amorphous silicon film or the p-type amorphous silicon film, to exposed portions of transparent conductive film.
    Type: Application
    Filed: March 29, 2012
    Publication date: December 25, 2014
    Applicant: Mitsubishi Electric Corporation
    Inventors: Tsutomu Matsuura, Hiroya Yamarin, Hidetada Tokioka
  • Patent number: 8916873
    Abstract: A photodetector includes a semiconductor substrate having an irradiation zone configured to generate charge carriers having opposite charge carrier types in response to an irradiation of the semiconductor substrate. The photodetector further includes an inversion zone generator configured to operate in at least two operating states to generate different inversion zones within the substrate, wherein a first inversion zone generated in a first operating state differs from a second inversion zone generated in a second operating state, and wherein the first inversion zone and the second inversion zone have different extensions in the semiconductor substrate. A corresponding method for manufacturing a photodetector and a method for determining a spectral characteristic of an irradiation are also described.
    Type: Grant
    Filed: September 14, 2011
    Date of Patent: December 23, 2014
    Assignee: Infineon Technologies AG
    Inventor: Thoralf Kautzsch
  • Publication number: 20140370646
    Abstract: A gallium-containing alloy is formed on the light-receiving surface of a CIGS absorber layer, and, in conjunction with a subsequent selenization or anneal process, is converted to a gallium-rich region at the light-receiving surface of the CIGS absorber layer. A second gallium-rich region is formed at the back contact surface of the CIGS absorber layer during selenization, so that the CIGS absorber layer has a double-graded gallium concentration that increases toward the light-receiving surface and toward the back contact surface of the CIGS absorber layer. The double-graded gallium concentration advantageously produces a double-graded bandgap profile for the CIGS absorber layer.
    Type: Application
    Filed: September 4, 2014
    Publication date: December 18, 2014
    Inventor: Haifan Liang
  • Patent number: 8912615
    Abstract: The present invention is a photodiode or photodiode array having improved ruggedness for a shallow junction photodiode which is typically used in the detection of short wavelengths of light. In one embodiment, the photodiode has a relatively deep, lightly-doped P zone underneath a P+ layer. By moving the shallow junction to a deeper junction in a range of 2-5 ?m below the photodiode surface, the improved device has improved ruggedness, is less prone to degradation, and has an improved linear current.
    Type: Grant
    Filed: January 24, 2013
    Date of Patent: December 16, 2014
    Assignee: OSI Optoelectronics, Inc.
    Inventors: Peter Steven Bui, Narayan Dass Taneja
  • Publication number: 20140360565
    Abstract: A photovoltaic device is presented. The photovoltaic device includes a layer stack; and an absorber layer is disposed on the layer stack. The absorber layer includes selenium, and an atomic concentration of selenium varies non-linearly across a thickness of the absorber layer. A method of making a photovoltaic device is also presented.
    Type: Application
    Filed: June 7, 2013
    Publication date: December 11, 2014
    Applicant: First Solar, Inc.
    Inventors: Holly Ann Blaydes, Kristian William Andreini, William Hullinger Huber, Eugene Thomas Hinners, Joseph John Shiang, Yong Liang, Jongwoo Choi, Adam Fraser Halverson
  • Patent number: 8901695
    Abstract: A photovoltaic device includes one or more layers of a photovoltaic stack formed on a substrate by employing a high deposition rate plasma enhanced chemical vapor deposition (HDR PECVD) process. Contacts are formed on the photovoltaic stack to provide a photovoltaic cell. Reduced defect zones are disposed adjacent to contact regions in portions of the photovoltaic cell and are formed by an anneal configured to improve overall performance.
    Type: Grant
    Filed: July 9, 2012
    Date of Patent: December 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Keith E. Fogel, Augustin J. Hong, Jeehwan Kim, Devendra K. Sadana
  • Patent number: 8895342
    Abstract: Inverted metamorphic multijunction solar cells having a heterojunction middle subcell and a graded interlayer, and methods of making same, are disclosed herein. The present disclosure provides a method of manufacturing a solar cell using an MOCVD process, wherein the graded interlayer is composed of (InxGa1-x)yAl1-yAs, and is formed in the MOCVD reactor so that it is compositionally graded to lattice match the middle second subcell on one side and the lower third subcell on the other side, with the values for x and y computed and the composition of the graded interlayer determined so that as the layer is grown in the MOCVD reactor, the band gap of the graded interlayer remains constant at 1.5 eV throughout the thickness of the graded interlayer.
    Type: Grant
    Filed: May 17, 2012
    Date of Patent: November 25, 2014
    Assignee: Emcore Solar Power, Inc.
    Inventors: Mark A. Stan, Arthur Cornfeld
  • Patent number: 8889978
    Abstract: A method of depositing III-V solar collection materials on a GeSn template on a silicon substrate including the steps of providing a crystalline silicon substrate and epitaxially growing a single crystal GeSn layer on the silicon substrate using a grading profile to grade Sn through the layer. The single crystal GeSn layer has a thickness in a range of approximately 3 ?m to approximately 5 ?m. A layer of III-V solar collection material is epitaxially grown on the graded single crystal GeSn layer. The graded single crystal GeSn layer includes Sn up to an interface with the layer of III-V solar collection material.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: November 18, 2014
    Assignee: Translucent, Inc.
    Inventors: Radek Roucka, Michael Lebby, Scott Semans
  • Patent number: 8889465
    Abstract: A method of processing a thin-film absorber material with enhanced photovoltaic efficiency. The method includes providing a soda-lime glass substrate having a surface region and forming a barrier material overlying the surface region, followed by formation of a stack structure including a first thickness of a first precursor, a second thickness of a second precursor, and a third thickness of a third precursor. The first thickness of the first precursor is sputtered with a first target device including a first mixture of copper, gallium, and a first sodium species. The method further includes subjecting the soda-lime glass substrate having the stack structure in a thermal treatment process with at least H2Se gas species at a temperature above 400° C. to cause formation of an absorber material. Moreover, the method includes transferring a second sodium species from a portion of the soda-lime glass substrate via gas-phase diffusion during the thermal treatment process.
    Type: Grant
    Filed: April 5, 2013
    Date of Patent: November 18, 2014
    Assignee: Stion Corporation
    Inventor: Robert D. Wieting
  • Publication number: 20140319641
    Abstract: A radiation conversion device such as a photovoltaic cell, a photodiode or a semiconductor radiation detection device, includes a semiconductor portion with first compensation zones of a first conductivity type and a base portion that separates the first compensation zones from each other. The first compensations zones are arranged in pillar structures. Each pillar structure includes spatially separated first compensation zones and extends in a vertical direction with respect to a main surface of the semiconductor portion. Between neighboring ones of the pillar structures the base portion includes second compensation zones of a second conductivity type, which is complementary to the first conductivity type. The radiation conversion device combines high radiation hardness with cost effective manufacturing.
    Type: Application
    Filed: April 24, 2013
    Publication date: October 30, 2014
    Inventors: Armin Willmeroth, Hans-Joachim Schulze
  • Publication number: 20140319640
    Abstract: A photodiode structure provides light sensitivity to both front side and backside illumination. The photodiode may include a deep N well (DNW) that extends over a Psub substrate. The DNW may be discontinuous, or may extend continuously over the Psub substrate. Additional DNW area under the diode area proportionally increases the sensitivity to backside illumination. In addition, the photodiode may use a lightly doped anode region to increase the depletion region between the anode region and the deep N well. The anode region may be lightly doped Psub, as opposed to Pwell, in order to increase the topside light sensitive area percentage of the total area. One highly sensitive implementation uses Psub doping in the anode region, and a deep N well under the entire diode. This provides maximum areal density of the diode intrinsic regions nearest the wafer backside.
    Type: Application
    Filed: April 29, 2013
    Publication date: October 30, 2014
    Applicant: Broadcom Corporation
    Inventors: Donald Edward Major, Chih-Chieh Shen
  • Patent number: 8871557
    Abstract: Provided are a photomultiplier and a manufacturing method thereof. The manufacturing method thereof may include forming a mask layer on an active region of a substrate doped with a first conductive type, ion implanting a second conductive type impurity opposite to the first conductive type into the substrate to form a first doped region in the active region under the mask layer and an non-active region exposed from the mask layer, forming a device isolation layer on the non-active region, removing the mask layer, and ion implanting the second conductive type impurity having a concentration higher than that of the first doped region into an upper portion of the first doped region in the active region to form a second doped region shallower than the first doped region.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: October 28, 2014
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Joon Sung Lee, Yong Sun Yoon
  • Patent number: 8866005
    Abstract: A new solar cell structure called a heterojunction barrier solar cell is described. As with previously reported quantum-well and quantum-dot solar cell structures, a layer of narrow band-gap material, such as GaAs or indium-rich InGaP, is inserted into the depletion region of a wide band-gap PN junction. Rather than being thin, however, the layer of narrow band-gap material is about 400-430 nm wide and forms a single, ultrawide well in the depletion region. Thin (e.g., 20-50 nm), wide band-gap InGaP barrier layers in the depletion region reduce the diode dark current. Engineering the electric field and barrier profile of the absorber layer, barrier layer, and p-type layer of the PN junction maximizes photogenerated carrier escape. This new twist on nanostructured solar cell design allows the separate optimization of current and voltage to maximize conversion efficiency.
    Type: Grant
    Filed: October 15, 2009
    Date of Patent: October 21, 2014
    Assignee: Kopin Corporation
    Inventor: Roger E. Welser
  • Patent number: 8859887
    Abstract: A photovoltaic device that exhibits increased open-circuit voltage and an improved fill factor due to an improvement in the contact properties between the n-layer and a back-side transparent electrode layer or intermediate contact layer, and a process for producing the photovoltaic device. The photovoltaic device comprises a photovoltaic layer having a p-layer, an i-layer and an n-layer stacked on top of a substrate, wherein the n-layer comprises a nitrogen-containing n-layer and an interface treatment layer formed on the opposite surface of the nitrogen-containing n-layer to the substrate, the nitrogen-containing n-layer comprises nitrogen atoms at an atomic concentration of not less than 1% and not more than 20%, and has a crystallization ratio of not less than 0 but less than 3, and the interface treatment layer has a crystallization ratio of not less than 1 and not more than 6.
    Type: Grant
    Filed: July 8, 2009
    Date of Patent: October 14, 2014
    Assignee: Mitsubishi Heavy Industries, Ltd.
    Inventors: Shigenori Tsuruga, Kengo Yamaguchi, Saneyuki Goya, Satoshi Sakai
  • Publication number: 20140295613
    Abstract: The disclosed technology generally relates photovoltaic devices, and more particularly to methods of fabricating heterojunction interdigitated back contact photovoltaic cells having interdigitated emitter regions and back surface field regions.
    Type: Application
    Filed: March 18, 2014
    Publication date: October 2, 2014
    Applicant: IMEC VZW
    Inventor: Barry O'Sullivan
  • Publication number: 20140290726
    Abstract: A solar cell includes an optical absorption layer; a buffer layer on the optical absorption layer, the buffer layer having a band gap energy gradient; and a transparent electrode layer on the buffer layer, wherein a band gap energy of a lower surface of the buffer layer is higher than a band gap energy of an upper surface of the buffer layer.
    Type: Application
    Filed: November 27, 2013
    Publication date: October 2, 2014
    Applicant: SAMSUNG SDI CO., LTD.
    Inventors: Cho-Young LEE, Min-Seok OH, Yun-Seok LEE, Jun-Ki HONG
  • Publication number: 20140264708
    Abstract: Optical absorbers, solar cells comprising the absorbers, and methods for making the absorbers are disclosed. The optical absorber comprises a semiconductor layer having a bandgap of between about 1.0 eV and about 1.6 eV disposed on a substrate, wherein the semiconductor comprises two or more earth abundant elements. The bandgap of the optical absorber is graded through the thickness of the layer by partial substitution of at least one grading element from the same group in the periodic table as the at least one of the two or more earth abundant elements.
    Type: Application
    Filed: September 23, 2013
    Publication date: September 18, 2014
    Applicant: Intermolecular, Inc.
    Inventors: Jeroen Van Duren, Haifan Liang
  • Patent number: 8835753
    Abstract: A solar cell includes a semiconductor base, a first doped semiconductor layer, an insulating layer, a second doped semiconductor layer and a first electrode layer. The semiconductor base has a first doped type. The first doped semiconductor layer, disposed on the semiconductor base, has a doped contact region. The insulating layer is disposed on the first doped semiconductor layer, exposing the doped contact region. The second doped semiconductor layer is disposed on the insulating layer and the doped contact region. The first doped semiconductor layer, the doped contact region and the second doped semiconductor layer have a second doped type, and a dopant concentration of the second doped semiconductor layer is between that of the first doped semiconductor layer and that of the doped contact region. The first electrode layer is disposed corresponding to the doped contact region.
    Type: Grant
    Filed: May 5, 2011
    Date of Patent: September 16, 2014
    Assignee: AU Optronics Corp.
    Inventors: Yen-Cheng Hu, Hsin-Feng Li, Zhen-Cheng Wu
  • Patent number: 8835979
    Abstract: Using a multiple layer, varied composition barrier layer in place of the typical single layer barrier layer of an infrared photodetector results in a device with increased sensitivity and reduced dark current. A first barrier is adjacent the semiconductor contact; a second barrier layer is between the first barrier layer and the absorber layer. The barrier layers may be doped N type or P type with Beryllium, Carbon, Silicon or Tellurium. The energy bandgap is designed to facilitate minority carrier current flow in the contact region and block minority current flow outside the contact region.
    Type: Grant
    Filed: June 3, 2011
    Date of Patent: September 16, 2014
    Assignee: HRL Laboratories, LLC
    Inventors: Terence J De Lyon, Rajesh D Rajavel, Hasan Sharifi
  • Publication number: 20140252528
    Abstract: In order to improve reliability by preventing an edge breakdown in a semiconductor photodetector having a mesa structure such as a mesa APD, the semiconductor photodetector comprises a mesa structure formed on a first semiconductor layer of the first conduction type formed on a semiconductor substrate, the mesa structure including a light absorbing layer for absorbing light, an electric field buffer layer for dropping an electric field intensity, an avalanche multiplication layer for causing avalanche multiplication to occur, and a second semiconductor layer of the second conduction type, wherein the thickness of the avalanche multiplication layer at the portion in the vicinity of the side face of the mesa structure is made thinner than the thickness at the central portion of the mesa structure.
    Type: Application
    Filed: May 21, 2014
    Publication date: September 11, 2014
    Applicants: FUJITSU LIMITED, SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventors: Nami YASUOKA, Haruhiko KUWATSUKA, Toru UCHIDA, Yoshihiro YONEDA
  • Patent number: 8828784
    Abstract: Methods and structures for extracting at least one electric parametric value from a back contact solar cell having dual level metallization are provided.
    Type: Grant
    Filed: April 23, 2013
    Date of Patent: September 9, 2014
    Assignee: Solexel, Inc.
    Inventors: Swaroop Kommera, Pawan Kapur, Mehrdad M. Moslehi
  • Patent number: 8828765
    Abstract: A method (50) is provided for processing a graded-density AR silicon surface (14) to provide effective surface passivation. The method (50) includes positioning a substrate or wafer (12) with a silicon surface (14) in a reaction or processing chamber (42). The silicon surface (14) has been processed (52) to be an AR surface with a density gradient or region of black silicon. The method (50) continues with heating (54) the chamber (42) to a high temperature for both doping and surface passivation. The method (50) includes forming (58), with a dopant-containing precursor in contact with the silicon surface (14) of the substrate (12), an emitter junction (16) proximate to the silicon surface (14) by doping the substrate (12). The method (50) further includes, while the chamber is maintained at the high or raised temperature, forming (62) a passivation layer (19) on the graded-density silicon anti-reflection surface (14).
    Type: Grant
    Filed: June 9, 2010
    Date of Patent: September 9, 2014
    Assignee: Alliance for Sustainable Energy, LLC
    Inventors: Hao-Chih Yuan, Howard M. Branz, Matthew R. Page
  • Publication number: 20140238476
    Abstract: A photoelectric conversion device in which a substantially intrinsic i-type amorphous hydrogen-containing semiconductor layer, a p-type amorphous hydrogen-containing semiconductor layer, and a first transparent conductive layer are stacked in this order on a first surface of an n-type semiconductor substrate that generates a photogenerated carrier by receiving light, wherein the first transparent conductive layer includes a hydrogen-containing area formed of a transparent conductive material that contains hydrogen and a hydrogen-diffusion suppression area that is present on a side of the p-type amorphous hydrogen-containing semiconductor layer with respect to the hydrogen-containing area and that is formed of a transparent conductive material that does not substantially contain hydrogen, and the hydrogen-diffusion suppression area has a hydrogen concentration distribution in which a hydrogen content on a side of the p-type amorphous hydrogen-containing semiconductor layer is lower than that on a side of the h
    Type: Application
    Filed: April 10, 2012
    Publication date: August 28, 2014
    Applicant: Mitsubishi Electric Corporation
    Inventors: Hirofumi Konishi, Tsutomu Matsuura, Yusuke Nishikawa, Katsutoshi Sugawara
  • Publication number: 20140231949
    Abstract: One or more embodiments of techniques or systems for mitigating dark current of an image sensor are provided herein. Generally, a silicon interface, such as an edge of a dielectric region or an edge between a back side interface (BSI) region and a pass region, is a source of electrons or holes which cause dark current. In some embodiments, the image sensor includes a surface protect region. For example, the surface protect region is doped with a first doping type and a photo-diode of the image sensor is doped with the same first doping type. In this manner, the surface protect region acts as an electron magnet or a hole magnet for electrons or holes from the silicon interface, thus mitigating electrons or holes from the silicon interface from being collected by the photo-diode, for example.
    Type: Application
    Filed: February 18, 2013
    Publication date: August 21, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Feng-Chi Hung, Dun-Nian Yaung, Jen-Cheng Liu, Shu-Ting Tsai, Shuang-Ji Tsai
  • Patent number: 8809106
    Abstract: Non-silicon based semiconductor devices are integrated into silicon fabrication processes by using aspect-ratio-trapping materials. Non-silicon light-sensing devices in a least a portion of a crystalline material can output electrons generated by light absorption therein. Exemplary light-sensing devices can have relatively large micron dimensions. As an exemplary application, complementary-metal-oxide-semiconductor photodetectors are formed on a silicon substrate by incorporating an aspect-ratio-trapping technique.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: August 19, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zhiyuan Cheng, James Fiorenza, Calvin Sheen, Anthony J. Lochtefeld