Fusion Or Solidification Of Semiconductor Region Patents (Class 438/89)
  • Patent number: 8143087
    Abstract: A fragile layer is formed in a region at a depth of less than 1000 nm from one surface of a single crystal semiconductor substrate, and a first impurity semiconductor layer and a first electrode are formed at the one surface side. After bonding the first electrode and a supporting substrate, the single crystal semiconductor substrate is separated using the fragile layer or the vicinity as a separation plane, thereby forming a first single crystal semiconductor layer over the supporting substrate. An amorphous semiconductor layer is formed on the first single crystal semiconductor layer, and a second single crystal semiconductor layer is formed by heat treatment for solid phase growth of the amorphous semiconductor layer. A second impurity semiconductor layer having a conductivity type opposite to that of the first impurity semiconductor layer and a second electrode are formed over the second single crystal semiconductor layer.
    Type: Grant
    Filed: December 23, 2010
    Date of Patent: March 27, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Fumito Isaka, Sho Kato, Koji Dairiki
  • Publication number: 20120028405
    Abstract: A method for providing a semiconductor material for photovoltaic devices, the method includes providing a sample of iron disilicide comprising approximately 90 percent or greater of a beta phase entity. The sample of iron disilicide is characterized by a substantially uniform first particle size ranging from about 1 micron to about 10 microns. The method includes combining the sample of iron disilicide and a binding material to form a mixture of material. The method includes providing a substrate member including a surface region and deposits the mixture of material overlying the surface region of the substrate. In a specific embodiment, the mixture of material is subjected to a post-deposition process such as a curing process to form a thickness of material comprising the sample of iron disilicide overlying the substrate member. In a specific embodiment, the thickness of material is characterized by a thickness of about the first particle size.
    Type: Application
    Filed: October 6, 2011
    Publication date: February 2, 2012
    Applicant: Stion Corporation
    Inventors: Howard W.H. Lee, Frederic Victor Mikulec, Bing Shen Gao, Jinman Huang
  • Patent number: 8101851
    Abstract: The invention pertains to a process for manufacturing a solar cell foil comprising the steps of: providing an etchable temporary substrate applying a front electrode of a transparent conductive oxide (TCO) onto the temporary substrate applying a photovoltaic layer onto the TCO layer applying a back electrode layer applying a permanent carrier ensuring that the front electrode and the back electrode are electrically connected in an interconnect to establish a series connection, the front and the back electrode each being interrupted by front and back groove, respectively, at different sides of the interconnect in any one of the preceding steps providing an etch resist on the non-TCO side of the temporary substrate at least at the location of the interconnect, and at least not at the entire location of the front groove selectively removing the temporary substrate where it is not covered with etch resist.
    Type: Grant
    Filed: July 16, 2004
    Date of Patent: January 24, 2012
    Assignee: Akzo Nobel N.V.
    Inventor: Gerrit Cornelis Dubbeldam
  • Publication number: 20120009728
    Abstract: An apparatus and a method for manufacturing a CIGS solar cell are disclosed. The apparatus includes a buffer chamber, a first chamber, a second chamber and a mechanical device. The first chamber and the second chamber are located adjacent to the buffer chamber respectively. The mechanical device moves a substrate among the buffer chamber, the first chamber and the second chamber. The first chamber includes a deposition device for depositing a back electrode layer onto the substrate. The second chamber includes heat treatment device and for becoming a thin-film layer onto the back electrode layer.
    Type: Application
    Filed: September 24, 2010
    Publication date: January 12, 2012
    Applicant: GCSOL TECH CO., LTD.
    Inventor: Yan-Way LI
  • Publication number: 20110306164
    Abstract: A method for manufacturing a solar cell according to an exemplary embodiment includes: forming a first doping film on a substrate; patterning the first doping film so as to form a first doping film pattern and so as to expose a portion of the substrate; forming a diffusion prevention film on the first doping film pattern so as to cover the exposed portion of the substrate; etching the diffusion prevention film so as to form spacers on lateral surfaces of the first doping film pattern; forming a second doping film on the first doping film pattern so as to cover the spacer and exposed substrate; forming a first doping region on the substrate surface by diffusing an impurity from the first doping film pattern into the substrate; and forming a second doping region on the substrate surface by diffusing an impurity from the second doping film pattern into the substrate.
    Type: Application
    Filed: September 29, 2010
    Publication date: December 15, 2011
    Inventors: Young Su KIM, Doo-Youl LEE
  • Patent number: 8058092
    Abstract: A method for providing a semiconductor material for photovoltaic devices, the method includes providing a sample of iron disilicide comprising approximately 90 percent or greater of a beta phase entity. The sample of iron disilicide is characterized by a substantially uniform first particle size ranging from about 1 micron to about 10 microns. The method includes combining the sample of iron disilicide and a binding material to form a mixture of material. The method includes providing a substrate member including a surface region and deposits the mixture of material overlying the surface region of the substrate. In a specific embodiment, the mixture of material is subjected to a post-deposition process such as a curing process to form a thickness of material comprising the sample of iron disilicide overlying the substrate member. In a specific embodiment, the thickness of material is characterized by a thickness of about the first particle size.
    Type: Grant
    Filed: September 12, 2008
    Date of Patent: November 15, 2011
    Assignee: Stion Corporation
    Inventors: Howard W. H. Lee, Frederic Victor Mikulec, Bing Shen Gao, Jinman Huang
  • Patent number: 8049103
    Abstract: A semiconductor device is provided, which comprises a first electrode, crystalline semiconductor particles, a semiconductor layer, and a second electrode. The crystalline semiconductor particles of which adjacent particles are fusion-bonded, the crystalline semiconductor particles have a first conductivity type, and the semiconductor layer has a second conductivity type which is different from the first conductivity type.
    Type: Grant
    Filed: January 12, 2007
    Date of Patent: November 1, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yasuyuki Arai
  • Patent number: 8039846
    Abstract: Disclosed are a light emitting diode having a thermal conductive substrate and a method of fabricating the same. The light emitting diode includes a thermal conductive insulating substrate. A plurality of metal patterns are spaced apart from one another on the insulating substrate, and light emitting cells are located in regions on the respective metal patterns. Each of the light emitting cells includes a P-type semiconductor layer, an active layer and an N-type semiconductor layer. Meanwhile, metal wires electrically connect upper surfaces of the light emitting cells to adjacent metal patterns. Accordingly, since the light emitting cells are operated on the thermal conductive substrate, a heat dissipation property of the light emitting diode can be improved.
    Type: Grant
    Filed: June 5, 2006
    Date of Patent: October 18, 2011
    Assignee: Seoul Opto Device Co., Ltd.
    Inventor: Jae-Ho Lee
  • Patent number: 8003432
    Abstract: A method for forming a thin film photovoltaic device. The method includes providing a transparent substrate comprising a surface region. The method forms a first electrode layer overlying the surface region of the transparent substrate. The method also forms a thin layer of indium material, using a sputtering target of indium material, overlying the first electrode layer to act as an intermediary glue layer to facilitate attachment to the first electrode layer. In a specific embodiment, the method forms a copper material overlying the thin layer of indium material. The method also forms an indium layer overlying the copper material to form a multi layered structure including at least the thin layer of indium material, copper material, and the indium layer. In a preferred embodiment, the multi-layered structure has a first thickness.
    Type: Grant
    Filed: April 17, 2009
    Date of Patent: August 23, 2011
    Assignee: Stion Corporation
    Inventor: Miljon T. Buquing
  • Patent number: 7998761
    Abstract: The present invention relates to a light emitting diode with enhanced luminance and light emitting performance due to increase in efficiency of current diffusion into an ITO layer, and a method of fabricating the light emitting diode. According to the present invention, there is manufactured at least one light emitting cell including an N-type semiconductor layer, an active layer and a P-type semiconductor layer on a substrate. The method of the present invention comprises the steps of (a) forming at least one light emitting cell with an ITO layer formed on a top surface of the P-type semiconductor layer; (b) forming a contact groove for wiring connection in the ITO layer through dry etching; and (c) filling the contact groove with a contact connection portion made of a conductive material for the wiring connection.
    Type: Grant
    Filed: December 8, 2006
    Date of Patent: August 16, 2011
    Assignee: Seoul Opto Device Co., Ltd.
    Inventors: Dae Won Kim, Yeo Jin Yoon, Duck Hwan Oh, Jong Hwan Kim
  • Publication number: 20110120552
    Abstract: A method for producing a monocrystalline solar cell having a passivated back side and a back side contact structure, having the following steps: applying a passivating dielectric layer onto the back side of the cell over the entire surface; removing the passivating layer locally in the area of bus bars and local contact locations; coating the back side of the cell homogeneously to develop an unpatterned, thin metal layer, which touches the surface of the substrate material in the areas free of the passivating layer; generating a thick layer from a conductive paste in the area of the bus bars and the local contact locations; and sintering of the thick layer at a temperature above a predefined eutectic temperature, and the formation of a eutectic, low-resistance connection of the thin metal layer to the surface of the substrate material as well as to the conductive particles of the thick layer paste.
    Type: Application
    Filed: May 5, 2009
    Publication date: May 26, 2011
    Inventors: Karsten Meyer, Hans-Joachim Krokoszinski
  • Patent number: 7947524
    Abstract: A method for processing a thin film photovoltaic module. The method includes providing a plurality of substrates, each of the substrates having a first electrode layer and an overlying absorber layer composed of copper indium gallium selenide (CIGS) or copper indium selenide (CIS) material. The absorber material comprises a plurality of sodium bearing species. The method maintains the plurality of substrates in a controlled environment after formation of at least the absorber layer through one or more processes up to a lamination process. The controlled environment has a relative humidity of less than 10% and a temperature ranging from about 10 Degrees Celsius to about 40 Degrees Celsius. The method subjects the plurality of substrates to a liquid comprising water at a temperature from about 10 Degrees Celsius to about 80 Degrees Celsius to process the plurality of substrates after formation of the absorber layer.
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: May 24, 2011
    Assignee: Stion Corporation
    Inventor: Robert D. Wieting
  • Publication number: 20110092013
    Abstract: A fragile layer is formed in a region at a depth of less than 1000 nm from one surface of a single crystal semiconductor substrate, and a first impurity semiconductor layer and a first electrode are formed at the one surface side. After bonding the first electrode and a supporting substrate, the single crystal semiconductor substrate is separated using the fragile layer or the vicinity as a separation plane, thereby forming a first single crystal semiconductor layer over the supporting substrate. An amorphous semiconductor layer is formed on the first single crystal semiconductor layer, and a second single crystal semiconductor layer is formed by heat treatment for solid phase growth of the amorphous semiconductor layer. A second impurity semiconductor layer having a conductivity type opposite to that of the first impurity semiconductor layer and a second electrode are formed over the second single crystal semiconductor layer.
    Type: Application
    Filed: December 23, 2010
    Publication date: April 21, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Fumito ISAKA, Sho KATO, Koji DAIRIKI
  • Patent number: 7923273
    Abstract: An optoelectronics chip-to-chip interconnects system is provided, including at least one packaged chip to be connected on the printed-circuit-board with at least one other packaged chip, optical-electrical (O-E) conversion mean, waveguide-board, and (PCB). Single to multiple chips interconnects can be interconnected provided using the technique disclosed in this invention. The packaged chip includes semiconductor die and its package based on the ball-grid array or chip-scale-package. The O-E board includes the optoelectronics components and multiple electrical contacts on both sides of the O-E substrate. The waveguide board includes the electrical conductor transferring the signal from O-E board to PCB and the flex optical waveguide easily stackable onto the PCB to guide optical signal from one chip-to-other chip. Alternatively, the electrode can be directly connected to the PCB instead of including in the waveguide board. The chip-to-chip interconnections system is pin-free and compatible with the PCB.
    Type: Grant
    Filed: July 31, 2007
    Date of Patent: April 12, 2011
    Assignee: Banpil Photonics, Inc.
    Inventor: Achyut Kumar Dutta
  • Patent number: 7867812
    Abstract: The invention relates to the formation of thin-film crystalline silicon using a zone-melting recrystallization process in which the substrate is a ceramic material. Integrated circuits and solar cells are fabricated in the recrystallized silicon thin film and lifted off the substrate. Following lift-off, these circuits and devices are self-sustained, lightweight and flexible and the released ceramic substrate can be reused making the device fabrication process cost effective.
    Type: Grant
    Filed: July 10, 2009
    Date of Patent: January 11, 2011
    Inventors: Duy-Phach Vu, Quoc-Bao Vu
  • Patent number: 7858431
    Abstract: A fragile layer is formed in a region at a depth of less than 1000 nm from one surface of a single crystal semiconductor substrate, and a first impurity semiconductor layer and a first electrode are formed at the one surface side. After bonding the first electrode and a supporting substrate, the single crystal semiconductor substrate is separated using the fragile layer or the vicinity as a separation plane, thereby forming a first single crystal semiconductor layer over the supporting substrate. An amorphous semiconductor layer is formed on the first single crystal semiconductor layer, and a second single crystal semiconductor layer is formed by heat treatment for solid phase growth of the amorphous semiconductor layer. A second impurity semiconductor layer having a conductivity type opposite to that of the first impurity semiconductor layer and a second electrode are formed over the second single crystal semiconductor layer.
    Type: Grant
    Filed: November 26, 2008
    Date of Patent: December 28, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Fumito Isaka, Sho Kato, Koji Dairiki
  • Patent number: 7838314
    Abstract: An organic light emitting display device includes a first substrate, an array of organic light emitting pixels formed on the substrate, a second substrate opposing the first substrate. A frit seal interconnects the first and second substrates and surrounds the array of organic light emitting pixels. A film structure interposed between the second substrate and the array of organic light emitting pixels and contacts both the second substrate and the array.
    Type: Grant
    Filed: May 13, 2009
    Date of Patent: November 23, 2010
    Assignee: Samsung Mobile Display Co., Ltd.
    Inventors: Dong-Soo Choi, Jin Woo Park, Tae-Seung Kim
  • Publication number: 20100261306
    Abstract: A photovoltaic cell is made by coating a metal foil substrate with cadmium telluride powder, moving the powder coated foil across a cold plate or series of cooled rollers to prevent the substrate from melting, while melting the cadmium telluride powder by passing the powder coated foil under a microwave energy source. This forms a thin film of cadmium telluride on the foil. The cadmium telluride coated foil is then coated with cadmium sulfide powder, which is melted by passing the powder coated foil under a microwave energy source, thereby creating a P-N junction, and the cadmium sulfide layer is coated with indium, which is fused to the cadmium sulfide layer by microwave heating.
    Type: Application
    Filed: April 8, 2009
    Publication date: October 14, 2010
    Inventor: David M. Schwartz
  • Patent number: 7700960
    Abstract: The present invention relates to a light emitting diode with enhanced luminance and light emitting performance due to increase in efficiency of current diffusion into an ITO layer, and a method of fabricating the light emitting diode. According to the present invention, there is manufactured at least one light emitting cell including an N-type semiconductor layer, an active layer and a P-type semiconductor layer on a substrate. The method of the present invention comprises the steps of (a) forming at least one light emitting cell with an ITO layer formed on a top surface of the P-type semiconductor layer; (b) forming a contact groove for wiring connection in the ITO layer through dry etching; and (c) filling the contact groove with a contact connection portion made of a conductive material for the wiring connection.
    Type: Grant
    Filed: October 23, 2009
    Date of Patent: April 20, 2010
    Assignee: Seoul Opto Device Co., Ltd.
    Inventors: Dae Won Kim, Yeo Jin Yoon, Duck Hwan Oh, Jong Hwan Kim
  • Patent number: 7691664
    Abstract: A precursor composition for the deposition and formation of an electrical feature such as a conductive feature. The precursor composition advantageously has a low viscosity enabling deposition using direct-write tools. The precursor composition also has a low conversion temperature, enabling the deposition and conversion to an electrical feature on low temperature substrates. A particularly preferred precursor composition includes silver metal for the formation of highly conductive silver features.
    Type: Grant
    Filed: December 21, 2006
    Date of Patent: April 6, 2010
    Assignee: Cabot Corporation
    Inventors: Toivo T. Kodas, Mark J. Hampden-Smith, Karel Vanheusden, Hugh Denham, Aaron D. Stump, Allen B. Schult, Paolina Atanassova, Klaus Kunze
  • Publication number: 20100075456
    Abstract: The present invention relates generally to production of photoelectric grade films or cells from semiconductor powders or dust. In one embodiment, the present invention provides a method for producing a photoelectric grade film from a semiconductor powder. The method includes providing a substrate, coating the substrate with a layer of the semiconductor powder and moving the substrate with the layer of the semiconductor powder under an energy source at a predefined rate, wherein the predefined rate is sufficient to melt the semiconductor powder by the energy source and to cool the substrate such that substantially all impurities are moved to an edge of the substrate.
    Type: Application
    Filed: May 5, 2009
    Publication date: March 25, 2010
    Inventor: ANGEL SANJURJO
  • Publication number: 20100055824
    Abstract: The present invention discloses a micro/nanostructure PN junction diode array thin-film solar cell and a method for fabricating the same, wherein a microstructure or sub-microstructure PN junction diode array, such as a nanowire array or a nanocolumns array, is transferred from a source-material wafer to two pieces of transparent substrates, which are respectively corresponding to two electric conduction types, to fabricate a thin-film solar cell. In the present invention, the micro/nanostructure PN junction diode array has advantages of a fine-quality crystalline semiconductor, and the semiconductor substrate can be reused to save a lot of semiconductor material. Besides, the present invention can make the best of sunlight energy via stacking up the solar cells made of different types of semiconductor materials to absorb different wavebands of the sunlight spectrum.
    Type: Application
    Filed: December 29, 2008
    Publication date: March 4, 2010
    Inventors: Ching-Fuh Lin, Jiun-Jie Chao, Shu-Chia Shiu
  • Patent number: 7635954
    Abstract: A structural configuration of a failsafe OLED chain with multiple OLED lighting components in series connection is described. During the manufacture of the lighting component a weak spot is specifically installed at an appropriate location of the structure in the form of a break-through layer, which in the event of a failure of the lighting component breaks down and bypasses the component with a bypass layer.
    Type: Grant
    Filed: November 30, 2007
    Date of Patent: December 22, 2009
    Assignee: Osram Opto Semiconductors GmbH
    Inventor: Peter Niedermeier
  • Publication number: 20090227065
    Abstract: A method for providing a semiconductor material for photovoltaic devices, the method includes providing a sample of iron disilicide comprising approximately 90 percent or greater of a beta phase entity. The sample of iron disilicide is characterized by a substantially uniform first particle size ranging from about 1 micron to about 10 microns. The method includes combining the sample of iron disilicide and a binding material to form a mixture of material. The method includes providing a substrate member including a surface region and deposits the mixture of material overlying the surface region of the substrate. In a specific embodiment, the mixture of material is subjected to a post-deposition process such as a curing process to form a thickness of material comprising the sample of iron disilicide overlying the substrate member. In a specific embodiment, the thickness of material is characterized by a thickness of about the first particle size.
    Type: Application
    Filed: September 12, 2008
    Publication date: September 10, 2009
    Applicant: Stion Corporation
    Inventors: HOWARAD W.H. LEE, Frederic Victor Mikulec, Bing Shen Gao, Jinman Huang
  • Patent number: 7569431
    Abstract: A semiconductor device and method of manufacturing the same includes an n?-single crystal silicon substrate, with an oxide film selectively formed thereon. On the oxide film, gate polysilicon is formed. The surface of the gate polysilicon is covered with a gate oxide film whose surface is covered with a cathode film doped in an n-type with an impurity concentration higher than that of the substrate as an n?-drift layer. In the cathode film, a section in contact with the substrate becomes an n+-buffer region with a high impurity concentration, next to which a p-base region is formed. Next to the p-base region, an n+-source region is formed. On the cathode film, an interlayer insulator film is selectively formed on which an emitter electrode is formed. A semiconductor device such as an IGBT is obtained with a high rate of acceptable products, an excellent on-voltage to turn-off loss tradeoff and an excellent on-voltage to breakdown voltage tradeoff.
    Type: Grant
    Filed: February 4, 2008
    Date of Patent: August 4, 2009
    Assignee: Fuji Electric Holdings Co., Ltd.
    Inventor: Manabu Takei
  • Publication number: 20090130795
    Abstract: The disclosed subject matter relates to the use of laser crystallization of thin films to create epitaxially textured crystalline thick films. In one or more embodiments, a method for preparing a thick crystalline film includes providing a film for crystallization on a substrate, wherein at least a portion of the substrate is substantially transparent to laser irradiation, said film including a seed layer having a predominant surface crystallographic orientation; and a top layer disposed above the seed layer; irradiating the film from the back side of the substrate using a pulsed laser to melt a first portion of the top layer at an interface with the seed layer while a second portion of the top layer remains solid; and re-solidifying the first portion of the top layer to form a crystalline laser epitaxial with the seed layer thereby releasing heat to melt an adjacent portion of the top layer.
    Type: Application
    Filed: November 21, 2008
    Publication date: May 21, 2009
    Applicant: TRUSTEES OF COLUMBIA UNIVERSITY
    Inventor: James S. IM
  • Publication number: 20090042334
    Abstract: A CMOS image sensor includes a substrate including silicon, a silicon germanium (SiGe) epitaxial layer formed over the substrate, the SiGe epitaxial layer formed through epitaxial growth and doped with a predetermined concentration level of impurities, an undoped silicon epitaxial layer formed over the SiGe epitaxial layer by epitaxial growth, and a photodiode region formed from a top surface of the undoped silicon epitaxial layer to a predetermined depth in the SiGe epitaxial layer.
    Type: Application
    Filed: October 2, 2008
    Publication date: February 12, 2009
    Inventor: Han-Seob Cha
  • Patent number: 7422921
    Abstract: This invention is related to a micromesh material and a mono-crystal high frequency capacitor manufactured with said micromesh material as well as the producing method for the mono-crystal high frequency capacitor, i.e., disperse a colloidal material unevenly to form a sub-micrometer ceramic cell structure to get a micromesh mono-crystal material on the basis of the theory of liquid-liquid phase transformation, and produce capacitors with the obtained material to enhance the high frequency characteristics of those capacitors with the micromesh mono-crystal structure (air medium) of dielectric ceramics.
    Type: Grant
    Filed: November 27, 2002
    Date of Patent: September 9, 2008
    Assignee: ABC Taiwan Electronics Corp.
    Inventor: Chavy Hsu
  • Publication number: 20080185674
    Abstract: The present invention relates to a photodiode of an image sensor using a three-dimensional multi-layer substrate, and more particularly, to a method of implementing a buried type photodiode and a structure thereof, and a trench contact method for connecting a photodiode in a multi-layer substrate and a transistor for signal detection.
    Type: Application
    Filed: March 11, 2008
    Publication date: August 7, 2008
    Applicants: Lumiense Photonics Inc., HANVISION CO., LTD.
    Inventor: Robert Steven Hannebauer
  • Patent number: 7364939
    Abstract: In order to provide an active matrix display device in which a thick insulating film is preferably formed around an organic semiconductive film of a thin film luminescent device without damaging the thin film luminescent device, the active matrix display device is provided with a bank layer (bank) along a data line (sig) and a scanning line (gate) to suppress formation of parasitic capacitance in the data line (sig), in which the bank layer (bank) surrounds a region that forms the organic semiconductive film of the thin film luminescent device by an ink-jet process. The bank layer (bank) includes a lower insulating layer formed of a thick organic material and an upper insulating layer of an organic material which is deposited on the lower insulating layer and has a smaller thickness so as to avoid contact of the organic semiconductive film with the upper insulating layer.
    Type: Grant
    Filed: March 4, 2005
    Date of Patent: April 29, 2008
    Assignee: Seiko Epson Corporation
    Inventor: Ichio Yudasaka
  • Patent number: 7365431
    Abstract: A semiconductor device having a first wiring layer including first wirings on a substrate, a contact layer on the first wiring layer and including contacts connected to the first wirings, and a second wiring layer on the contact layer and including second wirings connected to the contacts. Contact pitch is larger than the minimum wiring pitch of the first wirings or the minimum wiring pitch of the second wirings.
    Type: Grant
    Filed: December 3, 2004
    Date of Patent: April 29, 2008
    Assignee: NEC Electronics Corporation
    Inventor: Yoshihisa Matsubara
  • Patent number: 7172923
    Abstract: An imaging device unit comprises a CCD chip and a substrate on which the CCD chip is soldered. A light receiving surface is provided in the front surface of the CCD chip. A dustproof member for protect the light receiving surface from dust is attached around the light receiving surface. Chip terminals are arranged between the light receiving surface and the dustproof member. When the CCD chip is pressed against the rear surface of the substrate, the dustproof member is elastically deformed and tightly makes contact with the substrate. Since ultrasound is applied to the chip terminals and the substrate terminals in this state to melt them, the CCD chip is positioned in parallel with the substrate. Upon stopping ultrasound horns, both of the terminals are immediately soldered to each other, so that the CCD chip is securely fixed on the substrate with ease.
    Type: Grant
    Filed: April 16, 2003
    Date of Patent: February 6, 2007
    Assignee: Fuji Photo Film Co., Ltd.
    Inventor: Atsushi Misawa
  • Patent number: 7163836
    Abstract: A method of manufacturing a light emitting device is provided which requires low cost, is easy, and has high throughput. The method of manufacturing a light emitting device is characterized in that: a solution containing a light emitting material is ejected to an anode or cathode under reduced pressure; a solvent in the solution is volatilized until the solution reaches the anode or cathode; and the remaining light emitting material is deposited on the anode or cathode to form a light emitting layer. A burning step for reduction in film thickness is not required after the solution application. Therefore, the manufacturing method, which requires low cost and is easy but which has high throughput, can be provided.
    Type: Grant
    Filed: January 14, 2005
    Date of Patent: January 16, 2007
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Takashi Hamada, Satoshi Seo
  • Patent number: 7008813
    Abstract: A method of fabricating a germanium photodetector includes preparing a silicon wafer as a silicon substrate; depositing a layer of silicon nitride on the silicon substrate; patterning and etching the silicon nitride layer; depositing a first germanium layer on the silicon nitride layer; patterning and etching the germanium layer wherein a portion of the germanium layer is in direct physical contact with the silicon substrate; depositing a layer of silicon oxide on the germanium layer wherein the germanium layer is encapsulated by the silicon oxide layer; annealing the structure at a temperature wherein the germanium melts and the other layers remain solid; growing a second, single-crystal layer of germanium on the structure by liquid phase epitaxy; selectively removing the silicon oxide layer; and completing the germanium photodetector.
    Type: Grant
    Filed: February 28, 2005
    Date of Patent: March 7, 2006
    Assignee: Sharp Laboratories of America, Inc..
    Inventors: Jong-Jan Lee, Jer-Shen Maa, Douglas J. Tweet, Sheng Teng Hsu
  • Patent number: 6974719
    Abstract: The invention relates to an optical module and to method for manufacturing an optical module comprising the steps of: providing a groove in a substrate for positioning an optical component, providing the optical component, bonding the optical component to the groove by means of an aluminium-oxide bonding process, whereby an aluminium layer is formed on a lower portion of the optical component.
    Type: Grant
    Filed: December 4, 2002
    Date of Patent: December 13, 2005
    Assignee: Avanex Corporation
    Inventors: Joachim Kabs, Ingo Karla
  • Patent number: 6972469
    Abstract: A PIN diode includes a first p-area, an n-area, and in between an intermediate area on a first surface of a substrate, wherein a doping concentration of the intermediate area is lower than a doping concentration of the p-area and lower than a doping concentration of the n-area. Further, the PIN diode includes a first electrically conductive member, which is arranged on a side of the p-area, which faces away from the intermediate area, and a second electrically conductive member, which is arranged on a side of the n-area, which faces away from the intermediate area. The PIN diode is preferably separated from the substrate by an insulating layer, covered by a further insulating layer on the surface, which faces away from the substrate, and laterally surrounded by a trench filled with an insulating material, such that it is essentially fully insulated and encapsulated.
    Type: Grant
    Filed: December 8, 2003
    Date of Patent: December 6, 2005
    Assignee: Infineon Technologies AG
    Inventors: Raimund Peichl, Philipp Seng
  • Patent number: 6939753
    Abstract: A liquid crystal display device includes an upper plate, a lower plate, and a liquid crystal. A sealant is formed along edges of the upper and lower plates to join the upper plate with the lower plate, and a protrusion separates the sealant from a picture displaying area at an inner portion of the upper and lower plates. The liquid crystal injected into the picture displaying area.
    Type: Grant
    Filed: June 11, 2001
    Date of Patent: September 6, 2005
    Assignee: LG. Philips LCD Co., Ltd.
    Inventor: Sang Seok Lee
  • Patent number: 6887733
    Abstract: A method of encapsulating an organic device including flash evaporating a getter layer on the substrate is disclosed. The getter layer comprises an alkaline earth metal, such as barium. The getter layer serves to protect the active components by absorbing surrounding moisture and gases.
    Type: Grant
    Filed: September 11, 2002
    Date of Patent: May 3, 2005
    Assignee: Osram Opto Semiconductors (Malaysia) Sdn. Bhd
    Inventors: Hagen Klausmann, Bernd Fritz
  • Patent number: 6858464
    Abstract: A method of manufacturing a light emitting device is provided which requires low cost, is easy, and has high throughput. The method of manufacturing a light emitting device is characterized in that: a solution containing a light emitting material is ejected to an anode or cathode under reduced pressure; a solvent in the solution is volatilized until the solution reaches the anode or cathode; and the remaining light emitting material is deposited on the anode or cathode to form a light emitting layer. A burning step for reduction in film thickness is not required after the solution application. Therefore, the manufacturing method, which requires low cost and is easy but which has high throughput, can be provided.
    Type: Grant
    Filed: June 18, 2003
    Date of Patent: February 22, 2005
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Takashi Hamada, Satoshi Seo
  • Patent number: 6699739
    Abstract: Measure of forming an EL layer by selectively depositing through evaporation a material for forming the EL layer at a desired location is provided. When a material for forming an EL layer is deposited, a mask (113) is provided between a sample boat (111) and a substrate (110). By applying voltage to the mask (113), the direction of progress of the material for forming the EL layer is controlled to be selectively deposited at a desired location.
    Type: Grant
    Filed: March 2, 2001
    Date of Patent: March 2, 2004
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masaaki Hiroki, Noriko Ishimaru
  • Patent number: 6692981
    Abstract: A method of manufacturing a solar cell comprises interposing an intermediate layer containing p-type or n-type impurity between a silicon thin film and a support substrate, and heating all or part of the structure thus formed to a temperature at which the impurity contained in the intermediate layer diffuses into the silicon thin film, forming a high-concentration impurity layer in the silicon thin film.
    Type: Grant
    Filed: September 24, 2001
    Date of Patent: February 17, 2004
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventors: Hidetaka Takato, Ryuichi Shimokawa
  • Publication number: 20040026690
    Abstract: The invention relates to a memory, based on organic material and applied in combination with an organic integrated circuit (integrated plastic circuit). The invention particularly relates to a memory for a RFID-Tag (RFID-tags: radio frequency identification tags) and several methods for describing a memory.
    Type: Application
    Filed: March 13, 2003
    Publication date: February 12, 2004
    Inventors: Adolf Bernds, Wolfgang Clemens, Walter Fix, Markus Lorenz, Henning Rost
  • Patent number: 6670543
    Abstract: There are now provided thin-film solar cells and method of making. The devices comprise a low-cost, low thermal stability substrate with a semiconductor body deposited thereon by a deposition gas. The deposited body is treated with a conversion gas to provide a microcrystalline silicon body. The deposition gas and the conversion gas are subjected to a pulsed electromagnetic radiation to effectuate deposition and conversion.
    Type: Grant
    Filed: January 25, 2002
    Date of Patent: December 30, 2003
    Assignee: Schott Glas
    Inventors: Manfred Lohmeyer, Stefan Bauer, Burkhard Danielzik, Wolfgang Möhl, Nina Freitag
  • Publication number: 20030235935
    Abstract: A method of manufacturing a light emitting device is provided which requires low cost, is easy, and has high throughput. The method of manufacturing a light emitting device is characterized in that: a solution containing a light emitting material is ejected to an anode or cathode under reduced pressure; a solvent in the solution is volatilized until the solution reaches the anode or cathode; and the remaining light emitting material is deposited on the anode or cathode to form a light emitting layer. A burning step for reduction in film thickness is not required after the solution application. Therefore, the manufacturing method, which requires low cost and is easy but which has high throughput, can be provided.
    Type: Application
    Filed: June 18, 2003
    Publication date: December 25, 2003
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Takashi Hamada, Satoshi Seo
  • Patent number: 6649824
    Abstract: A photoelectric conversion device comprising at least an electron acceptive charge transfer layer, an electron donative charge transfer layer, and a light absorption layer existing between the charge transfer layers, wherein either one of the charge transfer layers comprises a semiconductor acicular crystal layer comprising an aggregate of acicular crystals or a mixture of an acicular crystal and another crystal, and a method of producing the device are disclosed. Consequently, a photoelectric conversion device being capable of smoothly carrying out transfer of electrons and having high photoelectric conversion efficiency is provided.
    Type: Grant
    Filed: September 20, 2000
    Date of Patent: November 18, 2003
    Assignee: Canon Kabushiki Kaisha
    Inventors: Tohru Den, Hiroshi Okura
  • Publication number: 20030203532
    Abstract: An imaging device unit comprises a CCD chip and a substrate on which the CCD chip is soldered. A light receiving surface is provided in the front surface of the CCD chip. A dustproof member for protect the light receiving surface from dust is attached around the light receiving surface. Chip terminals are arranged between the light receiving surface and the dustproof member. When the CCD chip is pressed against the rear surface of the substrate, the dustproof member is elastically deformed and tightly makes contact with the substrate. Since ultrasound is applied to the chip terminals and the substrate terminals in this state to melt them, the CCD chip is positioned in parallel with the substrate. Upon stopping ultrasound horns, both of the terminals are immediately soldered to each other, so that the CCD chip is securely fixed on the substrate with ease.
    Type: Application
    Filed: April 16, 2003
    Publication date: October 30, 2003
    Applicant: FUJI PHOTO FILM CO., LTD.
    Inventor: Atsushi Misawa
  • Publication number: 20030192584
    Abstract: The invention, in various embodiments, is directed to photovoltaic cells, modules and methods for making the same, wherein a plurality of discrete portions of metal foil having an interconnected nanoparticle material formed thereon are disposed, preferably as strips having a controlled size and relative spacing, between first and second flexible substrates.
    Type: Application
    Filed: January 24, 2003
    Publication date: October 16, 2003
    Applicant: Konarka Technologies, Inc.
    Inventors: Bill Beckenbaugh, Russell Gaudiana, Alan Montello, Edmund Montello
  • Patent number: 6576831
    Abstract: Directionally solidified, multicrystalline silicon having a low proportion of electrically active grain borders, its manufacturing and utilisation, as well as solar cells comprising said silicon and a method of manufacturing said cells.
    Type: Grant
    Filed: November 14, 2001
    Date of Patent: June 10, 2003
    Assignee: Deutsche Solar GmbH
    Inventors: Peter Woditsch, Gunther Stollwerck, Christian Hässler, Wolfgang Koch
  • Publication number: 20030041895
    Abstract: The disclosure describes an economical and environmentally benign method to recover crystalline silicon metal kerf from wiresaw slurries and to shape and sinter said recovered crystalline silicon kerf into thin-layer PV cell configurations with enhanced surface texture for metallization and reduced optical reflection losses.
    Type: Application
    Filed: August 23, 2002
    Publication date: March 6, 2003
    Inventors: Romain Louis Billiet, Hanh Thi Nguyen
  • Publication number: 20030020078
    Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. Optical processing layers can be placed on monocrystalline layers to process photons produced in the monocrystalline layers.
    Type: Application
    Filed: July 25, 2001
    Publication date: January 30, 2003
    Applicant: MOTOROLA, INC.
    Inventors: Tomasz Klosowiak, Kevin Jelley, George Valliath, Barbara Foley Barenburg, Daniel Gamota