Abstract: An antifuse structure of the present invention comprises an antifase layer and a bottom electrode which are immune to the damages caused by harmful processing environment. The three major components of the antifuse—the bottom electrode, the antifuse layer and the top buffer layer are formed consecutively in a friendly manufacturing environment. This antifuse structure can substantially improve the antifuse manufacturability.

Abstract: A semiconductor processing system having a holding chamber coupled to a mainframe processing system and at least one loadlock chamber coupled to the holding chamber in which unprocessed wafers are transferred from the loadlock chamber to the holding chamber for subsequent processing by the mainframe system.

Abstract: A multi-level shelf degas station relying on at least two heaters integrated within wafer holding shelves or slots, where the semiconductor wafers do not have direct contact with the heater shelves. The heaters provide conduction heating. In order to degas a wafer, the heater and wafer holder assembly is positioned in a sequential manner through each wafer slot to the next available slot. If a degassed wafer exists in the slot, a transfer chamber arm removes it. A loader arm then places a wafer in the available, empty slot and the stage is moved upwards to receive the wafer from the loader arm. The transfer chamber arm removes an individual wafer from the heater and wafer holder assembly allowing the removed wafer to be individually processed while the other wafers remain in the heater and wafer holder assembly. In some instances, a loader arm may also remove wafers.

Abstract: A method of forming an optical marker layer for etch endpoint determination in integrated circuit fabrication processes is disclosed. The optical marker layer is used in conjunction with organic and/or carbon-containing material layers that are used as bulk insulating materials and barrier materials. The optical marker layer is formed on the bulk insulating material layer and/or the barrier material layer by incorporating an optical marker into the surface thereof. The optical marker is incorporated into the surface of the bulk insulating material layer and/or the barrier material layer by treating such layer with an optical marker-containing gas. The optical marker layer provides an optical marker emission spectrum when it is etched during a subsequent patterning step.

Abstract: A method and apparatus for producing schedules for a wafer in a multichamber semiconductor wafer processing tool comprising the steps of providing a trace defining a series of chambers that are visited by a wafer as the wafer is processed by the tool; initializing a sequence generator with a value of a variable defining initial wafer positioning within the tool; generating all successor variables for the initial variable value to produce a series of values of the variable that represent a partial schedule; backtracking through the series of variables to produce further partial schedules; and stopping the backtracking when all possible variable combinations are produced that represent all possible valid schedules for the trace. All the possible schedules are analyzed to determine a schedule that produces the highest throughput of all the schedules.

Abstract: A substrate processing apparatus includes a plurality of evacuable treatment chambers connected to one another via an evacuable common chamber, and the common chamber is provided with means for transporting a substrate between each treatment chamber. More specifically, a substrate processing apparatus includes a plurality of evacuable treatment chambers, at least one of said treatment chambers having a film formation function through a vapor phase reaction therein, at least one of said treatment chambers having an annealing function with light irradiation and at least one of said treatment chambers having a heating function therein. The apparatus also has a common chamber through which said plurality of evacuable treatment chambers are connected to one another, and a transportation means provided in said common chamber for transporting a substrate between each treatment chamber.

Abstract: A cluster tool for forming semiconductor devices using a wafer process includes: at least a load port where wafers are loaded; a front end system including an ATM robot and an ATM aligner, the front end system positioned under atmospheric pressure in a clean room condition; at least a load lock chamber including at least a vacuum wafer transfer device; at least a process module where the wafer process are conducted on the wafers; and at least a slot valve located between the load lock chamber and the process module; wherein the ATM robot transfers the wafers from the load port to the ATM aligner for a positional aligning and then transfers the positional-aligned wafers to the vacuum wafer transfer device; wherein the ATM aligner aligns the wafers for adequate process in the process module; and wherein the vacuum wafer transfer device includes at least a end effector that supports the wafers transferring by the ATM robot, and then the vacuum transfer device puts the wafers into the process module for the wafer

Abstract: In a system and method for scheduling the movement of wafers in a wafer-processing tool, the wafer-processing tool can include a load module, a wafer-transfer unit, a process module, and a scheduler. The scheduler can be configured to generate a schedule for the movement of wafers in the wafer-processing tool based on the duration of the operations to be performed by the wafer-transfer unit and the process module in processing the wafers.

Abstract: A method of forming a low dielectric constant silicate material for use in integrated circuit fabrication processes is disclosed. The low dielectric constant silicate material is formed by reacting by reacting a gas mixture comprising an organosilane compound, an oxygen source, and an inert gas. Thereafter, a silicon carbide cap layer is formed on the silicate material by reacting a gas mixture comprising a silicon source and a carbon source. The silicon carbide cap layer protects the underlying organosilicate layer from cracking and peeling when it is hardened during a subsequent annealing step.

Abstract: An integrated workpiece vacuum processing system for processing semiconductor workpieces is provided using a stacked chamber design. The processing system comprises a multiple chamber support unit having a plurality of processing chamber support bays arranged in rows and columns wherein a vacuum processing chamber module is received in each support bay and a transfer chamber is coupled to the plurality of processing chamber modules.

Abstract: There is provided a clustered device for manufacturing a semiconductor device in which a cleaning chamber, a rapid thermal processing chamber, an optical measurement chamber, and the like are arranged around a load-lock room. In an optical measurement system, there are disposed an exciting light source, a measuring light source, a light detector, a control/analyze system, and the like. During the formation of an oxide film, for example, a wafer is cleaned in the cleaning chamber and then the amount of a natural oxide film remaining on the wafer or the like is measured by optical modulation reflectance spectroscopy in the optical measurement chamber. Thereafter, the wafer is oxidized in the rapid thermal processing chamber. As a result, the surface of the wafer is prevented from being oxidized on exposure to an atmosphere and the surface state of the wafer can be monitored in the course of sequential process steps.

Abstract: A method of manufacturing flash memory. The method includes using a single wafer consecutive system process. A silicon wafer is placed inside one of the reaction chambers of a chemical vapor deposition station. Tunneling oxide layer, silicon nitride floating gate, silicon oxide layer and control gate are simultaneously formed over wafers inside the station. Breaking the vacuum inside the station and cleaning the wafer are unnecessary between various processing steps.

Abstract: A system for processing a wafer is provided. Ultraviolet light radiates through a first amount of oxygen gas in an ozone generation chamber so that the first amount of oxygen gas is converted to a first amount of ozone gas. The first amount of ozone gas flows from the ozone generation chamber into a loadlock chamber and a wafer is exposed to the first amount of ozone gas. The ultraviolet light also radiates through a window and then through a second amount of oxygen gas in the loadlock chamber so that the second amount of unconverted gas is converted to a second amount of ozone gas. The wafer held by the wafer holder is also exposed to the second amount of ozone gas.

Abstract: A wafer handling system for a wafer processing apparatus includes a wafer load lock chamber, a wafer processing chamber and a transfer chamber operatively coupled to the wafer load lock chamber and the wafer processing chamber. The transfer chamber includes a wafer transfer mechanism comprising a transfer arm pivotably coupled to a portion of the transfer chamber which forms an axis. The transfer arm is operable to rotate about the axis to transfer a wafer between the wafer load lock chamber and the process chamber in a single axis wafer movement. The invention also includes a method of transferring a wafer to a wafer processing apparatus. The method includes loading a wafer into a wafer load lock chamber and rotating a transfer arm into the wafer load lock chamber to retrieve the wafer therein.

Abstract: When both a wafer transfer means in a first transfer device and a wafer transfer means in a second transfer device move downward at the same time, the amount of exhaust air by an exhaust fan is increased by the control of a control section, whereby the down flow of clean air is intensified. Turbulence of air flow caused when both the wafer transfer means in the first transfer device and the wafer transfer means in the second transfer device move downward at the same time is absorbed by the down flow intensified as described above.

Abstract: A semiconductor processing system having a holding chamber coupled to a mainframe processing system and at least one loadlock chamber coupled to the holding chamber in which unprocessed wafers are transferred from the loadlock chamber to the holding chamber for subsequent processing by the mainframe system.

Abstract: A wafer processing system which requires no isolation between the operational areas within the processing system. The system of the present invention includes operational areas, such as a loading area, a transport area, and a reactor or thermal processing area. Advantageously, since there are no isolation devices or gate valves separating the areas, the processing system effectively has each operational area combined into a “single” chamber. Preferably, the single chamber has a single slit valve, hinge door, or other vacuum sealable door disposed proximate to the loading area to allow for the removal/insertion of the wafers into the loading area. Once the door to the loading area has been closed the internal pressure within the chamber can be kept uniform throughout each operational area.

Abstract: Plasma treating a low-k dielectric layer (104) using an oxidation reaction (e.g., O2) to improve patterning. Resist poisoning occurs due to an interaction between low-k films (104), such as OSG, and DUV resist (130, 132). The plasma treatment is performed to either pretreat a low-k dielectric (104) before forming the pattern (130, 132), during a rework of the pattern (130, 132), or between via and trench patterning to reduce resist poisoning.

Abstract: After via etch, a low-k dielectric layer (104) is treated with an in-situ O2 plasma. Resist poisoning is caused by a N source that causes an interaction between low-k films (104), such as OSG, and DUV resist (130, 132). The in-situ plasma treatment immediately removes the source of poisoning to reduce or eliminate poisoning at trench patterning.

Abstract: A wafer processing system occupies minimal floor space by using vertically mounted modules such as reactors, load locks, and cooling stations. Further saving in floor space is achieved by using a loading station which employs rotational motion to move a wafer carrier into a load lock. The wafer processing system includes a robot having extension, rotational, and vertical motion for accessing vertically mounted modules. The robot is internally cooled and has a heat resistant end-effector, making the robot compatible with high temperature semiconductor processing.

Abstract: A method of manufacturing flash memory. The method includes using a single wafer consecutive system process. A silicon wafer is placed inside one of the reaction chambers of a chemical vapor deposition station. Tunneling oxide layer, silicon nitride floating gate, silicon oxide layer and control gate are simultaneously formed over wafers inside the station. Breaking the vacuum inside the station and cleaning the wafer are unnecessary between various processing steps.

Abstract: Embodiments of the present invention provide a process sequence and related hardware for filling a patterned feature on a substrate with a metal, such as copper. The sequence comprises first forming a reliable barrier layer in the patterned feature to prevent diffusion of the metal into the dielectric layer through which the patterned feature is formed. One sequence comprises forming a generally conformal barrier layer over a patterned dielectric, etching the barrier layer at the bottom of the patterned feature, depositing a second barrier layer, and then filling the patterned feature with a metal, such as copper.

Abstract: A method of searching for clustering faults is employed for semiconductor device manufacturing, The method enters data on faults present in a search target, calculates a frequency distribution of the faults in unit cells divided from the search target, approximates the frequency distribution by overlaying at least two discrete distribution functions, and searches for clustering faults according to weights of the discrete distribution functions on the frequency distribution.

Abstract: A substrate processing apparatus includes a housing, a process tube for performing variable batch processes on substrates, and product substrate carriers. The product substrate carriers have a capacity of a predetermined number of substrates. A number of the product substrates processed during one batch process are less than or equal to the predetermined number of the substrates. All of the product substrates contained in one product substrate carrier is processed in the process tube at a same time.

Abstract: A method of producing a semiconductor device having a multilayered wiring conductors and a system for producing the same. The nonuniformity of SOG coating film effectively suppressed and various treatments are simple and less time-consuming. A wiring conductor is formed on a semiconductor substrate, and an insulating layer covering the wiring conductor and the semiconductor substrate is formed, and the insulating layer is then subjected to a wet etching prior to the formation of SOG layer, thereby to increase a wettabiltity by the coating solution on the insulating layer.

Abstract: A method and apparatus for analyzing and comparing in real-time the presence of contaminants in a semiconductor substrate processing system. The analysis is made and compared against a statistical baseline of data points established from the analysis of acceptable substrates undergoing the same procedure. A decision can then be made as to whether to remove the wafers for reprocessing. The comparison is to be made not only with the above baseline, but also in accordance with process dependent information provided by a supplemental data port in the processing tool. Thus, the baseline is dynamic and not a static, pre-determined figure.

Abstract: Disclosed is an apparatus for manufacturing a semiconductor device including a metal film which is formed on a semiconductor substrate in a film formation region containing the interior of a hole formed in the semiconductor substrate. The apparatus includes a degassing chamber, a film forming chamber, and a cooing chamber. The degassing chamber 34 is provided for carrying out a degassing process by heating the semiconductor substrate to a degassing temperature. The film forming chamber 40 is provided for forming a metal film on the film formation region in a state in which the semiconductor substrate is heated to a film formation temperature. The cooling chamber 38 is provided for cooling, after completion of the degassing process and before beginning of the formation of the metal film, the semiconductor substrate to a cold temperature being lower than the film formation temperature and in a range of −50° C. to 150° C.

Abstract: A new configuration of a basic concatenatable integrated modular multiple chamber vacuum processing system for wafer manufacturing vacuum processes is disclosed. The basic system includes at least one multiple ported transfer vacuum chamber, an R-&thgr; transfer means contained within each chamber, a multiplicity of ports adaptable for appending a variety of vacuum process chambers as well as forming entrance/exit ports with at least one dual port pass through chamber attached to one entrance/exit port. Each pass through chamber contains a wafer alignment and/or orientation means for aligning or orienting the wafer as necessary in any of the appended process chambers. The configuration minimizes alignment or orientation errors due to inherent instability of the concatenated transfer means operations.

Abstract: A semiconductor processing apparatus includes a load chamber, an unload chamber, a common transfer chamber, a first process chamber, and a second process chamber, which are connected via gate valves. The load and unload chambers are connected to a first vacuum-exhaust mechanism including a common dry pump. The common transfer chamber is connected to a second vacuum-exhaust mechanism including a dry pump. The first and second processes chambers are connected to a third vacuum-exhaust mechanism including a common dry pump, and first and second turbo molecular pumps. The processing apparatus includes a controller which can drive and stop the dry pumps independently of each other in coordination with open/closed switching of the gate valves, while keeping the turbo molecular pumps driven.

Abstract: A method for forming high quality integrated circuit devices and apparatus therefor. The method includes the steps of forming an oxide layer on a semiconductor material wafer and then depositing a nitride or oxynitride layer over the oxide layer. All steps being taken without exposing the wafer to surrounding atmosphere. The invention also relates to a cluster tool for carrying out the above steps.

Abstract: A method for forming a film according to the invention includes a setting step for putting an object to be processed in a processing container that can be brought into a vacuum, and a film-forming step for introducing both of a high-melting-point metal composition gas and a reducing gas into the processing container in order to deposit a predetermined film onto a surface of the object to be processed, subsequently to the setting step. In addition, the method also includes a pre-flowing step for introducing only one of the high-melting-point metal composition gas and the reducing gas into the processing container for a predetermined time, before the setting step.

Abstract: A method of manufacturing thin film field effect transistors is described. The channel region of the transistors is formed by depositing an amorphous semiconductor film in a first sputtering apparatus followed by thermal treatment for converting the amorphous phase to a polycrystalline phase. The gate insulating film is formed by depositing an oxide film in a second sputtering apparatus connected to the first apparatus through a gate valve. The sputtering for the deposition of the amorphous semiconductor film is carried out in an atmosphere comprising hydrogen in order to introduce hydrogen into the amorphous semiconductor film. On the other hand the gate insulating oxide film is deposited by sputtering in an atmosphere comprising oxygen.

Abstract: In a method of manufacturing a semiconductor device having a capacitor portion consisting of a lower electrode, a dielectric film, and an upper electrode on a semiconductor substrate, a silicon film is formed on a surface of the lower electrode and a surface of an insulating film adjacent to the lower electrode. Annealing is preformed in an atmosphere containing nitrogen or ammonia to nitride the silicon film. A silicon nitride film is formed by LP-CVD.

Abstract: Resin sealed lead frames are processed by modular processing work stations related in number to a plurality of steps used in processing the lead or leads of the resin sealed lead frame. The work stations are separate modules which are detachably interconnected, whereby the number of modules can be exactly correlated to the number of steps actually required for processing the lead or leads of the resin sealed lead frame. As required, modules can be added or omitted. The resin sealed lead frame is sequentially advanced through the modules in steps corresponding to at least two pitches, whereby one pitch is defined as the on-center spacing between two neighboring products on the lead frame. Such feed advance permits performing at least two processing steps simultaneously. Thus, the method for processing the resin sealed lead frame and the apparatus therefore are adaptable to a change in the type of processing and to the production volume.

Abstract: The present invention provides an effective barrier layer for improved via fill in high aspect ratio sub-micron apertures at low temperature, particularly at the contact level on a substrate. In one aspect of the invention, a feature is filled by first depositing a barrier layer onto a substrate having high aspect ratio contacts or vias formed thereon. The barrier layer is preferably comprised of Ta, TaNx, W, WNx, or combinations thereof. A CVD conformal metal layer is then deposited over the barrier layer at low temperatures to provide a conformal wetting layer for a PVD metal. Next, a PVD metal layer is deposited onto the previously formed CVD conformal metal layer at a temperature below that of the melting point temperature of the metal to allow flow of the CVD conformal layer and the PVD metal layer into the vias.

Abstract: A batch process for the high-pressure forming of metal plugs in the dielectric layers of semiconductor wafers. After holes are etched in the dielectric layer of each wafer, and a layer of a metal such as aluminum deposited over the dielectric, both the etching and the deposition being done in vacuum chamber cluster machines, the wafers are removed from the cluster machines and placed together in a high pressure chamber where they are subjected to high isostatic pressure that forces the metal into the holes.

Abstract: A cluster tool includes a block which is formed with an inner high vacuum chamber, at least two loadlock chambers that are in fluid communication with the high vacuum chamber, and at least two slot valves for selectively isolating each loadlock chamber from the high vacuum chamber. The cluster tool also includes a high vacuum pump that is connected to the high vacuum chamber and a water pump comprising a refrigeration unit and a cryoplate. The cryoplate is cooled by the refrigeration unit and projects into the high vacuum chamber between the loadlock chambers. Selective operation of the slot valves allows a single water pump to serve a plurality of loadlock chambers. Each loadlock chamber includes a refrigerated platen that projects into the loadlock chamber, a heat lamp assembly that radiates into the loadlock chamber, and a tray for holding the wafer therein. The platen has a cooling system for selectively cooling the wafer, and selective radiation of the heat lamp assembly degasses the wafer.

Abstract: An apparatus and method for reducing particles in reactors. The apparatus includes an enclosure with a wafer handling chamber connected by an isolation gate valve to a processing chamber. Pipes deliver purge gas into the wafer handling chamber to eliminate particles from the enclosure. A pilot operated back pressure regulator regulates the delivery and removal of the purge gas. The apparatus actuates the isolation gate valve in a controlled rate to reduce disturbances from the purge gas entering into the enclosure. A Bernoulli wand is provided for lifting and holding a single semiconductor wafer. A dome loaded regulator actuated by a pilot gas is used to control the ramp rates of gas to the Bernoulli wand. The ramping rates of the Bernoulli wand gas can be controlled by restrictions and check valves in the pilot gas line. The apparatus also utilizes ionizers in the purge gas lines entering the wafer handling chamber and load locks.

Abstract: A wafer processing method is provided for processing a plurality of wafer lots concurrently in a plurality of different tanks. Each wafer lot is assigned a specific start number, position number, tank number and wafer number. Upon a wafer completing a process in a tank, a finish signal is generated, and a next wafer lot information for a wafer lot that needs the completed tank for processing is loaded into a memory. Once the tank is free and available, the next wafer from a wafer lot is moved in while all other tanks are being processed independently and concurrently. The wafer lots do not need to queue in sequence for other wafer lots to complete processing in different tanks. Total processing time can therefore be reduced and through-put increased.

Abstract: A method and apparatus are provided for forming a silicide on a semiconductor substrate by integrating under a constant vacuum the processes of removing an oxide from a surface of a semiconductor substrate and depositing a metal on the cleaned surface without exposing the cleaned surface to air. The method and apparatus of the present invention eliminates the exposure of the cleaned substrate to air between the oxide removal and metal deposition steps. This in-situ cleaning of the silicon substrate prior to cobalt deposition provides a cleaner silicon substrate surface, resulting in enhanced formation of cobalt silicide when the cobalt layer is annealed.

Abstract: A method of manufacturing thin film field effect transistors is described. The channel region of the transistors is formed by depositing an amorphous semiconductor film in a first sputtering apparatus followed by thermal treatment for converting the amorphous phase to a polycrystalline phase. The gate insulating film is formed by depositing an oxide film in a second sputtering apparatus connected to the first apparatus through a gate valve. The sputtering for the deposition of the amorphous semiconductor film is carried out in an atmosphere comprising hydrogen in order to introduce hydrogen into the amorphous semiconductor film. On the other hand the gate insulating oxide film is deposited by sputtering in an atmosphere comprising oxygen.

Abstract: A method and apparatus for controlling a multiple chamber semiconductor wafer processing system. The processing system includes a plurality of process chambers about the periphery of the transfer chamber. A centrally located wafer transfer mechanism effects moving wafers between the process chambers. The process sequencer control is a real time, multi-tasking control program having a presequencer or look ahead feature for preventing delays in the processing. In one implementation, the look ahead feature identifies mid-sequence or oriented wafers which cannot be further processed because their destination chamber is busy. Rather than expend system resources waiting for the destination chamber to become available, the wafers are transferred to a holding position, preferably the load lock, and rescheduled at the earliest time to finish their processing.

Abstract: A method for preventing corrosion in a load-lock chamber used in a cluster-type wafer processing system by utilizing an additional degas chamber and by the execution of an additional degas operation is provided. In the method, a degas chamber which is equipped with a purge gas inlet and a purge gas outlet directed at a wafer surface positioned in the degas chamber is used. The wafer is degassed by a purge gas of N.sub.2, O.sub.2 or any other suitable gas prior to being transferred back to a load-lock chamber. A suitable purge gas flow rate between about 100 sccm and about 5,000 sccm is used to effectively purge away undesirable, residual process gas from the surface of a wafer. In an alternate embodiment, the purge gas of N.sub.2 or O.sub.2 may be preheated to at least 30.degree. C. to improve the efficiency of purging. In another alternate embodiment, the wafer itself may be heated in the degas chamber to a temperature of between about 100.degree. C. and about 250.degree. C.

Abstract: Disclosed is a fabricating system including a plurality of processing apparatuses connected to each other by means of an inter-apparatus transporter, wherein one group of semiconductor wafers are processed in processing apparatuses and other group of wafers are transported to specified processing apparatuses for a time interval from (To+T) to a time To; and another group of wafers are processed and the remaining group of wafers are transported for a time interval from (To+T) to (To+2T). Since processing apparatuses can receive at least one of works from the inter-apparatus transporter for a time interval T min, the distribution of works from the transporter to processing apparatuses is completed for the time interval T min. The transporter is emptied for each time interval T min, and works are unloaded to the emptied transporter, which makes easy the scheduling, control and management of the transporting of a plurality of works in the fabricating system.

Abstract: An integrated circuit transistor is provided having a gate oxide and a gate conductor arranged upon a semiconductor topography, the gate oxide and gate conductor are formed within a common chamber. The initial semiconductor topography includes a silicon substrate having isolation regions disposed within its upper surface. The semiconductor topography may include an defined region, or well, doped opposite the substrate. The semiconductor topography is first placed in the common chamber. A separate chamber is operably placed gaseous communication with the common chamber. A plasma is created within the separate chamber, causing nitrogen, silicon, and oxygen containing compounds therein to form ions, molecular fragments, and excited molecules which are transported to the common chamber. The ions, molecular fragments, and excited molecules react and bombard the surface of the semiconductor topography to form an oxide layer thereon. The oxide layer is incorporated with nitrogen atoms which act as barrier atoms.

Abstract: A continuous assembly apparatus comprising means for transporting a lead frame, for adhering a semiconductor chip to a supporting member of the lead frame, for connecting chip electrodes via bonding wires to inner leads of the lead frame, for forming a protective coating on the chip, wire and lead frame, and for separating the inner leads from the supporting member.

Abstract: Submicron contact holes in semiconductor bodies are metalized in a single operation. A titanium-rich layer is first deposited, which is followed by a low-resistance TiSi.sub.2 layer. The two layers are thus deposited in one contiguous CVD process inside a single CVD chamber.

Abstract: Wafers from plural non-vacuum multiple wafer carriers are loaded and unloaded in an atmospheric front end of a wafer processing machine and transferred to and from a high vacuum chamber of a transfer module of a wafer processing cluster tool, or back end, through a single two-wafer loadlock. Preferably, with the wafers oriented horizontally throughout, two wafers are sequentially loaded into and simultaneously moved inbound to the high vacuum back end of the system, through one loadlock and sequentially moved into and simultaneously moved outbound through the same loadlock, the loadlock having a pair of water cooled supports for simultaneously actively cooling the two wafers. In both the atmospheric front end and vacuum back end environments, transfer arms load and unload the loadlock, and transfer wafers within the environments when all loadlocks are sealed. Preferably, two wafers are actively cooled in the loadlock.

Abstract: An apparatus for low pressure chemical vapor deposition for fabricating a semiconductor device comprises a group of reaction chambers, a group of high-vacuum pumps connected to the reaction chambers, a group of gate valves connected to the high-vacuum pumps, and a low-vacuum pump connected to the gate valves. There are fewer gate valves than high-vacuum pumps. A method for fabricating a semiconductor device using the above apparatus includes the sequence and duration of opening gate valves, injecting reaction gases, and pumping with the low vacuum pump. According to the present invention, since the number of pumps is reduced, the cost for installation, operation and maintenance of the semiconductor device fabrication apparatus is reduced.

Abstract: A semiconductor processing system having a holding chamber coupled to a mainframe processing system and at least one loadlock chamber coupled to the holding chamber in which unprocessed wafers are transferred from the loadlock chamber to the holding chamber for subsequent processing by the mainframe system.