Abstract: A gas curtain for use with a semiconductor processing system to prevent unwanted gases from entering a processing chamber. The gas curtain includes both upward and downward flows of gas surrounding an isolation valve adjacent a delivery port into the processing chamber. In the valve open position, the downward flows extends between the valve and the delivery port, and the upward flow extends in an opposite direction behind the isolation valve. In the valve closed position, one of the flows extends through a slot in the isolation valve, while the other flow is directed in an opposite direction on the rear side of the isolation valve. In a method of using the gas curtain apparatus, a pick-up wand operating on a Bernoulli principal uses gases which are unwanted in the processing chamber, and just prior to loading wafers into the processing chamber, the gas flow in the Bernoulli wand is switched from a first gas to a second gas. Desirably, the second gas is hydrogen.

Abstract: Two or more processes selected from heat treatment for anihilation of oxygen donors, formation of a gettering region, and formation of a dopant-volatilization-prevention film are simultaneously performed in a common apparatus in accordance with the specifications of silicon wafers to be manufactured. Therefore, productivity can be improved.

Abstract: A method of forming a tapered via includes steps of forming a via, coating the walls and bottom of the via with a reflow material, removing the reflow material from the bottom the via and causing the reflow material to become non-solid. Surface tension and other liquid forces cause the reflow material to form a tapered shape (i.e., be thicker at the bottom than the top). Therefore, with the invention, there is more control over the reflow process.

Abstract: A method of manufacturing a semiconductor device, comprises the steps of: forming an amorphous silicon film on a substrate having an insulating surface; processing said amorphous silicon film by plasma of a gas that mainly contains hydrogen or helium; and giving an energy to said amorphous silicon film.

Abstract: Methods of depositing films on semiconductor wafers include the steps of loading a deposition apparatus with a first plurality of semiconductor wafers from a first run cassette and then depositing a first material such as undoped silica glass (USG) or borophosphosilicate glass (BSPG), for example, thereon. After a first film has been completely deposited on each of the loaded wafers, a first wafer in the first plurality is removed from the apparatus and another wafer from the first run cassette is loaded into the apparatus. A second film of the first material is then deposited on the remaining first plurality of wafers and the added wafer. Following this deposition step, a second wafer from the first plurality is removed from the apparatus and another wafer (e.g., seventh wafer) from the first run cassette is loaded into the apparatus.

Abstract: Wafers from plural non-vacuum multiple wafer carriers are loaded and unloaded in an atmospheric front end of a wafer processing machine and transferred to and from the high vacuum chamber of a transfer module of a wafer manufacturing cluster tool through a plurality of single wafer loadlocks. Preferably, with the wafers oriented horizontally throughout, wafers are moved inbound to the high vacuum atmosphere through one loadlock and moved outbound through another loadlock, the outbound loadlock also actively cooling the wafer. In both the atmospheric and vacuum environments, transfer arms load and unload the loadlocks as often as possible when the other loadlock or loadlocks are sealed, and transfer wafers within the environments when all loadlocks are sealed. Preferably, the wafers are actively cooled in the outbound loadlock. Preferably also, wafers are passed through a wafer aligner after being removed from a carrier and before placed in a loadlock.

Abstract: Described is an improved polysilicon/tungsten silicide (WSi.sub.x) composite layer formed over an integrated circuit structure on a semiconductor wafer and characterized by improved step coverage and non tungsten-rich tungsten:silicon ratio of the WSi.sub.x layer, and a method of forming same. A doped layer of polysilicon is formed in a first deposition chamber over an integrated circuit structure previously formed on a semiconductor substrate and a capping layer of undoped polysilicon is then deposited in the first deposition chamber over the doped polysilicon layer. The substrate is then transferred from the first deposition chamber into a second deposition chamber without exposing the surface of the polysilicon layer to an oxidizing media.

Abstract: Apparatus and concomitant method for performing priority based scheduling of wafer processing within a multiple chamber semiconductor wafer processing system (cluster tool). The sequencer assigns priority values to the chambers in a cluster tool, then moves wafers from chamber to chamber in accordance with the assigned priorities. The sequencer is capable of determining the amount of time available before a priority move is to be performed and, if time is sufficient, the sequencer performs a non-priority move while waiting. The sequencer also dynamically varies assigned priorities depending upon the availability of chambers in the tool. Lastly, the sequencer prioritizes the chambers based upon the minimum time required for the robot to move the wafers in a particular stage.

Abstract: An integrated circuit transistor is provided having a gate oxide and a gate conductor arranged upon a semiconductor topography, the gate oxide and gate conductor are formed within a common chamber. The initial semiconductor topography includes a silicon substrate having isolation regions disposed within its upper surface. The semiconductor topography may include an defined region, or well, doped opposite the substrate. The semiconductor topography is first placed in the common chamber. A separate chamber is operably placed in gaseous communication with the common chamber. A plasma is created within the separate chamber, causing nitrogen, silicon, and oxygen containing compounds therein to form ions, molecular fragments, and excited molecules which are transported to the common chamber. The ions, molecular fragments, and excited molecules react and bombard the surface of the semiconductor topography to form an oxide layer thereon. The oxide layer is incorporated with nitrogen atoms which act as barrier atoms.

Abstract: A process chamber for semiconductor wafers is formed of multiple compartments. A first compartment is provided for supplying an isolated environment for processing the wafers, and a second compartment is provided, in selective communication with the first compartment, to load and unload wafers from the chamber. The wafer handling equipment is located in the second compartment to isolate it from the process environment, and thus form a clean, non-contaminating, environment for the wafer handling equipment. When the chamber must be cleaned, only the first compartment must be cleaned, as no processing occurs in the second chamber. Therefore, the entire first chamber may be removed for cleaning, and replaced with a clean first compartment to decrease chamber turnaround time during chamber cleaning operations.

Abstract: A batch process for the high-pressure forming of metal plugs in the dielectric layers of semiconductor wafers. After holes are etched in the dielectric layer of each wafer, and a layer of a metal such as aluminum deposited over the dielectric, both the etching and the deposition being done in vacuum chamber cluster machines, the wafers are removed from the cluster machines and placed together in a high pressure chamber where they are subjected to high isostatic pressure that forces the metal into the holes.

Abstract: Disclosed is a fabricating system including a plurality of processing apparatuses connected to each other by means of an inter-apparatus transporter, wherein one group of semiconductor wafers are processed in processing apparatuses and other group of wafers are transported to specified processing apparatuses for a time interval from (To+T) to a time To; and another group of wafers are processed and the remaining group of wafers are transported for a time interval from (To+T) to (To+2T). Since processing apparatuses can receive at least one of works from the inter-apparatus transporter for a time interval T min, the distribution of works from the transporter to processing apparatuses is completed for the time interval T min. The transporter is emptied for each time interval T min, and works are unloaded to the emptied transporter, which makes easy the scheduling, control and management of the transporting of a plurality of works in the fabricating system.

Abstract: The substrate unloaded from the exposure device is received at the interface unit, and then carried by the substrate carrying means to the heat treatment unit, where a heat treatment is carried out on the substrate. After that, the substrate is carried from the heat treatment unit to the cooling unit, where the substrate is cooled. After the completion of the cooling process, the substrate is carried by the carrying means from the cooling unit to the development unit, where the resist film on the substrate is developed. In this resist process, the required time for the process at the heat treatment unit is changed in accordance with the required time for the process at the exposure unit. The required time for the process at the heat treatment unit is equalized with the required time for the process at the exposure device. The required time for the process at the heat treatment process is changed by prolonging or shortening the pre-process at the heat treatment unit.

Abstract: An electroless deposition apparatus and a method of electroless deposition that uses a single process chamber for performing multiple processes by moving through the process chamber a variety of fluids one at a time in a sequential order.

Abstract: A process for manufacturing microelectronic components that can be fabricated in a facility 1 including integrated circuits on silicon wafers, flat panel displays on glass substrates or any other microelectronic components fabricated in a similar fashion, a process of constructing the facility, and the facility. The fabrication facility 1 relies on a central hub 3 from which processing areas 2 extend out radially like spokes. The processing areas 2 are arranged in a pattern so as to be served by common services which include gases, chemicals, ultra pure water, vapor exhaust, liquid waste, air conditioning, centralized vacuum, centralized clean compressed air, hot water, steam, natural gas, power including emergency, conditioned, and unconditioned power, and process cooling water.

Abstract: The present invention relates to a method of a sequencial WSi/.alpha.-Si sputtering process, more particularly to a method of in-situ wafer cooling for a sequencial WSi/.alpha.-Si sputtering process. A sputtering process of WSi and a sputtering process of .alpha.-Si are finished in a multi-chamber sputtering apparatus according to the invention; meanwhile, a wafer is cooled down by bolwing of inert gas before a process of sputtering .alpha.-Si starts. Thus, compared to traditional art of finishing WSi/.alpha.-Si sputtering in two apparatus, partial time of vacuuming and venting required in a sputtering process is saved according to the invention, thereby, shortening the production cycle time, reducing the possibility of wafer contamination, and suppressing the fabricating cost.