Schottky Barrier Junction Patents (Class 438/92)
  • Patent number: 10217821
    Abstract: A power integrated device includes a channel region, a source region, a drift region, and a drain region. A stacked gate includes a gate insulation layer and a gate electrode. The stacked gate having a plurality of stacked gate extension portions that extend from the stacked gate to over the plurality of deep trench field insulation layers. A plurality of deep trench field insulation layers is disposed in the drift region. The deep trench field insulation layers are spaced apart from each other in a channel width direction. A height of the deep trench field insulation layers is greater than a width of the deep trench field insulation layer.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: February 26, 2019
    Assignee: SK HYNIX SYSTEM IC INC.
    Inventors: Joo Won Park, Sang Hyun Lee
  • Patent number: 9520327
    Abstract: Methods for forming electrical contacts are provided. First and second FETs are formed over a semiconductor substrate. Openings are etched in a dielectric layer formed over the substrate, where the openings extend to source and drain regions of the FETs. A hard mask is formed over the source and drain regions of FETs. A first portion of the hard mask is removed, where the first portion is formed over the source and drain regions of the first FET. First silicide layers are formed over the source and drain regions of the first FET. A second portion of the hard mask is removed, where the second portion is formed over the source and drain regions of the second FET. Second silicide layers are formed over the source and drain regions of the second FET. A metal layer is deposited within the openings to fill the openings.
    Type: Grant
    Filed: October 15, 2015
    Date of Patent: December 13, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chun-Wen Nieh, Hung-Chang Hsu, Wei-Jung Lin, Yan-Ming Tsai, Chen-Ming Lee, Mei-Yun Wang
  • Patent number: 9165838
    Abstract: Methods for forming electrical contacts are provided. First and second FETs are formed over a semiconductor substrate. Openings are etched in a dielectric layer formed over the substrate, where the openings extend to source and drain regions of the FETs. A hard mask is formed over the source and drain regions of FETs. A first portion of the hard mask is removed, where the first portion is formed over the source and drain regions of the first FET. First silicide layers are formed over the source and drain regions of the first FET. A second portion of the hard mask is removed, where the second portion is formed over the source and drain regions of the second FET. Second silicide layers are formed over the source and drain regions of the second FET. A metal layer is deposited within the openings to fill the openings.
    Type: Grant
    Filed: February 26, 2014
    Date of Patent: October 20, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chun-Wen Nieh, Hung-Chang Hsu, Wei-Jung Lin, Yan-Ming Tsai, Chen-Ming Lee, Mei-Yun Wang
  • Publication number: 20150084061
    Abstract: A photo-detecting device includes a first nitride layer, a low-current blocking layer disposed on the first nitride layer, a light absorption layer disposed on the low-current blocking layer, and a Schottky junction layer disposed on the light-absorption layer. The low-current blocking layer includes a multilayer structure.
    Type: Application
    Filed: September 25, 2014
    Publication date: March 26, 2015
    Inventors: Ki Yon PARK, Hwa Mok KIM, Kyu-Ho LEE, Sung Hyun LEE, Hyung Kyu KIM
  • Patent number: 8987124
    Abstract: A silicon carbide substrate having a main face is prepared. By applying thermal oxidation to the main face of the silicon carbide substrate at a first temperature, an oxide film is formed on the main face. After the oxide film is formed, heat treatment is applied to the silicon carbide substrate at a second temperature higher than the first temperature. An opening exposing a portion of the main face is formed at the oxide film. A Schottky electrode is formed on the main face exposed by the opening.
    Type: Grant
    Filed: October 11, 2012
    Date of Patent: March 24, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Tomihito Miyazaki, Toru Hiyoshi
  • Patent number: 8969995
    Abstract: High-efficiency Schottky diodes (HED) and rectifier systems having such semiconductor devices are provided, which Schottky diodes (HED) are composed of at least one Schottky diode combined with an additional semiconductor element, e.g., with magnetoresistors (TMBS) or with pn diodes (TJBS), and have trenches. Such high-efficiency Schottky diodes make it possible to construct rectifiers which are suitable for higher temperatures and can therefore be used in motor vehicle generators, without particular cooling measures such as heat sinks being required.
    Type: Grant
    Filed: October 11, 2005
    Date of Patent: March 3, 2015
    Assignee: Robert Bosch GmbH
    Inventors: Richard Spitz, Alfred Goerlach, Gert Wolf, Markus Mueller
  • Patent number: 8936964
    Abstract: The present invention provides a silicon carbide Schottky-barrier diode device and a method for manufacturing the same. The silicon carbide Schottky bather diode device includes a primary n? epitaxial layer, an n+ epitaxial region, and a Schottky metal layer. The primary n? epitaxial layer is deposited on an n+ substrate joined with an ohmic metal layer at an undersurface thereof. The n+ epitaxial region is formed by implanting n+ ions into a central region of the primary n? epitaxial layer. The Schottky metal layer is deposited on the n+ epitaxial layer.
    Type: Grant
    Filed: June 18, 2014
    Date of Patent: January 20, 2015
    Assignee: Hyundai Motor Company
    Inventors: Kyoung Kook Hong, Jong Seok Lee
  • Patent number: 8927328
    Abstract: A 3D semiconductor device and a method of manufacturing the same are provided. The method includes forming a first semiconductor layer including a common source node on a semiconductor substrate, forming a transistor region on the first semiconductor layer, wherein the transistor region includes a horizontal channel region substantially parallel to a surface of the semiconductor substrate, and source and drain regions branched from the horizontal channel region to a direction substantially perpendicular to the surface of the semiconductor substrate, processing the first semiconductor layer to locate the common source node corresponding to the source region, forming a gate in a space between the source region and the drain region, forming heating electrodes on the source region and the drain region, and forming resistance variable material layers on the exposed heating electrodes.
    Type: Grant
    Filed: October 18, 2013
    Date of Patent: January 6, 2015
    Assignee: SK Hynix Inc.
    Inventor: Suk Ki Kim
  • Patent number: 8853526
    Abstract: Photovoltaic devices are driven by intense photoemission of “hot” electrons from a suitable nanostructured metal. The metal should be an electron source with surface plasmon resonance within the visible and near-visible spectrum range (near IR to near UV (about 300 to 1000 nm)). Suitable metals include silver, gold, copper and alloys of silver, gold and copper with each other. Silver is particularly preferred for its advantageous opto-electronic properties in the near UV and visible spectrum range, relatively low cost, and simplicity of processing.
    Type: Grant
    Filed: July 17, 2008
    Date of Patent: October 7, 2014
    Assignee: The Regents of The University of California
    Inventors: Robert Kostecki, Samuel Mao
  • Patent number: 8816466
    Abstract: A protective element for electronics has at least one Schottky diode and at least one Zener diode which are located between a power supply and the electronics, the anode of the Schottky diode being connected to the power supply and the cathode of the Schottky diode being connected to the electronics, and the cathode and the anode of the Zener diode are connected to ground. The Schottky diode is a trench MOS barrier junction diode or trench MOS barrier Schottky (TMBS) diode or a trench junction barrier Schottky (TJBS) diode and includes an integrated semiconductor arrangement, which has at least one trench MOS barrier Schottky diode and a p-doped substrate, which is used as the anode of the Zener diode.
    Type: Grant
    Filed: September 21, 2010
    Date of Patent: August 26, 2014
    Assignee: Robert Bosch GmbH
    Inventors: Ning Qu, Alfred Goerlach
  • Patent number: 8809107
    Abstract: A method for making a Schottky barrier diode includes the following steps. A first metal layer, a second metal layer and a carbon nanotube composite material are provided. The carbon nanotube composite material is applied on the first metal layer and the second metal layer to form a semiconductor layer. The carbon nanotube composite material includes an insulated polymer and a number of carbon nanotubes dispersed in the insulated polymer. The semiconductor layer is in Schottky contact with the first metal layer and in ohmic contact with the second metal layer.
    Type: Grant
    Filed: December 26, 2011
    Date of Patent: August 19, 2014
    Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.
    Inventors: Chun-Hua Hu, Chang-Hong Liu, Shou-Shan Fan
  • Patent number: 8772836
    Abstract: To provide a semiconductor device in which a rectifying element capable of reducing a leak current in reverse bias when a high voltage is applied and reducing a forward voltage drop Vf and a transistor element are integrally formed on a single substrate. A semiconductor device has a transistor element and a rectifying element on a single substrate. The transistor element has an active layer formed on the substrate and three electrodes (source electrode, drain electrode, and gate electrode) disposed on the active layer. The rectifying element has an anode electrode disposed on the active layer, a cathode electrode which is the drain electrode, and a first auxiliary electrode between the anode electrode and cathode electrode.
    Type: Grant
    Filed: March 8, 2011
    Date of Patent: July 8, 2014
    Assignee: Sanken Electric Co., Ltd.
    Inventor: Osamu Machida
  • Patent number: 8766232
    Abstract: According to a method of fabricating the semiconductor memory device, a contact plug can be protected while mold openings are formed. A semiconductor memory device may include a mold dielectric layer on an entire surface of a substrate, the substrate including a first region and a second region. A contact plug may be provided in a contact hole formed through the mold dielectric layer in the first region. A variable resistor may be provided in a mold opening formed through the mold dielectric layer in the second region. An upper surface of the contact plug may be at a level equal to or lower than an upper surface of the mold dielectric layer.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: July 1, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sukhun Choi, Boun Yoon, Kevin Ahn, Doo-Sung Yun
  • Patent number: 8754397
    Abstract: The carbon nanotube-based electronic and photonic devices are disclosed. The devices are united by the same technology as well as similar elements for their fabrication. The devices consist of the vertically grown semiconductor nanotube having two Schottky barriers at the nanotube ends and one Schottky barrier at the middle of the nanotube. Depending on the Schottky barrier heights and bias arrangements, the disclosed devices can operate either as transistors, CNT MESFET and CNT Hot Electron Transistor, or as a CNT Photon Emitter.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: June 17, 2014
    Assignee: Nano-Electronic and Photonic Devices and Circuits, LLC
    Inventor: Alexander Kastalsky
  • Patent number: 8679954
    Abstract: A schottky diode includes a SiC substrate which has a first surface and a second surface facing away from the first surface, a semiconductor layer which is formed on the first surface of the SiC substrate, a schottky electrode which is in contact with the semiconductor layer, and an ohmic electrode which is in contact with the second surface of the SiC substrate. The first surface of the SiC substrate is a (000-1) C surface, upon which the semiconductor layer is formed.
    Type: Grant
    Filed: May 6, 2013
    Date of Patent: March 25, 2014
    Assignee: Rohm Co., Ltd.
    Inventors: Shingo Ohta, Tatsuya Kiriyama, Takashi Nakamura, Yuji Okamura
  • Publication number: 20140004653
    Abstract: Various embodiments relate to a functional low cost photovoltaic (PV) cell (e.g., solar cell) and a method for the large scale production of the device. The manufacturing method to produce a pseudo-Schottky photovoltaic (PSPV) cell, includes depositing a metal contact on a reverse side of the wafer; superposing a mask on an obverse side of the wafer; disposing a conductive paint to the obverse side of the wafer; removing the mask on the obverse side of the wafer; and attaching electrical conduction leads between the paint and the metal contact.
    Type: Application
    Filed: May 30, 2006
    Publication date: January 2, 2014
    Applicant: United States of America via Secr. of Navy
    Inventors: Blaise L. Corbett, William P. Adams, Kevin D. Collier
  • Patent number: 8551558
    Abstract: Photovoltaic devices and techniques for enhancing efficiency thereof are provided. In one aspect, a photovoltaic device is provided. The photovoltaic device comprises a photocell having a photoactive layer and a non-photoactive layer adjacent to the photoactive layer so as to form a heterojunction between the photoactive layer and the non-photoactive layer; and a plurality of high-aspect-ratio nanostructures on one or more surfaces of the photoactive layer. The plurality of high-aspect-ratio nanostructures are configured to act as a scattering media for incident light. The plurality of high-aspect-ratio nanostructures can also be configured to create an optical resonance effect in the incident light.
    Type: Grant
    Filed: February 29, 2008
    Date of Patent: October 8, 2013
    Assignee: International Business Machines Corporation
    Inventors: Supratik Guha, Oki Gunawan
  • Patent number: 8492254
    Abstract: A method of manufacturing a semiconductor device is disclosed. The method includes forming a first trench and a second trench in an n-type substrate surface, the first trenches being spaced apart from each other, the second trench surrounding the first trenches, the second trench being wider than the first trench. The method also includes forming a gate oxide film on the inner surfaces of the first and second trenches, and depositing an electrically conductive material to the thickness a half or more as large as the first trench width. The method further includes removing the electrically conductive material using the gate oxide film as a stopper layer, forming an insulator film thicker than the gate oxide film, and polishing the insulator film by CMP for exposing the n-type substrate and the electrically conductive material in the first trench.
    Type: Grant
    Filed: November 10, 2011
    Date of Patent: July 23, 2013
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Tomonori Mizushima
  • Patent number: 8492261
    Abstract: A method for manufacturing a III-V CMOS device is disclosed. The device includes a first and second main contact and a control contact. In one aspect, the method includes providing the control contact by using damascene processing. The method thus allows obtaining a control contact with a length of between about 20 nm and 5 ?m and with good Schottky behavior. Using low-resistive materials such as Cu allows reducing the gate resistance thus improving the high-frequency performance of the III-V CMOS device.
    Type: Grant
    Filed: January 19, 2010
    Date of Patent: July 23, 2013
    Assignee: IMEC
    Inventors: Marleen Van Hove, Joff Derluyn
  • Publication number: 20130133718
    Abstract: Photovoltaic (PV) devices employing layers of semiconducting carbon nanotubes as light absorption elements are disclosed. In one aspect a layer of p-type carbon nanotubes and a layer of n-type carbon nanotubes are used to form a p-n junction PV device. In another aspect a mixed layer of p-type and n-type carbon nanotubes are used to form a bulk hetero-junction PV device. In another aspect a metal such as a low work function metal electrode is formed adjacent to a layer of semiconducting nanotubes to form a Schottky barrier PV device. In another aspect various material deposition techniques well suited to working with nanotube layers are employed to realize a practical metal-insulator-semiconductor (MIS) PV device. In another aspect layers of metallic nanotubes are used to provide flexible electrode elements for PV devices. In another aspect layers of metallic nanotubes are used to provide transparent electrode elements for PV devices.
    Type: Application
    Filed: January 22, 2013
    Publication date: May 30, 2013
    Applicant: Nantero, Inc.
    Inventor: Nantero, Inc.
  • Patent number: 8450826
    Abstract: Disclosed herein is a nitride based semiconductor device. There is provided a nitride based semiconductor device including a base substrate; a semiconductor layer disposed on the base substrate; and an electrode structure disposed on the semiconductor layer, wherein the electrode structure includes: a first electrode ohmic-contacting the semiconductor layer; a ohmic contact unit ohmic-contacting the semiconductor layer and spaced apart from the first electrode; and a schottky contact unit schottky-contacting the semiconductor layer and covering the ohmic contact unit.
    Type: Grant
    Filed: March 16, 2011
    Date of Patent: May 28, 2013
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Younghwan Park, Kiyeol Park, Woochul Jeon
  • Patent number: 8445312
    Abstract: A method of manufacturing a crystalline silicon solar cell, subsequently including: providing a crystalline silicon substrate having a first side and a second side opposite the first side; pre-diffusing Phosphorus into a first side of the substrate to render a Phosphorus diffused layer having an initial depth; blocking the first side of the substrate; exposing a second side of the substrate to a Boron diffusion source; heating the substrate for a certain period of time and to a certain temperature so as to diffuse Boron into the second side of the substrate and to simultaneously diffuse the Phosphorus further into the substrate.
    Type: Grant
    Filed: November 13, 2008
    Date of Patent: May 21, 2013
    Assignee: Stichting Energieonderzoek Centrum Nederland
    Inventors: Valentin Dan Mihailetchi, Yuji Komatsu
  • Patent number: 8421181
    Abstract: A Schottky barrier diode comprises a first-type substrate, a second-type well isolation region on the first-type substrate, and a first-type well region on the second-type well isolation region. With embodiments herein a feature referred to as a perimeter capacitance well junction ring is on the second-type well isolation region. A second-type well region is on the second-type well isolation region. The perimeter capacitance well junction ring is positioned between and separates the first-type well region and the second-type well region. A second-type contact region is on the second-type well region, and a first-type contact region contacts the inner portion of the first-type well region. The inner portion of the first-type well region is positioned within the center of the first-type contact region. Additionally, a first ohmic metallic layer is on the first-type contact region and a second ohmic metallic layer is on the first-type well region.
    Type: Grant
    Filed: July 21, 2010
    Date of Patent: April 16, 2013
    Assignee: International Business Machines Corporation
    Inventors: Frederick G. Anderson, Jenifer E. Lary, Robert M. Rassel, Mark E. Stidham
  • Publication number: 20130082241
    Abstract: Ultraviolet or Extreme Ultraviolet and/or visible detector apparatus and fabrication processes are presented, in which the detector includes a thin graphene electrode structure disposed over a semiconductor surface to provide establish a potential in the semiconductor material surface and to collect photogenerated carriers, with a first contact providing a top side or bottom side connection for the semiconductor structure and a second contact for connection to the graphene layer.
    Type: Application
    Filed: September 28, 2012
    Publication date: April 4, 2013
    Inventors: Francis J. Kub, Travis Anderson, Karl D. Hobart
  • Patent number: 8390091
    Abstract: A monolithic semiconductor structure includes a stack of layers. The stack includes a substrate; a first layer made from a first semiconductor material; and a second layer made from a second semiconductor material. The first layer is situated between the substrate and the second layer and at least one of the first semiconductor material and the second semiconductor material contains a III-nitride material. The structure includes a power transistor, including a body formed in the stack of layers; a first power terminal at a side of the first layer facing the second layer; a second power terminal at least partly formed in the substrate; and a gate structure for controlling the propagation through the body of electric signals between the first power terminal and the second power terminal.
    Type: Grant
    Filed: February 3, 2009
    Date of Patent: March 5, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Philippe Renaud
  • Patent number: 8384179
    Abstract: A black silicon based metal-semiconductor-metal photodetector includes a silicon substrate and a black silicon layer formed on the silicon substrate. An interdigitated electrode pattern structure is formed on the black silicon layer, which can be a planar or U-shaped structure. A thin potential barrier layer is deposited at the interdigitated electrode pattern structure. An Al or transparent conductive ITO thin film is deposited on the thin potential barrier layer. A passivation layer is provided on the black silicon layer. In the black silicon based metal-semiconductor-metal photodetector, the black silicon layer, as a light-sensitive area, can respond to ultraviolet, visible and near infrared light.
    Type: Grant
    Filed: July 13, 2010
    Date of Patent: February 26, 2013
    Assignee: University of Electronic Science and Technology of China
    Inventors: Yadong Jiang, Jing Jiang, Anyuan Zhang, Zhengyu Guo, Guodong Zhao, Zhiming Wu, Wei Li
  • Publication number: 20130009143
    Abstract: A photo sensor and a method of fabricating the same are disclosed, the photo sensor of the present invention has ultra-high Schottky junction area per unit volume, and the photo sensor comprises: a first conductive layer; plural metallic nanowires, in which one end of each metallic nanowire connects with the first conductive layer and is covered with a semiconductive layer having a width of 1 nm to 20 nm; and a second conductive layer locating opposite to the first conductive layer, whereby the plural metallic nanowires locate between the first conductive layer and the second conductive layer, and the semiconductive layer contacts with the second conductive layer, wherein the photo sensor of the present invention is used to detect ultra violet (UV) light with a wavelength of 10 nm-400 nm.
    Type: Application
    Filed: October 5, 2011
    Publication date: January 10, 2013
    Inventors: Chih Chen, Chien-Min Liu, Yuan-Chieh Tseng
  • Patent number: 8350290
    Abstract: Provided is a light-receiving device which has light-receiving sensitivity superior to that of a conventional Schottky diode type light-receiving device and also has sufficiently-strengthened junction of a Schottky electrode. A first contact layer formed of AlGaN and having conductivity, a light-receiving layer formed of AlGaN, and a second contact layer formed of AlN and having a thickness of 5 nm are epitaxially formed on a predetermined substrate in the stated order, and a second electrode is brought into Schottky junction with the second contact layer, to thereby form MIS junction. Further, after the Schottky junction, heat treatment is performed under a nitrogen gas atmosphere at 600° C. for 30 seconds.
    Type: Grant
    Filed: August 19, 2009
    Date of Patent: January 8, 2013
    Assignee: NGK Insulators, Ltd.
    Inventors: Makoto Miyoshi, Mitsuhiro Tanaka
  • Patent number: 8338219
    Abstract: A detector array for an imaging system may exploit the different sensitivities of array pixels to an incident flux of low energy photons with a wavelength falling near the high end of the range of sensitivity of the semiconductor. The detector array may provide the de-multiplexable spatial information. The detector array may include a two-terminal multi-pixel array of Schottky photodiodes electrically connected in parallel.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: December 25, 2012
    Assignee: STMicroelectronics S.R.L.
    Inventor: Massimo Cataldo Mazzillo
  • Publication number: 20120306042
    Abstract: A UV detector is designed to provide a photoresponse with a cutoff wavelength below a predetermined wavelength. The detector uses a sensor element having an active layer comprising a MgS component grown directly on a substrate. A thin layer metal layer is deposited over the active layer and forms a transparent Schottky metal layer.
    Type: Application
    Filed: June 5, 2012
    Publication date: December 6, 2012
    Applicant: THE HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Iam Keong SOU, Ying Hoi LAI, Shu Kin LOK, Wai Yip CHEUNG, George Ke Lun WONG, Kam Weng TAM, Sut Kam HO
  • Patent number: 8319308
    Abstract: The present invention provides a semiconductor device including: a base substrate; a first semiconductor layer disposed on the base substrate; first ohmic electrodes disposed on a central region of the first semiconductor layer; a second ohmic electrode having a ring shape surrounding the first ohmic electrodes, on edge regions of the first semiconductor layer; a second semiconductor layer interposed between the first ohmic electrodes and the first semiconductor layer; and a Schottky electrode part which covers the first ohmic electrodes on the central regions, and is spaced apart from the second ohmic electrode.
    Type: Grant
    Filed: January 7, 2010
    Date of Patent: November 27, 2012
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Woo Chul Jeon, Jung Hee Lee, Young Hwan Park, Ki Yeol Park
  • Publication number: 20120285517
    Abstract: A Schottky Barrier solar cell having at least one of a low work function region and a high work function region provided on the front or back surface of a lightly-doped absorber material, which may be produced in a variety of different geometries. The method of producing the Schottky Barrier solar cells allows for short processing times and the use of low temperatures.
    Type: Application
    Filed: May 9, 2011
    Publication date: November 15, 2012
    Applicant: International Business Machines Corporation
    Inventors: Joel P. de Souza, Harold John Hovel, Daniel Inns, Jeehwan Kim, Christian Lavoie, Conal Eugene Murray, Devendra K. Sadana, Katherine L. Saenger, Ghavam Shahidi, Davood Shahrjerdi, Zhen Zhang
  • Patent number: 8212281
    Abstract: A variable-resistance material memory (VRMM) device includes a container conductor disposed over an epitaxial semiconductive prominence that is coupled to a VRMM. A VRMM device may also include a conductive plug in a recess that is coupled to a VRMM. A VRMM array may also include a conductive plug in a surrounding recess that is coupled to a VRMM. Apparatuses include the VRMM with one of the diode constructions.
    Type: Grant
    Filed: January 16, 2008
    Date of Patent: July 3, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Jun Liu, Michael P. Violette
  • Patent number: 8168466
    Abstract: In one embodiment, a Schottky diode is formed on a semiconductor substrate with other semiconductor devices and is also formed with a high breakdown voltage and a low forward resistance.
    Type: Grant
    Filed: June 1, 2007
    Date of Patent: May 1, 2012
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Mohammed Tanvir Quddus, Shanghui L. Tu, Antonin Rozsypal, Zia Hossain
  • Patent number: 8154127
    Abstract: An optical device includes a first electrode of a first conductivity type, and a second electrode of a second conductivity type. A nanowire is positioned between the first and second electrodes. The nanowire has at least two segments and a junction region formed between the at least two segments. One of the segments is the first conductivity type and the other of the segments is the second conductivity type. At least one of the at least two segments has a predetermined characteristic that affects optical behavior of the junction region.
    Type: Grant
    Filed: July 30, 2007
    Date of Patent: April 10, 2012
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Theodore I. Kamins, Alexandre M. Bratkovski, Shashank Sharma
  • Publication number: 20120031477
    Abstract: A Schottky-barrier-reducing layer is provided between a p-doped semiconductor layer and a transparent conductive material layer of a photovoltaic device. The Schottky-barrier-reducing layer can be a conductive material layer having a work function that is greater than the work function of the transparent conductive material layer. The conductive material layer can be a carbon-material layer such as a carbon nanotube layer or a graphene layer. Alternately, the conductive material layer can be another transparent conductive material layer having a greater work function than the transparent conductive material layer. The reduction of the Schottky barrier reduces the contact resistance across the transparent material layer and the p-doped semiconductor layer, thereby reducing the series resistance and increasing the efficiency of the photovoltaic device.
    Type: Application
    Filed: August 4, 2010
    Publication date: February 9, 2012
    Applicants: EGYPT NANOTECHNOLOGY CENTER, INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Keith E. Fogel, Jee H. Kim, Devendra K. Sadana, George S. Tulevski, Ahmed Abou-Kandil, Hisham S. Mohamed, Mohamed Saad, Osama Tobail
  • Publication number: 20120012967
    Abstract: A black silicon based metal-semiconductor-metal photodetector includes a silicon substrate and a black silicon layer formed on the silicon substrate. An interdigitated electrode pattern structure is formed on the black silicon layer, which can be a planar or U-shaped structure. A thin potential barrier layer is deposited at the interdigitated electrode pattern structure. An Al or transparent conductive ITO thin film is deposited on the thin potential barrier layer. A passivation layer is provided on the black silicon layer. In the black silicon based metal-semiconductor-metal photodetector, the black silicon layer, as a light-sensitive area, can respond to ultraviolet, visible and near infrared light.
    Type: Application
    Filed: July 13, 2010
    Publication date: January 19, 2012
    Inventors: Yadong Jiang, Guodong Zhao, Zhiming Wu, Wei Li, Jing Jiang, Anyuan Zhang, Zhengyu Guo
  • Patent number: 8093094
    Abstract: A process for applying blocking contacts on an n-type CdZnTe specimen includes cleaning the CdZnTe specimen; etching the CdZnTe specimen; chemically surface treating the CdZnTe specimen; and depositing blocking metal on at least one of a cathode surface and an anode surface of the CdZnTe specimen.
    Type: Grant
    Filed: June 12, 2008
    Date of Patent: January 10, 2012
    Assignee: The United States of America as represented by the Administrator of the National Aeronautics and Space Administration
    Inventors: Carl M. Stahle, Bradford H. Parker, Sachidananda R. Babu
  • Publication number: 20110315201
    Abstract: Embodiments of the present invention provide methods to fabricate semiconductor nanostructure/polymer heterojunctions of solar cells. The methods comprise that a conductive polymer is adhered on the surface of semiconductor nanostructures by capillary effect and core-sheath shaped heterojunctions are formed. The incident photo-to-current conversion efficiency (IPCE) of the solar cells having core-sheath heterojunctions can reach 30% or more.
    Type: Application
    Filed: December 22, 2010
    Publication date: December 29, 2011
    Applicant: NATIONAL TAIWAN UNIVERSITY
    Inventors: CHING-FUH LIN, SHU-JIA SYU
  • Publication number: 20110215434
    Abstract: Provided are a thin-film photoelectric conversion device of which thickness can be reduced to several tens nanometers (nm) or below, and a method of manufacturing the thin-film photoelectric conversion device. The thin-film photoelectric conversion device includes a metal silicide layer formed on a surface of a silicon substrate by diffusion of a first metal and silicon, a conductive thin-film layer formed on the surface of the silicon substrate in a region where the second metal thin-film layer is laminated, and a silicon diffused portion formed between the metal silicide layer and the conductive thin-film layer near the surface of the silicon substrate by diffusion of silicon nano-particles.
    Type: Application
    Filed: September 14, 2008
    Publication date: September 8, 2011
    Applicant: SI-NANO INC.
    Inventor: Jose Briceno
  • Patent number: 8008114
    Abstract: A phase change memory device comprises a photolithographically formed phase change memory cell having first and second electrodes and a phase change element positioned between and electrically coupling the opposed contact elements of the electrodes to one another. The phase change element has a width, a length and a thickness. The length, the thickness and the width are less than a minimum photolithographic feature size of the process used to form the phase change memory cell. The size of the photoresist masks used in forming the memory cell may be reduced so that the length and the width of the phase change element are each less than the minimum photolithographic feature size.
    Type: Grant
    Filed: July 26, 2010
    Date of Patent: August 30, 2011
    Assignee: Macronix International Co., Ltd.
    Inventors: Hsiang-Lan Lung, Shih-Hung Chen
  • Publication number: 20110203632
    Abstract: Photovoltaic (PV) devices employing layers of semiconducting carbon nanotubes as light absorption elements are disclosed. In one aspect a layer of p-type carbon nanotubes and a layer of n-type carbon nanotubes are used to form a p-n junction PV device. In another aspect a mixed layer of p-type and n-type carbon nanotubes are used to form a bulk hetero-junction PV device. In another aspect a metal such as a low work function metal electrode is formed adjacent to a layer of semiconducting nanotubes to form a Schottky barrier PV device. In another aspect various material deposition techniques well suited to working with nanotube layers are employed to realize a practical metal-insulator-semiconductor (MIS) PV device. In another aspect layers of metallic nanotubes are used to provide flexible electrode elements for PV devices. In another aspect layers of metallic nanotubes are used to provide transparent electrode elements for PV devices.
    Type: Application
    Filed: February 22, 2010
    Publication date: August 25, 2011
    Inventors: RAHUL SEN, SUCHIT SHAH, HAO-YU LIN, THOMAS RUECKES
  • Patent number: 7985615
    Abstract: The present invention relates to embodiments of TPV cell structures based on carbon nanotube and nanowire materials. One embodiment according to the present invention is a p-n junction carbon nanotube/nanowire TPV cell, which is formed by p-n junction wires. A second embodiment according to the present invention is a carbon nanotube/nanowire used as a p-type (or n-type), and using bulk material as the other complementary type to a form p-n junction TPV cell. A third embodiment according to the present invention uses a controllable Schottky barrier height between a one-dimensional nanowire and a metal contact to form the built-in potential of the TPV cells.
    Type: Grant
    Filed: November 20, 2006
    Date of Patent: July 26, 2011
    Assignee: The Regents of the University of California
    Inventors: Fei Liu, Ma Siguang, Kang L. Wang
  • Patent number: 7964431
    Abstract: A photovoltaic cell is formed by bonding a donor body to a receiver element and cleaving a thin lamina from the donor body. Electrical contact is made to the bonded surface of the lamina through vias formed in the lamina. In some embodiments the emitter exists only at the bonded surface or only at the cleaved surface face; the emitter does not wrap through the vias between the surfaces. Wiring contacting each of the two surfaces is formed only at the cleaved face, and one set of wiring contacts the bonded surface through conductive material formed in the vias, insulated from the via sidewalls.
    Type: Grant
    Filed: March 19, 2009
    Date of Patent: June 21, 2011
    Assignee: Twin Creeks Technologies, Inc.
    Inventors: Christopher J Petti, Mohamed M Hilali
  • Publication number: 20110143494
    Abstract: A method for forming a Schottky barrier diode on a SiGe BiCMOS wafer, including forming a structure which provides a cutoff frequency (Fc) above about 1.0 THz. In embodiments, the structure which provides a cutoff frequency (Fc) above about 1.0 THz may include an anode having an anode area which provides a cutoff frequency (FC) above about 1.0 THz, an n-epitaxial layer having a thickness which provides a cutoff frequency (FC) above about 1.0 THz, a p-type guardring at an energy and dosage which provides a cutoff frequency (FC) above about 1.0 THz, the p-type guardring having a dimension which provides a cutoff frequency (FC) above about 1.0 THz, and a well tailor with an n-type dopant which provides a cutoff frequency (FC) above about 1.0 THz.
    Type: Application
    Filed: February 16, 2011
    Publication date: June 16, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jeffrey B. JOHNSON, Xuefeng LIU, Bradley A. ORNER, Robert M. RASSEL
  • Publication number: 20110101485
    Abstract: An apparatus comprises a substrate having a type of conductivity, an intrinsic region above the substrate, and a metal layer on a portion of the surface of the intrinsic region. The intrinsic region has a surface. The metal layer may have a thickness that is configured to allow a plurality of photons to pass through the metal layer into the intrinsic region and form a rectifying contact with the intrinsic region.
    Type: Application
    Filed: November 5, 2009
    Publication date: May 5, 2011
    Applicant: The Boeing Company
    Inventor: Eric Yuen-Jun Chan
  • Patent number: 7923273
    Abstract: An optoelectronics chip-to-chip interconnects system is provided, including at least one packaged chip to be connected on the printed-circuit-board with at least one other packaged chip, optical-electrical (O-E) conversion mean, waveguide-board, and (PCB). Single to multiple chips interconnects can be interconnected provided using the technique disclosed in this invention. The packaged chip includes semiconductor die and its package based on the ball-grid array or chip-scale-package. The O-E board includes the optoelectronics components and multiple electrical contacts on both sides of the O-E substrate. The waveguide board includes the electrical conductor transferring the signal from O-E board to PCB and the flex optical waveguide easily stackable onto the PCB to guide optical signal from one chip-to-other chip. Alternatively, the electrode can be directly connected to the PCB instead of including in the waveguide board. The chip-to-chip interconnections system is pin-free and compatible with the PCB.
    Type: Grant
    Filed: July 31, 2007
    Date of Patent: April 12, 2011
    Assignee: Banpil Photonics, Inc.
    Inventor: Achyut Kumar Dutta
  • Patent number: 7915703
    Abstract: Fabrication of a Schottky diodes may include providing a Schottky contact layer containing a low barrier metal layer with spaced apart high barrier metal islands therein on a first surface of a substrate. A diode contact is formed on a second surface of the substrate that is opposite to the first surface. Formation of the Schottky contact layer may include providing a liquid mixture of a high barrier metal and a low barrier metal on the first surface of the substrate. Temperature and/or relative concentrations of the high and low barrier metals in the liquid mixture may be controlled to cause regions of the high barrier metal to solidify within the liquid mixture and agglomerate to form the spaced apart high barrier metal islands while inhibiting solidification of the low barrier metal. The temperature and relative concentrations may then be controlled to cause the low barrier metal to solidify and form the low barrier metal layer containing the high barrier metal islands.
    Type: Grant
    Filed: May 13, 2009
    Date of Patent: March 29, 2011
    Assignee: Cree, Inc.
    Inventors: Jason Patrick Henning, Allan Ward
  • Patent number: 7863172
    Abstract: A gallium nitride based semiconductor Schottky diode fabricated from a n+ doped GaN layer having a thickness between one and six microns disposed on a sapphire substrate; an n? doped GaN layer having a thickness greater than one micron disposed on said n+ GaN layer patterned into a plurality of elongated fingers and a metal layer disposed on the n? doped GaN layer and forming a Schottky junction therewith. The layer thicknesses and the length and width of the elongated fingers are optimized to achieve a device with breakdown voltage of greater than 500 volts, current capacity in excess of one ampere, and a forward voltage of less than three volts.
    Type: Grant
    Filed: October 10, 2008
    Date of Patent: January 4, 2011
    Assignee: Power Integrations, Inc.
    Inventors: TingGang Zhu, Bryan S. Shelton, Marek K. Pabisz, Mark Gottfried, Linlin Liu, Milan Pophristic, Michael Murphy, Richard A. Stall
  • Patent number: 7820473
    Abstract: A Schottky diode capable of sustaining a voltage of greater than about 250 volts and a method for its manufacture. An epitaxial layer of N-type conductivity is disposed on a semiconductor substrate of N-type conductivity. A guard ring of P-type conductivity extends into the epitaxial layer from its surface. A stacked structure is formed on a portion of the guard ring and a portion of the epitaxial layer. The stacked structure includes a layer of semi-insulating semiconductor material disposed on a layer of dielectric material. A first metal layer is formed on the portion of the epitaxial layer adjacent a first side of the stacked structure and on a first portion of the stacked structure. A second metal layer is formed on the portion of the epitaxial layer adjacent a second side of the stacked structure and on a second portion of the stacked structure.
    Type: Grant
    Filed: March 21, 2005
    Date of Patent: October 26, 2010
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Linghui Chen, Blanca Estela Kruse, Mark Duskin, John D. Moran