Abstract: A semiconductor structure and a method for forming the same. The structure includes (a) a substrate which includes semiconductor devices and (b) a first ILD (inter-level dielectric) layer on top of the substrate. The structure further includes N first actual metal lines in the first ILD layer, N being a positive integer. The N first actual metal lines are electrically connected to the semiconductor devices. The structure further includes first trenches in the first ILD layer. The first trenches are not completely filled with solid materials. If the first trenches are completely filled with first dummy metal lines, then (i) the first dummy metal lines are not electrically connected to any semiconductor device and (ii) the N first actual metal lines and the first dummy metal lines provide an essentially uniform pattern density of metal lines across the first ILD layer.

Abstract: The present invention provides a high-k gate dielectric/metal gate MOSFET that has a reduced parasitic capacitance. The inventive structure includes at least one metal oxide semiconductor field effect transistor (MOSFET) 100 located on a surface of a semiconductor substrate 12. The least one MOSFET 100 includes a gate stack including, from bottom to top, a high-k gate dielectric 28 and a metal-containing gate conductor 30. The metal-containing gate conductor 30 has gate corners 31 located at a base segment of the metal-containing gate conductor. Moreover, the metal-containing gate conductor 30 has vertically sidewalls 102A and 102B devoid of the high-k gate dielectric 28 except at the gate corners 31. A gate dielectric 18 laterally abuts the high-k gate dielectric 28 present at the gate corners 31 and a gate spacer 36 laterally abuts the metal-containing gate conductor 30.

Abstract: A method for manufacturing a semiconductor device has forming a first insulating film on a semiconductor substrate, forming an electrode layer on said first insulating film, etching said electrode layer, said first insulating film and said semiconductor substrate of a first predetermined region to form a trench, burying an element-isolating insulating film in said trench, forming a second insulating film on said element-isolating insulating film and above said electrode layer, etching said second insulating film, said electrode layer and said element-isolating insulating film of a second predetermined region to form a gate pattern and a dummy pattern, forming a third insulating film for covering said gate pattern and said dummy pattern, and planarizing said third insulating film using said second insulating film as a stopper.

Abstract: A semiconductor device capable of improving the efficiency of dispersing heat via a dummy pad. The semiconductor device may be included in a semiconductor package, stack module, card, or system. Also disclosed is a method of manufacturing the semiconductor device. In the semiconductor device, a semiconductor substrate has a first surface and a second surface opposite to the first surface, and at least one conductive pad is arranged on a predetermined region of the first surface. At least one dummy pad is arranged on the first or second surface, and is not electrically coupled to the at least one conductive pad. The dummy pad or pads may be used to disperse heat. Accordingly, it is possible to increase the efficiency of dispersing heat of a semiconductor device, thereby improving the yield of semiconductor devices.

Abstract: A method for forming a semiconductor device includes providing a plurality of features in a layout, selecting critical features from the plurality of features, placing a first plurality of short-range dummy etch features in the layout at a first distance from the critical features to increase the feature density near the critical features, wherein each of the first plurality of short-range dummy etch features has a first width, removing at least one of the first plurality of short-range dummy etch features from the layout that will subsequently interfere with the electrical performance of at least one active feature so that a second plurality of short-range dummy etch features remains, and using the layout to pattern a layer on a semiconductor substrate.

Abstract: The present disclosure provide a method of manufacturing a microelectronic device. The method includes forming a top metal layer on a first substrate, in which the top metal layer has a plurality of interconnect features and a first dummy feature; forming a first dielectric layer over the top metal layer; etching the first dielectric layer in a target region substantially vertically aligned to the plurality of interconnect features and the first dummy feature of the top metal layer; performing a chemical mechanical polishing (CMP) process over the first dielectric layer; and thereafter bonding the first substrate to a second substrate.

Abstract: In one embodiment, a mandrel and an outer dummy spacer may be employed to form a first conductivity type region. The mandrel is removed to form a recessed region wherein a second conductivity type region is formed. In another embodiment, a mandrel is removed from within shallow trench isolation to form a recessed region, in which an inner dummy spacer is formed. A first conductivity type region and a second conductivity region are formed within the remainder of the recessed region. An anneal is performed so that the first conductivity type region and the second conductivity type region abut each other by diffusion. A gate electrode is formed in self-alignment to the p-n junction between the first and second conductivity regions. The p-n junction controlled by the gate electrode, which may be sublithographic, constitutes an inventive tunneling effect transistor.

Abstract: An embodiment of the invention provides a semiconductor integrated circuit device having a dummy pattern for improving micro-loading effects. The device comprises an active region in a substrate and an isolation region in the substrate adjacent the active region. A plurality of dummy patterns are formed over the isolation region, wherein each dummy pattern is aligned parallel to and lengthwise dimension of the active region. The dummy patterns may have non-uniform spacing or non-uniform aspect ratios. The dummy pattern may have, in plan view, a rectangular shape, wherein its length is greater than the lengthwise dimension of the active region. The spacing between the dummy pattern and the active region may be less than about 1500 nm.

Abstract: According to one embodiment of the present invention, a method of manufacturing a semiconductor device includes below steps. A step of preparing a phase shift mask and a normal photomask. A step of stacking a first wiring layer on a semiconductor substrate, and further stacking, on the first wiring layer, a second wiring layer. The a second wiring layer includes a second wiring and a third wiring. A step of stacking an interlayer insulating film on the second wiring layer. A step of forming, in the interlayer insulating film, a first opening in which the second wiring is exposed, and a second opening in which the third wiring is exposed by photolithography using the normal photomask. A step of burying a metal in the first opening and the second opening. A step of providing a pad to be overlaid on the first and second openings.

Abstract: The present invention provides a high-k gate dielectric/metal gate MOSFET that has a reduced parasitic capacitance. The inventive structure includes at least one metal oxide semiconductor field effect transistor (MOSFET) 100 located on a surface of a semiconductor substrate 12. The least one MOSFET 100 includes a gate stack including, from bottom to top, a high-k gate dielectric 28 and a metal-containing gate conductor 30. The metal-containing gate conductor 30 has gate corners 31 located at a base segment of the metal-containing gate conductor. Moreover, the metal-containing gate conductor 30 has vertically sidewalls 102A and 102B devoid of the high-k gate dielectric 28 except at the gate corners 31. A gate dielectric 18 laterally abuts the high-k gate dielectric 28 present at the gate corners 31 and a gate spacer 36 laterally abuts the metal-containing gate conductor 30.

Abstract: A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the semiconductor body. A gate electrode is then formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the first and second laterally opposite sidewalls of the semiconductor body. The gate electrode comprises a metal film formed directly adjacent to the gate dielectric layer. A pair of source and drain regions are then formed in the semiconductor body on opposite sides of the gate electrode.

Abstract: A dummy gate may be formed over an isolation layer. A sidewall spacer may be formed next to the dummy gate. The dummy gate and the sidewall spacer may substantially cover or completely cover the edge of isolation layer that is adjacent to an active area of a silicon substrate. Damage to the isolation layer due to a contact hole etching may be prevented, even if there are misalignments.

Abstract: A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the semiconductor body. A gate electrode is then formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the first and second laterally opposite sidewalls of the semiconductor body. The gate electrode comprises a metal film formed directly adjacent to the gate dielectric layer. A pair of source and drain regions are then formed in the semiconductor body on opposite sides of the gate electrode.

Abstract: Disclosed herein is a method of forming a floating gate in a non-volatile memory device having a self-aligned shallow trench isolation (SA-STI) structure. First, a tunnel oxide layer is formed on a semiconductor substrate having a SA-STI structure. Next, a first floating gate layer is formed on the tunnel oxide layer at a first temperature of no less than about 530° C. A second floating gate layer is then formed on the first floating gate layer at a second temperature of no more than 580° C. After depositing the first floating gate layer, the second floating gate layer is in-situ deposited to prevent the growth of a native oxide layer on the surface of the first floating gate layer. Thus, gate resistance can be reduced and process time can be shortened.

Abstract: A semiconductor device, has a semiconductor substrate; a first insulating film which is disposed above the semiconductor substrate; a second insulating film which is disposed above the first insulating film; a wiring which is disposed in the first insulating film and has a plug connecting part; a plug which is disposed in the second insulating film and connected to the plug connecting part; a plurality of first dummy wirings which are disposed in a first area near the plug connecting part in the first insulating film; and a plurality of second dummy wirings which are disposed in a second area near the wiring excepting the plug connecting part in the first insulating film, and have at least either a width smaller than that of the first dummy wirings or a pattern coverage ratio larger than that of the first dummy wirings.

Abstract: A method for fabricating a flash memory device is disclosed that improves hot carrier injection efficiency by forming a gate after forming source and drain implants using a sacrificial insulating layer pattern, which includes forming a sacrificial insulating pattern layer over a flash memory channel region of a semiconductor substrate; forming source and drain regions in the semiconductor substrate by ion implantation using the sacrificial insulating pattern layer as a mask; removing portions of the sacrificial insulating pattern layer; sequentially forming an ONO-type dielectric layer and a gate material layer; selectively etching the gate material layer and at least part of the gate dielectric layer to form a gate; and forming gate sidewall spacers at sides of the gate.

Abstract: A pattern forming method includes determining an allowable value of an etching conversion difference, obtaining a maximum distance between patterns generating the etching conversion difference within the allowable value, the patterns including main patterns or both main patterns and a dummy pattern, preparing a first design layout in which a first distance between the main patterns is smaller than the maximum distance, or a second design layout in which a second distance between the main patterns and the dummy pattern is smaller than the maximum distance, performing a design data conversion based on the first or second design layout to form first or second design data, and forming the main patterns by using the first design data, or forming both the main patterns and the dummy pattern by using the second design data.

Abstract: A package including a package substrate, a die-substrate assembly including a substrate including a plurality of layers including a layer having a mesh to stiffen the substrate adapted to mount one or more dice, one or more dice mounted on the substrate and a molding compound to attach the substrate to the package substrate. Various embodiments include a method comprising providing a substrate including a layer having an outer surface, depositing a metal layer on the outer surface, and etching the metal layer to form an opening, the opening enclosing an area on the outer surface to mount one or more dice.

Abstract: In a method of fabricating a semiconductor device, a liner is deposited over a conductive region of a wafer and a stencil layer is deposited over the liner. The stencil layer and the liner are etched to form a stencil pattern for a conductive layer. A second liner is deposited over exposed surfaces of the stencil pattern, and the exposed horizontal surfaces of the second liner are removed by sputtering. A low-k dielectric layer is then deposited over the wafer, and the wafer is planarized down to the stencil pattern by chemical-mechanical polishing. The stencil pattern is removed with a wet etch to form an aperture in the wafer exposing the liner and remaining portions of the second liner. Metal is deposited in the aperture, and the surface of the wafer is replanarized by chemical-mechanical polishing to produce a planar surface for additional metallization layers that may be deposited.

Abstract: A method, structure and design method for dissipating charge during fabrication of an integrated circuit. The structure includes: a substrate contact in a substrate; one or more wiring levels over the substrate; one or more electrically conductive charge dissipation structures extending from a top surface of an uppermost wiring level of the one or more wiring levels through each lower wiring level of the one or more wiring levels to and in electrical contact with the substrate contact; and circuit structures in the substrate and in the one or more wiring layers, the charge dissipation structures not electrically contacting any the circuit structures in any of the one or more wiring levels, the one or more charge dissipation structures dispersed between the circuit structures.

Abstract: An integrated circuit system comprised by forming a first region, a second region and a third region within a dielectric over a substrate. The first region includes tungsten plugs. The second region is formed adjacent at least a portion of the perimeter of the first region and the third region is formed between the first region and the second region. An opening is formed in the third region and a material is deposited within the opening for preventing erosion of the first region.

Abstract: An electronic device can include an NVM array, wherein portions of word lines are formed within trenches. Insulating features are formed over heavily doped regions within the substrate. In one embodiment, charge storage stacks and a control gate electrode layer can be formed and substantially fill the trench. The insulating features help to reduce capacitive coupling between the heavily doped regions and the control gate electrode layer. In a particular embodiment, the insulating features are recessed from a top surface of a layer outside the trenches. The control gate electrode layer can form a substantially continuous electrical path along the lengths of the word lines. This particular embodiment substantially eliminates the formation of stringers or other residual etching artifacts from the control gate electrode layer within the array. A process can be performed to form the electronic device.

Abstract: A method is provided for transferring a single-crystal silicon (Si) film to a glass substrate. The method deposits a germanium (Ge)-containing material overlying a Si wafer, forming a sacrificial Ge-containing film. A single-crystal Si film is formed overlying the sacrificial Ge-containing film. The Si film surface is bonded to a transparent substrate, forming a bonded substrate. The bonded substrate is immersed in a Ge etching solution to remove the sacrificial Ge-containing film, which separates the transparent substrate from the Si wafer. The result is a transparent substrate with an overlying single crystal Si film. Optionally, channels can be formed to distribute the Ge etching solution, and promote the removal of the Ge-containing film.

Abstract: Methods are provided for the fabrication of multiple finger transistors. A method comprises forming a layer of gate-forming material overlying a semiconductor substrate and forming a layer of dummy gate material overlying the layer of gate-forming material. The layer of dummy gate material is etched to form a dummy gate and sidewall spacers are formed about sidewalls of the dummy gate. The dummy gate is removed and the layer of gate-forming material is etched using the sidewall spacers as a mask to form at least two gate electrodes.

Abstract: In a method and system for relieving stress induced within a dielectric layer of a semiconductor device (100), areas in the dielectric layer (236, 238, 242) where the stress exceeds a threshold are identified. The areas, which are in parallel alignment with electrical interconnects such as conductive bumps (130), include a selected number of outer rows of the conductive bumps (130) having a high stress level. Within the identified areas where the stress exceeds the threshold, patterned zones (250) having an adjustable zone density are provided by adding reinforcing elements (240) to relieve the stress below the threshold.

Abstract: An MOS transistor formed on a heavily doped substrate is described. Metal gates are used in low temperature processing to prevent doping from the substrate from diffusing into the channel region of the transistor.

Abstract: An evaluation method includes the steps of forming a dummy pattern having a patterned part with the same critical dimension as a minimum critical dimension of an actual device having a fine pattern that is so fine that a probe for a continuity test cannot be connected to both ends of the fine pattern, in forming the fine pattern, while connecting both ends of the dummy pattern to a pair of pads to which the probe is connectible, performing the continuity test of the dummy pattern using the probe and the pads, and evaluating an insulating characteristic of the fine pattern based on a result of the continuity test.

Abstract: A new method to prevent cracking at the corners of a semiconductor die during dicing is described. Dummy metal structures are fabricated at the corners of the die to prevent cracking. The design for the dummy metal structures can be generated automatically by a computer program.

Abstract: A three-dimensional structure element having a plurality of three-dimensional structural bodies and capable of being uniformly formed without producing a dispersion in shape of the three-dimensional structural bodies, comprising a substrate (11) and the three-dimensional structural bodies (1) disposed in a predetermined effective area (20) on the substrate (11), the three-dimensional structural bodies (1) further comprising space parts formed in the clearances thereof from the substrate (11) by removing sacrificing layers, the substrate (11) further comprising a dummy area (21) having dummy structural bodies (33) so as to surround the effective area (20), the dummy structural body (33) further comprising space parts formed in the clearances thereof from the substrate (11) by removing the sacrificing layers, whereby since the dummy area (21) is heated merely to approx.

Abstract: A method including forming a hard mask and an etch stop layer over a sacrificial material patterned as a gate electrode, wherein a material for the hard mask and a material for the etch stop layer are selected to have a similar stress property; removing the material for the hard mask and the material for the etch stop layer sufficient to expose the sacrificial material; replacing the sacrificial material with another material. A system including a computing device including a microprocessor, the microprocessor including a plurality of transistor devices, at least one of the plurality of transistor devices including a gate electrode formed on a substrate surface; a discontinuous etch stop layer conformally formed on the substrate surface and adjacent side wall surfaces of the gate electrode; and a dielectric material conformally formed over the etch stop layer.

Abstract: The semiconductor device includes a semiconductor substrate, a plate electrode, and a metal layer. The semiconductor substrate includes a capacitor region and a dummy region. The plate electrode is formed over the semiconductor substrate, wherein a dummy plug of the plate electrode is formed in the dummy region. The metal layer is formed over the plate electrode, the metal layer being in contact with the dummy plug.

Abstract: A method of fabricating an ultrathin SOI memory transistor includes preparing a substrate, including forming an ultrathin SOI layer of the substrate; adjusting the threshold voltage of the SOI layer; depositing a layer of silicon oxide on the SOI layer; patterning and etching the silicon oxide layer to form a sacrificial oxide gate in a gate region; depositing a layer of silicon nitride and forming the silicon nitride into a silicon nitride sidewall for the sacrificial oxide gate; depositing and smoothing a layer of amorphous silicon; selectively etching the sacrificial gate oxide; growing a layer of oxide in the gate region; depositing and smoothing a second layer of amorphous silicon; patterning and etching the second layer of amorphous silicon; implanting ion to form a source region and a drain region; annealing the structure; and depositing a layer of passivation oxide.

Abstract: A method and system for improving the topography of a memory array is disclosed. In one embodiment, a dummy bitline is formed over a field oxide region at an interface between a memory array and interface circuitry. In addition, a poly-2 layer is applied above the dummy bitline on the field oxide region wherein the utilization of the field oxide region for placement of the dummy bitline provides a uniform surface between an actual bitline and the periphery of the memory array. Furthermore, a landing pad is formed at the end of the dummy bitline on the field oxide region, wherein the dummy bitline does not cause erroneous operation of the landing pad.

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods comprise providing a substrate comprising a first transistor structure comprising an n-type gate material and second transistor structure comprising a p-type gate material, selectively removing the n-type gate material to form a recess in the first gate structure, and then filling the recess with an n-type metal gate material.

Abstract: An embodiment of the present invention includes a gate dielectric layer, a polysilicon layer, and a gate electrode. The gate dielectric layer is on a substrate. The substrate has a gate area, a source area, and a drain area. The polysilicon layer is on the gate dielectric layer at the gate area. The gate electrode is on the polysilicon layer and has arc-shaped sidewalls.

Abstract: A method for forming a transistor including a self aligned metal gate is provided. According to various method embodiments, a high-k gate dielectric is formed on a substrate and a sacrificial carbon gate is formed on the gate dielectric. Sacrificial carbon sidewall spacers are formed adjacent to the sacrificial carbon gate, and source/drain regions for the transistor are formed using the sacrificial carbon sidewall spacers to define the source/drain regions. The sacrificial carbon sidewall spacers are replaced with non-carbon sidewall spacers, and the sacrificial carbon gate is replaced with a desired metal gate material to provide the desired metal gate material on the gate dielectric. Various embodiments form source/drain extensions after removing the carbon sidewall spacers and before replacing with non-carbon sidewall spacers. An etch barrier is used in various embodiments to separate the sacrificial carbon gate from the sacrificial carbon sidewall spacers.

Abstract: A method for forming a transistor including a self aligned metal gate is provided. According to various method embodiments, a high-k gate dielectric is formed on a substrate and a sacrificial carbon gate is formed on the gate dielectric. Sacrificial carbon sidewall spacers are formed adjacent to the sacrificial carbon gate, and source/drain regions for the transistor are formed using the sacrificial carbon sidewall spacers to define the source/drain regions. The sacrificial carbon sidewall spacers are replaced with non-carbon sidewall spacers, and the sacrificial carbon gate is replaced with a desired metal gate material to provide the desired metal gate material on the gate dielectric. Various embodiments form source/drain extensions after removing the carbon sidewall spacers and before replacing with non-carbon sidewall spacers. An etch barrier is used in various embodiments to separate the sacrificial carbon gate from the sacrificial carbon sidewall spacers.

Abstract: Metal interconnection lines of semiconductor devices and methods of forming the same are disclosed. Improved reliability is achieved in a disclosed metal line of a semiconductor device by preventing metal layers from eroding and preventing metal lines from being destroyed due to electro-migration (EM) and stress-migration (SM). An illustrated metal interconnection line includes: a semiconductor substrate; a metal pattern on the substrate; a glue pattern under the metal pattern; an anti-reflection pattern on the metal pattern; and dummy patterns surrounding side walls of the metal pattern.

Abstract: A method for making a semiconductor device is described. That method comprises forming on a substrate a dielectric layer and a sacrificial structure that comprises a first layer and a second layer, such that the second layer is formed on the first layer and is wider than the first layer. After the sacrificial structure is removed to generate a trench, a metal gate electrode is formed within the trench.

Abstract: A method of manufacturing a capacitor and a metal gate on a semiconductor device comprises forming a dummy gate on a substrate, forming a trench layer on the substrate and adjacent the dummy gate, forming a capacitor trench in the trench layer, forming a bottom electrode layer in the capacitor trench, removing the dummy gate to provide a gate trench, forming a dielectric layer in the capacitor trench and the gate trench, and forming a metal layer over the dielectric layer in the capacitor trench and the gate trench.

Abstract: A method for manufacturing a non-volatile memory. The method comprises steps of forming a first dielectric layer on a substrate and forming a dummy gate layer on the first dielectric layer. Further, the dummy gate layer is defined to form a plurality of dummy gates and a doped region is formed in the substrate by using the dummy gates as a mask. A second dielectric layer is formed on a portion of the first dielectric layer corresponding to the location of the doped region and the dummy gates are removed to expose a portion of the first dielectric layer. A conductive layer is formed over the substrate to cover the second dielectric layer and the first dielectric layer.

Abstract: A method for homogenizing the thickness of a uniform layer deposited on a layer of a material etched according to functional patterns, consisting of filling the empty areas with dummy patterns; a function, providing the thickness variation of the uniform layer for a given distribution of the functional and dummy patterns, being known; the method comprising: determining a guard distance greater than the minimum possible distance between patterns; calculating the thickness variation which would be obtained if dummy patterns were placed inside of a region defined by the dimension of the empty area reduced by said guard distance; and if the calculated thickness variation is satisfactory, adopting the chosen dummy pattern distribution, otherwise iteratively repeating the process with a reduced guard distance.

Abstract: A method includes steps of: (a) providing a wafer on which a film has been deposited; (b) exposing an annular area in an edge exclusion zone of the wafer to radiation having a wavelength suitable for patterning the film in the annular area; and (c) modulating the radiation while exposing the annular area to form a pattern in the film in the annular area.

Abstract: A non-volatile memory cell having a local silicon nitride layer to control dispersion of hot electrons is disclosed. The dual-bit non-volatile memory cell has a stack of layers including silicon on the surface of a substrate. The stack of layers has at least one first oxide silicon layer and a silicon nitride layer overlying the first oxide silicon layer. An opening is formed in the stack of layers and a gate oxide layer is deposited on the surface of the substrate within the opening. A control gate is formed on the gate oxide layer followed by a second oxide silicon layer overlying the surfaces of the control gate and the stack of layers. A second polysilicon layer is formed overlying the gate oxide layer. Dual split-gates are then formed on the second polysilicon layer.

Abstract: At least a p-type and n-type semiconductor device deposited upon a semiconductor wafer containing metal or metal alloy gates. More particularly, a complementary metal-oxide-semiconductor (CMOS) device is formed on a semiconductor wafer having n-type and p-type metal gates.

Abstract: Chemical-mechanical polishing (“CMP”) processes performed on bodies (10), each having areas (16 and 18) of different depression pattern densities, are compared by correlating polishing data accumulated, for one such body, on an area (16) of one pattern density to polishing data accumulated, for that body, on an area of another pattern density for each of the CMP processes.

Abstract: At least a p-type and n-type semiconductor device deposited upon a semiconductor wafer containing metal or metal alloy gates. More particularly, a complementary metal-oxide-semiconductor (CMOS) device is formed on a semiconductor wafer having n-type and p-type metal gates.

Abstract: A structure includes a substrate, first and second signal lines above the substrate, where unused substrate surface area exists between the first and second signal lines, and a first shield line in the unused substrate surface area. To define the first shield line, the signal line layout which includes the first and second signal lines is defined. Any areas which are not signal lines are then defined as unused areas of the substrate. The shield lines including the first shield line are then defined in portions of the unused areas of the substrate. In this manner, shield lines are automatically designed at every available location without requiring any allocation of substrate surface area.

Abstract: A wiring pattern has been enlarged by mutually different values, thereby forming two enlarged wiring patterns are formed. Then, regions where the two enlarged wiring patterns overlap each other are removed, thereby forming a dummy pattern. Alternatively, a simple-figure pattern made of simple figures is formed and a dummy pattern is formed using the simple-figure pattern. A gap that is not wider than a predetermined value is located in a final wiring pattern made of the wiring pattern and the dummy pattern is defined as an air gap region. Thus, an interconnection structure incorporating air gaps between wiring patterns is formed.

Abstract: An electrical monitor comprising a via array and method for determining and reducing an electrically charged state of a semiconductor process wafer the method including providing a metal filled via array including a plurality of interspersed electrically isolated dummy metal portions to form a via array monitor; exposing the semiconductor process wafer including the via array monitor to an electrical charge altering process including to produce an electrically charged state over at least a portion of the semiconductor wafer; carrying out electrical measurements of the via array monitor to determine a level of the electrically charged state; and, carrying out an electrically charge neutralizing process to reduce a level of the electrically charged state to a predetermined acceptable level prior to carrying out a subsequent process.