Abstract: In preparation for etch processing a semiconductor chip having areas of little or no pattern and areas that are heavily patterned, adding non-operative patterns to the areas having little or no pattern so that the overall pattern density is about the same across the chip.

Abstract: In a process for arranging printed conductors on the surface of a semiconductor component, distances from the first forbidden zones are maintained. This is accomplished by converting the first forbidden zones to second forbidden zones by enlargement, where the zones are enlarged in the x and y directions by a different factor than in the a and b directions. Then paths are produced outside of or at the edge of the second forbidden zones for the arrangement of printed conductors.

Abstract: A method for manufacturing semiconductor device is provided, this method comprises the steps of: depositing a metal film for forming wirings on a substrate; forming a wiring layer, wherein dummy wiring is inserted between wiring space where the dummy wiring can be inserted, and wiring space, where the dummy wiring cannot be inserted, is reduced by widening wiring pattern facing the wiring space; forming an interlayer insulating film on said wiring layer; and flattening surface of the interlayer insulating film. The film can be flattened by a CMP method or by an etchback of entire surface of the film. It is possible to flatten the surface of the semiconductor device cost-effectively and precisely.

Abstract: A method for forming within an integrated circuit a patterned conductor layer from a blanket conductor layer through a plasma etch method, where there is simultaneously avoided plasma induced electrical discharge damage to an integrated circuit structure formed beneath the blanket conductor layer. There is first provided a substrate. There is then formed over the substrate an integrated circuit structure. There is then formed over the substrate and the integrated circuit structure a blanket conductor layer.

Abstract: A method of improving the planarity of spin-on-glass layers in semiconductor wafer processing is disclosed. Gaps in between active conductive traces in a trace layer that exceed a predetermined distance are provided with dummy lines having a specific geometry in order to improve the planarity achieved in subsequently applied spin-on glass layers. In some embodiments, the predetermined distance is greater than approximately 1 micrometer, as for example in the range of approximately 3 to 6 micrometers. In some applications, both the active conductive traces and the dummy lines are formed from a metallic material that is deposited in one single step with a passivation layer being deposited over both the conductive traces and the raised lines prior to application of the spin-on glass layer.

Abstract: A device having, at least, a first film having a surface on which neither a natural oxide film nor impurity grains caused by a resist residue is or are present, and a conductive material layer formed on a surface adjacent to the surface of the first film, wherein an insulative compound film is formed on a surface of the conductive material layer by a surface reaction with the conductive material layer, and a predetermined second film required for an arrangement is formed on the surface of the first film.

Abstract: A method of improving the planarity of spin-on glass layers in semiconductor wafer processing is disclosed. Gaps in between active conductive traces on a trace layer of a semiconductor wafer that exceed a predetermined threshold distance are provided with dummy surfaces arranged in a micro-pattern in order to improve the planarity achieved in subsequently applied spin-on glass layers. In some embodiments, the predetermined threshold distance is greater than approximately 2 micrometers, as for example in the range of approximately 4.65 to 5 micrometers. In some applications, both the active conductive traces and the dummy surfaces are formed from a metallic material that is deposited in one single step with a dielectric layer being deposited over both the active conductive traces and the dummy surfaces prior to application of the spin-on glass layer.

Abstract: A method for manufacturing semiconductor device having conductive metal leads 14 with improved reliability, and device for same, comprising conductive metal leads 14 on a substrate 12, a first insulating material 18 at least between the conductive metal leads 14, and dummy leads 16 proximate the conductive metal leads 14. Heat from the conductive metal leads 14 is transferable to the dummy leads 16, and the dummy leads 16 are capable of dissipating the heat. The first insulating material 18 has a dielectric constant of less than 3.5. An optional heatsink 22 may be formed in contact with the first dummy leads 16 to further dissipate the Joule's heat from the conductive metal leads 14. An advantage of the invention is to improve reliability of metal leads for circuits using low-dielectric constant materials.

Abstract: A method for controlling the spacing between the emitter mesa and the base ohmic metal of a heterojunction bipolar transistor (HBT) to obtain a relatively high gain (.beta.) with a low-parasitic base resistance. In a first method, after the emitter, base and collector layers are epitaxially grown on a substrate, a sacrificial layer is deposited on top of the emitter layer. The emitter mesa is patterned with a photoresist using conventional lithography. Subsequently, the sacrificial layer is etched to produce an undercut. The emitter layer is then etched and a photoresist is applied over the first photoresist used to pattern the emitter mesa, as well as the entire device. The top layer of photoresist is patterned with a conventional process for lift-off metalization, such that the final resist profile has a re-entrant slope. The base ohmic metal is deposited and then lifted off by dissolving both the second layer of photoresist, as well as the original photoresist over the emitter mesa.

Abstract: A method of automatically generating dummy metals for multilevel interconnection makes use of a quantum array pattern accompanying an operating pattern to from a metal pattern. The method comprises the combination selected from intersection (AND), union (OR), oversizing, downsizing, or incorporation operation through computer-aided design (CAD). Therefore, the application of the metal pattern to a process for fabricating a multimetal structure can acquire full planarization between two metal layers because of the arrangement that several dummy metals are positioned among the metal lines to diminish the spacing which exceeds the planarization limit. Also, the dummy metals are shaped in blocks thereby preventing the loading effect during etching and decreasing the parasitic capacitance therebetween.

Abstract: A method for fabricating a mask for forming a metallurgy system on a semiconductor device that provides a planar top surface is described. An initial mask pattern for the metallurgy system is designed that includes operative conductive lines that electrically connect device structure, and include parallel lines that are non-uniformly spaced, resulting in large areas. The mask design is re-designed to fill in parallel dummy lines in the large areas where the spacing of the conductive lines is equal to or greater than three times the feature size, or alternatively, the width of the lines.

Abstract: Undercutting of conductive lines in a dense array on a dielectric layer containing an open field is prevented by providing one or more non-functional components, such as one or more non-functional conductive lines, in the dielectric layer under the dense array of conductive lines.

Abstract: A narrow dummy pattern made of aluminum is formed between an identification area of a semiconductor chip and a dicing line to prevent film peeling in a dicing operation from reaching the identification area.

Abstract: A method for improving the end-point detection for contact and via etching is disclosed. The disclosure describes the deliberate addition of dummy patterns in the form of contact and via holes to the regular functional holes in order to increase the amount of etchable surface area. It is shown that, one can then take advantage of the marked change in the composition of the etchant gas species that occurs as soon as what was once a large exposed area has now been consumed through the etching process. This then gives a strong and robust signal for the end of the etching process. This in turn results in better controlled and more reliable product. It is also indicated that with the full uniform pattern of the via layers now possible, the chemical/mechanical polishing process becomes much less pattern sensitive.

Abstract: Spin-on glass etchback is a technique commonly used to planarize the surface of a semiconductor wafer during fabrication. The etch rate of spin-on glass is largely affected by the amount of oxide exposed during the spin-on glass etchback process. The amount of oxide exposed during spin-on glass etchback is dependent upon the underlying pattern density of topography. A method of standardizing the pattern density of topography for different layers of semiconductor wafers to improve the spin-on glass etchback process used to planarize the surface of a wafer during processing is disclosed. In order to achieve a standardized pattern density of topography on the surface of a wafer, dummy raised areas are added into gaps between active conductive traces on a trace layer. In some embodiments, the standardized pattern density is in the range of approximately 40% to 80%.