Abstract: A method of making nanometer Si islands for single electron transistors is disclosed. Initially, a pad oxide is deposited over a silicon substrate. Oxygen ions are implanted into the silicon substrate to form an oxygen amorphized region and a high-temperature annealing is performed to form a buried oxide layer in the silicon substrate. Then, a thermal silicon oxide is formed to reduce the thickness of the silicon substrate on the buried oxide layer. The thermal oxide is removed and an ultra-thin oxide layer is then formed on the silicon substrate. A plurality of silicon nitride blocks is formed on the ultra-thin silicon oxide. Afterwards, the spacers of the silicon nitride blocks are formed. The silicon nitride blocks are removed by using wet etching technique. The ultra-thin silicon oxide is etched back and the polysilicon spacers are used as hard mask to Si substrate to form a plurality of nanometer silicon islands.

Abstract: A masking and etching technique during the formation of a memory cell capacitor which simultaneously separates storage poly into individual storage poly nodes and etches recesses into the storage poly nodes which increase the surface area of the storage poly nodes and thereby increase the capacitance of a completed memory cell without additional processing steps.

Abstract: A removable oxide spacer is used to reduce the size of a contact opening in a memory cell between polysilicon word lines below a lithographic minimum. The removable spacer is deposited before the buried contact patterning and etching. Since word lines diverge at a cell location, the removable spacer retains a lesser thickness over the divergent area contact opening and a greater thickness elsewhere between word lines due to the more narrow gap therebetween and the spacer being deposited such that it fills the gap. The removable spacer reduces the buried contact size since the actual self-aligned contact area is defined by the spacer sidewall. The removable spacer is formed of materials having higher etching selectivity relative to materials forming underlying structures. Etching of the spacer creates a buried contact opening smaller than a lithographic minimum because silicon oxide surrounding the buried contact area is protected by the removable spacer.

Abstract: The present invention provides a method of forming a opening in a semiconductor dielectric layer. In an advantageous embodiment, the method comprises the steps of forming a hardmask layer on the dielectric layer wherein the hardmask layer has an etch rate less than an etch rate of the dielectric layer, forming a guide opening through the hardmask layer, forming a spacer within the guide opening that reduces a diameter of the guide opening and forming the opening in the dielectric layer through the guide opening. The method may further include the steps of depositing a conductive material in the opening and guide opening and over at least a portion of the hardmask layer that extends beyond the guide opening, and removing the hardmask layer and the conductive material layer that extend beyond the guide opening. In certain embodiments, the contact opening may be formed to a width equal to or less than 0.25 .mu.m.

Abstract: A method for forming a reduced size contact hole over a structure.

Abstract: A method for forming a trenched polysilicon structure can be applied to a semiconductor device. The method includes steps of: a) providing a polysilicon layer; b) forming a dielectric layer on the polysilicon layer; c) forming a rugged oxide layer on the dielectric layer; d) removing a portion of the dielectric layer which is not covered by the rugged oxide layer for exposing a corresponding portion of the polysilicon layer; e) forming a plurality of microtrenches by etching the corresponding portion of the polysilicon layer; and f) removing the rugged oxide layer and the dielectric layer to obtain the trenched polysilicon structure.

Abstract: The present invention is directed to a method for forming a semiconductor device having a reduced channel length. The method comprises forming a layer of a dielectric material above a surface of a semiconducting substrate, and forming a layer of polysilicon above the layer of dielectric material. The method further comprises forming a layer of silicon nitride or silicon oxynitride above the layer of polysilicon, and patterning said layer of polysilicon and layer of silicon nitride or silicon oxynitride to define an opening and expose a sidewall surface of the polysilicon layer. The method continues with the growth of a lateral extension of the polysilicon layer and the oxidation of the extension. The method concludes with the patterning of the polysilicon layer to define a gate conductor, and the formation of source and drain regions in the substrate.

Abstract: A method is provided for filling undesired sublithographic contact hole defects in a semiconductor structure caused by misalignment and undesirable overlap of metal line images over contact openings during photolithographic patterning. Unwanted contact between conductive metallization levels through these defects is thereby diminished. The method also provides self-alignment of the lines and contact holes for subsequent formation of stud via connections through which contact is desired to underlying metallization levels. Deposition of a conformal sacrificial material film fills the small, undesired sublithographic contact hole image formed and covers both mask surfaces through which the misaligned line image and contact opening were etched. Isotropic etching removes the conformal layer from all planar surfaces except those of the undesired sublithographic contact hole image.

Abstract: A method of lithographically fabricating small line width features in a device in accordance with a desired pattern, the small line width features being smaller than that capable of a lithographic process alone, is disclosed. A first layer of material is provided upon a substrate, the first layer including that in which the small line width features are to be made. A lithographically patterned layer is then provided upon the first layer in accordance with a second pattern defined in conjunction with the desired pattern. The patterned layer includes a second material selected to be compatible with the material of the first layer. A conformal layer is then deposited upon the patterned layer, the conformal layer including a third material selected to be compatible in conjunction with the first material and with the second material.

Abstract: A stacked capacitor having very thin fins and subminimum dimension supports for the fins is described. The capacitor includes a stack of conductive layers on a substrate. A plurality of subminimum dimension trenches are formed in the stack and a columnar conductive layer lines the trenches in contact with alternate layers of the stack. An insulator lines these alternate layers and the columnar conductive layer and capacitively couples these alternate layers and the columnar conductive layer to a second plate layer that is formed between the alternate layers, within the columnar layers in the trenches, and extending between stacked capacitors.

Abstract: A cascading transistor gate structure and method for fabricating the same are disclosed. A substrate is provided, and a layer of gate dielectric material is formed over the substrate. A layer of electrically conductive material is formed over the gate dielectric. A layer of hard mask material is formed on the layer of electrically conductive material. A photoresist mask is used to pattern the layer of hard mask material to form a hard mask. A layer of spacer material is deposited over the existing structures, and the layer of spacer material is etched to form a pair of spacers adjacent to the hard mask. The hard mask is removed, leaving the spacers. The layer of electrically conductive material is etched in alignment with the spacers. The spacers are then removed, revealing two transistor gates. A conductive region in formed in the substrate between the two gates. The two gates operate in tandem, yielding a cascading gate with an effective length that is the lengths of the two gates combined.

Abstract: A method for producing sublithographic etching masks for creating structured features in semiconductor products having a large scale of integration, includes applying lines that are orthogonal to one another in successive steps with the aid of the spacer technique. Through the use of various etching steps, a grid of extremely small etching masks is obtained, which is formed by the intersection points of the lines. The size of the etching masks is determined by the layer thickness of the spacer layer, and not by the feature or structure size of the photographic technique.

Abstract: A new method for forming a feature having a feature size of one half the resolution of the photolithography process by adjusting the etching conditions is achieved. A capping oxide layer is deposited overlying the feature layer. A first layer of photoresist is patterned using a photolithography process to provide a first photomask having a first feature size. The oxide layer is etched vertically through no more than half of its thickness and the photomask and oxide layer are etched horizontally to provide a first oxide mask having a second feature size one half the width of the first feature size. The first photomask is removed. A second photoresist layer is patterned to provide a second photomask for forming the second feature wherein the second photomask has a first feature size and is shifted horizontally by twice the desired feature size from the first photomask.

Abstract: A base is etched using as mask a first masking layer which has been patterned, softened and deformed. Then, the first masking layer is eroded, a second masking layer is selfaligningly formed only on bare portions of the base, and the base is again etched using as mask the second masking layer. Within a pitch of the first masking layer, the base can thus be etched in two regions which are separated from each other. These treatments can also be conducted in two directions.

Abstract: A low voltage electro-static discharge protective device includes a field oxide layer on a substrate, source/drain regions beside the field oxide layer in the substrate, and a threshold voltage adjustment region under the field oxide layer. The fabricating of the protective device includes forming a pad oxide layer and a silicon nitride layer on a substrate, etching the silicon nitride layer to form an opening, forming a oxide spacer on the exposed portion of the pad oxide layer around the periphery of the opening, implanting ions into the substrate, forming a field oxide layer in the opening, so that the certain type of ions form a threshold voltage adjustment region under the field oxide layer, removing the silicon nitride layer, removing the exposed pad oxide layer, and forming source/drain regions beside the field oxide layer.

Abstract: The present invention relates to a method of forming a self-contact hole on a semiconductor substrate. A polysilicon layer is formed over a substrate. A photoresist is patterned on the polysilicon layer. Then an etching is performed to etch the polysilicon layer, and during the etch polymers are formed on the side wall the polysilicon layer and the photoresist. Using the polymer side wall spacer as a mask to formed an opening in the polysilicon layer. Subsequently, the photoresist and side wall spacer are removed. A opening which is smaller than the conventional one is formed, that will increase the accuracy of a contact hole alignment.

Abstract: A thick column is formed by masking and etching a substrate, and the column is thinned to a very small diameter (e.g., .ltoreq.5 nm) by oxidizing the column and removing the oxide layer. A metal layer is deposited on the surface of the substrate, and the column and substrate are etched to form a pit. The backside of the substrate is etched to form an aperture surrounded by the metal layer. Alternatively, the metal layer is removed and a dopant layer is implanted into the substrate, followed by the etching of the backside, leaving an aperture surrounded by the dopant layer. In a second alternative, the oxidized column is broken from the substrate, and the backside is etched, leaving an aperture surrounded by an oxide layer. These processes can be used to fabricate apertures of very small and reproducible dimensions for such instruments as near field scanning optical microscopes and scanning ion conductance microscopes.

Abstract: A method for forming a gap in a silicon layer is described. A silicon layer is formed over a substrate. A nitride layer is formed over the silicon layer and an oxide layer is formed over the silicon layer, adjacent to the nitride layer. A portion of the oxide layer is then removed to form an exposed region of the silicon layer. Then an etchant is applied to the exposed region to form an gap of the silicon layer.

Abstract: A semiconductor process in which a dielectric layer is formed on an upper surface of a semiconductor substrate which includes a silicon base layer. Thereafter, an upper silicon layer is formed on an upper surface of the dielectric layer. The dielectric layer and the upper silicon layer are then patterned to form first and second silicon-dielectric stacks on the upper surface of the base silicon layer. The first and second silicon-dielectric stacks are laterally displaced on either side of a channel region of the silicon substrate and each include a proximal sidewall and a distal sidewall. The proximal sidewalls are approximately coincident with respective boundaries of the channel region. Thereafter, proximal and distal spacer structures are formed on the proximal and distal sidewalls respectively of the first and second silicon-dielectric stacks. A gate dielectric layer is then formed on exposed portions of the silicon base layer over a channel region of the base silicon layer.

Abstract: A device and method is provided for programming an output logic level based on one or more revisions to mask layers utilized for forming an integrated circuit. The programmed logic level is represented as a logic value and is output from a device embodied within the integrated circuit formed from the mask layers. Each revision of mask layers is represented as a binary value at bit locations within a revision code output from the present system. The device and method hereof is used to program the system in accordance with an infinite numbers of mask layers and revisions to those mask layers. The programmed output from the system is represented as a revision code of numerous bits output through a pin location extending from the outer surface of a package surrounding the integrated circuit. Ready access to the pin location allows an end user to access and determine a version of integrated circuit product embodied within a sealed package, without opening the package and destroying the enclosed product.

Abstract: The present invention provides a method for fabricating a multiple pillar shaped capacitor which has pillars of a smaller dimension than the resolution of the photolithography tool. The invention has two embodiments for forming the pillars and third embodiment for patterning a conductive layer into discrete bottom electrodes. The method begins by forming a conductive layer on a first planarization layer. For the first embodiment, the pillars are formed using a photolithography mask with a pattern of spaced transparent areas. The dimensions of the spaced transparent areas and distances between the spaced transparent areas are smaller then that of the resolution of the lithographic tool. Spaced oxide islands are formed with the mask and are used as an etch mask to form spaced pillars from the conductive layer. The second embodiment for forming the pillars involves using small titanium silicide islands as an etch mask to define the pillars.

Abstract: A method of manufacturing a capacitor for use in semiconductor memories includes forming an undoped dot silicon layer on a doped polysilicon layer. Thermal oxidation is used to convert the dot silicon layer and portions of the doped polysilicon layer into silicon oxide. Then a CMP process is used to remove the oxidized dot silicon layer to create a silicon oxide etching mask. Next, an etching process is performed to form a large number of cavities in the doped polysilicon layer. The silicon oxide layer is then removed and the doped polysilicon layer is patterned and etched to form a bottom storage node of the capacitor.

Abstract: The present invention relates to forming a narrow gate MOSFET having a local ion implantation to reduce the junction capacitance. A polysilicon layer is formed over a semiconductor substrate. An opening is formed in the polysilicon layer by using patterning and etching. Subsequently, a thermal oxidation is performed to oxidize the polysilicon layer into a polysilicon-oxide layer that is expanded in volume relative to the polysilicon layer thereby narrowing said opening. Then an ion implantation is performed by using said polysilicon-oxide layer as a mask.

Abstract: A method of forming an isolation region is provided. A silicon oxide layer (4) is formed on a wafer (2). A first silicon oxynitride (6) layer is formed on the silicon oxide layer, and a silicon nitride layer (8) is formed on the first silicon oxynitride layer. The silicon nitride layer and a portion of the silicon oxynitride layer are etched. A TEOS-oxide layer (10) is deposited on the first silicon oxynitride layer and on the silicon nitride layer. Sidewall spacers (12) are formed on the sidewalls of the silicon nitride layer. A second silicon oxynitride layer (14) is deposited on the silicon nitride layer, sidewall spacers, and the silicon oxide layer. A second silicon nitride layer (16) is deposited and formed on the second oxynitride layer. A sacrificial oxide layer (18) is deposited on the second silicon nitride layer. A portion of the sacrificial oxide layer is etched.

Abstract: A method of forming a gate electrode for an insulated-gate field-effect transistor (IGFET) is disclosed. The method includes forming a gate material for providing a gate electrode over a semiconductor substrate, forming a first mask over the gate material wherein the first mask includes an opening that defines a first edge of the gate electrode, removing a first portion of the gate material to form the first edge of the gate electrode as defined by the first mask, forming a second mask over the gate material after removing the first mask wherein the second mask includes an opening that defines a second edge of the gate electrode, removing a second portion of the gate material to form the second edge of the gate electrode as defined by the second mask, and removing the second mask. Thus, the gate electrode is defined by a lateral displacement between the openings in the first and second masks.

Abstract: A method is provided for filling undesired sublithographic contact hole defects in a semiconductor structure caused by misalignment and undesirable overlap of metal line images over contact openings during photolithographic patterning. Unwanted contact between conductive metallization levels through these defects is thereby diminished. The method also provides self-alignment of the lines and contact holes for subsequent formation of stud via connections through which contact is desired to underlying metallization levels. Deposition of a conformal sacrificial material film fills the small, undesired sublithographic contact hole image formed and covers both mask surfaces through which the misaligned line image and contact opening were etched. Isotropic etching removes the conformal layer from all planar surfaces except those of the undesired sublithographic contact hole image.

Abstract: Germanium is employed as an antireflective coating material for use in active area lithography and gate area lithography steps in the formation of a semiconductor integrated circuit. A germanium layer is deposited over an active area nitride layer or over a gate area nitride layer, and a photoresist layer is then formed on the germanium layer. The photoresist layer is than exposed and developed. During exposure, the germanium layer substantially reduces reflection from the underlying nitride layer, thereby relieving the dependency of exposure energy and resulting line width on the underlying nitride layer thickness. Germanium-silicon may also be employed as the antireflective layer.

Abstract: A process for forming a shallow trench isolation is disclosed. Initially, a gate oxide layer is formed on a substrate, and a silicon nitride, which defines an active area, is then patterned on the gate oxide layer. Next, hemispherical grain silicon is formed on the silicon nitride, the sidewalls of the silicon nitride, and the exposed gate oxide layer. Portions of the gate oxide layer are removed to form oxide islands using the silicon nitride and the hemispherical grain silicon as mask. Thereafter, portions of the substrate are removed using the oxide islands as mask. Finally, the exposed substrate is thermally oxidized to form the field oxide structure of the present invention.

Abstract: A method for fabricating small contact openings in the polysilicon/metal 1 dielectric (PMD) layer on semiconductor substrates using polymer sidewall spacers was achieved. This extends the current photoresist resolution limits while simplifying the manufacturing process. The method involves depositing a polysilicon layer on the PMD layer and using a photoresist mask having openings over device contact areas in the substrate. The polysilicon layer is then patterned to form openings with vertical sidewalls to the PMD insulating layer. The contact openings are then anisotropically plasma etched in a gas mixture that simultaneously forms polymer sidewall spacers on the sidewalls in the openings in the polysilicon layer. These sidewall spacers further reduce the contact opening size. The remaining photoresist layer and polymer sidewall spacers are simultaneously removed to complete the narrow contact openings. This method eliminates the need to use an additional deposition and etch-back step to form the sidewalls.

Abstract: A method for forming contact holes in a semiconductor device, involving formation of a ring-shaped pad at a contact region. The ring-shaped pad is used as an etch barrier film upon forming a contact hole. The use of such a ring-shaped pad enables easy formation of a contact hole with a critical dimension. In accordance with this method, it is possible to increase a process margin upon the formation of contact holes for providing contacts with a critical dimension while maintaining an insulation between neighboring conductors.

Abstract: In accordance with the present invention, there is provided a method by which narrow lateral dimensioned microelectronic structures can be formed using low temperature processes. An uncured resist layer (e.g. PMMA 42) is deposited on a supporting layer (e.g. silicon 40) and patterned. Then, by using an isotropic process such as a low temperature chemical vapor deposition, a conformal layer (e.g. silicon oxynitride 44) is deposited substantially evenly on the vertical walls and on the horizontal surfaces of the uncured resist layer. An anisotropic etch such as reactive ion etching is then used to substantially remove the conformal layer from the horizontal surfaces without substantially etching the conformal layer from the vertical walls of the resist. The resist can then be selectively removed, producing isolated vertical sidewall structures (e.g. silicon oxynitride 46) which could be used, for example, as a negative tone mask. Alternatively, instead of removing the resist, another resist layer (e.g.

Abstract: A scanning probe microscope is used to pattern a layer of resist, and the pattern is transferred to a substrate. First, an underlayer formed of, for example, polyimide and a top layer formed of, for example, amorphous silicon are deposited on the substrate. A pattern is formed on the top layer using the tip of the cantilever in a scanning probe microscope. The pattern may consist of an oxide formed by an electric field at the cantilever tip. The top layer is then etched using the pattern as a mask and using an etchant that is selective against the underlayer. The underlayer is then etched using an etchant that is selective against the top layer and substrate. The substrate is etched with an etchant that removes the top layer but is selective against the underlayer. Finally, the underlayer is removed.