Method for forming interconnect structure having airgap
A method for forming an interconnect structure with airgaps, includes: providing a structure having a trench formed on a substrate; depositing a spacer oxide layer on sidewalls of the trench as sidewall spacers by plasma enhanced atomic layer deposition; filling the trench having the sidewall spacers with copper; removing the sidewall spacers to form an airgap structure; and encapsulating the airgap structure, wherein airgaps are formed between the filled copper and the sidewalls of the trench.
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1. Field of the Invention
The present invention generally relates to a method for forming interconnect structures, particularly to a method for forming interconnect structures having airgaps.
2. Description of the Related Art
As the dimension between metal lines decreases for each successive technology node, it is necessary to continue scaling down the capacitance between metal lines to reduce cross-talk and RC delay. Towards this objective, the k value (dielectric constant) of dielectric materials has been scaled down aggressively in the past decade from 4.0 to about 2.5. Leading edge manufacturing companies have recently reached a Keff of about 2.7 (effective k value) with the use of low-k CDO (carbon doped oxide) having a k value of about 2.5 and SiCN dielectric diffusion barrier having a k value of about 5.0. In order to achieve scaling Keff significantly below 2.5, a further decrease of k value from 2.5 to less than 2.3 will be required. The ITRS roadmap stated the target k value for bulk dielectric should be about 2.2 for a 22-nm technology node. However, it has been difficult to develop a dielectric material having a k value of less than 2.5 with good mechanical and suitable integration properties. For example, if a high porosity material is used for forming a dielectric film having a k value of less than 2.5, its mechanical strength will be significantly degraded. In addition, high porosity can lead to connected-pore problems, causing severe process integration challenges (e.g., diffusion problems in ALD/CVD-based metal process technology).
Considering the above, drastic changes have been proposed to develop airgap technology to achieve a Keff reduction for future extendibility. Nevertheless, all of the airgap processes require drastic changes to the existing process schemes. For example, Hsien-Wei Chen, et al. (“A Self-aligned Airgap Interconnect Scheme,” Interconnect Technology Conference, 2009. IITC 2009. IEEE International, 1-3 Jun. 2009, pp. 146-148) use a plasma damage layer as a sacrificing layer for forming an airgap. Although this scheme does not require an additional patterning step for forming an airgap, it is difficult to control the thickness of airgap because the thickness of the plasma damage layer is not readily controllable. Patterning the airgaps is also difficult because it is difficult to deposit a sacrificing layer on sidewalls of trenches with high conformality. The conformality of a layer formed by thermal CVD tends to be better than that of plasma enhanced CVD, but thermal CVD requires high heat which is not suitable for metal (e.g., copper) interconnect structures.
SUMMARYConsequently, some embodiments of the present invention uses conformal dielectric ALD (atomic layer deposition) process to create airgap spacing, thus reducing Keff without having to further scale down the k value of the bulk dielectric while keeping the current process flow intact or without substantial changes. More specifically, in some embodiments, the dielectric ALD process is performed at a temperature of lower than 400° C. to be compatible with BEOL (back end of line) copper damascene processing. In some embodiments, plasma enhanced ALD (PEALD) is used in a manner to control spacing for pitch halving and airgap formation simultaneously. Airgaps are formed by using sidewall spacers as sacrificing layers. In some embodiments, the sacrificing layer may be made of SiO or SiON. In some embodiments, a pore-sealing layer is deposited on sidewalls of a trench as an underlying layer for the sacrificing layer, and/or a protective layer is deposited on the sacrificing layer, which protective layer protects a surface of copper. In some embodiments, the protective layer is deposited by PEALD and may be made of SiCN or SiN.
For purposes of summarizing aspects of the invention and the advantages achieved over the related art, certain objects and advantages of the invention are described in this disclosure. Of course, it is to be understood that not necessarily all such objects or advantages may be achieved in accordance with any particular embodiment of the invention. Thus, for example, those skilled in the art will recognize that the invention may be embodied or carried out in a manner that achieves or optimizes one advantage or group of advantages as taught herein without necessarily achieving other objects or advantages as may be taught or suggested herein.
Further aspects, features and advantages of this invention will become apparent from the detailed description which follows.
These and other features of this invention will now be described with reference to the drawings of preferred embodiments which are intended to illustrate and not to limit the invention. The drawings are oversimplified for illustrative purposes and are not necessarily to scale.
An embodiment provides a method for forming an interconnect structure with airgaps, comprising: (i) providing a structure having a trench formed on a substrate; (ii) depositing a spacer oxide layer on sidewalls of the trench as sidewall spacers preferably by plasma enhanced atomic layer deposition; (iii) filling the trench having the sidewall spacers with copper; (iv) removing the sidewall spacers to form an airgap structure; and (v) encapsulating the airgap structure, wherein airgaps are formed between the filled copper and the sidewalls of the trench.
In some embodiments, the method may further comprise depositing a SiCxNy-based spacer layer (hereinafter in “SiCxNy”, x and y indicate a type of film, rather than indicating actual atomic compositions, and are independently 0 or 1, typically both x and y are 1) on the sidewall spacers by atomic layer deposition before filling the trench, wherein airgaps are formed between the SiCxNy-based spacer layer and the sidewalls of the trench. In some embodiments, the method may further comprise depositing a pore-sealing layer on the sidewalls before depositing the spacer oxide layer, wherein airgaps are formed between the pore-sealing layer and the SiCxNy-based spacer layer.
In any of the foregoing embodiments, the step of providing the structure may comprise: (a) producing a via structure on the substrate; (b) performing SLAM (simultaneous location and mapping) processing to cover the via structure with a SLAM layer; and (c) forming a trench by etching part of the SLAM layer, wherein the method further comprises forming a via by removing a remaining part of the SLAM layer after the SiC-based spacer layer is deposited on the sidewall spacers but before filling the trench with copper wherein the trench and the via are filled with copper. In some embodiments, the method may further comprise depositing a SiCxNy-based spacer layer on the sidewall spacers by atomic layer deposition before forming the via, wherein airgaps are formed between the SiCxNy-based spacer layer and the sidewalls of the trench. In some embodiments, the method may further comprise depositing a pore-sealing layer on the sidewalls of the trench before depositing the spacer oxide layer, wherein airgaps are formed between the SiCxNy-based spacer layer and the pore-sealing layer.
In some embodiments, the spacer oxide layer may be a silicon oxide layer.
In some embodiments, the structure having the trench on the substrate may be a layered structure comprising a diffusion barrier layer, a low-k layer, and a hard mask formed in this layering order on the substrate, wherein the trench penetrates the hard mask, the low-k layer, and the diffusion barrier layer.
In some embodiments, the step of providing the structure may comprises: (i) forming a photoresist pattern on the hard mask; (ii) depositing an oxide spacer on the photoresist and an area of the hard mask uncovered by the photoresist, by PEALD at a temperature of 400° C. or lower; (iii) etching the oxide spacer by a thickness of the oxide spacer in a thickness direction, thereby leaving a sidewall portion of the oxide spacer deposited on sidewalls of the photoresist; (iv) etching an area of the hard mask exposed after the etching of the oxide spacer, followed by removing the sidewall portion of the oxide spacer and the photoresist to obtain a patterned hard mask and an exposed portion of the low-k layer; (v) forming a second photoresist pattern on the exposed portion of the low-k layer and a part of the patterned hard mask; (vi) depositing a second oxide spacer on the second photoresist and an area of the patterned hard mask uncovered by the second photoresist, by PEALD at a temperature of 400° C. or lower; (vii) etching the second oxide spacer by a thickness of the second spacer in a thickness direction, thereby leaving a sidewall portion of the second oxide spacer deposited on sidewalls of the second photoresist; (viii) etching an area of the patterned hard mask exposed after the etching of the second oxide spacer, followed by removing the sidewall portion of the second oxide spacer and the second photoresist to obtain a second patterned hard mask and an exposed portion of the low-k layer; and (ix) etching the low-k layer and the diffusion barrier layer using the second patterned hard mask. The above scheme is a double-exposure BEOL process, wherein a photoresist is used twice to form a trench.
In some embodiment, the step of providing the structure comprises: (i) forming a photoresist pattern on the hard mask; (ii) trimming the photoresist to reduce the dimensions; (iii) depositing an oxide spacer on the trimmed photoresist and an area of the hard mask uncovered by the trimmed photoresist, by PEALD at a temperature of 400° C. or lower; (iv) etching the oxide spacer by a thickness of the oxide spacer in a thickness direction, thereby leaving a sidewall portion of the oxide spacer deposited on sidewalls of the trimmed photoresist, followed by removing the trimmed photoresist; (v) etching an area of the hard mask exposed after the etching of the oxide spacer and the removal of the trimmed photoresist, followed by etching the sidewall portion of the oxide spacer to obtain a patterned hard mask and an exposed portion of the low-k layer; and (vi) etching the low-k layer and the diffusion barrier layer using the patterned hard mask. The above process is a single-exposure BEOL process, wherein a photoresist is used once for forming a trench.
In any of the disclosed embodiments, either the above double-exposure process or the single-exposure process can be used to etch any interlayer dielectric.
In some embodiments, the SiCxNy-based spacer layer on the sidewall spacers may be constituted by SiCN.
In some embodiments, the structure having the trench on the substrate may be a layered structure comprising a diffusion barrier layer, a low-k layer, and a hard mask formed in this layering order on the substrate, wherein the trench penetrates the hard mask and the low-k layer, but does not penetrate the diffusion barrier layer, whereby the pore-sealing layer is disposed on the sidewalls of the hard mask and the low-k layer, followed by extending the trench downward to penetrate the diffusion barrier layer before depositing the spacer oxide layer.
In some embodiments, the via structure may be a layered structure comprising a diffusion barrier layer, a low-k layer, and a hard mask in this layering order on the substrate, wherein a via penetrates the hard mask and the low-k layer, but not the diffusion barrier layer, wherein when the via is formed by removing the remaining part of the SLAM layer, the diffusion barrier layer is also removed.
In some embodiments, the via structure may be a layered structure comprising a diffusion barrier layer, a dense low-k layer, a porous low-k layer, and a hard mask in this layering order on the substrate, wherein a via penetrates the hard mask, the porous low-k layer, and the dense low-k layer, wherein the step of forming the trench comprises etching the porous low-k layer, but not the dense low-k layer, wherein when the via is formed by removing the remaining part of the SLAM layer, the diffusion barrier layer is also removed.
In any of the foregoing embodiments, the method may further comprise selecting a thickness of the spacer oxide layer to achieve a targeted dielectric constant of the encapsulated airgap structure between the copper filled in the trench and copper filled in an immediately adjacent trench, and the step of depositing the spacer oxide layer is controlled to obtain the spacer oxide layer at the selected thickness. In some embodiments, the thickness of the spacer oxide layer may be controlled at 0.4 nm to 10 nm. In some embodiments, the targeted dielectric constant of the encapsulated airgap structure may be less than 2.5.
In this disclosure, the term “trench” may refer to a deeply etched area used to isolate one area from another or to form a storage capacitor on a wafer. The trench may be filled with copper and constitute a metal layer.
The term “via” may refer to an opening in the dielectric layer(s) through which a riser passes, or in which the walls are made conductive; an area that provides an electrical pathway (typically a vertical pathway) from one metal layer to the metal layer above or below. The via may connect two trench layers formed in a layering direction.
The term “Keff” may refer to the effective dielectric constant of a material constituted by more than one layer or portion which can be calculated based on the dielectric constant of each layer or portion constituting the material and the thickness of each layer or portion, wherein the layer or portion includes an “airgap” which has a dielectric constant of one.
A “layer” may consist of a single layer (uniform or homogenous layer) or may be comprised of multiple layers stacked in a thickness or layering direction, and may be a continuous or discontinuous layer extending in a direction perpendicular to a thickness or layering direction. “Forming a layer on another layer” may refer to a layer formed immediately or directly on another layer or formed indirectly on another layer where one or more intervening layers are formed therebetween. Further, “gas” may include vaporized solid and/or liquid and may be constituted by a mixture of gases.
In the present disclosure where conditions and/or structures are not specified, the skilled artisan in the art can readily provide such conditions and/or structures, in view of the present disclosure, as a matter of routine experimentation.
Also, in the present disclosure, the numerical numbers applied in specific embodiments can be modified by a range of at least ±50% in other embodiments, and the ranges applied in embodiments may include or exclude the endpoints.
The present invention will be explained in detail with reference to preferred embodiments which are not intended to limit the present invention.
The first three process flows described below are related to a single damascene process, and the second three process flows described later are related to a dual damascene process. However, the present invention is not intended to be limited to these particular applications. The skilled artisan would appreciate that the process flows disclosed herein can be applied to any suitable process schemes for forming interconnect structures. Unless specified otherwise, deposition of layers can be accomplished by any suitable plasma methods including enhanced CVD, thermal CVD, high density plasma CVD, UV radiation, plasma enhanced ALD, and thermal ALD.
The first process flow is shown in
As shown in
In the above, the SiCN layer can be deposited by any suitable methods including, but not limited to, those disclosed in U.S. Patent Application Publication No. 2008/0038485, the disclosure of which is herein incorporated by reference in its entirety. The CDO layer can be deposited by any suitable methods including, but not limited to, those disclosed in U.S. Pat. No. 6,455,445, the disclosure of which is herein incorporated by reference in its entirety. The porous CDO layer can be deposited by any suitable methods including, but not limited to, those disclosed in U.S. Pat. No. 7,098,149, the disclosure of which is herein incorporated by reference in its entirety. The TiN layer (hard mask) can be deposited by any suitable methods including, but not limited to, spattering and thermal CVD.
Next, a spacer oxide layer 20 is deposited as a sidewall spacer as shown in
In this embodiment, as described above, three spacers 16, 18, 20 are used. The spacers 16, 18 can be deposited in methods which are similar to or the same as those for the spacer 20, so that accurate patterning can be realized due to the high conformality of deposited layers. Low-temperature PEALD methods, particularly methods disclosed in above-mentioned U.S. patent application Ser. No. 12/416,809, are preferably used for spacers 16 and 18 if the heat resistance of photoresists 15 and 17 is not sufficient, and also for spacer 20 if a lower film density and a higher film removal rate of the spacer are desired.
Next, the spacer oxide layer is etched in a vertical direction so as to form a sidewall spacer 20 as shown in
Keff (airgap)=[(2Y*Keff)+(X/2−2Y)]/X/2=1+4Y/X*(Keff−1)
In the above, when the thickness of the low-k layer (e.g., K=2.9 for dense CDO) is 40 nm, and the thickness of the diffusion barrier layer (e.g., K=5.0 for SiCN) is 10 nm, Keff can be calculated at 3.32. When the target pitch X is 50 nm, Keff (airgap) can be adjusted as shown in
In this disclosure, the process conditions described in relation to an embodiment can readily apply to another embodiment unless described otherwise.
The second process flow is shown in
As shown in
Next, a spacer oxide layer 39 is deposited as a sidewall spacer at a thickness of Z (e.g., Z=1 nm to 100 nm, in some embodiment Z=3 nm to 20 nm) as shown in
The spacer oxide layer is then etched in a vertical direction so as to form a sidewall spacer 39 as shown in
The liner 40 is then etched in a vertical direction so as to form a sidewall liner layer 40 as shown in
Keff (airgap)=[2Z+(K(SiCN)*(X/2−2Y−2Z)+(Keff*2Y)]/X/2=4Z/X+Keff*4Y/X+K(SiCN)(1−4Y/X−4Z/X)
In the above, when the thickness of the low-k layer (e.g., K=2.7 for CDO) is 40 nm, and the thickness of the diffusion barrier layer (e.g., K=5.0 for SiCN) is 10 nm, Keff can be calculated at 3.32. The thickness of the sidewall liner layer is 2 nm, and K(SiCN) is 5.0. When the target pitch X is 50 nm, Keff (airgap) can be adjusted as shown in
The third process flow is shown in
As shown in
After the etching for interlayer dielectric (ILD) wiring patterns of the low-k layer, a pore-sealing layer 153 is deposited at a thickness of W (e.g., W=1 nm to 10 nm, in some embodiments W=2 nm to 6 nm) to seal pores of sidewalls of the ultra low-k layer as shown in
The pore-sealing layer 153 is then etched in a vertical direction, and further the diffusion barrier layer is etched in a vertical direction as shown in
The spacer oxide layer is then etched in a vertical direction so as to form a sidewall spacer 154 as shown in
Keff (airgap)=[(K(SiCN)*(X/2−2Y−2W−2Z)+2Z+(Kps1)*W+(Keff*2Y)]/X/2=4Z/X+Keff*4Y/X+Kps1*4W/X+K(SiCN)(1−4Y/X−4W/X−4Z/X)
In the above, when the thickness of the ultra low-k layer (e.g., K=2.2 for porous CDO) is 40 nm, and the thickness of the diffusion barrier layer (e.g., K=5.0 for SiCN) is 2 nm, Keff can be calculated at 2.76. The thickness of the sidewall liner layer is 2 nm, and K(SiCN) is 5.0. The thickness of the pore-sealing layer is 2 nm, and Kps1 is 5.0. When the target pitch X is 50 nm, Keff (airgap) can be adjusted as shown in
The next three process flows relate to dual damascene schemes. These process flows basically use the same principle as described in relation to the first three process flows of single damascene schemes.
The first process flow is shown in
As shown in
A photoresist 78 is formed and subjected to patterning wherein a pitch is set at 2X as shown in
Next, a spacer oxide layer 82 is deposited as a sidewall spacer at a thickness of X/4−Y (e.g., 1 nm to 100 nm, in some embodiments 3 nm to 20 nm), followed by spacer etching in a vertical direction as shown in
The SLAM material and the diffusion barrier layer are then etched to form a via 83 as shown in
When the thickness of the low-k layer (e.g., K=2.9 for dense CDO) is 90 nm, and the thickness of the diffusion barrier layer (e.g., K=5.0 for SiCN) is 10 nm (Keff is about 3.1). When the target pitch X is 50 nm, Keff (airgap) can be adjusted as shown in
The second process flow is shown in
As shown in
Next, a spacer oxide layer 102 is deposited as a sidewall spacer at a thickness of Z (e.g., 1 nm to 100 nm, in some embodiments 3 nm to 20 nm), followed by spacer etching in a vertical direction as shown in
Next, as a protective layer, a liner layer (e.g., SiCN) 103 is deposited at a thickness of, e.g., X/4−Y−Z (e.g., 1 nm to 100 nm, in some embodiments 3 nm to 20 nm). The liner 103 is then etched in a vertical direction so as to form a sidewall liner layer 103 as shown in
When the thickness of the low-k layer (e.g., K=2.7 for CDO) is 90 nm, and the thickness of the diffusion barrier layer (e.g., K=5.0 for SiCN) is 10 nm (Keff is about 2.9). The thickness of the liner layer is 2 nm (e.g., K=5.0 for metal liner). When the target pitch X is 50 nm, Keff (airgap) can be adjusted as shown in
The third process flow is shown in
As shown in
Next, a pore-sealing layer 128 is deposited at a thickness of W (e.g., W=1 nm to 10 nm) to seal pores of sidewalls of the porous low-k layer. The pore-sealing layer 128 is then etched in a vertical direction, and a spacer oxide layer 122 is deposited as a sidewall spacer at a thickness of Z (e.g., 1 nm to 100 nm), followed by etching the same in a vertical direction as shown in
Next, as a protective layer, a liner layer (e.g., SiCN) 123 is deposited at a thickness of, e.g., X/4−Y−W−Z (e.g., 1 nm to 100 nm). The liner 123 is then etched in a vertical direction so as to form a sidewall liner layer 103 as shown in
When the thickness of the porous ultra low-k layer (trench dielectric, e.g., K=2.2 for porous CDO) is 50 nm, the dense low-k layer (via dielectric, e.g., K=2.9 for dense CDO) is 40 nm, and the thickness of the diffusion barrier layer (e.g., K=5.0 for SiCN) is 10 nm (Keff is about 2.76). The thickness of the liner layer is 2 nm (e.g., K=5.0 for metal liner). The thickness of the pore-sealing layer is 2 nm (e.g., K=5.0). When the target pitch X is 50 nm, Keff (airgap) can be adjusted as shown in
It will be understood by those of skill in the art that numerous and various modifications can be made without departing from the spirit of the present invention. Therefore, it should be clearly understood that the forms of the present invention are illustrative only and are not intended to limit the scope of the present invention.
Claims
1. A method for forming an interconnect structure with airgaps, comprising:
- forming photoresist patterns at a pitch of 2X on a hard mask, each photoresist pattern having a width of X;
- etching the hard mask between adjacent photoresist patterns, each etched portion having a width of (X−2Y);
- etching the hard mask underneath each photoresist pattern, each etched portion having a width of (X−2Y), thereby forming hard mask patterns at a pitch of X, each hard mask pattern having a width of 2Y;
- etching a layer underneath the hard mask patterns, thereby providing a structure having trenches formed on a substrate;
- depositing a spacer oxide layer on sidewalls of each trench as sidewall spacers so that the sidewall spacers-provided trenches each have a width of X/2 and are distanced at an interval of X/2;
- filling the trenches having the sidewall spacers with copper, thereby forming copper patterns at a pitch of X;
- removing the sidewall spacers to form an airgap structure; and
- encapsulating the airgap structure, wherein airgaps are formed between the copper patterns, where the copper patterns each have a width of X/2 and are distanced at an interval of X/2, and the airgaps each have a width of (X/2−2Y)/2 or less,
- wherein X and Y are selected to achieve a targeted dielectric constant of the encapsulated airgap structure between the copper patterns.
2. The method according to claim 1, wherein the spacer oxide layer is deposited by plasma enhanced atomic layer deposition (PEALD).
3. The method according to claim 1, further comprising depositing a SiCxNy-based spacer layer, wherein x and y are independently 0 or 1, on the sidewall spacers by atomic layer deposition before filling the trench, wherein airgaps are formed between the SiCxNy-based spacer layer and the sidewalls of the trench.
4. The method according to claim 3, further comprising depositing a pore-sealing layer on the sidewalls before depositing the spacer oxide layer, wherein airgaps are formed between the pore-sealing layer and the SiCxNy-based spacer layer.
5. The method according to claim 3, wherein the SiCxNy-based spacer layer on the sidewall spacers is constituted by SiCN.
6. The method according to claim 4, wherein the structure having the trench on the substrate is a layered structure comprising a diffusion barrier layer, a low-k layer, and a hard mask formed in this layering order on the substrate, wherein the trench penetrates the hard mask and the low-k layer, but does not penetrate the diffusion barrier layer, whereby the pore-sealing layer is disposed on the sidewalls of the hard mask and the low-k layer, followed by extending the trench downward to penetrate the diffusion barrier layer before depositing the spacer oxide layer.
7. The method according to claim 1, wherein the spacer oxide layer is a silicon oxide layer.
8. The method according to claim 1, wherein the structure having the trench on the substrate is a layered structure comprising a diffusion barrier layer, a low-k layer, and the hard mask formed in this layering order on the substrate, wherein the trench penetrates the hard mask, the low-k layer, and the diffusion barrier layer.
9. The method according to claim 8, wherein the step of providing the structure comprises:
- forming a photoresist pattern on the hard mask;
- trimming the photoresist to reduce the dimensions;
- depositing an oxide spacer on the trimmed photoresist and an area of the hard mask uncovered by the trimmed photoresist, by PEALD at a temperature of 400° C. or lower;
- etching the oxide spacer by a thickness of the oxide spacer in a thickness direction, thereby leaving a sidewall portion of the oxide spacer deposited on sidewalls of the trimmed photoresist, followed by removing the trimmed photoresist;
- etching an area of the hard mask exposed after the etching of the oxide spacer and the removal of the trimmed photoresist, followed by etching the sidewall portion of the oxide spacer to obtain a patterned hard mask and an exposed portion of the low-k layer; and
- etching the low-k layer and the diffusion barrier layer using the patterned hard mask.
10. The method according to claim 1, further comprising selecting a thickness of the spacer oxide layer to achieve a targeted dielectric constant of the encapsulated airgap structure between the copper filled in the trench and copper filled in an immediately adjacent trench, and the step of depositing the spacer oxide layer is controlled to obtain the spacer oxide layer at the selected thickness.
11. The method according to claim 10, wherein the thickness of the spacer oxide layer is controlled at 0.4 nm to 10 nm.
12. The method according to claim 10, wherein the targeted dielectric constant of the encapsulated airgap structure is less than 2.5.
13. A method for forming an interconnect structure with airgaps, comprising
- providing a structure having a trench formed on a substrate;
- depositing a spacer oxide layer on sidewalls of the trench as sidewall spacers;
- filling the trench having the sidewall spacers with copper;
- removing the sidewall spacers to form an airgap structure; and
- encapsulating the airgap structure, wherein airgaps are formed between the filled copper and the sidewalls of the trench,
- wherein the structure having the trench on the substrate: is a layered structure comprising a diffusion barrier layer, a low-k layer, and the hard mask formed in this layering order on the substrate, wherein the trench penetrates the hard mask, the low-k layer, and the diffusion barrier layer,
- wherein the step of providing the structure comprises:
- forming a photoresist pattern on the hard mask;
- depositing an oxide spacer on the photoresist and an area of the hard mask uncovered by the photoresist, by PEALD at a temperature of 400° C. or lower;
- etching the oxide spacer by a thickness of the oxide spacer in a thickness direction, thereby leaving a sidewall portion of the oxide spacer deposited on sidewalls of the photoresist;
- etching an area of the hard mask exposed after the etching of the oxide spacer, followed by removing the sidewall portion of the oxide spacer and the photoresist to obtain a patterned hard mask and an exposed portion of the low-k layer;
- forming a second photoresist pattern on the exposed portion of the low-k layer and a part of the patterned hard mask;
- depositing a second oxide spacer on the second photoresist and an area of the patterned hard mask uncovered by the second photoresist, by PEALD at a temperature of 400° C. or lower;
- etching the second oxide spacer by a thickness of the second spacer in a thickness direction, thereby leaving a sidewall portion of the second oxide spacer deposited on sidewalls of the second photoresist;
- etching an area of the patterned hard mask exposed after the etching of the second oxide spacer, followed by removing the sidewall portion of the second oxide spacer and the second photoresist to obtain a second patterned hard mask and an exposed portion of the low-k layer; and
- etching the low-k layer and the diffusion barrier layer using the second patterned hard mask.
5916365 | June 29, 1999 | Sherman |
6455445 | September 24, 2002 | Matsuki |
6472266 | October 29, 2002 | Yu et al. |
6652924 | November 25, 2003 | Sherman |
6876017 | April 5, 2005 | Goodner |
7098149 | August 29, 2006 | Lukas |
20080038485 | February 14, 2008 | Fukazawa |
20100001409 | January 7, 2010 | Humbert et al. |
20100015813 | January 21, 2010 | McGinnis et al. |
- IEEE International, Interconnect Technology Conference, 2009 article entitled: “A Self-aligned Airgap Interconnect Scheme,” by Hsien-Wei Chen, Shin-Puu Jeng, Hao-Yi Tsai, Yu-Wen Iiu, Hsiu-Ping Wei, Douglas CH Yu and YC Su, Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC), Hsinchu, Taiwan, R.O.C., Volume, Issue, Jun. 1-3, 2009 (pp. 146-148).
Type: Grant
Filed: Mar 5, 2010
Date of Patent: Aug 14, 2012
Patent Publication Number: 20110217838
Assignee: ASM Japan K.K. (Tama-shi, Tokyo)
Inventors: Julian J. Hsieh (Zhubei), Nobuyoshi Kobayashi (Kawagoe), Akira Shimizu (Sagamihara), Kiyohiro Matsushita (Fuchu), Atsuki Fukazawa (Tama)
Primary Examiner: Leonard Chang
Attorney: Snell & Wilmer L.L.P.
Application Number: 12/718,731
International Classification: H01L 21/76 (20060101);