Roughened Surface Patents (Class 438/964)
  • Patent number: 8951825
    Abstract: Multicrystalline silicon (mc-Si) solar cells having patterned light trapping structures (e.g., pyramid or trough features) are generated by printing a liquid mask material from an array of closely-spaced parallel elongated conduits such that portions of the mc-Si wafer are exposed through openings defined between the printed mask features. Closely spaced mask pattern features are achieved using an array of conduits (e.g., micro-springs or straight polyimide cantilevers), where each conduit includes a slit-type, tube-type or ridge/valley-type liquid guiding channel that extends between a fixed base end and a tip end of the conduit such that mask material supplied from a reservoir is precisely ejected from the tip onto the mc-Si wafer. The exposed planar surface portions are then etched to form the desired patterned light trapping structures (e.g., trough structures).
    Type: Grant
    Filed: September 10, 2013
    Date of Patent: February 10, 2015
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Scott J. H. Limb, Dirk DeBruyker, Sean Garner
  • Patent number: 8679874
    Abstract: This invention provides an optoelectronic semiconductor device having a rough surface and the manufacturing method thereof. The optoelectronic semiconductor device comprises a semiconductor stack having a rough surface and an electrode layer overlaying the semiconductor stack. The rough surface comprises a first region having a first topography and a second region having a second topography. The method comprises the steps of forming a semiconductor stack on a substrate, forming an electrode layer on the semiconductor stack, thermal treating the semiconductor stack, and wet etching the surface of the semiconductor stack to form a rough surface.
    Type: Grant
    Filed: August 28, 2012
    Date of Patent: March 25, 2014
    Assignee: Epistar Corporation
    Inventors: Chiu-Lin Yao, Ta-Cheng Hsu
  • Patent number: 8637897
    Abstract: A semiconductor light emitting device includes a substrate and a plurality of light emitting cells arranged on the substrate. Each of the light emitting cells includes a first-conductivity-type semiconductor layer, a second-conductivity-type semiconductor layer, and an active layer disposed therebetween to emit blue light. An interconnection structure electrically connects the first-conductivity-type and the second-conductivity-type semiconductor layers of one light emitting cell to the first-conductivity-type and the second-conductivity-type semiconductor layers of another light emitting cell. A light conversion part is formed in a light emitting region defined by the light emitting cells and includes a red and/or a green light conversion part respectively having a red and/or a green light conversion material.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: January 28, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Je Won Kim, Tae Sung Jang, Jong Gun Woo, Jong Ho Lee
  • Patent number: 8637876
    Abstract: Disclosed are a light emitting device and a light emitting device package having the same. The light emitting device includes a plurality of light emitting cells including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer; a first electrode layer connected to the first conductive semiconductor layer of a first light emitting cell of the plural light emitting cells; a plurality of second electrode layers under the light emitting cells, a portion of the second electrode layers being connected to the first conductive semiconductor layer of an adjacent light emitting cells; a third electrode layer disposed under a last light emitting cell of the plural light emitting cells; a first electrode connected to the first electrode layer; a second electrode connected to the third electrode layer; an insulating layer around the first to third electrode layers; and a support member under the insulating layer.
    Type: Grant
    Filed: August 30, 2010
    Date of Patent: January 28, 2014
    Assignee: LG Innotek Co., Ltd.
    Inventors: Sang Youl Lee, Jung Hyeok Bae, Ji Hyung Moon, Juno Song
  • Patent number: 8598619
    Abstract: A semiconductor light emitting device includes a substrate and a plurality of light emitting cells arranged on the substrate. Each of the light emitting cells includes a first-conductivity-type semiconductor layer, a second-conductivity-type semiconductor layer, and an active layer disposed therebetween to emit blue light. An interconnection structure electrically connects the first-conductivity-type and the second-conductivity-type semiconductor layers of one light emitting cell to the first-conductivity-type and the second-conductivity-type semiconductor layers of another light emitting cell. A light conversion part is formed in a light emitting region defined by the light emitting cells and includes a red and/or a green light conversion part respectively having a red and/or a green light conversion material.
    Type: Grant
    Filed: February 24, 2011
    Date of Patent: December 3, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Je Won Kim, Tae Sung Jang, Jong Gun Woo, Jong Ho Lee
  • Patent number: 8551869
    Abstract: A method for roughening an epitaxy structure layer, including: providing an epitaxy structure layer; and etching a surface of the epitaxy structure layer by an excimer laser having an energy density of 1000 mJ/cm2 or less to form a roughened surface. In addition, a method for manufacturing a light-emitting diode having a roughened surface is provided.
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: October 8, 2013
    Assignee: National Cheng Kung University
    Inventors: Shui-Jinn Wang, Wei-Chi Lee
  • Patent number: 8420436
    Abstract: A solar cell manufacturing method according to the present invention is a solar cell manufacturing method that forms a transparent conductive film of ZnO as an electric power extracting electrode on a light incident side, the method comprises at least in a following order: a process A forming the transparent conductive film on a substrate by applying a sputtering voltage to sputter a target made of a film formation material for the transparent conductive film; a process B forming a texture on a surface of the transparent conductive film; a process C cleaning the surface of the transparent conductive film on which the texture has been formed using an UV/ozone; and a process D forming an electric power generation layer on the transparent conductive film.
    Type: Grant
    Filed: October 27, 2009
    Date of Patent: April 16, 2013
    Assignee: ULVAC, Inc.
    Inventors: Hirohisa Takahashi, Satoru Ishibashi, Sadayuki Ukishima, Masahide Matsubara, Satoshi Okabe
  • Patent number: 8367446
    Abstract: A method for preparing patterned substrate by using nano- or micro-particles is disclosed, which comprises the following steps: (A) providing a substrate with a photoresist layer formed thereon; (B) coating a surface of the photoresist layer with plural nano- or micro-particles, to form a particle layer; (C) exposing and developing the photoresist layer to obtain a patterned photoresist layer; and (D) removing the particle layer. In addition, after the particle layer is removed, the method of the present invention further comprises: (E1) using the patterned photoresist layer as an etching template to etch the substrate; and (E2) removing the patterned photoresist layer to obtain a patterned substrate with plural cavities formed thereon.
    Type: Grant
    Filed: May 18, 2010
    Date of Patent: February 5, 2013
    Assignee: National Central University
    Inventors: Chia-Hua Chan, Chia-Hung Hou, Tsing-Jen Chen, Chii-Chang Chen
  • Patent number: 8334153
    Abstract: A semiconductor light emitting device has a light emitting element, a first electrode layer, a second electrode layer, a seed electrode layer and a plated layer. The light emitting element has a nitride-based III-V compound semiconductor on a substrate. The light emitting element having a light extraction surface. The first electrode layer on the light extraction surface. The second electrode layer is provided on a surface opposite to the light extraction surface of the light emitting element. The seed electrode layer is configured to cover the entire surface of the second electrode layer. The plated layer is provided on the seed electrode layer. The light emitting element has a light emitting layer, a first conductive type semiconductor layer, and a second conductive type semiconductor layer.
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: December 18, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toru Gotoda, Toshiyuki Oka, Shinya Nunoue, Kotaro Zaima
  • Patent number: 8278672
    Abstract: A semiconductor light-emitting device is disclosed. The semiconductor light-emitting device comprises a multilayer epitaxial structure disposed on a semiconductor substrate. The semiconductor substrate has a predetermined lattice direction perpendicular to an upper surface thereof, wherein the predetermined lattice direction is angled toward [0 11] or [01 1] from [100], or toward [011] or [0 11] from [ 100] so that the upper surface of the semiconductor substrate comprises at least two lattice planes with different lattice plane directions. The multilayer epitaxial structure has a roughened upper surface perpendicular to the predetermined lattice direction. The invention also discloses a method for fabricating a semiconductor light-emitting device.
    Type: Grant
    Filed: March 26, 2007
    Date of Patent: October 2, 2012
    Assignee: Epistar Corporation
    Inventors: Ya-Ju Lee, Ta-Cheng Hsu, Ming-Ta Chin, Yen-Wen Chen, Wu-Tsung Lo, Chung-Yuan Li, Min-Hsun Hsieh
  • Patent number: 8153353
    Abstract: A method and a material for creating an antireflective coating on an integrated circuit. A preferred embodiment comprises applying a dark polymer material on a reflective surface, curing the dark polymer material, and roughening a top surface of the dark polymer material. The roughening can be achieved by ashing the dark polymer material in an ash chamber. The dark polymer material, preferably a black matrix resin or a polyimide black matrix resin, when ashed in an oxygen rich atmosphere for a short period of time, forms a surface that is capable of absorbing light as well as randomly refracting light it does not absorb. A protective cap layer may be formed on top of the ashed dark polymer material to provide protection for the dark polymer material.
    Type: Grant
    Filed: October 8, 2009
    Date of Patent: April 10, 2012
    Assignee: Texas Instruments Incorporated
    Inventor: Jason Michael Neidrich
  • Patent number: 8080474
    Abstract: The present invention provides a method for making an electrode. Firstly, a conducting substrate is provided. Secondly, a plurality of nano-sized structures is formed on the conducting substrate by a nano-imprinting method. Thirdly, a coating is formed on the nano-sized structures. The nano-sized structures are configured for increasing specific surface area of the electrode.
    Type: Grant
    Filed: June 1, 2009
    Date of Patent: December 20, 2011
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventor: Ga-Lane Chen
  • Patent number: 8021945
    Abstract: In accordance with an aspect of the invention, a method is provided for fabricating a semiconductor chip including a trench capacitor. In such method, a monocrystalline semiconductor region can be etched in a vertical direction through an opening in a dielectric layer to form a trench exposing a rough surface of monocrystalline semiconductor material. The trench has an initial lateral dimension in a first direction transverse to the vertical direction. The semiconductor material exposed at the surface of the trench then is etched in a crystallographic orientation-dependent manner to expose a multiplicity of crystal facets of the semiconductor material at the trench surface. A dopant-containing liner may then be deposited to line the surface of the trench and a temperature of the substrate then be elevated to drive a dopant from the dopant-containing liner into the semiconductor region adjacent to the surface. During such step, typically a portion of the semiconductor material exposed at the wall is oxidized.
    Type: Grant
    Filed: April 14, 2009
    Date of Patent: September 20, 2011
    Assignee: International Business Machines Corporation
    Inventors: Xi Li, Russell H. Arndt, Kangguo Cheng, Richard O. Henry, Jinghong H. Li
  • Patent number: 7985683
    Abstract: A method of treating a semiconductor substrate has forming convex patterns over the semiconductor substrate by dry etching, cleaning and modifying a surface of the convex patterns by using chemical, forming a hydrophobic functional surface on the modified surface of the convex patterns, after forming the hydrophobic functional surface, rinsing the semiconductor substrate by using water, drying the semiconductor substrate, and removing the hydrophobic functional group from the hydrophobic functional surface of the convex patterns.
    Type: Grant
    Filed: May 26, 2010
    Date of Patent: July 26, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Tomita, Tatsuhiko Koide, Hisashi Okuchi, Kentaro Shimayama, Hiroyasu Iimori, Linan Ji
  • Patent number: 7972883
    Abstract: In a method of manufacturing a photoelectric device, a transparent conductive layer is formed on a substrate, and the transparent conductive layer is partially etched using an etching solution including hydrofluoric acid. Thus, a transparent electrode having a concavo-convex pattern on its surface is formed. When the transparent conductive layer is partially etched, a haze of the transparent electrode may be controlled by adjusting an etching time of the transparent conductive layer. Also, since the etching solution is sprayed to the transparent conductive layer to etch the transparent conductive layer, the concavo-convex pattern on the surface of the transparent electrode may be easily formed even though the size of the substrate increases.
    Type: Grant
    Filed: March 9, 2009
    Date of Patent: July 5, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Jae Jung, Byoung-June Kim, Jin-Seock Kim, Czang-Ho Lee, Myung-Hun Shin, Joon-Young Seo, Dong-Uk Choi, Byoung-Kyu Lee
  • Patent number: 7973332
    Abstract: An LED lamp includes a board, a metal wiring provided on the board, an LED mounted on the metal wiring, and a metal heat dissipation film mainly made of a metal different from a metal for forming the metal wiring. The metal heat dissipation film partially overlaps the metal wiring. The metal heat dissipation film has an irregular surface. The metal heat dissipation film is mainly made of a metal that is softer than the metal wiring. The metal heat dissipation film intervenes between the board and the metal wiring, and part of the metal heat dissipation film that is in contact with the metal wiring has an irregular surface.
    Type: Grant
    Filed: May 26, 2009
    Date of Patent: July 5, 2011
    Assignee: Rohm Co., Ltd.
    Inventor: Hiroyuki Fukui
  • Patent number: 7868338
    Abstract: A liquid crystal display array board includes a plurality of gate wiring lines formed on a substrate and a plurality of data wiring lines crossing the plurality of gate wiring lines, a plurality of thin film transistors formed in areas defined by crossings of the gate wiring lines and the data wiring lines, a plurality of storage capacitor first electrodes that run parallel to the gate wiring lines and patterned to have concavo-convex patterns, a plurality of storage capacitor second electrodes integrated with the drain electrodes of the thin film transistors and formed on the storage capacitor first electrodes, and a plurality of pixel electrodes electrically connected to the drain electrodes.
    Type: Grant
    Filed: September 12, 2006
    Date of Patent: January 11, 2011
    Assignee: Samsung Mobile Display Co., Ltd.
    Inventors: Do Young Kim, Hae Jin Heo
  • Patent number: 7863199
    Abstract: The invention includes methods of forming particle-containing materials, and also includes semiconductor constructions comprising particle-containing materials. One aspect of the invention includes a method in which a first monolayer is formed across at least a portion of a semiconductor substrate, particles are adhered to the first monolayer, and a second monolayer is formed over the particles. Another aspect of the invention includes a construction containing a semiconductor substrate and a particle-impregnated conductive material over at least a portion of the semiconductor substrate. The particle-impregnated conductive material can include tungsten-containing particles within a layer which includes tantalum or tungsten.
    Type: Grant
    Filed: October 29, 2009
    Date of Patent: January 4, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Garo J. Derderian, Gurtej S. Sandhu
  • Patent number: 7825438
    Abstract: A CMOS image sensor cell includes a semiconductor active region of first conductivity type having a surface thereon and a P-N junction photodiode in the active region. A drive transistor is also provided in the semiconductor active region. The drive transistor has a gate electrode that is configured to receive charge generated in the P-N junction photodiode during an image capture operation (i.e., during capture of photons received from an image). This drive transistor has a gate electrode and a contoured channel region extending underneath the gate electrode. The contoured channel region has an effective channel length greater than a length of the gate electrode.
    Type: Grant
    Filed: August 9, 2006
    Date of Patent: November 2, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-wan Jung, Duck-hyung Lee
  • Patent number: 7812450
    Abstract: The present invention relates to an electrode 100 with high capacitance. The electrode includes a conducting substrate 10 with a number of nano-sized structures 13 thereon and a coating 15. The nano-sized structures are concave-shaped and are of a size in the range from 2 nanometers to 50 nanometers. The nano-sized structures are configured for increasing specific surface area of the electrode. The present invention also provides a method for making the above-described electrode. The method includes steps of providing a conducting substrate, forming a number of nano-sized structures on the conducting substrate, and forming a coating on the nano-sized structures.
    Type: Grant
    Filed: March 28, 2006
    Date of Patent: October 12, 2010
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventor: Ga-Lane Chen
  • Patent number: 7749782
    Abstract: An improved method of forming a LED with a roughened surface is described. Traditional methods of roughening a LED surface utilizes strong etchants that require sealing or protecting exposed areas of the LED. The described method uses a focused laser to separate the LED from the substrate, and a second laser to roughen the LED surface thereby avoiding the use of strong etchants. A mild etchant may be used on the laser roughened LED surface to remove unwanted metals.
    Type: Grant
    Filed: December 17, 2008
    Date of Patent: July 6, 2010
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Clifford F Knollenberg, David P Bour, Christopher L Chua, Jeng Ping Lu
  • Patent number: 7749870
    Abstract: Provided is a method for producing an SOI substrate comprising a transparent insulating substrate and a silicon film formed on a first major surface of the insulating substrate wherein a second major surface of the insulating substrate which is opposite to the major surface is roughened, the method suppressing the generation of metal impurities and particles in a simple and easy way.
    Type: Grant
    Filed: March 27, 2009
    Date of Patent: July 6, 2010
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Makoto Kawai, Yoshihiro Kubota, Atsuo Ito, Kouichi Tanaka, Yuji Tobisaka, Shoji Akiyama, Hiroshi Tamura
  • Patent number: 7749909
    Abstract: A method of treating a semiconductor substrate has forming convex patterns over the semiconductor substrate by dry etching, cleaning and modifying a surface of the convex patterns by using chemical, forming a hydrophobic functional surface on the modified surface of the convex patterns, after forming the hydrophobic functional surface, rinsing the semiconductor substrate by using water, drying the semiconductor substrate, and removing the hydrophobic functional group from the hydrophobic functional surface of the convex patterns.
    Type: Grant
    Filed: October 6, 2009
    Date of Patent: July 6, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Tomita, Tatsuhiko Koide, Hisashi Okuchi, Kentaro Shimayama, Hiroyasu Iimori, Linan Ji
  • Patent number: 7727888
    Abstract: An interconnect structure and a method for forming the same are described. Specifically, under the present invention, a gouge is created within a via formed in the interconnect structure before any trenches are formed. This prevents the above-mentioned trench damage from occurring. That is, the bottom surface of the trenches will have a roughness of less than approximately 20 nm, and preferably less than approximately 10 nm. In addition to the via, gouge and trench(es), the interconnect structure of the present invention includes at least two levels of metal wiring. Further, in a typical embodiment, the interconnect structure utilizes any dielectrics having a dielectric constant no greater than approximately 5.0.
    Type: Grant
    Filed: August 31, 2005
    Date of Patent: June 1, 2010
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Louis C. Hsu, Rajiv V. Joshi
  • Patent number: 7687225
    Abstract: Systems and techniques involving optical coatings for semiconductor devices. An implementation includes a substantially isotropic, heterogeneous anti-reflective coating having a substantially equal thickness normal to any portion of a substrate independent of the orientation of the portion.
    Type: Grant
    Filed: September 29, 2004
    Date of Patent: March 30, 2010
    Assignee: Intel Corporation
    Inventors: Sergei V. Koveshnikov, Juan E. Dominguez, Kyle Y. Flanigan, Ernisse Putna
  • Patent number: 7687294
    Abstract: The present invention provides a nitride semiconductor device. The nitride semiconductor device comprises an n-type nitride semiconductor layer formed on a nitride crystal growth substrate. An active layer is formed on the n-type nitride semiconductor layer. A first p-type nitride semiconductor layer is formed on the active layer. A micro-structured current diffusion pattern is formed on the first p-type nitride semiconductor layer. The current diffusion pattern is made of an insulation material. A second p-type nitride semiconductor layer is formed on the first p-type nitride semiconductor layer having the current diffusion pattern formed thereon.
    Type: Grant
    Filed: March 5, 2007
    Date of Patent: March 30, 2010
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Je Won Kim, Sun Woon Kim, Dong Joon Kim
  • Patent number: 7629204
    Abstract: A surface roughening method for an embedded semiconductor chip structure is proposed. The method includes providing a carrier board with an opening and mounting a semiconductor chip in the opening of the carrier board, the semiconductor chip having a plurality of electrode pads; and performing a surface roughening process on a surface of the electrode pads of the semiconductor chip, so as to form a rough structure on a surface of the semiconductor chip exposed by the opening of the carrier board. Thus, adhesion between the chip and a dielectric layer is improved during subsequently forming circuit build-up layers on the roughened surface of the semiconductor chip and on the surface of carrier board.
    Type: Grant
    Filed: May 12, 2006
    Date of Patent: December 8, 2009
    Assignee: Phoenix Precision Technology Corporation
    Inventor: Shih-Ping Hsu
  • Patent number: 7629024
    Abstract: The invention includes methods of forming particle-containing materials, and also includes semiconductor constructions comprising particle-containing materials. One aspect of the invention includes a method in which a first monolayer is formed across at least a portion of a semiconductor substrate, particles are adhered to the first monolayer, and a second monolayer is formed over the particles. Another aspect of the invention includes a construction containing a semiconductor substrate and a particle-impregnated conductive material over at least a portion of the semiconductor substrate. The particle-impregnated conductive material can include tungsten-containing particles within a layer which includes tantalum or tungsten.
    Type: Grant
    Filed: July 13, 2006
    Date of Patent: December 8, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Garo J. Derderian, Gurtej S. Sandhu
  • Patent number: 7579205
    Abstract: A light emitting device wafer having a light emitting layer section 24 having an AlGaInP-base double heterostructure, and a GaP light extraction layer 20 disposed on the light emitting layer section so as to allow a first main surface thereof to compose a first main surface of the wafer is fabricated so that the first main surface of the GaP light extraction layer appears as the (100) surface. The first main surface of the GaP light extraction layer 20 composed of the (100) surface is etched using an etching solution for surface roughening to thereby form surface roughening projections 40f. Accordingly, there can be provided a method of fabricating a light emitting device having the GaP light extraction layer agreed with the (100) main surface, capable of readily subjecting the (100) main surface to surface roughening.
    Type: Grant
    Filed: April 13, 2005
    Date of Patent: August 25, 2009
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Hitoshi Ikeda, Kingo Suzuki, Akio Nakamura
  • Patent number: 7575978
    Abstract: Isolated conductive nanoparticles on a dielectric layer and methods of fabricating such isolated conductive nanoparticles provide charge storage units in electronic structures for use in a wide range of electronic devices and systems. The isolated conductive nanoparticles may be used as a floating gate in a flash memory. In an embodiment, conductive nanoparticles are deposited on a dielectric layer by a plasma-assisted deposition process such that each conductive nanoparticle is isolated from the other conductive nanoparticles to configure the conductive nanoparticles as charge storage elements.
    Type: Grant
    Filed: August 4, 2005
    Date of Patent: August 18, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Brenda D Kraus, Eugene P. Marsh
  • Patent number: 7560351
    Abstract: An integrated circuit arrangement and fabrication method is presented. The integrated circuit arrangement contains a semiconductor and a metal electrode. The contact area between a semiconductor and the electrode is increased without increasing the lateral dimensions using partial regions of the semiconductor and/or of the electrode that extend through a transition layer between the semiconductor and electrode.
    Type: Grant
    Filed: January 3, 2006
    Date of Patent: July 14, 2009
    Assignee: Infineon Technologies AG
    Inventors: Franz Hofmann, Richard Johannes Luyken, Wolfgang Roesner, Michael Specht
  • Patent number: 7501332
    Abstract: A doping method includes implanting first impurity ions into a semiconductor substrate, so as to form a damaged region in the vicinity of a surface of the semiconductor substrate, the first impurity ions not contributing to electric conductivity; implanting second impurity ions into the semiconductor substrate through the damaged region, the second impurity ions having an atomic weight larger than the first impurity ions and contributing to the electric conductivity; and heating the surface of the semiconductor substrate with a light having a pulse width of about 0.1 ms to about 100 ms, so as to activate the second impurity ions.
    Type: Grant
    Filed: April 4, 2005
    Date of Patent: March 10, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takayuki Ito, Kyoichi Suguro
  • Patent number: 7414297
    Abstract: The invention includes methods of forming rugged electrically conductive surfaces. In one method, a layer is formed across a substrate and subsequently at least partially dissociated to form gaps extending to the substrate. An electrically conductive surface is formed to extend across the at least partially dissociated layer and within the gaps. The electrically conductive surface has a rugged topography imparted by the at least partially dissociated layer and the gaps. The topographically rugged surface can be incorporated into capacitor constructions. The capacitor constructions can be incorporated into DRAM cells, and such DRAM cells can be incorporated into electrical systems.
    Type: Grant
    Filed: September 21, 2007
    Date of Patent: August 19, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Marsela Pontoh, Cem Basceri, Thomas M. Graettinger
  • Patent number: 7338855
    Abstract: A method for fabricating a semiconductor device is provided, wherein a large MIM capacitor including an uneven surface if formed to increase capacitance. The method includes forming a polysilicon layer on a lower metal layer by plasma-enhanced chemical vapor deposition; forming an uneven surface in the polysilicon layer by etching the polysilicon layer with an isotropic etchant; forming an upper metal layer on the polysilicon layer; sequentially etching the upper metal layer and the polysilicon layer; and performing chemical-mechanical polishing after completing a gap-fill process on the upper metal layer.
    Type: Grant
    Filed: December 21, 2005
    Date of Patent: March 4, 2008
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Jae Suk Lee
  • Patent number: 7274059
    Abstract: The invention includes methods of forming rugged electrically conductive surfaces. In one method, a layer is formed across a substrate and subsequently at least partially dissociated to form gaps extending to the substrate. An electrically conductive surface is formed to extend across the at least partially dissociated layer and within the gaps. The electrically conductive surface has a rugged topography imparted by the at least partially dissociated layer and the gaps. The topographically rugged surface can be incorporated into capacitor constructions. The capacitor constructions can be incorporated into DRAM cells, and such DRAM cells can be incorporated into electrical systems.
    Type: Grant
    Filed: July 12, 2006
    Date of Patent: September 25, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Marsela Pontoh, Cem Basceri, Thomas M. Graettinger
  • Patent number: 7253104
    Abstract: The invention includes methods of forming particle-containing materials, and also includes semiconductor constructions comprising particle-containing materials. One aspect of the invention includes a method in which a first monolayer is formed across at least a portion of a semiconductor substrate, particles are adhered to the first monolayer, and a second monolayer is formed over the particles. Another aspect of the invention includes a construction containing a semiconductor substrate and a particle-impregnated conductive material over at least a portion of the semiconductor substrate. The particle-impregnated conductive material can include tungsten-containing particles within a layer which includes tantalum or tungsten.
    Type: Grant
    Filed: December 1, 2003
    Date of Patent: August 7, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Garo J. Derderian, Gurtej S. Sandhu
  • Patent number: 7169620
    Abstract: According to one aspect of the invention, a method of constructing a memory array is provided. An insulating layer is formed on a semiconductor wafer. A first metal stack is then formed on the insulating layer and etched to form first metal lines. A polymeric layer is formed over the first metal lines and the insulating layer. A puddle of smoothing solvent is then allowed to stand on the wafer. The smoothing solvent is then removed. After the smoothing solvent is removed, the polymeric layer has a reduced surface roughness. A second metal stack is then formed on the polymeric layer and etched to form second metal lines.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: January 30, 2007
    Assignee: Intel Corporation
    Inventors: Michael J. Leeson, Ebrahim Andideh
  • Patent number: 7160744
    Abstract: The present invention relates to a fabrication method of LEDs incorporating a step of surface-treating a substrate by a laser and an LED fabricated by such a fabrication method. The present invention can use a laser in order to implement finer surface treatment to an LED substrate over the prior art. As a result, the invention can improve the light extraction efficiency of an LED while protecting the substrate from chronic problems of the prior art such as stress or defects induced from chemical etching and/or physical polishing.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: January 9, 2007
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Young Ho Park, Hun Joo Hahm, Kun Yoo Ko, Hyo Kyong Cho
  • Patent number: 7112503
    Abstract: A capacitor fabrication method may include atomic layer depositing a conductive barrier layer to oxygen diffusion over the first electrode. A method may instead include chemisorbing a layer of a first precursor at least one monolayer thick over the first electrode and chemisorbing a layer of a second precursor at least one monolayer thick on the first precursor layer, a chemisorption product of the first and second precursor layers being comprised by a layer of a conductive barrier material. The barrier layer may be sufficiently thick and dense to reduce oxidation of the first electrode by oxygen diffusion from over the barrier layer. An alternative method may include forming a first capacitor electrode over a substrate, the first electrode having an inner surface area per unit area and an outer surface area per unit area that are both greater than an outer surface area per unit area of the substrate. A capacitor dielectric layer and a second capacitor electrode may be formed over the dielectric layer.
    Type: Grant
    Filed: August 31, 2000
    Date of Patent: September 26, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Vishnu K. Agarwal, Garry A. Mercaldi
  • Patent number: 7081384
    Abstract: The present invention refers to a method of forming a silicon dioxide layer by thermally oxidizing at least one monocrystalline silicon surface region on a semiconductor substrate. The silicon surface region has a curved surface. The method can include providing a semiconductor substrate having at least one monocrystalline silicon surface region having a curved surface, roughening the surface of the at least one monocrystalline silicon surface region to produce a layer of porous silicon, and thermally oxidizing the at least one roughened monocrystalline silicon surface.
    Type: Grant
    Filed: April 14, 2004
    Date of Patent: July 25, 2006
    Assignee: Infineon Technologies, AG
    Inventors: Albert Birner, Matthias Goldbach, Irene Sperl
  • Patent number: 7071508
    Abstract: The invention includes a method of forming a semiconductor construction. A semiconductor substrate is provided, and a conductive node is formed to be supported by the semiconductor substrate. A first conductive material is formed over the conductive node and shaped as a container. The container has an opening extending therein and an upper surface proximate the opening. The container opening is at least partially filled with an insulative material. A second conductive material is formed over the at least partially filled container opening and physically against the upper surface of the container. The invention also includes semiconductor structures.
    Type: Grant
    Filed: March 13, 2003
    Date of Patent: July 4, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Cem Basceri, Garo J. Derderian
  • Patent number: 7071129
    Abstract: Adhesion between silicon nitride etch-stop layers and carbon doped oxide films may be improved by using plasma argon densification treatments of the carbon doped oxide films. The resulting surface layer of the carbon doped oxide films may be carbon-depleted and may include a relatively rough interface to improve the adhesion of deposited silicon nitride films.
    Type: Grant
    Filed: September 12, 2002
    Date of Patent: July 4, 2006
    Assignee: Intel Corporation
    Inventors: Chia-Hong Jan, Tracey Scherban, Ying Zhou, Adam Schafer, Brett Robert Schroeder
  • Patent number: 7060615
    Abstract: A method of forming a roughened layer of platinum, including: a) providing a substrate within a reaction chamber; b) forming an adhesion layer over the substrate; c) flowing an oxidizing gas into the reaction chamber; d) flowing a platinum precursor into the reaction chamber and depositing platinum from the platinum precursor onto the adhesion layer in the presence of the oxidizing gas; and e) maintaining a temperature within the reaction chamber at from about 0° C. to less than 300° C. during the depositing.
    Type: Grant
    Filed: December 17, 2003
    Date of Patent: June 13, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Eugene P. Marsh
  • Patent number: 6949427
    Abstract: The invention includes a method of forming a capacitor electrode. A sacrificial material sidewall is provided to extend at least partially around an opening. A first silicon-containing material is formed within the opening to partially fill the opening, and is doped with conductivity-enhancing dopant. A second silicon-containing material is formed within the partially filled opening, and is provided to be less heavily doped with conductivity-enhancing dopant than is the first silicon-containing material. At least some of the second silicon-containing material is converted into hemispherical grain silicon, and at least some of the sacrificial material sidewall is removed. The invention also encompasses methods of forming capacitors and capacitor assemblies incorporating the above-described capacitor electrode. Further, the invention encompasses capacitor assemblies and capacitor structures.
    Type: Grant
    Filed: February 13, 2002
    Date of Patent: September 27, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Shenlin Chen, Er-Xuan Ping
  • Patent number: 6943089
    Abstract: A hemispherical grain (HSG) formation process for enlarging the surface area of a capacitor electrode, wherein stable, defect-free HSG, having outstanding selectivity, is formed. An amorphous silicon layer, which constitutes a capacitor electrode, is formed on an Si wafer, on which is formed a silicon-based dielectric layer, which constitutes an interlevel dielectric layer. An HSG layer, in which there exists practically no defects, is formed on the amorphous silicon layer at a crystal nuclei formation temperature of under 620° C. Further, in accordance with properly controlling the crystal nuclei formation temperature, and the flow rate of monosilane (SiH4), which is supplied for crystal nuclei formation, it is possible to furnish selectivity such that HSG nuclei are formed solely on the amorphous silicon layer, without being formed on a silicon-based dielectric layer.
    Type: Grant
    Filed: October 24, 2001
    Date of Patent: September 13, 2005
    Assignee: Kokusai Electric Co., Ltd.
    Inventors: Yushin Takasawa, Hajime Karasawa
  • Patent number: 6916723
    Abstract: The invention includes a method of forming a rugged semiconductor-containing surface. A first semiconductor layer is formed over a substrate, and a second semiconductor layer is formed over the first semiconductor layer. Subsequently, a third semiconductor layer is formed over the second semiconductor layer, and semiconductor-containing seeds are formed over the third semiconductor layer. The seeds are annealed to form the rugged semiconductor-containing surface. The first, second and third semiconductor layers are part of a common stack, and can be together utilized within a storage node of a capacitor construction. The invention also includes semiconductor structures comprising rugged surfaces. The rugged surfaces can be, for example, rugged silicon.
    Type: Grant
    Filed: April 25, 2003
    Date of Patent: July 12, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Shenlin Chen, Trung Tri Doan, Guy T. Blalock, Lyle D. Breiner, Er-Xuan Ping
  • Patent number: 6905984
    Abstract: The present invention is directed to a method for clamping and processing a semiconductor substrate using a semiconductor processing apparatus. According to one aspect of the present invention, a multi-polar electrostatic chuck and associated method is disclosed which provides heating or cooling of a substrate by thermal contact conduction between the electrostatic chuck and the substrate. The multi-polar electrostatic chuck includes a semiconductor platform having a plurality of protrusions that define gaps therebetween, wherein a surface roughness of the plurality of protrusions is less than 100 Angstroms. The electrostatic chuck further includes a voltage control system operable to control a voltage applied to the electrostatic chuck to thus control a contact heat transfer coefficient of the electrostatic chuck, wherein the heat transfer coefficient of the electrostatic chuck is primarily a function of a contact pressure between the substrate and the plurality of protrusions.
    Type: Grant
    Filed: October 10, 2003
    Date of Patent: June 14, 2005
    Assignee: Axcelis Technologies, Inc.
    Inventors: Peter L. Kellerman, Shu Qin, Ernie Allen, Douglas A. Brown
  • Patent number: 6887755
    Abstract: The invention encompasses a method of forming a rugged silicone-containing surface. A layer comprising amorphous silicon is provided within a reaction chamber at a first temperature. The temperature is increased to a second temperature at least 40° C. higher than the first temperature while flowing at least one hydrogen isotope into the chamber. After the temperature reaches the second temperature, the layer is seeded with seed crystals. The seeded layer is then annealed to form a rugged silicon-containing surface. The rugged silicon-containing surface can be incorporated into a capacitor construction. The capacitor construction can be incorporated into a DRAM cell, and the DRAM cell can be utilized in an electronic system.
    Type: Grant
    Filed: September 5, 2003
    Date of Patent: May 3, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Guy T. Blalock, Lyle D. Breiner
  • Patent number: 6884691
    Abstract: The invention includes methods of forming a substrate having a surface comprising at least one of Pt, Pd, Co and Au in at least one of elemental and alloy forms. In one implementation, a substrate is provided which has a first substrate surface comprising at least one of Pt, Pd, Co and Au in at least one of elemental and alloy forms. The first substrate surface has a first degree of roughness. Within a chamber, the first substrate surface is exposed to a PF3 comprising atmosphere under conditions effective to form a second substrate surface comprising at least one of Pt, Pd, Co and Au in at least one of elemental and alloy forms which has a second degree of roughness which is greater than the first degree of roughness. The substrate having the second substrate surface with the second degree of roughness is ultimately removed from the chamber.
    Type: Grant
    Filed: March 18, 2003
    Date of Patent: April 26, 2005
    Assignee: Micron Technology, Inc.
    Inventor: Eugene P. Marsh
  • Patent number: 6864138
    Abstract: The invention encompasses DRAM constructions, capacitor constructions, integrated circuitry, and methods of forming DRAM constructions, integrated circuitry and capacitor constructions. The invention encompasses a method of forming a capacitor wherein: a) a first layer is formed; b) a semiconductive material masking layer is formed over the first layer; c) an opening is etched through the masking layer and first layer to a node; d) a storage node layer is formed within the opening and in electrical connection with the masking layer; e) a capacitor storage node is formed from the masking layer and the storage node layer; and f) a capacitor dielectric layer and outer capacitor plate are formed operatively proximate the capacitor storage node.
    Type: Grant
    Filed: December 4, 2002
    Date of Patent: March 8, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Kunal R. Parekh, John K. Zahurak