Abstract: A method of making a semiconductor device includes forming a semiconductor substrate having an undulated surface, a gate insulating layer on the semiconductor substrate, a gate electrode on the gate insulating layer, and a source/drain impurity diffusion region in the substrate. The method of fabricating the semiconductor device includes the steps of forming an undulated surface on the substrate by using HSG (hemispherical grain), forming a gate insulating layer on the substrate, forming a gate electrode on the gate insulating layer, and forming an impurity region in the substrate.

Abstract: Trench cells with increased storage capacity are prepared with roughened sidewalls using a layer of grainy polysilicon or hemispherical grain polysilicon. The top collar region of the trench is protected with oxide while the lower portion of the trench coated with polysilicon or hemispherical grain polysilicon is etched isotropically. The trench structure created has roughened sidewalls for increased volume of storage.

Abstract: A field oxide region is formed with a reduced bird's beak by selectively implanting impurity atoms into the semiconductor substrate to increase the oxidation rate of the substrate and thermally oxidizing the implanted region of the semiconductor substrate. In another embodiment, a gate oxide layer having a differential thickness is formed by implanting impurity atoms into the semiconductor substrate in a selected region wherein a thick portion of the gate oxide is to be formed and thermally oxidizing the semiconductor substrate.

Abstract: A semiconductor processing method of providing a polysilicon film having induced outer surface roughness includes, a) providing a substrate within a chemical vapor deposition reactor; b) chemical vapor depositing an in situ conductively doped amorphous silicon layer over the substrate within the reactor at a first temperature, the first temperature being below 600.degree. C., the doped amorphous silicon layer having an outer surface of a first degree of roughness; c) within the chemical vapor deposition reactor and after depositing the doped amorphous silicon layer, raising the substrate temperature at a selected rate to an annealing second temperature, the annealing second temperature being from 550.degree. C. to 950.degree. C.

Abstract: A method for fabricating a semiconductor wafer to reduce the number of processing steps and produce low-cost wafers in a short time is disclosed. The method involves surface grinding both the front surface and back surface of a single-crystal silicon wafer which has been sliced from a rod and chamfered. In the surface grinding step, the size numbers of abrasive grains are larger than #2000 for front surface grinding, and smaller than #600 for back surface grinding. The front surface is then chemical polished as a mirror surface which satisfies the requirement of a later photolithography step. Moreover, a deformation layer formed on the back surface of the semiconductor wafer is partially etched and left to provide an extrinsic gettering function. An epitaxial layer can be formed on the front surface to make the wafer an epitaxial wafer. The method of the present invention requires fewer process steps as compared with conventional methods, thereby reducing manufacturing time and cost.

Abstract: Disclosed is an improved stacked capacitor with rounded corners for increasing capacitor breakdown voltage, and a method of constructing the same. The preferred method comprises rounding corners of a container-shaped bottom electrode. In particular, sharp corners of a pre-fabricated conductive silicon container are exposed to an ammonium hydroxide/peroxide mixture. The slow etching effect of the clean rounds angled surfaces thereby minimizing the high field effects usually associated with corners and other angled surfaces. Reducing such field effects by reducing or eliminating sharp corners helps prevent breakdown of the capacitor structure dielectric. Where the conductive container includes a rough layer, such as hemispherical grained silicon, the invention provides the additional advantage of separating individual hemispherical grains, thus allowing later deposition of a uniformly thick dielectric layer.

Abstract: A method of measuring a semiconductor device in forming a capacitor by successively laminating a dielectric film and an opposed electrode above an upper face of a charge storing electrode a surface of which is formed in an irregular shaper, including the steps of forming the irregular shape of the charge storing electrode and measuring an area of the charge storing electrode which is to constitute an effective area of the capacitor by an atomic force microscope.

Abstract: A stacked capacitor DRAM is formed on a substrate having a pass transistor and a wiring line covered by a layer of insulator. A self-aligned contact process is used to expose the surface of one of the source/drain regions of the pass transistor and three layer stack is deposited over the layer of insulator. The lowest, first layer is polysilicon in contact with the one source/drain region of the pass transistor, the second layer is silicon oxide, and the third, topmost layer of the stack is either silicon nitride or polysilicon. A mask is formed over the third layer to laterally define the capacitor structure and then the third and second layers are etched down to the surface of the first, polysilicon layer. Differential etching is then performed to laterally etch the second layer without etching the first or third layers. The mask is removed and hemispherical grained silicon (HSG-Si) is grown over all of the exposed surfaces of the device.

Abstract: An improved method for forming a dynamic random access memory (DRAM) capacitor with increased capacitance includes depositing a first oxide layer over a substrate, and patterning a first photoresist layer on the first oxide layer, thereby defining a node contact area. A node trench is etched in the first oxide layer using the first photoresist as a mask. Afterwards, a polysilicon layer is deposited on the first oxide layer, and a second photoresist layer is patterned on this polysilicon layer, defining an electrode area. A hemispherical-grain (HSG) polysilicon layer is deposited on the polysilicon layer and the first oxide layer. The HSG polysilicon layer is then etched back to form a HSG spacer on the sidewalls of the polysilicon layer, and to form a large number of micro-grooves in the upper portion of the polysilicon layer corresponding to the HSG topography of the HSG polysilicon layer. A nitride layer is then conformally deposited to line the micro-grooves.

Abstract: A method of manufacturing a capacitor for use in semiconductor memories includes forming an undoped dot silicon layer on a doped polysilicon layer. Thermal oxidation is used to convert the dot silicon layer and portions of the doped polysilicon layer into silicon oxide. Then a CMP process is used to remove the oxidized dot silicon layer to create a silicon oxide etching mask. Next, an etching process is performed to form a large number of cavities in the doped polysilicon layer. The silicon oxide layer is then removed and the doped polysilicon layer is patterned and etched to form a bottom storage node of the capacitor.

Abstract: On a semiconductor substrate (1), a polysilicon layer (3) of a random crystal structure is formed. The polysilicon layer (3) is treated by an etchant to provide a roughened surface (3a) of the polysilicon layer (3). The roughened surface (3a) is formed along grains of a random crystal structure and extends over all of top and side surfaces of the polysilicon layer (3). Thus, the polysilicon layer (3) serves as a lower electrode (4) having an increased surface area. A capacitor insulator layer (5) is deposited on the lower electrode (4). An upper electrode (6) is deposited on the capacitor insulator layer (5).

Abstract: A method of creating an STC structure, used for high density, DRAM designs, has been developed. The process consists of creating a saw-toothed topography for the top surface of a polysilicon storage node electrode. The saw-toothed topography is obtained by placing intrinsic HSG polysilicon spots on an underlying doped polysilicon layer. Thermal oxidation creates thick silicon oxide regions in areas of exposed doped polysilicon, while thinner silicon oxide regions form in areas in which the intrinsic HSG polysilicon spots are oxidized. Removal of both thick and thinner silicon oxide regions, creates the saw-toothed topography in the polysilicon storage node electrode, resulting in surface area, and capacitance increases.

Abstract: Uniformity of thin deposited layers on textured surfaces is enhanced by reducing the total surface area available to film deposition. The backside surface area of a semiconductor wafer is reduced prior to film deposition, thereby reducing the available surface to deposition when a deposition process is supply-limited. Reducing the backside surface area suppresses nonuniformities in thin film deposition when the deposition process is substantially supply-limited. The present invention is advantageous for improving uniformity of nitride capacitor dielectric layers deposited on textured electrodes.

Abstract: A method of creating an STC structure, used for high density, DRAM designs, has been developed. The process consists of creating a grated top surface topography for a polysilicon storage node electrode. The grated top surface topography is obtained by using a composite spot structure, of silicon oxide on small diameter, HSG polysilicon spots, as a mask for an anisotropic dry etch procedure, used to define lower features in an underlying polysilicon layer. The raised features of the grated top surface topography of the polysilicon storage node electrode, is comprised of the masking, small diameter, HSG polysilicon spots, on regions of the unetched polysilicon layer.

Abstract: The invention is directed to a thin film transistor (TFT) fabricated by using a planarized poly plug as the bottom gate for use in any integrated circuit and in particular a static random access memory (SRAM). The TFT is used in an SRAM device to form a planarized SRAM cell comprising: a pulldown transistor having a control gate and source/drain terminals; a planarized insulating layer having grooves therein, each groove providing access to an underlying conductive material; a planarized conductive plug residing inside each groove, whereby a first conductive plug forms a thin film transistor gate connecting to an to an adjacent inverter and a second conductive plug provides connection to the gate of the pulldown device; a gate dielectric overlying the first planarized conductive plug; and a patterned semiconductive layer doped such that a channel region aligns to each thin film transistor gate and a source/drain region aligns to each side of the channel region is formed.

Abstract: A simple and low cost ULSI integrated heatsink more efficiently removes heat from a silicon package by integrating the heat sink material into the silicon die, transforming the present two-dimensional art into three dimensions. The fabrication of a high power integrated ULSI package and heatsink begins by fabricating an integrated circuit wafer up to the point of dicing the wafer into individual chips. The front side of the wafer is protected, while the backside of the wafer is exposed. The exposed backside is roughened by chemical and/or mechanical process. Optionally, a gettering process is then performed to remove impurities. The roughened backside is then coated with metal interlayers, preferably aluminum (Al) by chromium (Cr). A layer of copper (Cu) is optionally coated on the metal interlayers. A highly conductive reflowable material, such as solder or gold eutectic, is deposited on the metal interlayers. At this point, the wafer is diced to form chips.

Abstract: Disclosed is a method of fabricating hemispherical grained (HSG) silicon layers. A surface seeding method is disclosed, wherein an amorphous silicon layer is doped with germanium. The silicon may be doped with germanium during deposition, or a previously formed silicon layer may be implanted with the germanium. The layer may also be in situ conductively doped. The Ge-doped amorphous silicon is then subjected to a vacuum anneal in which surface migration of silicon atoms causes a redistribution in the layer, and hemispherical grains or bumps result. A seeding source gas may flow during the anneal to aid in nucleation. The method permits HSG silicon formation at lower temperature and shorter duration anneals than prior art methods. Greater silicon mobility in the presence of germanium dopants also enables the growth of larger grains, thus enhancing surface area. At the same time, the germanium provides conductivity for memory cell charge storage.

Abstract: A method of forming HSG is disclosed, in which a layer of starting material is formed on a wafer, the layer of starting material is seeded with a species and the seeded layer is annealed. The seeding and annealing steps can be performed under different conditions and can be varied independently of each other.

Abstract: A method for fabricating a polycrystalline silicon having a roughed surface, which is useful for a capacitor electrode is disclosed. The method is featured by depositing a polycrystalline silicon layer in such a manner that grains of silicon are caused at the surface of the polycrystalline silicon layer. The polycrystalline silicon layer thus obtained has a large effective area and is suitable for a capacitor electrode because of its increased effective surface area.

Abstract: After formation of a node-contact hole through an interlayer insulation film, an LPCVD using a monosilane gas is employed to form a non-doped polycrystalline silicon film on the interlayer insulation film, filling the node-contact hole. The non-doped polycrystalline silicon film is converted into an n-type polycrystalline silicon film. Using a disilane gas and a phosphine gas as raw gases, an n-type doped amorphous silicon film is formed. After patterning, a heat treatment is employed under a super-high vacuum pressure to convert the n-type doped amorphous silicon film into an n-type polycrystalline silicon film with a rugged surface. A capacitive element is fabricated with a reduced dispersion of capacitance in a simplified manner suitable for a miniaturization of cell size.

Abstract: An embodiment of the present discloses a thermal process for forming hemispherical grained silicon on a silicon material by the steps of: heating the silicon material to a steady state temperature; exposing the silicon material to a hydrogen containing ambient; and causing a decreasing temperature differential of the silicon material while exposing the silicon material to a silicon hydride gas. This embodiment is accomplished by using a thermal cycle having a temperature ramp up period, a temperature steady state period during at least a portion of which the H.sub.2 ambient is present and temperature ramp down period during at least a portion of which the diluted silicon hydride gas is present. A second embodiment discloses a process for forming a hemispherical grained silicon surface on at least one capacitor plate made of silicon material, by increasing the temperature of the capacitor plate in an H.sub.

Abstract: A method of the invention for fabricating a semiconductor device includes the steps of: forming an oxide film having a non-uniform thickness on silicon; reducing at least a portion of the oxide film using gas containing a metal element, and growing a metal film containing the metal element on the silicon by reacting an exposed surface of the silicon with the gas; and removing the metal film.

Abstract: Hemispherical grain (HSG) silicon for a semiconductor device, is formed by: introducing a crystallization nucleus into a silicon material; and converting the silicon material into the HSG silicon by promoting the growth of the crystallization nucleus during a high vacuum anneal. An embodiment of the present invention is a semiconductor device having hemispherical grain (HSG) silicon, where the HSG silicon comprises a silicon material converted into the HSG silicon from the growth of at least one implanted crystallization nucleus.

Abstract: An embodiment of the present invention develops a process for forming Hemi-Spherical Grained silicon by the steps of: forming amorphous silicon from a gas source comprising at least one of dichlorosilane, disilane or trisilane, wherein the amorphous silicon comprising at least one impurity doped amorphous portion, the amorphous silicon is deposited at a deposition temperature no greater than 525.degree. C; and annealing the amorphous silicon for a sufficient amount of time and at an elevated annealing temperature, thereby transforming the amorphous silicon into the Hemi-Spherical Grained silicon.

Abstract: In a method for manufacturing a capacitor, a lower electrode is formed by an amorphous refractory metal silicide layer and its underlying conductive layer, a heating operation is performed upon the amorphous refractory metal silicide layer, so that the amorphous refractory metal silicide layer is converted into a polycrystalline refractory metal layer having an uneven surface.

Abstract: A method and apparatus for electrically interconnecting various electronic elements, including circuit components, assemblies, and subassemblies. A particle enhanced material metal contact layer, having a surface, formed on the electronic elements, includes particles of greater hardness disposed on and/or within the metal contact layer, which particles form protuberances that concentrate stress when said contact surface is brought into contact with an opposing surface under pressure, to thereby penetrate the opposing surface and form a metal matrix between the two surfaces.

Abstract: The present invention develops a process for forming hemi-spherical grained silicon storage capacitor plates by the steps of: forming a silicon layer over a pair of neighboring parallel conductive lines, the silicon layer making contact to an underlying conductive region; patterning the silicon layer to form individual silicon capacitor plates; exposing the silicon capacitor plates to a fluorine based gas mixture during an high vacuum annealing period, thereby transforming the silicon capacitor plates into the semi-spherical grained silicon capacitor plates; conductively doping the hemi-spherical grained silicon capacitor plates; forming a capacitor dielectric layer adjacent and coextensive the semi-spherical grained silicon capacitor plates; and forming a second conductive silicon layer superjacent and coextensive the capacitor dielectric layer.

Abstract: A semiconductor laser such as a laser diode includes a semiconductor substrate and a laser diode region disposed on said semiconductor substrate and having a laser beam emission end. The semiconductor substrate has a front surface directly below said laser beam emission end, said front surface being retracted from said laser beam emission end. The front surface may be formed as an optically roughened surface as a side wall surface of a groove when the groove is defined in the semiconductor substrate by dicing. The laser diode region includes an active layer of GaAs or AlGaAs. The front surface may further be optically roughened by etching or sputtering.