Abstract: A method for reliably forming polysilicon of a desired surface roughness includes providing a layer of doped or undoped amorphous silicon on a substrate and heating said substrate while monitoring the emission of said substrate and comparing the monitored emission with an expected emission attributable to the heating regime employed. An increase in the monitored emission not attributable to the heating regime signals a transition of the layer of amorphous silicon to rough polysilicon. A decrease in the monitored emission not attributable to the heating regime signals a transition to smooth polysilicon. The increases and decreases in the monitored emission can be used to end the heating regime at the time at which the desired surface roughness of polysilicon is formed, or merely to passively monitor the process. The power supplied to heat the substrate to a desired temperature can also be monitored, in that a drop in required power is indicative of the formation of polysilicon.

Abstract: The present invention relates to an improved photolithography process particularly suitable for high-resolution optical lithography techniques using the g, h and i lines of the spectrum of mercury and short-wavelength UV, comprising, prior to deposition of the photosensitive resin on the layer of material to be lithographically patterned, the formation of an antireflective porous layer within the said layer to be lithographically patterned and on the surface of the latter.

Abstract: A method for forming a cylinder-shaped capacitor for dynamic random access memories (DRAMs) is disclosed. The method includes forming a silicon layer having a gap therein over a semiconductor substrate, followed by conformably forming a first dielectric layer on the silicon layer. Next, a second dielectric layer is formed on the first dielectric layer, filling the gap. After etching back the second dielectric layer, the first dielectric layer is removed until the silicon layer is exposed. Then the second dielectric layer is removed, and the silicon layer is etched using the first dielectric layer as a mask, thus forming a cylinder-shaped structure of the silicon layer over the substrate.

Abstract: The method includes forming a metal layer over a substrate. Subsequently, a discrete dot masking is deposited on the surface of the metal layer. A discrete rugged polysilicon or hemispherical grained silicon (HSG-Si) can be chosen as the discrete dot masking. The source gas used to form the discrete rugged polysilicon includes Si2H6 at a temperature of about 400 to 450° C. An anisotropically etching step is performed to etch the metal layer by using the discrete dot masking as an etching mask, thereby forming a surface pattern formed thereon. Then, the discrete dot masking is removed. The metal layer is patterned to a conductive line pattern. An organic material layer with low dielectric constant is formed on the patterned metal layer. A silicon oxide layer is successively formed on the organic material layer, followed by polishing the silicon oxide layer using a chemical mechanical polishing (CMP).

Abstract: The present invention relates to a method for forming rugged polysilicon capacitance electrodes uses for dynamic random access memory processes is disclosed. The method is capable in reducing process time, enhancing yield, and saving production cost. Wherein, the process of the present invention comprises: firstly, a semiconductor wafer is delivered into a low pressure chemical vapor deposition (LPCVD) tube. Herein, a non-doped or doped amorphous silicon layer is deposited on the surface top of electrodes. A rugged polysilicon capacitance is formed on top of the non-doped or doped amorphous silicon layer by using the methods of rising temperature and decreasing pressure. Then, an ion implantation is applied and follows by a wafer cleaning procedure and an annealing process, wherein those procedures are accomplished after the removal of the wafer from LPCVD tube.

Abstract: A method of manufacturing a chip type electronic component includes the steps of forming a multilayer body including a major surface and a side surface by laminating a plurality of substrates and at least one internal electrode interposed between two of the substrates, forming a groove between the two substrates at the side surface of the multilayer body so as to expose an end of the at least one internal electrode, and making the side surface of the multilayer body rough by performing barrel polishing on the multilayer body, the barrel polishing being performed in a barrel pot in which water, media, an abrasive powder and the multilayer body are provided and forming an external electrode on the side surface of the multilayer body, the external electrode being connected to the end of the internal electrode exposed at the groove.

Abstract: A method is provided for fabricating a tunneling oxide layer over a semiconductor substrate with a textured surface. The method is suitable for a semiconductor substrate, such as a silicon substrate, having a polysilicon layer formed over the substrate. The method has several steps of performing a thermal oxidation process to over oxidize the polysilicon layer so as to form an interfacial oxide layer between the substrate and the polysilicon layer, which actually is oxidized as an oxide layer. Due to material property of polysilicon, a textured surface is naturally formed on a top of the substrate. After removing the oxide layer and the interfacial oxide layer, a tunneling oxide layer is formed over the substrate with the textured surface.

Abstract: A method of forming hemispherical grain (HSG) silicon is disclosed. The method comprises the steps of: forming a doped amorphous silicon layer on a substrate; seeding and annealing the amorphous silicon layer until HSG silicon is formed; enlarging the HSG silicon grains during the annealing stage; and performing a chemical dry etch on the HSG silicon to remove an undoped silicon layer from the surface of the HSG silicon.

Abstract: A structure and method of fabricating a stacked capacitor which forms a hemispherical grain (HSG) polysilicon on the surface of a crown shaped amorphous silicon layer. By selective tungsten deposition, the HSG polysilicon and the amorphous silicon layer are displaced with a rough tungsten layer. A material with a high dielectric constant and a metal layer are formed in sequence as a dielectric layer and an upper electrode of the capacitor, so as to form a crown metal-insulator-metal (MIM) capacitor.

Abstract: A method of manufacturing a capacitor is provided where at least a portion of a silicon surface is amorphized. The amorphized silicon surface is then subjected to an annealing process to form hemispherical silicon grains (HSG) from the amorphized portion of the silicon surface to form at least a portion of a first electrode of the capacitor. A capacitor dielectric is then formed over the hemispherical silicon grains. A second electrode is then formed over the capacitor dielectric.

Abstract: An embodiment of the present invention develops a process for forming Hemi-Spherical Grained silicon by the steps of: forming amorphous silicon from a gas source comprising at least one of dichlorosilane, disilane or trisilane, wherein the amorphous silicon comprising at least one impurity doped amorphous portion, the amorphous silicon is deposited at a deposition temperature no greater than 525.degree. C.; and annealing the amorphous silicon for a sufficient amount of time and at an elevated annealing temperature, thereby transforming the amorphous silicon into the Hemi-Spherical Grained silicon.

Abstract: A process for creating a capacitor structure, for a DRAM device, in which the capacitance has been increased via use of a high dielectric constant capacitor dielectric layer, and via the use of a storage node electrode, comprised of a top surface HSG layer, has been developed. The process features deposition of an HSG TiN layer, used as part of a storage node structure, resulting in an increase in storage node electrode surface area, and thus an increase in capacitance.

Abstract: In a method for forming in a semiconductor device a stacked structure capacitor having a lower capacitor plate and an upper capacitor plate sandwiching a dielectric film therebetween, after a first conducting film, which becomes the lower capacitor plate, is formed, ionized clusters are implanted or impacted to a surface of the first conducting film. Thereafter, cluster-implanted regions are selectively removed from the surface of the first conducting film to resultantly roughen the surface of the first conducting film. Then, a dielectric film is formed on the roughened surface of the first conducting film, and a second conducting film, which becomes the upper capacitor plate, is formed on the dielectric film.

Abstract: The present invention discloses a method for forming a DRAM capacitor that has improved charge capacitance which can be carried out by first depositing an oxide layer on a semiconducting substrate, forming an uneven surface on the oxide layer, forming a capacitor node in the oxide layer to expose the substrate, depositing a polysilicon layer on top of the oxide layer and in the node such that the uneven surface on the oxide layer is substantially reproduced in a top surface of the polysilicon layer, depositing a dielectric layer and a second polysilicon layer sequentially on top of the first polysilicon layer to reproduce the uneven surface on the oxide layer, and then defining the DRAM capacitor.

Abstract: A method for manufacturing a capacitor, applied to a memory unit including a substrate forming thereon a dielectric layer forming thereon a first conducting layer, includes the steps of a) forming a sacrificial layer over the first conducting layer, b) partially removing the sacrificial layer, the first conducting layer, and the dielectric layer to form a contact window, c) forming a second conducting layer over the sacrificial layer and in the contact window, d) partially removing the second conducting layer and the sacrificial layer to expose a portion of the sacrificial layer and retain a portion of the second conducting layer, and e) forming a third conducting layer alongside the portions of the second conducting layer and the sacrificial layer, and removing the portion of the sacrificial layer to expose the first conducting layer, wherein the first conducting layer, the portion of the second conducting layer, and the third conducting layer construct a capacitor plate with a generally crosssectionally mod

Abstract: A method for selective controlled etching of a material particularly by sequentially switching between two (2) or more modes of radiofrequency waves and/or by distance from a source of the microwaves. The modes and/or distance are selected depending upon the surface of the material to be etched. The etching is rapidly conducted at 0.5 mtorr to 10 torr, preferably using microwave plasma etching.

Abstract: The present invention provides methods of forming in situ doped rugged silicon and semiconductor devices incorporating conductive rugged silicon. In one aspect, the methods involve forming a layer of doped amorphous silicon on a substrate at a substantially constant deposition temperature; and converting the amorphous silicon layer into hemispherical grain silicon by annealing the amorphous silicon layer at substantially the deposition temperature while varying pressure. In another aspect, the methods involve forming a discontinuous first layer of doped silicon on a substrate; forming a second layer of amorphous silicon on the first layer of doped silicon and the substrate not covered by the first layer of doped silicon; and annealing the first and second layers. In yet another aspect, the methods involve forming a discontinuous first layer of silicon on a substrate and forming a second conformal layer of doped amorphous silicon on the first layer of doped silicon.

Abstract: A honeycomb/webbed, high surface area capacitor formed by etching a storage poly using an etch mask having a plurality of micro vias. The etch mask is preferably formed by applying an HSG polysilicon layer on a surface of the storage poly with a mask layer being deposited over the HSG polysilicon layer. An upper portion of the mask layer is removed to expose the uppermost portions of the HSG polysilicon layer and the exposed HSG polysilicon layer portions are then etched, which translates the pattern of the exposed HSG polysilicon layer portions into the storage poly. The capacitor is completed by depositing a dielectric material layer over the storage poly layer and depositing a cell poly layer over the dielectric material layer.

Abstract: A method for forming a semiconductor memory device storage cell structure having an increased surface area. The storage cell structure has one or more rough polysilicon surfaces formed by depositing the polysilicon under conditions that result in gas phase dominant nucleation.

Abstract: A method of fabricating a capacitor, comprising the steps of: providing a conductive layer over a semiconductor substrate having a transistor formed thereon to connect a source/drain region of the transistor; forming a hemispherical grained silicon layer over the conductive layer; using an implantation method to implant ions into the hemispherical grained silicon layer; performing a thermal treatment process to convert the ions into a barrier layer over the hemispherical grained silicon layer; performing a wet etching process to clean a surface of the barrier layer; forming a dielectric layer over the barrier layer and forming a top electrode over the dielectric layer.

Abstract: Disclosed is a method to reduce step difference of a cell region and a peripheral region, and to increase the capacitance. A first intermetal insulating layer, a planarization layer and a second intermetal insulating layer are formed successively on the semiconductor layer including a storage node. A contact hole is formed by etching the first intermetal insulating layer, the planarization layer and the second intermetal insulating layer so that a selected portion of the storage node is exposed. A photoresist pattern in which a wave of saw-teeth shape is formed at sidewalls, is formed on the second intermetal insulating layer so as to fill the contact hole. Spacers are formed at both sidewalls of the photoresist pattern in which the wave of saw-teeth shape is formed. Herein, a wave of saw-teeth shape is formed at inner surfaces of the spacer owing to both sidewalls of the photoresist pattern. The photoresist pattern in which the waves of saw-teeth shape are formed at sidewalls thereof, is removed.

Abstract: A process for creating a storage node structure, for a DRAM capacitor structure, featuring increased storage node surface area, via use of an HSG silicon layer, on an underlying storage node shape, has been developed. The process features the use of an isotropic, buffered HF etch procedure, applied to the HSG silicon layer, to increase the space between the concave and convex features, of the HSG silicon layer. The increased space between the concave and convex features of the HSG silicon layer, allows a capacitor dielectric layer, of uniform thickness, to be formed on the isotopically etched, HSG silicon layer.

Abstract: A surface of a conductive member such as a gate electrode provided with a silicon layer is roughened. The roughened silicon layer is silicified so that its width is substantially increased, whereby phase transition of the silicide layer is simplified. Thus, the resistance of the refined silicide layer is reduced due to the simplified phase transition.

Abstract: A process for creating a crown shaped storage node electrode, covered with an HSG silicon layer, used to increase the surface area, and thus the capacitance of, high density, DRAM designs, has been developed. The process features creating a crown shaped storage node shape, from a composite amorphous silicon layer, wherein the composite amorphous silicon layer is comprised of a heavily doped amorphous silicon layer, used to alleviate capacitance depletion phenomena, sandwiched between undoped, or lightly doped, amorphous silicon layers, used to selectively accept the overlying HSG silicon layer. The process also features the use an HF vapor pre-clean procedure, followed by an in situ, selective deposition of HSG silicon seeds, in a conventional LPCVD chamber, prior to anneal cycle used to form the HSG silicon layer.

Abstract: On a silicon substrate is formed a silicon dioxide film and then hemispherical grains made of silicon, each having an extremely small diameter, are deposited thereon by LPCVD. After annealing the hemispherical grains, the silicon dioxide film is etched using the hemispherical grains as a first dotted mask, thereby forming a second dotted mask composed of the silicon dioxide film. The resulting second dotted mask is used to etch the silicon substrate to a specified depth from the surface thereof, thereby forming an aggregate of semiconductor micro-needles. Since the diameter of each of the semiconductor micro-needles is sufficiently small to cause the quantum size effects as well as has only small size variations, remarkable quantum size effects can be obtained. Therefore, it becomes possible to constitute a semiconductor apparatus with a high information-processing function by using the aggregate of semiconductor micro-needles (quantized region).

Abstract: Disclosed is a method of increasing capacitance of a memory cell capacitor. A bottom electrode, comprising a hemispherical grained (HSG) silicon layer, is subjected to a dry etch process. The etch tends to separate the individual grains of the HSG silicon, thereby facilitating formation of a uniformly thick capacitor dielectric over the HSG silicon surface. Average thickness of the dielectric may therefore be reduced while maintaining reliability of the memory cell. The described embodiments include HCl/HF vapor etch, and NF.sub.3 plasma etch. Both of the preferred embodiments are configured to operate isotropically. Due to precisely controllable etch rates, the dry etch of the present invention is viable for separating grains of HSG silicon layers incorporated into extremely dense circuits (e.g., 64 Mbit DRAM) and correspondingly scaled down circuit dimensions.

Abstract: A method of forming a capacitor includes the step of forming an electrode on an integrated circuit substrate wherein the electrode covers a first portion of the integrated circuit substrate and wherein the electrode exposes a second portion of the integrated circuit substrate. An etch masking pattern including a plurality of ions is formed on the surface of the electrode wherein the etch masking pattern exposes portions of the surface of the electrode. The exposed portions of the electrode are etched using the etch masking pattern as an etching mask so that recesses are formed in the surface of the electrode thereby increasing a surface area thereof. The etch masking pattern is removed, a dielectric layer is formed on the electrode including the recesses, and a conductive layer is formed on the dielectric layer opposite the electrode.

Abstract: A method of forming a capacitor for use in DRAM or other circuits is described. A first polysilicon node, which will form the first capacitor plate, is formed on a layer of first oxide on an integrated circuit wafer. A layer of titanium silicide is formed on the first polysilicon node by depositing titanium and reacting the titanium with the polysilicon using a first rapid thermal anneal. The titanium silicide is then agglomerated by means of a second rapid thermal anneal thereby forming titanium silicide agglomerates on the surface of the first polysilicon node with exposed first polysilicon between the titanium silicide agglomerates. The exposed first polysilicon is then etched thereby increasing the surface area of the surface of the first polysilicon node and forming a first capacitor plate. A layer of second oxide is then formed on the first capacitor plate. A patterned layer of second polysilicon is then formed on the layer of second oxide forming a second capacitor plate.

Abstract: The capacitor of a DRAM cell is formed by depositing a layer of doped polysilicon, patterning the layer of doped polysilicon to define the extent of the capacitor's lower electrode and depositing a layer of hemispherical-grained silicon (HSG-Si) on the layer of doped polysilicon. A thin layer of amorphous silicon is then formed over the HSG-Si layer. This textured polysilicon structure forms the lower electrode of the DRAM capacitor. A dielectric layer is formed on the lower electrode, and an upper electrode is formed from a second layer of doped polysilicon. As-formed HSG-Si grains tend to form sharp intersections with the polysilicon layers on which they grow. When these HSG-Si grains are exposed to a thermal oxidation environment, poor quality oxides are formed at the sharp corners between the HSG-Si grains and the doped polysilicon layer.

Abstract: A method for manufacturing DRAM capacitor comprising the steps of providing a substrate having a transistor already formed thereon and an insulating layer covered on top, wherein the insulating layer has an opening exposing one source/drain region of the transistor. Next, a first conductive layer, a first hemispherical grained silicon layer and a material layer are sequentially formed over the insulating layer and the source/drain region exposed through the contact opening, and then followed by a patterning operation. After that, a second conductive layer, a second hemispherical grained silicon layer are sequentially formed over the device, and then etched to expose the insulating layer and the material layer. Subsequently, the material layer is removed to expose the first hemispherical grained silicon layer forming a lower electrode. Finally, a dielectric layer and an upper electrode are sequentially formed over the lower electrode.

Abstract: A method for fabricating a stack capacitor with a hemi-spherical grain (HSG) structure is provided. A dielectric layer with a cave is first formed on a substrate. A conformal multi-layer amorphous silicon layer with low dopant concentration is formed over the substrate to cover the cave surface. An amorphous silicon layer with a sufficiently high dopant concentration is formed on the multi-layer amorphous silicon layer to fill the cave. After a planarization process, a remaining portion of the multi-layer amorphous silicon layer and the amorphous silicon layer form a storage node to fill the cave. The dielectric layer is removed to expose the storage node. A HSG is formed on the exposed surface of the storage node. An annealing process is performed to obtain a uniform dopant concentration. A dielectric thin film is formed over the storage node and the HSG layer. An upper electrode is formed to accomplish the stack capacitor.

Abstract: A method of forming an integrated circuit device includes the steps of forming a conductive pattern on an integrated circuit device, and forming an insulating layer on the conductive pattern and on the integrated circuit substrate. An upper surface portion of the insulating layer opposite the substrate is removed, and a photoresist layer is formed on the insulating layer after the step of removing the upper surface portion. The photoresist layer is patterned, and exposed portions of the insulating layer are etched using the patterned photoresist layer as an etching mask thereby forming contact holes through the insulating layer.

Abstract: A technique to form a structure with a rough topography (415) in a planarized semiconductor process. The rough topography (415) is formed by creating cored contacts (433). Subsequent process layers may be further stacked on top of the cored contacts in order to augment the nonplanar characteristics of the cored contacts. This rough topography structure may be used to align integrated circuits and wafers. An integrated circuit may be laser aligned using this alignment structure.

Abstract: A method for forming a trenched polysilicon structure can be applied to a semiconductor device. The method includes steps of: a) providing a polysilicon layer; b) forming a dielectric layer on the polysilicon layer; c) forming a rugged oxide layer on the dielectric layer; d) removing a portion of the dielectric layer which is not covered by the rugged oxide layer for exposing a corresponding portion of the polysilicon layer; e) forming a plurality of microtrenches by etching the corresponding portion of the polysilicon layer; and f) removing the rugged oxide layer and the dielectric layer to obtain the trenched polysilicon structure.

Abstract: A method for forming HSG polysilicon with reduced dielectric bridging and increased capacitance. A first polysilicon layer is deposited and doped with impurities to increase conductivity. A second polysilicon layer is deposited at a reduced temperature to cause a nucleation of the second polysilicon layer. Grains are formed on the surface of the second polysilicon layer as a result of the nucleation. Next a wet etch is performed to remove portions of the polysilicon grains and portions of the first polysilicon layer. The duration of the wet etch is controlled to retain a roughened surface area. The size of the grains decreases during the wet etch and the distance between the grains increases. A dielectric layer is deposited to overlie the rough polysilicon following the wet etch. The thickness of the dielectric layer tends to be uniform thereby reducing bridging of the dielectric between the grains of the of the polysilicon.

Abstract: A porous silicon layer is created by using wet etching to etch a polysilicon layer. In preferred embodiment, the polysilicon layer is treated by H.sub.3 PO.sub.4 solution at 60-165.degree. C. for about 3-200 minutes. The porous silicon layer is subsequently treated by using a SC-1 solution at a temperature about 50-100.degree. C. for about 5-30 minutes to form a roughened polysilicon layer. The SC-1 solution is composed of NH.sub.4 OH, H.sub.2 O.sub.2 and H.sub.2 O. The volume ratio for the three compounds of said SC-1 is NH.sub.4 OH:H.sub.2 O.sub.2 :H.sub.2 O=0.1-5:0.1-5:1-20. The next step of the formation is the deposition of a dielectric film along the roughened surface of the micro-islands polysilicon layers. A conductive layer is deposited over the dielectric film. Next, photolithgraphy and etching process are used to etch the conductive layer, the dielectric film and the micro-islands polysilicon layer into a portion of the layer.

Abstract: This invention provides a method for efficiently making semiconductor wafers having uniform thickness where the thickness of the back side does not influence the front side and where the front side of the wafer is capable of being distinguished from the back side. A semiconductor ingot is sliced to obtain wafers. The sliced surfaces of the wafers are flattened. The flattened wafer is etched in alkaline etching solution. Both the front and back sides of the etched wafer are polished using a double sided polishing apparatus so that the front side is a mirror surface and an unevenness remains on the back side to distinguish the front and back sides, thereof. The polished wafer is cleaned.

Abstract: A silicon structure is formed that includes a free-standing wall having opposing roughened inner and outer surfaces using ion implantation and an unimplanted silicon etching process which is selective to implanted silicon. In general, the method provides a recess in a layer of insulating material into which a polysilicon layer is formed. A layer of HSG or CSG polysilicon is subsequently formed on the polysilicon layer, after which ions are implanted into both the layer of HSG or CSG polysilicon and the underlying polysilicon layer. The aforementioned selective etching process is then conducted to result in a relatively unimplanted portion being etched away and a highly implanted portion being left standing to form the free-standing wall. The free-standing wall has an inner surface that is roughened by the layer of HSG or CSG polysilicon. The free-standing wall also has a roughened outer surface to which has been transferred a near-impression image topography of the opposing inner surface.

Abstract: A method for reliably forming polysilicon of a desired surface roughness includes providing a layer of doped or undoped amorphous silicon on a substrate and heating said substrate while monitoring the emission of said substrate and comparing the monitored emission with an expected emission attributable to the heating regime employed. An increase in the monitored emission not attributable to the heating regime signals a transition of the layer of amorphous silicon to rough polysilicon. A decrease in the monitored emission not attributable to the heating regime signals a transition to smooth polysilicon. The increases and decreases in the monitored emission can be used to end the heating regime at the time at which the desired surface roughness of polysilicon is formed, or merely to passively monitor the process.

Abstract: An electrode structure is fabricated on a microelectronic substrate by forming an amorphous silicon electrode on the microelectronic substrate and cleaning the surface of the amorphous silicon electrode to remove contaminants and surface oxides therefrom. A thin amorphous silicon layer is formed on the clean surface of the amorphous silicon electrode. Silicon crystal nuclei are then formed and grown on the thin amorphous silicon layer. The electrode structure may be used as a bottom electrode for an integrated circuit capacitor, such as the storage capacitor for an integrated circuit DRAM.

Abstract: A method for reducing stress in a TiN layer of a metallization structure, and a silicon wafer portion made by this method. The surface of the dielectric under the TiN is roughened using a water polish with a hard pad, to provide micromounts and valleys on the dielectric surface.

Abstract: A capacitor and method for forming the capacitor having HSG polysilicon with reduced dielectric bridging, increased capacitance, and minimal depletion effects. A first polysilicon layer is deposited and doped with impurities to increase conductivity. A second polysilicon layer is deposited at a temperature adjusted to cause a nucleation of the second polysilicon layer. As a result of the nucleation the second polysilicon layer is altered to resemble hemispherical grains. Next the first and second polysilicon layers are oxidized in an oxygen/phosphine ambient. During the oxidation portions of the first and second polysilicon layers are consumed forming a phosphine rich oxide layer on the surface of the hemispherical grains and in portions of the first polysilicon layer lying between the grains which are reduced in size due to the oxidation. A wet etch is then performed to remove the oxide layer. Phosphorous ions are driven into the hemispherical grains during the oxidation thereby doping the grains.

Abstract: A method of direct-bonding semiconductor wafers limits the time interval between a bonding step and a bonding anneal step or performs a baking step between the bonding and bonding anneal steps at a predetermined temperature for a predetermined time interval to prevent the formulation of voids on the edge regions of the wafers. The method for fabricating laminated semiconductor wafers includes a bonding step to fit together two polished semiconductor wafers by bonding jigs, and a succeeding bonding anneal step to laminate the wafers. In the method the bonding anneal step is preferably carried out within an hour following the bonding step; or a baking step at a predetermined temperature for a predetermined time interval is carried out between the bonding step and the bonding anneal step. Further, the method can prevent heavy metal impurities attached to the surface of the wafer from diffusing into the wafer by baking the wafer for over 5 minutes at above 100.degree. C.

Abstract: A stacked capacitor having very thin fins and subminimum dimension supports for the fins is described. The capacitor includes a stack of conductive layers on a substrate. A plurality of subminimum dimension trenches are formed in the stack and a columnar conductive layer lines the trenches in contact with alternate layers of the stack. An insulator lines these alternate layers and the columnar conductive layer and capacitively couples these alternate layers and the columnar conductive layer to a second plate layer that is formed between the alternate layers, within the columnar layers in the trenches, and extending between stacked capacitors.

Abstract: An ammonia-based etchant is employed, in dilute aqueous solution and preferably with a moderating agent, to etch polysilicon. Ammonium fluoride and ammonium hydroxide are the preferred etchants, with acetic acid and isopropyl alcohol the preferred moderating agents for use with the respective etchants. Dilute solutions of these etchants and their respective moderating agents provide a controllable, uniform polysilicon etch with reasonably good selectivity to undoped polysilicon over doped polysilicon. A dilute solution of ammonium fluoride and acetic acid provides particularly good selectivity. These etchants are applied to the etching of doped polysilicon upon which undoped hemispherical grain (HSG) polysilicon has been formed. The undoped HSG polysilicon is etched at a slower rate than the doped polysilicon which is etched at a greater but controllable and uniform rate. The result is a surface with greater total surface area contained within the same wafer area.

Abstract: The method of fabricating a capacitor of a memory cell is disclosed including the steps of forming a transistor on a semiconductor substrate; sequentially forming an etch stop layer, an insulating layer and a first conductive layer on the semiconductor substrate and the transistor; converting a portion of the first conductive layer into a first porous layer through anodization; patterning a predetermined portion of the first porous layer to form a storage node contact; forming a second conductive layer on the semiconductor substrate and the first porous layer; converting a portion of the second conductive layer into a second porous layer through anodization; patterning a portion of the second porous layer and forming a storage node electrode pattern through an etching process; forming a dielectric layer on an overall surface of the storage node electrode pattern; and forming a third conductive layer on an overall surface of the dielectric layer.

Abstract: This invention discloses a method of forming an electrode of semiconductor device. In the present invention, an amorphous silicon film is formed on a substrate, and silicon seeds are formed on the silicon film. Thereinafter, the heat treatment is performed for growing, thereby forming an hemispherical roughness structure on surface of said charge storage electrode and increasing a surface area in unit area.

Abstract: A method to form a texturized polysilicon surfaced capacitor plate structure and a texturized polysilicon surfaced capacitor plate structure formed by the method are disclosed. The method steps are: depositing an amorphous silicon layer over a capacitor plate by plasma dissociation of SiH.sub.4 ; exposing the amorphous silicon layer to a mixture of CF.sub.4 and Ar; forming amorphous silicon seeding sites that are distributed on the surface of the first amorphous silicon layer by exposing the first amorphous layer to fluorine atoms; and vacuum annealing the amorphous silicon layer to form a texturized polysilicon on the capacitor plate, where the step of vacuum annealing is performed after the amorphous silicon material is exposed to the fluorine atoms.

Abstract: An embodiment of the present discloses a thermal process for forming hemispherical grained silicon on a silicon material by the steps of: heating the silicon material to a steady state temperature; exposing the silicon material to a hydrogen containing ambient; and causing a decreasing temperature differential of the silicon material while exposing the silicon material to a silicon hydride gas. This embodiment is accomplished by using a thermal cycle having a temperature ramp up period, a temperature steady state period during at least a portion of which the H.sub.2 ambient is present and temperature ramp down period during at least a portion of which the diluted silicon hydride gas is present. A second embodiment discloses a process for forming a hemispherical grained silicon surface on at least one capacitor plate made of silicon material, by increasing the temperature of the capacitor plate in an H.sub.

Abstract: A method of forming a silicon layer having a roughened outer surface includes, a) providing a substantially amorphous silicon layer over a substrate, the amorphous silicon layer having an outer surface; b) providing a seeding layer over the amorphous silicon layer outer surface; and c) annealing the amorphous silicon layer and seeding layer under temperature and pressure conditions effective to transform said amorphous layer into a silicon layer having a roughened outer surface. The amorphous silicon layer is preferably provided by providing a first silicon source gas (i.e., silane) within a chemical vapor deposition reactor under first reactive temperature and pressure conditions effective to deposit a substantially amorphous first silicon layer on the substrate. After the amorphous silicon layer deposition, a second silicon source gas (i.e.