Abstract: A preparation method for a solar cell back electrode and an application thereof are provided. The method comprises setting a back electrode barrier layer and using back-side silver paste in coordination. The back electrode barrier layer comprises the following components: 20 to 80 parts by weight of metal nitride powder, nitrogen-silicon compound powder, oxide powder or low-melting-point metal powder in total; 0.5 to 5 parts by weight of lead-free glass powder; 10 to 40 parts by weight of organic carrier; and 0.1 to 1 part by weight of organic additives. The back-side silver paste comprises the following components: 5 to 60 parts by weight of hollow spherical silver powder; 5 to 30 parts by weight of flaky silver powder; 0.5 to 5 parts by weight of lead-free glass powder; 10 to 50 part by weight of organic binder; and 0.1 to 1 part by weight of organic additives.

Abstract: A method for particle abatement in a wafer processing tool implements at least one cleaning-purposed mobile electrostatic carrier (MESC) including electrostatic field generating (EFG) circuits. Each EFG circuit is charged with the cleaning-purposed MESC. The cleaning-purposed MESC is then loaded into the wafer processing tool in a facedown orientation. A normal-purposed MESC is loaded into the wafer processing tool in a faceup orientation. Next, foreign materials are bonded to the cleaning-purposed MESC as the cleaning-purposed MESC is moved along a processing path through the wafer processing tool in the facedown orientation. The normal-purposed MESC travels the processing path during normal operation of the wafer processing tool in the faceup orientation. The cleaning-purposed MESC is then unloaded from the wafer processing tool. Next, the foreign materials are debonded from the cleaning-purposed MESC by discharging each EFG circuit with the cleaning-purposed MESC.

Abstract: A flexible and rollable back-contact solar cell module, wherein a length of it can be extended infinitely and the back-contact solar cell module includes a plurality of large cell blocks connected in series or in parallel. The large cell block includes a plurality of small cell strings connected in series or in parallel. The small cell string includes a plurality of small square cell pieces connected in series or in parallel. The series-connection or the parallel-connection between the large cell blocks, the small cell strings, or the small square cell pieces is achieved by welding a flexible interconnected bar in the horizontal or vertical direction. Electrodes of the small square cell pieces are all on a back side and the small square cell pieces are formed by cutting a back-contact solar cell. A protective layer is attached to a surface of a light-receiving side by using an adhesive layer.

Abstract: The present disclosure relates to an all-back-contact photovoltaic device that includes, in order, a substrate, a first electrode having a first surface, an insulator, a second electrode having a second surface, and an active material, where the insulator and the second electrode form a cavity, the active material substantially fills the cavity and is in physical contact with the first surface and the second surface, the insulator includes a first layer and a second layer with the second layer positioned between the first layer and the second contact, and the first layer is constructed of a first material that is different than a second material used to construct the second layer.

Abstract: Embedded packaging for high voltage, high temperature operation of power semiconductor devices is disclosed, wherein a semiconductor die is embedded in a dielectric body comprising a dielectric polymer composition characterized by a conductivity transition temperature Tc, a first activation energy EaLow for conduction in a temperature range below Tc, and a second activation energy EaHigh for conduction in a temperature range above Tc. A test methodology is disclosed for selecting a dielectric epoxy composition having values of Tc, EaLow, and EaHigh that provide a conduction value below a required reliability threshold, e.g. ?5×10?13 S/cm, for a specified operating voltage and temperature. For example, the power semiconductor device comprises a GaN HEMT rated for operation at ?100V wherein the package body is formed from a laminated dielectric epoxy composition for operation at >150 C, wherein Tc is ?75 C, EaLow is ?0.

Abstract: A method for manufacturing an electronic device includes forming a first source layer including a trench, forming a first sacrificial layer in the trench, forming a first structure over the first source layer, wherein the first structure includes first material layers and second material layers which are alternately stacked over the each other, forming first openings passing through the first structure and extending to the first sacrificial layer, forming first channel layers in the first openings, forming a slit passing through the first structure and extending to the first sacrificial layer, forming a second opening by removing the first sacrificial layer through the slit, and forming a second source layer in the second opening, wherein the second source layer is coupled to the first channel layers.

Abstract: A ReRAM device manufactured using 2-D Si2Te3 (silicon telluride) nanowires or nanoplates. The Si2Te3 nanowires exhibit a unique reversible resistance switching behavior driven by an applied electrical potential, which leads to switching of the NWs from a high-resistance state (HRS) to a low-resistance state (LRS). This switched LRS is highly stable unless the opposite potential is applied to switch the resistance back. This provides a new class of resistive switching based on semiconductor rather than dielectric materials. In several embodiments, the polarity of the initially applied potential along the Si2Te3 nanowires defines the switch “on” and “off” directions, which become permanent once set.

Abstract: Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first and a second semiconductor structures. The first semiconductor structure includes a first interconnect layer including first interconnects. At least one first interconnect is a first dummy interconnect. The first semiconductor structure further includes a first bonding layer including first bonding contacts. Each first interconnect is in contact with a respective first bonding contact. The second semiconductor structure includes a second interconnect layer including second interconnects. At least one second interconnect is a second dummy interconnect. The second semiconductor structure further includes a second bonding layer including second bonding contacts. Each second interconnect is in contact with a respective second bonding contact. The semiconductor device further includes a bonding interface between the first and second bonding layers.

Abstract: A method is described that includes sputtering multiple layers on a back surface of the photovoltaic structure, the photovoltaic structure being made of at least one group III-V semiconductor material, and evaporating, over the multiple layers, one or more additional layers including a metal layer, the back metal structure being formed by the multiple layers and the additional layers. A photovoltaic device is also described that includes a back metal structure disposed over a back surface of a photovoltaic structure made of a group III-V semiconductor material, the back metal structure including one or more evaporated layers disposed over multiple sputtered layers, the one or more evaporated layers including a metal layer. By allowing evaporation along with sputtering, tool size and costs can be reduced, including minimizing a number of vacuum breaks. Moreover, good yield and reliability, such as reducing dark line defects (DLDs), can also be achieved.

Abstract: A wire processing apparatus for a tabbing apparatus is provided. The wire processing apparatus for a tabbing apparatus has: a wire supplying device cutting a wire to a predetermined length; a cell conveying device, on which the wire and a cell are placed, and which conveys the wire and the cell in a conveyance direction; and a wire transferring device receiving the wire from the wire supplying device and transferring the wire to the cell conveying device. The cell is placed on the wire in the state where the wire transferring device grips the wire placed on the cell conveying device.

Abstract: A method of manufacturing a finger electrode for a solar cell includes printing a conductive paste on a front surface of a substrate using a printing mask having an opening rate of 65% or more, and baking the printed conductive paste. The conductive paste may include a conductive powder, a glass frit, and an organic vehicle, and the conductive powder may include a first conductive powder having a particle diameter (D50) of about 0.1 ?m to about 1.5 ?m and a second conductive powder having a particle diameter (D50) of greater than 1.5 ?m to about 5 ?m, and the conductive powder as a whole has a particle diameter (D10) of about 0.5 ?m or less.

Abstract: A multi-junction solar cell comprising a high-crystalline silicon solar cell and a high-crystalline germanium solar cell. The high-crystalline silicon solar including a first p-doped layer and a n+ layer and the high-crystalline germanium solar cell including a second p layer and a heavily doped layer. The multi-junction solar cell can also be comprised of a heavily doped silicon layer on a non-light receiving back surface of the high-crystalline germanium solar cell and a tunnel junction between the high-crystalline silicon solar cell and the high-crystalline germanium solar cell.

Abstract: An efficient back surface field paste for used crystalline silicon solar cells and its preparation method include Paste A and Paste B. Paste A comprises by weight: 50-60% aluminum powder, 2-6% inorganic binder, 10-20% organic binder, 16-26% organic solvent and 2-8% additives, and the sum of weight percentages of each component is 100%. Paste B comprises by weight: 85-90% aluminum powder, 0.1-1% inorganic binder, 1-5% organic binder, 2-8% organic solvent and 1-3% additives, and the sum of weight percentages of each component is 100%.

Abstract: A method of manufacturing a solar cell includes: forming a conductive thin film layer on a semiconductor substrate; forming an insulating film on the conductive thin film layer; forming a conductive thin film layer exposed portion by removing a part of the insulating film; forming a plating film in the conductive thin film layer exposed portion; and removing the insulating film and the conductive thin film layer in an area not overlapping the plating film, wherein the plating film formed in the forming of a plating film is formed to cover the insulating film.

Abstract: Photovoltaic device includes a wafer, wherein it comprises a plurality of discontinuous first conductors oriented in a first direction, which conductors are interrupted in interconnection zones, and in that at least one second conductor electrically connects the first conductors to one another in the interconnection zones, and in that it includes at least one metal strip or braid fastened to at least one electrical conductor, this at least one metal strip or braid including fastening zones in which it is mechanically and electrically connected to an electrical conductor and non-connected zones in which the metal strip or braid is not mechanically fastened to an electrical conductor.

Abstract: A method of manufacturing a finger electrode for a solar cell including printing a conductive paste on one surface of a substrate using a print mask having an aperture ratio of about 65% or more, and baking the printed conductive paste. The conductive paste includes a conductive powder, a glass frit, and an organic vehicle. The organic vehicle includes a solvent having a vapor pressure of about 0.1 Pa to about 500 Pa at room temperature and a flash point of about 90° C. to about 150° C.

Abstract: A method for manufacturing a solar cell includes forming an emitter layer on a first surface of a substrate, forming a back surface field layer on a second surface opposite the first surface of the substrate, forming a first anti-reflection layer on the emitter layer, forming a second anti-reflection layer on the back surface field layer, and forming a plurality of first electrodes each including a first metal seed layer and a first conductive layer on a plurality of first contact regions of the first anti-reflection film and a plurality of second electrodes each including a second metal seed layer and a second conductive layer on a plurality of second contact regions of the second anti-reflection film, the plurality of first contact regions being partially formed at the first anti-reflection layer and each having a first width.

Abstract: A bonding apparatus includes a heat source, a first plate, a second plate, and an actuation mechanism. The first plate is coupled to the heat source. The first and second plates are thermally conductive and configured to cover an entire solar cell. The actuation mechanism moves the bonding apparatus between an open position and a closed position. In the closed position, the first plate and the second plate contact opposite surfaces of the solar cell. The second plate is configured to dissipate heat such that the second plate has a lower temperature than the first plate when in the closed position. The first plate and the second plate apply a force to the solar cell, the force at a first end of the solar cell being different than at a second end of the solar cell when the bonding apparatus is in or moving to the closed position.

Abstract: A semiconductor apparatus includes a silicon layer including first and second semiconductor regions; an insulator film, on the silicon layer, having first and second holes positioned on the first and second semiconductor regions; a first metal portion containing a first metal element in the first hole; a first conductor portion containing a second metal element between the first metal portion and the first semiconductor region; a first silicide region containing the second metal element between the first conductor portion and the first semiconductor region; a second metal portion containing the first metal element in the second hole; a second conductor portion containing the second metal element between the second metal portion and the second semiconductor region; and a second silicide region containing a third metal element between the second conductor portion and the second semiconductor region, wherein the first conductor portion thickness is greater than the second conductor portion thickness.

Abstract: A highly filled back surface field aluminum paste for point contacts in PERC cells and its preparation method include dissolving ethyl cellulose in organic solvent, stirring under a certain temperature to prepare a homogeneous and transparent organic carrier, adding aluminum powder, nanosized aluminum-boron-antimony alloy powder and auxiliary additive, and three-roller grinding, comprising 70-85 parts by weight of aluminum powder, 1-5 parts by weight of nanosized aluminum-boron-antimony alloy powder, 10-25 parts by weight of organic carrier, 0.1-6 parts by weight of inorganic binder and 0.01-1 part by weight of auxiliary additive.

Abstract: A method of manufacturing a solar cell includes: forming a conductive thin film layer on a semiconductor substrate; forming an insulating film on the conductive thin film layer; forming a conductive thin film layer exposed portion by removing a part of the insulating film; forming a plating film in the conductive thin film layer exposed portion; and removing the insulating film and the conductive thin film layer in an area not overlapping the plating film, wherein the plating film formed in the forming of a plating film is formed to cover the insulating film.

Abstract: Embodiments include devices and methods, including a device including a substrate comprising a semiconductor, the substrate including a front side comprising active elements and a backside opposite the front side. The device includes a dielectric layer on the backside, and a passive component on the dielectric layer on the backside. In certain embodiments, the passive device is formed on a self-assembled monolayer (SAM). Other embodiments are described and claimed.

Abstract: A method of manufacturing a bonded body in which a first body and a second body are bonded using a glass paste. The glass paste includes a crystallized glass frit (A) and a solvent (B). A remelting temperature of the crystallized glass frit (A) is higher than a crystallization temperature thereof which is higher than a glass transition temperature thereof. The method includes: applying the glass paste on at least one of the first and second bodies, bonding the first and second bodies by interposing the glass paste therebetween, heating the bonded first and second bodies to a temperature that is not lower than the crystallization temperature and lower than the remelting temperature of the crystallized glass frit (A), and obtaining the bonded body by cooling the bonded first and second bodies to a temperature that is not higher than the glass transition temperature of the crystallized glass frit.

Abstract: A heterojunction photovoltaic cell includes at least one crystalline silicon oxide film directly placed onto one of the front or rear faces of a crystalline silicon substrate, between said substrate and a layer of amorphous or microcrystalline silicon. The thin film is intended to enable the passivation of said face of the substrate. The thin film is more particularly obtained by radically oxidizing a surface portion of the substrate, before depositing the layer of amorphous silicon. Moreover, a thin layer of intrinsic or microdoped amorphous silicon can be placed between said think film and the layer of amorphous or microcrystalline silicon.

Abstract: A manufacturing method includes a first process for forming a first gate electrode for a first MOS transistor and a second gate electrode for a second MOS transistor on a substrate including a semiconductor region defined by an insulator region for element isolation, a second process for masking a portion located above the semiconductor region of the first gate electrode to introduce an impurity to a source-drain region of the first MOS transistor, and a third process for forming a first conductor member being in contact with the portion of the first gate electrode through a first hole disposed on an insulator member covering the substrate and a second conductor member being in contact with the second gate electrode through a second hole disposed on the insulator member.

Abstract: The invention provides an electroconductive paste comprising metallic particles, an inorganic reaction system, and an organic vehicle. The inorganic reaction system includes a lead-tellurium-magnesium composition of Formula (II): Pba—Teb—(Mgw—Cax—Sry—Baz)-Md-Oe, wherein 0<a, b, or d?1, 0?w, x, y, z?1, w+x+y+z=c, at least one of w, x, y and z is greater than zero, the sum of a, b, c and d is 1, 0<c?0.2, 0?d?0.5, a:b is between about 10:90 and about 90:10, (a+c+d):b is between about 10:90 and about 90:10, M is one or more elements, and e is a number sufficient to balance the Pb, Te, Mg—Ca—Sr—Ba and M components.

Abstract: A composition for solar cell electrodes and a solar cell electrode fabricated using the composition, the composition including a conductive powder; a glass frit; and an organic vehicle, wherein the glass frit has an initial crystallization temperature of about 300° C. to about 540° C., wherein the glass frit has an A value of about 0.0001 ?V/mg·° C. to about 0.2 ?V/mg·° C., as calculated by Equation 1: A = ? ? ? H ? ? ? T .

Abstract: There is provided a silver powder, which is able to obtain a conductive paste having a high thixotropic ratio and a high Casson yield value and which is able to form a conductive pattern having a low resistance, and a method for producing the same. An aliphatic amine such as hexadecylamine is added to a silver powder, the surface of which is coated with a fatty acid such as stearic acid, to be stirred and mixed to form the aliphatic amine on the outermost surface of the silver powder while allowing the fatty acid to react with the aliphatic amine to form an aliphatic amide such as hexadecanamide between the fatty acid and the aliphatic amine.

Abstract: A solar cell includes: a semiconductor substrate having a light-receiving surface and a back surface; a first-conductivity-type first semiconductor layer on the back surface; a second-conductivity-type second semiconductor layer on the back surface; a first electrode electrically connected to the first semiconductor layer; a second electrode electrically connected to the second semiconductor layer; and an insulating layer in a boundary region between a first-conductivity-type region of the first semiconductor layer and a second-conductivity-type region of the second semiconductor layer. The insulating layer has an inclined side surface adjacent the second-conductivity-type region inclined such that the thickness of the insulating layer decreases with decreasing distance from the second-conductivity-type region.

Abstract: Screen-printable metallization pastes for forming thin oxide tunnel junctions on the back-side surface of solar cells are disclosed. Interdigitated metal contacts can be deposited on the oxide tunnel junctions to provide all-back metal contact to a solar cell.

Abstract: A method for creating a photovoltaic cell, includes forming a first doped region in a semiconductor substrate having a first concentration of doping elements; forming, by ion implantation, alignment units, the largest size of which is smaller than one millimeter, and a second doped region, adjacent to the first region with a second concentration of doping elements; heat-treating the substrate to activate the doping elements and to form an oxide layer at the surface of the substrate, the second concentration and the heat treatment conditions being selected such that the oxide layer has a thickness above the alignment units that is larger, by at least 10 nm, than the thickness of the oxide layer above an area of the substrate adjacent to the alignment units; depositing an antireflection layer onto the oxide layer; and depositing an electrode onto the antireflection coating, through a screen, opposite the second region.

Abstract: The present disclosure relates to a method the present disclosure relates to an integrated chip having an active pixel sensor with a gate dielectric protection layer that reduces damage to an underlying gate dielectric layer during fabrication, and an associated method of formation. In some embodiments, the integrated chip has a photodetector disposed within a substrate, and a gate structure located over the substrate. A gate dielectric protection layer is disposed over the substrate and extends from along a sidewall of the gate structure to a location overlying the photodetector. The gate dielectric protection layer has an upper surface that is vertically below an upper surface of the gate structure.

Abstract: The present invention addresses the problem of providing a composite nanometal paste which is relatively low in price and is excellent in terms of bonding characteristics, thermal conductivity, and electrical property. The present invention is a copper-filler-containing composite nanometal paste that contains composite nanometal particles each comprising a metal core and an organic coating layer formed thereon. The metal paste contains a copper filler and contains, as binders, first composite nanometal particles and second composite nanometal particles which differ from the first composite nanometal particles in the thermal decomposition temperature of the organic coating layer, wherein the mass proportion W1 of the organic coating layer in the first composite nanometal particles is in the range of 2-13 mass %, the mass proportion W2 of the organic coating layer in the second composite nanometal particles is in the range of 5-25 mass %, and these particles satisfy the relationships W1.

Abstract: The present disclosure provides a method of manufacturing a pattern including: forming a trench structure on a substrate using an inkjet method; filling an interior portion of the trench structure with a filler; and removing the trench structure, and a pattern manufactured using the same, and a method of manufacturing a solar battery using the method of manufacturing a pattern and a solar battery manufactured using the same.

Abstract: A solar cell can include a substrate and a semiconductor region disposed in or above the substrate. The solar cell can also include a conductive contact disposed on the semiconductor region with the conductive contact including a paste, a first metal, and a first conductive portion that includes a conductive alloy formed from the first metal at an interface of the substrate and the semiconductor region.

Abstract: A method of manufacturing a solar cell includes: forming a dopant layer by doping a dopant to a semiconductor substrate; and forming an electrode electrically connected to the dopant layer. The forming of the electrode includes forming a metal layer on the dopant layer; and heat-treating the metal layer to form a first layer and a second layer. In the heat-treating of the metal layer, a portion of the metal layer adjacent to the semiconductor substrate forms the first layer including a compound formed by a reaction of the metal layer and the semiconductor substrate, and a remaining portion of the metal layer forms the second layer that covers the first layer.

Abstract: A fabricating method of a back-illuminated image sensor includes the following steps. First, a silicon wafer having a first surface and a second surface is provided, wherein a number of trench isolations are formed in the first surface, and at least one image sensing member is formed between the trench isolations. Then, a first chemical mechanical polishing (CMP) process is performed to the second surface using the trench isolations as a polishing stop layer to thin the silicon wafer. Because the polishing rate of the silicon material in the silicon wafer is different with that of the isolation material of the trench isolations in the first CMP process, at least one dishing depression is formed in the second surface of the silicon wafer. Finally, a microlens is formed above the dishing depression, and a surface of the microlens facing the dishing depression is a curved surface.

Abstract: Fabrication methods for making back contact back junction solar cells. A base dopant source, a field emitter dopant source, and an emitter dopant source are deposited on the back surface of a solar cell substrate. The solar cell substrate is annealed forming emitter contact regions corresponding to the emitter dopant source, field emitter regions corresponding to the field emitter dopant, and base contact regions corresponding to the base dopant source. The base dopant source, field emitter dopant source, and the emitter dopant source are etched. A backside passivation layer is deposited on the back surface of the solar cell. Contacts are opened to the emitter contact regions and the base contact regions through the backside passivation layer. Patterned base metallization and patterned emitter metallization is formed on the back surface of the solar cell with electrical interconnections to the base contact regions and the emitter contact regions.

Abstract: An integrated circuit structure includes a semiconductor substrate, and a dielectric pad extending from a bottom surface of the semiconductor substrate up into the semiconductor substrate. A low-k dielectric layer is disposed underlying the semiconductor substrate. A first non-low-k dielectric layer is underlying the low-k dielectric layer. A metal pad is underlying the first non-low-k dielectric layer. A second non-low-k dielectric layer is underlying the metal pad. An opening extends from a top surface of the semiconductor substrate down to penetrate through the semiconductor substrate, the dielectric pad, and the low-k dielectric layer, wherein the opening lands on a top surface of the metal pad. A passivation layer includes a portion on a sidewall of the opening, wherein a portion of the passivation layer at a bottom of the opening is removed.

Abstract: A high-K/metal gate semiconductor device is provided with larger self-aligned contacts having reduced resistance. Embodiments include forming a first high-k metal gate stack on a substrate between source/drain regions, a second high-k metal gate stack on an STI region, and a first ILD between the metal gate stacks, forming an etch stop layer and a second ILD sequentially over the substrate, with openings in the second ILD over the metal gate stacks, forming spacers on the edges of the openings, forming a third ILD over the second ILD and the spacers, removing the first ILD over the source/drain regions, removing the etch stop layer, the second ILD, and the third ILD over the source/drain regions, adjacent the spacers, and over a portion of the spacers, forming first trenches, removing the third ILD over the second high-k metal gate stack and over a portion of the spacers, forming second trenches, and forming contacts in the first and second trenches.

Abstract: A method for fabricating a photovoltaic device includes forming an adhesion layer on a substrate, forming a material layer on the adhesion layer and applying release tape to the material layer. The substrate is removed at a weakest interface between the adhesion layer and the substrate by mechanically pulling the release tape to form a transfer substrate including the adhesion layer, the material layer and the release tape. The transfer substrate is transferred to a target substrate to contact the adhesion layer to the target substrate. The transfer substrate includes a material sensitive to formation processes of the transfer substrate such that exposure to the formation processes of the transfer substrate is avoided by the target substrate.

Abstract: A method for vapor deposition of a sublimated source material, such as CdTe, onto substrates in a continuous, non-stop manner through the apparatus is provided. The sublimated source material moves through a distribution plate and deposits onto the upper surface of the substrates as they are conveyed through the deposition area. The substrates move into and out of the deposition area through entry and exit slots that are defined by transversely extending entrance and exit seals. The seals are disposed at a gap distance above the upper surface of the substrates that is less than the distance or spacing between the upper surface of the substrates and the distribution plate. The seals have a ratio of longitudinal length (in the direction of conveyance of the substrates) to gap distance of from about 10:1 to about 100:1.

Abstract: According to one embodiment, a solid-state image sensing device manufacturing method includes forming a photoelectric converting element, a diffusion layer included in a floating diffusion, and a read transistor, in a photoelectric converting element formation region of a semiconductor substrate, a floating diffusion formation region, and a read transistor formation region located between the photoelectric converting element formation region and the floating diffusion formation region, respectively, and forming a semiconductor layer including a impurity on the diffusion layer on the semiconductor substrate.

Abstract: A method for manufacturing back contact solar cells, comprising steps of: (a) providing a silicon substrate doped with phosphorus; (b) doping the front surface and the rear surface of the substrate homogeneously with boron in a blanket pattern, thereby forming a front side p+ region on the front surface and a rear side p+ region on the rear surface; (c) forming a silicon dioxide layer on the front surface and the rear surface; (d) depositing a phosphorus-containing doping paste on the silicon dioxide layer of the rear surface in a second pattern; (e) heating the silicon substrate in order to locally diffuse phosphorus into the rear surface of the silicon substrate, thereby forming a rear side n+ region on the rear surface of the silicon substrate beneath the phosphorus-containing doping paste; and (f) removing the silicon dioxide layer from the silicon substrate.

Abstract: A solar cell according to an embodiment of the invention includes a substrate of a first conductive type, an emitter region of a second conductive type opposite the first conductive type, which is positioned at the substrate, an anti-reflection layer including a first opening exposing the emitter region and a plurality of second openings which expose the emitter region and are separated from one another, a first electrode which is positioned on a first portion of the emitter region exposed through the first opening and is connected to the first portion, a first bus bar which is positioned on a second portion of the emitter region exposed through the plurality of second openings and is connected to the second portion and the first electrode, and a second electrode which is positioned on the substrate and is connected to the substrate.

Abstract: A back contact solar cell comprises an active semiconductor absorber for use in a back contact solar cell having a light capturing front side and a backside opposite the light capturing front side. A first interdigitated metallization is positioned over the backside of the active semiconductor absorber. The first interdigitated metallization forming base and emitter contact metallization of the back contact solar cell. A backplane is positioned over the backside of the active semiconductor absorber and the first interdigitated metallization. A second interdigitated metallization is positioned over the backplane. The second interdigitated metallization is connected to the first interdigitated metallization for extracting photovoltaic power from the active semiconductor absorber. The second interdigitated metallization has base and emitter busbars over the backplane for electrical connection.

Abstract: Light to current converter devices, such as solar cells, are disclosed. The devices may include via holes extending through the cell substrate and may include through-hole electrodes within the via holes. The through-hole electrodes may be made from one or more materials and may be hollow, partially hollow, or fully filled. Front and rear electrodes may also be formed on the device and can be made of the same or different materials as the through-hole electrode. The devices may include emitters located only on the top surface of the cell, located on the top surface and symmetrically or asymmetrically along a portion of the inner surface of the via holes, or located on the top surface and full inner surface of the via holes. Processes for making light to current converter devices are also disclosed.

Abstract: A method for manufacturing an interdigitated back contact solar cell, comprising steps of: (a) providing a doped silicon substrate; (b) doping the rear surface of the substrate homogeneously with boron in a blanket pattern, thereby forming a p+ region on the rear surface of the silicon substrate; (c) forming a silicon dioxide layer on the front and rear surface; (d) depositing a phosphorus-containing doping paste on the rear surface in a second pattern; (e) heating the silicon substrate to locally diffuse phosphorus into the rear surface of the silicon substrate, thereby forming an n+ region on the rear surface of the silicon substrate through the second pattern, wherein the p+ region and the n+ region on the rear surface collectively form an interdigitated pattern; and (f) removing the second silicon dioxide layer from the silicon substrate.

Abstract: A fault position analysis method and a fault position analysis device for a semiconductor device, through which a fault position of a SiC semiconductor device can be analyzed and specified by an OBIRCH method, are disclosed. The fault position analysis method for the semiconductor device scans and irradiates a device and a circuit on a front surface of a substrate with a laser beam from a rear surface side of the substrate of the semiconductor device to heat the device and the circuit. It causes a current to flow to the device and the circuit while being heated, detects a change in a resistance value caused by a change in a current, and analyzes the fault position. The semiconductor device is a semiconductor device which uses an N-doped SiC substrate. Laser beams having wavelengths of 650 to 810 nm are used.

Abstract: A silicon solar cell having a silicon substrate includes p-type and n-type emitters on a surface of the substrate, the emitters being doped nano-particles of silicon. To reduce high interface recombination at the substrate surface, the nano-particle emitters are preferably formed over a thin interfacial tunnel oxide layer on the surface of the substrate.