Overlying Second, Coextensive Micro Panel Circuit Arrangement Patents (Class 439/69)
  • Publication number: 20040063343
    Abstract: A processor actuation system for engaging electrical contacts of a processor with mating elements of a socket. The processor actuation system comprises a socket, a processor, a heat sink and a cam actuator. The socket includes a base, an actuator-receiving member and a sliding cover. The processor includes electrical contacts extending from a surface of the processor. The processor is mounted on a processor-interface surface of the sliding cover. The heat sink mounts on at least one of the processor and the socket. The cam actuator connects to the actuator-receiving member. The cam actuator moves the sliding cover in a longitudinal direction with respect to the base, such that movement of the sliding cover along the longitudinal direction moves the processor and the heat sink along the longitudinal direction to lock the processor.
    Type: Application
    Filed: October 1, 2002
    Publication date: April 1, 2004
    Inventor: Keith McQuilkin Murr
  • Patent number: 6709277
    Abstract: A land grid array (LGA) socket is connected to a power converter using compression contact technology eliminating the need for an edge-card connector typically required in such applications. The LGA socket is mounted to the power converter in a single direction of assembly (i.e., the vertical axis).
    Type: Grant
    Filed: April 12, 2002
    Date of Patent: March 23, 2004
    Assignee: Intel Corporation
    Inventors: Thomas G. Ruttan, Ed Stanford, Peter A. Davison, Tony Harrison
  • Patent number: 6707684
    Abstract: A first package for an integrated circuit has both a first set of electrical contacts and a first connector. A second package has a second set of electrical contacts and a second connector. The first and the second connector are mating connectors that are electrically and physically coupled. The first set of electrical contacts and the first connector are disposed on opposite surfaces of the first package and the second set of electrical contacts and the second connector are disposed on the same surface of the second package. The first and second set of electrical contacts couple to a printed circuit board directly or indirectly through a socket. The connectors allow higher speed signals to be routed over the first and second connectors, while power, ground and slower speed signals can be routed over the first set and second set of electrical contacts.
    Type: Grant
    Filed: April 2, 2001
    Date of Patent: March 16, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Anthony M. Andric, Ruel Hill, Doug Markwardt
  • Patent number: 6676438
    Abstract: A contact structure for establishing electrical connection with contact targets has a unique mounting mechanism for easy assembly. The contact structure is formed of a contactor carrier and a plurality of contactors. The contactor carrier includes a sliding layer for locking the contactors on the contactor carrier. The contactor has an upper end having a cut-out to engage with the sliding layer, a lower end oriented in a direction opposite to the upper end and functions as a contact point for electrical connection with a contact target, and a diagonal beam portion provided between the upper end and the lower end to function as a spring.
    Type: Grant
    Filed: December 3, 2001
    Date of Patent: January 13, 2004
    Assignee: Advantest Corp.
    Inventors: Yu Zhou, David Yu, Robert Edward Aldaz, Theodore A. Khoury
  • Patent number: 6669488
    Abstract: An assembly for mounting elongated electrical contact elements to an integrated circuit package or printed circuit board. The assembly comprises a a base plate having a first surface and a multiplicity of recesses aligned with each other in the first surface. Each of the recesses is sized and configured to receive a respective one of the contact elements. The assembly also comprises first and second spaced apart supports extending from the base plate. The assembly also comprises first and second rods received by the first and second supports and supported parallel to each other. The first and second rods define an intervening slot aligned with the recesses. The assembly also comprises a multiplicity of the contact elements. One end of each of the contact elements is received in a respective one of the recesses. The contact elements are engaged by the first and second rods, whereby the contact elements are held in their respective recesses.
    Type: Grant
    Filed: December 10, 2001
    Date of Patent: December 30, 2003
    Assignee: International Business Machines Corporation
    Inventors: Dierk Kaller, Willi Recktenwald, Gerhard Ruehle
  • Patent number: 6652291
    Abstract: The leadframe interposer is provided with an upset which is formed by shaping in a central region and enlarges the vertical dimension of the interposer there in such a way that, during the assembly of a housing stack of a plurality of semiconductor chips, the upset presses against a topside or underside of a chip housing in such a way that a compensating torque is exerted on the interposer, which prevents a possible strain or deformation when the leads are pressed onto the contact regions of the interposer. The contact regions are laterally offset with respect to one another.
    Type: Grant
    Filed: August 14, 2002
    Date of Patent: November 25, 2003
    Assignee: Infineon Technologies AG
    Inventor: Andreas Wörz
  • Patent number: 6572387
    Abstract: The present invention provides a flexible circuit connector for electrically coupling IC devices to one another in a stacked configuration. Each IC device includes: (1) a package having top, bottom, and peripheral sides; and (2) external leads that extend out from at least one of the peripheral sides. In one embodiment, the flexible circuit connector comprises a plurality of discrete conductors that are adapted to be mounted between the upper side of a first package and the lower side of a second package. The flexible circuit connector also includes distal ends that extend from the conductors. The distal ends are adapted to be electrically connected to external leads from the first and second packages to interconnect with one another predetermined, separate groups of the external leads. In this manner, individual devices within a stack module can be individually accessed from traces on a circuit card.
    Type: Grant
    Filed: March 19, 2002
    Date of Patent: June 3, 2003
    Assignee: Staktek Group, L.P.
    Inventors: Carmen D. Burns, David Roper, James W. Cady
  • Publication number: 20030073330
    Abstract: A device for retaining by pressure at least two electronic components disposed opposite each other and on each side of the same connection board.
    Type: Application
    Filed: October 3, 2002
    Publication date: April 17, 2003
    Inventors: Claude Petit, Thierry Fromont, Jean-Paul Prevot
  • Publication number: 20030027437
    Abstract: The leadframe interposer is provided with an upset which is formed by shaping in a central region and enlarges the vertical dimension of the interposer there in such a way that, during the assembly of a housing stack of a plurality of semiconductor chips, the upset presses against a topside or underside of a chip housing in such a way that a compensating torque is exerted on the interposer, which prevents a possible strain or deformation when the leads are pressed onto the contact regions of the interposer. The contact regions are laterally offset with respect to one another.
    Type: Application
    Filed: August 14, 2002
    Publication date: February 6, 2003
    Inventor: Andreas Worz
  • Patent number: 6473308
    Abstract: A stackable integrated circuit chip package comprising a flex circuit. The flex circuit itself comprises a flexible substrate having opposed, generally planar top and bottom surfaces. Disposed on the top surface is a first conductive pad array, while disposed on the bottom surface is a second conductive pad array and third and fourth conductive pad arrays which are positioned on opposite sides of the second conductive pad array and electrically connected thereto. The chip package further comprises an integrated circuit chip which is electrically connected to the first and second conductive pad arrays, and hence to the third and fourth conductive pad arrays. The substrate is wrapped about at least a portion of the integrated circuit chip such that the third and fourth conductive pad arrays collectively define a fifth conductive pad array which is electrically connectable to another stackable integrated circuit chip package.
    Type: Grant
    Filed: April 19, 2001
    Date of Patent: October 29, 2002
    Inventor: John A. Forthun
  • Patent number: 6469257
    Abstract: An integrated circuit package is mounted on a socket pedestal. External terminals such as ball electrodes may be provided in an array on a mounting surface. Recessed sections can also be provided in the mounting surface in a peripheral section of a region where the external terminals are arranged. The recessed sections can be used for positioning. When the integrated circuit package is subject to an electrical characteristic test (or a burn-in test), the recessed sections can be coupled to protrusions provided on a side of a socket and positioned. As a result, the external terminals can be securely and accurately connected to socket terminals. Thus, integrated circuit packages are provided which have arrayed electrodes for face-down mounting, and which improves the connection accuracy with respect to a socket for conducting electrical characteristic tests.
    Type: Grant
    Filed: December 18, 2001
    Date of Patent: October 22, 2002
    Assignee: Seiko Epson Corporation
    Inventor: Shinji Honda
  • Patent number: 6430057
    Abstract: A device is provided for structurally and electrically interfacing an integrated circuit (IC) chip with a printed circuit board (PCB) designed for another IC chip, where the two IC chips have different structural and/or electrical operating characteristics. The device provides structural and/or electrical interfaces for interfacing the IC chip with the PCB.
    Type: Grant
    Filed: August 17, 2000
    Date of Patent: August 6, 2002
    Assignee: Lucent Technologies Inc.
    Inventors: Martin Nordhoff Hoffmann, Mamatha D. R. Naidu
  • Publication number: 20020102870
    Abstract: The present invention provides a flexible circuit connector for electrically coupling IC devices to one another in a stacked configuration. Each IC device includes: (1) a package having top, bottom, and peripheral sides; and (2) external leads that extend out from at least one of the peripheral sides. In one embodiment, the flexible circuit connector comprises a plurality of discrete conductors that are adapted to be mounted between the upper side of a first package and the lower side of a second package. The flexible circuit connector also includes distal ends that extend from the conductors. The distal ends are adapted to be electrically connected to external leads from the first and second packages to interconnect with one another predetermined, separate groups of the external leads. In this manner, individual devices within a stack module can be individually accessed from traces on a circuit card.
    Type: Application
    Filed: March 19, 2002
    Publication date: August 1, 2002
    Inventors: Carmen D. Burns, David Roper, James W. Cady
  • Patent number: 6418034
    Abstract: A stacked printed circuit board memory module in which a plurality of daughter circuit boards can be stacked onto a primary circuit board. The primary board and each of the plurality of daughter boards have electronic memory ICs mounted on the respective surfaces. The primary board and each of the daughter boards have mounted connectors so that the boards can be electronically and mechanically interconnected with another board.
    Type: Grant
    Filed: November 27, 2001
    Date of Patent: July 9, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Rick Weber, Corey Larsen, James Howarth
  • Patent number: 6407930
    Abstract: A structure of a printed circuit board with stacked daughter board. The structure has a motherboard and at least a daughter board. The motherboard has a first signal layer, a second signal layer, a first power layer, a first ground layer and isolation layers between every layer. The first signal layer and the second signal layer serve as surfaces of the motherboard and first contacts are formed on the first signal layer. The daughter board includes a third signal layer, a fourth signal layer, a second power layer, a second ground layer and isolation layers between every layer. The second power layer or the second ground layer serves as a surface of the daughter board and second contacts are formed on the surface. The daughter board is stacked on the motherboard and the second contacts are coupled with the first contacts.
    Type: Grant
    Filed: July 9, 1999
    Date of Patent: June 18, 2002
    Assignee: ASUSTek Computer Inc.
    Inventor: Hsien-Yueh Hsu
  • Patent number: 6390827
    Abstract: A high current capacity socket (1) includes a base (10) and a number of side contacts (20). The base includes a bottom plate (100), a pair of sidewalls (101) extending upwardly from opposite sides of the bottom plate. A number of passageways (102) are defined in the bottom plate and corresponding terminals (11) are received in the passageways. A receiving room (104) is defined in the center of the bottom plate. The side contacts are fixed in the sidewall (101) of the base (10) to transmit current to a printed circuit board or grounded to reduce the dimension of an integrated circuit package that is received in the receiving room.
    Type: Grant
    Filed: December 11, 2001
    Date of Patent: May 21, 2002
    Assignee: Hon Hai Precision Ind. Co., Ltd.
    Inventors: David G. Howell, Yu Hsu Lin, Pei-Lun Sun
  • Patent number: 6382986
    Abstract: A socket for mounting memory module boards on a printed circuit board (PCB) includes a first socket, a second socket and a third socket. The first socket includes a first socket body that receives a first memory module board, a first clip that connects to a tab of the first memory module board, and a first signal line connected to the first clip and extending outside of the first socket body. The second socket is in an area adjacent to the first socket and includes a second socket body that receives the first and a second memory module boards on opposite sides of the second socket body, two sets of upper socket pins disposed within the second socket body, and two sets of lower socket pins disposed to be opposite to the upper socket pins.
    Type: Grant
    Filed: July 8, 2000
    Date of Patent: May 7, 2002
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-ryeul Kim, Byung-se So
  • Patent number: 6377466
    Abstract: A header containing a semiconductor die, method of manufacture thereof and electronic device employing the same. In one embodiment, the header includes first and second contacts, and an intermediate body. The intermediate body includes an insulated section interposed between the first and second contacts and has a cavity therein. The intermediate body also includes a semiconductor die, located within the cavity, adapted to condition a signal passing through at least a portion of the header.
    Type: Grant
    Filed: March 10, 2000
    Date of Patent: April 23, 2002
    Assignee: Lucent Technologies Inc.
    Inventors: Shiaw-Jong Steve Chen, Roger J. Hooey
  • Publication number: 20020039848
    Abstract: An electric cable connector includes a connector housing, a cable, and a wire management member. The connector housing includes a plurality of terminals, the terminals each having a tail extending out of one end of the connector housing for electrically soldering to respective wires of the cable. The wire management member is joined to the connector housing, and includes a plurality of terminal grooves adapted to receive the tail of each of the terminals, thereby preventing the tail of each terminal from being suspended in the air, and a plurality of wire grooves adapted to receive the wires of the cable for enabling the wires to be respectively positively soldered to the tail of each of the terminals. Positioning rods are also included on the wire management member to be received within cavities in the connector housing.
    Type: Application
    Filed: September 21, 2001
    Publication date: April 4, 2002
    Inventor: Chun-Hsiang Chiang
  • Patent number: 6328574
    Abstract: A high current capacity socket (1) comprises a base (10) and a number of side contacts (20). The base includes a bottom plate (100), a pair of sidewalls (101) extending upwardly from opposite sides of the bottom plate. A number of passageways (102) are defined in the bottom plate and corresponding terminals (11) are received in the passageways. A receiving room (104) is defined in the center of the bottom plate. The side contacts are fixed in the sidewall (101) of the base (10) to transmit current to a printed circuit board or grounded to reduce the dimension of an integrated circuit package that is received in the receiving room.
    Type: Grant
    Filed: July 27, 2001
    Date of Patent: December 11, 2001
    Assignee: Hon Hai Precision Ind. Co., Ltd.
    Inventors: David G. Howell, Yu Hsu Lin, Pei-Lun Sun
  • Patent number: 6330164
    Abstract: The present invention provides an ancillary electrical component in very close proximity to a semiconductor device, preferably mounted directly to the semiconductor device. In one preferred embodiment, the ancillary electrical component is a capacitor. In a preferred embodiment, a terminal is provided on the semiconductor device such that the capacitor can be electrically connected directly to the terminals, as by soldering or with conductive epoxy. Connecting the capacitor between terminals of a power loop provides superior noise and transient suppression. The very short path between the capacitor and the active circuit provides for extremely low inductance, allowing for the use of relatively small capacitors. The semiconductor device then is connected to an electronic device such as a PC board for further connection to other circuitry.
    Type: Grant
    Filed: July 13, 1998
    Date of Patent: December 11, 2001
    Assignee: FormFactor, Inc.
    Inventors: Igor Y. Khandros, David V. Pedersen, Benjamin N. Eldridge, Richard S. Roy, Gaetan Mathieu
  • Patent number: 6322374
    Abstract: A micro-zero insertion force socket is fabricated capable of connecting pins with diameters of 25 to 200 microns and minimum pitches of from 3:1 to 10:1 using micro-fabrication techniques, MEMS components, and high-density interconnections.
    Type: Grant
    Filed: July 28, 2000
    Date of Patent: November 27, 2001
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventors: John H. Comtois, James C. Lyke
  • Patent number: 6324071
    Abstract: A stacked printed circuit board memory module in which a plurality of daughter circuit boards can be stacked onto a primary circuit board. The primary board and each of the plurality of daughter boards have electronic memory ICs mounted on the respective surfaces. The primary board and each of the daughter boards have mounted connectors so that the boards can be electrically and mechanically interconnected with another board.
    Type: Grant
    Filed: January 14, 1999
    Date of Patent: November 27, 2001
    Assignee: Micron Technology, Inc.
    Inventors: Rick Weber, James Howarth, Corey Larsen
  • Patent number: 6278284
    Abstract: An IC socket for testing a grid array package, is configured to be fitted with an adapter socket mounted on a test board. The IC socket includes an IC socket body having a bottom plate formed with a number of contact holding holes penetrating through the bottom plate and arranged in the form of a matrix, and a number of contacts each having a contacting end, a spring portion, a fixing base portion and a contacting pin which are arranged in the named order, the fixing base portion of each of the contacts being inserted into a corresponding contact holding hole of the IC socket body from the upperside of the bottom plate.
    Type: Grant
    Filed: February 16, 1999
    Date of Patent: August 21, 2001
    Assignee: NEC Corporation
    Inventors: Yoichi Mori, Yoshihiro Aoki
  • Patent number: 6262895
    Abstract: A stackable integrated circuit chip package comprising a flex circuit. The flex circuit itself comprises a flexible substrate having opposed, generally planar top and bottom surfaces. Disposed on the top surface is a first conductive pad array, while disposed on the bottom surface is a second conductive pad array and third and fourth conductive pad arrays which are positioned on opposite sides of the second conductive pad array and electrically connected thereto. The chip package further comprises an integrated circuit chip which is electrically connected to the first and second conductive pad arrays, and hence to the third and fourth conductive pad arrays. The substrate is wrapped about at least a portion of the integrated circuit chip such that the third and fourth conductive pad arrays collectively define a fifth conductive pad array which is electrically connectable to another stackable integrated circuit chip package.
    Type: Grant
    Filed: January 13, 2000
    Date of Patent: July 17, 2001
    Inventor: John A. Forthun
  • Patent number: 6239977
    Abstract: A PCMCIA (Personal Computer Memory Card International Association) modem card includes a PCB (printed circuit board) sealed in a slender enclosure, typically the size of a credit card. The PCB contains a hole for receiving a drop-in electronic component, such as a resetting fuse. The fuse comprises a block of positive-temperature-coefficient material sandwiched between a pair of parallel contacts. Each contact includes a tab for surface mounting the fuse to an array of conductive films located on the surface of the PCB. The tabs lie in a common plane and in a plane parallel to the planes of the contacts.
    Type: Grant
    Filed: May 17, 1999
    Date of Patent: May 29, 2001
    Assignee: 3Com Corporation
    Inventors: Tim Urry Price, Patrick A. Tucker
  • Patent number: 6222739
    Abstract: A module for insertion into an expansion slot of a computer includes a primary board and a pair of auxiliary boards. The auxiliary boards are mounted in a spaced relationship on respective sides of the primary board to define air paths between the boards. The air paths allow air to circulate between the boards. The auxiliary boards each have a trace for electrically connecting the board to the primary board, and the primary board has a trace for connecting chips mounted thereon to an interface with the expansion slot. The traces of the auxiliary boards are substantially the same length. The trace of the primary boards is only slightly longer than the traces of the auxiliary boards.
    Type: Grant
    Filed: January 12, 1999
    Date of Patent: April 24, 2001
    Assignee: Viking Components
    Inventors: Jayesh R. Bhakta, Kavous Vakilian
  • Patent number: 6210175
    Abstract: A circuit board includes a semiconductor socket which permits insertion of gull wing semiconductor integrated circuit devices with gull wing contacts. The socketed devices are retained in an inverted alignment. Ribs are used to align the gull wing contacts and ridges are used to isolate split contacts. The isolation of the split contacts permits the use of aligned leads of different ones of the stacked devices. The socket may be mounted beneath the circuit board. This permits stacking and/or socketing of such integrated circuit devices, and further permits alignment of such socketed devices beneath similar devices which are surface mounted to the circuit board, by mounting the socket on the circuit board's opposite (backplane) side. In one configuration, multiple integrated circuit devices may be inserted into the socket in a stacked arrangement. The socket permits the socketing of integrated devices which are packaged for fusion bonding applications.
    Type: Grant
    Filed: February 20, 1998
    Date of Patent: April 3, 2001
    Assignee: Hewlett-Packard Company
    Inventor: David M. Payne
  • Patent number: 6206705
    Abstract: A three-dimensional connection system uses a plurality of printed wiring boards with connectors completely around the printed wiring boards, and connected by an elastomeric interface connector. The device includes internal space to allow room for circuitry. The device is formed by stacking an electronics module, an elastomeric interface board on the electronics module such that the interface board's exterior makes electrical connection with the connectors around the perimeter of the interface board, but the internal portion is open to allow room for the electrical devices on the printed wiring board. A plurality of these devices are stacked between a top stiffener and a bottom device, and held into place by alignment elements.
    Type: Grant
    Filed: October 1, 1998
    Date of Patent: March 27, 2001
    Assignee: California Institute of Technology
    Inventors: Gary S. Bolotin, John Cardone
  • Patent number: 6205031
    Abstract: An electronic control unit having a housing, a substrate, particularly a hybrid, arranged in the housing and having an electronic control circuit. The electronic control unit also includes at least one device plug secured to the housing having contact elements that are electrically conductively connected to the control circuit of the substrate. A second substrate is arranged in the housing, spatially separated from the first substrate. At least one power component disposed in the housing and, electrically connected to the control circuit on the first substrate. One connecting printed circuit trace disposed in housing and conductively connected to the power component. The connecting printed circuit trace are conductively connected to a contact element, conducting power currents, of the device plug. Using the arrangement, in the event of a large number of contact elements in a device plug, the electrical connecting of the contact elements to the substrate can be simplified.
    Type: Grant
    Filed: December 22, 1999
    Date of Patent: March 20, 2001
    Assignee: Robert Bosch GmbH
    Inventors: Achim Herzog, Jürgen Spachmann, Uwe Wagner, Thomas Raica
  • Patent number: 6181567
    Abstract: A method of securing an electronic package to a circuit board includes the step of providing a retainer having a locating cavity defined therein. The method further includes the step of positioning the electronic package within the locating cavity so that the electronic package is fixed in relationship to the retainer. Moreover, the method includes the step of securing the retainer in fixed relationship to the circuit board so as to sandwich the electronic package between the retainer and the circuit board. The securing step is performed after the positioning step. An apparatus for securing an electronic package to a circuit board is also disclosed.
    Type: Grant
    Filed: June 4, 1997
    Date of Patent: January 30, 2001
    Assignee: NCR Corporation
    Inventors: Robert W. Roemer, Eddie V. Williams
  • Patent number: 6176709
    Abstract: A socket for an integrated circuit which is used for attaching the integrated circuit to a socket mounted on a primary wiring board with an intermediate wiring board interposed therebetween, an adapter for an integrated circuit utilizing the integrated circuit socket, and an integrated circuit assembly utilizing the integrated circuit adapter. The integrated circuit socket includes: a housing to be directly fitted with the integrated circuit; a long insertion pin which is to be inserted through the intermediate wiring board and to be fitted in the socket of the primary wiring board; a short insertion pin which is to be inserted through the intermediate wiring board but not to reach the socket of the primary wiring board; and a surface-mount pin which is to be connected to a surface of the intermediate wiring board opposed to the housing; the long insertion pin, the short insertion pin and the surface-mount pin being implanted in the housing.
    Type: Grant
    Filed: December 27, 1999
    Date of Patent: January 23, 2001
    Assignees: Melco Inc, Japan Solderless Terminal Mfg. Co., LTD
    Inventors: Yoshiiku Sonobe, Makoto Oya, Satoru Watanabe, Osamu Nishida
  • Patent number: 6144559
    Abstract: Disclosed is a process to manufacture an interposer which includes an interposer socket assembly to use in probing dense pad arrays that minimizes the associated extraneous pin loading and cross-talk caused by a probe tip. The process comprises the steps of: mounting a number of resistors onto a number of predetermined positions in a pad array on an interposer board; inserting a number of interposer pins of a pin socket into the pads of the pad array on the interposer board, wherein the ends of the interposer pins protrude through the interposer board; placing a solder preform around the ends of the interposer pins; and, heating the solder preforms in a solder re-flow oven to solder the interposer pins to the respective pads of the pad array.
    Type: Grant
    Filed: April 8, 1999
    Date of Patent: November 7, 2000
    Assignee: Agilent Technologies
    Inventors: Kenneth W Johnson, Thomas J Zamborelli, Larry Bartosch
  • Patent number: 6111756
    Abstract: A universal multi-chip interconnect system using a set of at least two types of standardized interconnect components is disclosed. One of the component types comprises a chip carrier capable of holding at least one IC chip in a first portion thereof and providing a plurality of standardized interconnections from the first portion to one or more second portions of the carrier, where one or more interconnect components of a different type may be connected. Another of the component types comprises a bridge connector which is capable of connecting to two or more chip carriers at their second portions. Each bridge connector has at least two interconnect portions which are capable of connecting to chip carriers at their second portions, and a standardized pattern of interconnect wires between the interconnect portions.
    Type: Grant
    Filed: September 11, 1998
    Date of Patent: August 29, 2000
    Assignee: Fujitsu Limited
    Inventor: Larry L. Moresco
  • Patent number: 6097611
    Abstract: A land grid array (LGA) carrier includes an interposer having a first surface and a second surface opposite the first surface, with a plurality of locations on the first surface adapted to receive a plurality of semiconductor dice and passive components. The second surface has a plurality of conductive pads coupled thereto.
    Type: Grant
    Filed: September 17, 1999
    Date of Patent: August 1, 2000
    Assignee: Intel Corporation
    Inventors: William A. Samaras, Paul T. Phillips, Michael P. Brownell
  • Patent number: 6093029
    Abstract: An arrangement for coupling a first packaged integrated circuit to a second packaged integrated circuit comprises a first packaged integrated circuit that includes a first set of electrical interconnection elements arranged on a first surface and a second set of electrical interconnection elements arranged on a second surface which is opposite to the first side. A thermally conductive material is disposed on the second surface and the second set of electrical interconnection elements are arranged around at least a portion of the periphery of the second surface. A second packaged integrated circuit includes a third set of electrical interconnection elements arranged on a first surface of the second packaged integrated circuit. The third set of electrical interconnection elements are shaped to mechanically and electrically couple and decouple to or from the second set of electrical interconnection elements non-destructively by application of manual force.
    Type: Grant
    Filed: September 8, 1998
    Date of Patent: July 25, 2000
    Assignee: S3 Incorporated
    Inventors: Young Kwon, Jon Ewanich, Bill Gervasi, Paul Franklin
  • Patent number: 6040530
    Abstract: A printed circuit board can be used as a test card. The printed circuit board has a first image and a second image. The first image includes a first array pattern for attaching a package, a first power plane, and a first ground plane. The second image includes a second array pattern for attaching a package, a second power plane, and a second ground plane. A first routing area between the first image and the second image electrically and physically isolates the first power plane from the second power plane. The first routing area also physically isolates the first ground plane from the second ground plane. A first single trace extends through the first routing area. The first single trace electrically connects the first ground plane to the second ground plane.
    Type: Grant
    Filed: December 5, 1997
    Date of Patent: March 21, 2000
    Assignee: Hewlett-Packard Company
    Inventors: Robert J. Wharton, Eric R. Daniel, Joseph D. Brown
  • Patent number: 6014533
    Abstract: A couple of electrical connectors for electrical connection includes first and second connectors. The first connector has first electrical contacts and has a memory. The second connector has second electrical contacts adjacent one end for electrical connection with the first connector. The second connector also has third electrical contacts adjacent another end for connection with a cable connector, for transmission of a signal of the memory. The interval of the second electrical contacts are different from that of the third electrical contacts. The interval of the third electrical contacts is smaller than that of the first electrical contacts. This structure facilitates the downsizing of the cable connector.
    Type: Grant
    Filed: May 12, 1998
    Date of Patent: January 11, 2000
    Assignee: Canon Kabushiki Kaisha
    Inventor: Takashi Kawana
  • Patent number: 5991161
    Abstract: A land grid array (LGA) carrier includes an interposer having a first surface and a second surface opposite the first surface, with a plurality of locations on the first surface adapted to receive a plurality of semiconductor dice and passive components. The second surface has a plurality of conductive pads coupled thereto.
    Type: Grant
    Filed: December 19, 1997
    Date of Patent: November 23, 1999
    Assignee: Intel Corporation
    Inventors: William A. Samaras, Paul T. Phillips, Michael P. Brownell
  • Patent number: 5969953
    Abstract: A stacked memory module having alternating layers of printed circuit boards and spacers. Connections between a given circuit board surface and an adjacent (facing) stacked printed circuit board surface, are made using at least one conductive pad incorporated into the electrical circuitry printed on and within the perimeter of each of the adjacent pair of board surfaces; together with means for interconnecting these conductive pads. The spacers can, for example, take the form of standoffs, spacer boards provided with clearance cutouts for components on the printed circuit boards, etc. The printed circuit boards and spacers are then aligned and fastened together using, for example, one or more alignment rods. According to a preferred embodiment of the invention, the fastened assembly is placed in a hollow memory module housing (e.g., a metal cylinder) to complete the fabrication of the memory module.
    Type: Grant
    Filed: September 23, 1998
    Date of Patent: October 19, 1999
    Assignee: L3 Communications
    Inventors: Gregory W. Purdom, Endre M. Berecz
  • Patent number: 5936844
    Abstract: A memory system printed circuit board having an array of memory units disposed on a surface of the printed circuit board. The memory units are arranged in a matrix of row and columns. A first pair of elongated electrical conductor is disposed on an inner portion of the printed circuit board. Each one of the electrical conductors has disposed along a length thereof a plurality of laterally displaced legs. Each one of the legs has a proximal end extending from the conductor. A plurality of conductive vias pass through the printed circuit board, each one of such vias having one end thereof in contact with a one of the legs and a second end at the surface of the printed circuit board for electrical connection to a corresponding one of the rows of memory units. An array of electrical contact pads disposed on a surface of the printed circuit board and arranged for connection to balls of a ball grid array package, such pads being arranged in rows.
    Type: Grant
    Filed: March 31, 1998
    Date of Patent: August 10, 1999
    Assignee: EMC Corporation
    Inventor: John K. Walton
  • Patent number: 5910885
    Abstract: An electronic stack module is disclosed comprising two or more substrates having upper and lower surfaces with one or more electronic components disposed on the surfaces and electrically connected to connector pads disposed in a predetermined pattern at the substrate edges. A plurality of clip leads are electrically attached to the connector pads, where each clip lead comprises a clip section, a standoff section of specified length, and a mounting section, the clip section configured to frictionally engage both upper and lower substrate surfaces. Stacking of substrates is accomplished by aligning and bonding clip sections of one substrate to corresponding mating sections of the adjacent substrate.
    Type: Grant
    Filed: December 3, 1997
    Date of Patent: June 8, 1999
    Assignee: White Electronic Designs Corporation
    Inventors: Alan M. Gulachenski, Joseph Praino, Jack Seidler
  • Patent number: 5910640
    Abstract: A multi-die encapsulation device has a plurality of die chambers. Each of the die chambers has parallel opposing walls, retaining edges which define an insertion void, and a retaining contact in contact with a printed circuit board. Each of the retaining contacts is characterized as having a compliant foot for making contact with a printed circuit board. The encapsulation device comprises a cap with a compression pad for protecting and biasing each of the bare die in its respective chamber.
    Type: Grant
    Filed: February 20, 1998
    Date of Patent: June 8, 1999
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Alan G. Wood, Tim J. Corbett
  • Patent number: 5902152
    Abstract: The active connector for a chip card is made up of a component (1) for control of the reading-writing operations of the chip card (20) and a reading frame for the chip card comprising a support component (2) made of insulating material and receiving contact terminals of a first type (3) projecting from an upper plane (4) of the support made of insulating material in order to be in electrical contact with contact areas (5) of the chip card.
    Type: Grant
    Filed: December 20, 1996
    Date of Patent: May 11, 1999
    Assignee: Framatome Connectors International
    Inventor: Bernard Robert
  • Patent number: 5841640
    Abstract: An IC socket comprises a socket body including a plurality of contacts for interconnecting an IC and a wiring board. Each of the contacts comprises a contacting arm including an upper end contact portion for a lead of an IC to overlie and contact, and a lower end contact portion including a downwardly facing projection capable of abutting with a wiring portion of the wiring board, and a pressing element projecting backwardly of the contacting arm from an area in the vicinity of a connecting portion between the projection and the contacting arm. The projection forming the lower end contact portion is received in an upwardly and downwardly open through-hole formed in the socket body, so as to be subjected to abutment with the wiring portion.
    Type: Grant
    Filed: July 31, 1997
    Date of Patent: November 24, 1998
    Assignee: Yamaichi Electronics Co., Ltd.
    Inventor: Sueji Shibata
  • Patent number: 5841638
    Abstract: A stacked memory module having alternating layers of printed circuit boards and spacers. Connections between a given circuit board surface and an adjacent (facing) stacked printed circuit board surface, are made using at least one conductive pad incorporated into the electrical circuitry printed on and within the perimeter of each of the adjacent pair of board surfaces; together with means for interconnecting these conductive pads. The spacers can, for example, take the form of standoffs, spacer boards provided with clearance cutouts for components on the printed circuit boards, etc. The printed circuit boards and spacers are then aligned and fastened together using, for example, one or more alignment rods. According to a preferred embodiment of the invention, the fastened assembly is placed in a hollow memory module housing (e.g., a metal cylinder) to complete the fabrication of the memory module.
    Type: Grant
    Filed: February 15, 1996
    Date of Patent: November 24, 1998
    Assignee: L3 Communications
    Inventors: Gregory W. Purdom, Endre M. Berecz
  • Patent number: 5835357
    Abstract: A ceramic package for an integrated circuit (IC) and a method of manufacturing the ceramic package.
    Type: Grant
    Filed: September 5, 1995
    Date of Patent: November 10, 1998
    Assignee: Dell USA, L.P.
    Inventors: Deepak Swamy, Thomas J. Kocis
  • Patent number: 5825631
    Abstract: Two hybrid circuit components are connected to one another by a ceramic block. Electrical connections are made between the hybrid components by conductive vias through the ceramic block. The ceramic block is disposed toward an edge of the hybrid components so that integrated circuits and/or discrete electrical components may be attached to a major portion of both surfaces of each hybrid substrate. The interconnected hybrid components form a compact electrical device, for example, a hearing aid.
    Type: Grant
    Filed: April 16, 1997
    Date of Patent: October 20, 1998
    Assignee: Starkey Laboratories
    Inventor: Dave Prchal
  • Patent number: 5818699
    Abstract: An approximately lead-free mounting pad is formed on a first surface of a substrate having wiring circuits, and an electronic element having an approximately lead-free electrode is face-down mounted on the first surface. An approximately lead-free bump is formed on the approximately lead-free electrode of an electronic element. Mounting pads and approximately lead-free bumps are electrically and mechanically connected to each other by approximately lead-free conductive resin. An approximately lead-free sealing pattern is formed at the area which encloses the electronic element mounted area, of the first surface of the substrate. A weld ring made of Kovar is brazed onto the sealing pattern with approximately lead-free solder. The opening edge of a sealing cap made of Kovar disposed opposite to the weld ring and the weld ring are bonded at the deposited zone by welding.
    Type: Grant
    Filed: July 3, 1996
    Date of Patent: October 6, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshitaka Fukuoka
  • Patent number: 5810608
    Abstract: An integrated circuit package that contains a fan assembly which is mounted to the package. The package includes a printed circuit board substrate which has a top surface, an opposite bottom surface and an inner die cavity. A plurality of pins extend from the bottom surface of the substrate so that the package can be connected to an external printed circuit board. A metal lid may be mounted to the top surface to enclose an integrated circuit located within the die cavity of the substrate. The integrated circuit may be mounted to the lid and is electrically coupled to the pins by various routing features of the package. The package includes a plurality of metal disks that are soldered to corresponding surface pads on the top surface of the substrate. The lid exposes the disks. A fan assembly is mounted to the lid and connected to the disks so that the fan receives electrical current through the package.
    Type: Grant
    Filed: October 15, 1996
    Date of Patent: September 22, 1998
    Assignee: Intel Corporation
    Inventors: Duncan D. MacGregor, Rodney K. Rose