Abstract: A multimode power amplifier module, a chip and a communication terminal. In the module, a control circuit (104) sends a bias signal to a low-frequency power amplifier (102) or a high-frequency power amplifier (106) according to a baseband signal, so as to control the amplification of an accessed low-frequency radio frequency signal or a high-frequency radio frequency signal by the low-frequency power amplifier (102) or the high-frequency power amplifier (106); and a transceiving switch (108) selects a corresponding operation mode to conduct transmission or receiving according to an operation mode selection signal. A power amplification path is reused according to different modes, so that the power amplification path can be shared by different operation modes of a high and low frequency band with the adjustment of the control circuit (104), thus simplifying the complexity in designing the power amplifier module, and reducing the cost of relevant design implementation.

Abstract: A payment terminal has a clock management unit for providing clock signals to components of the payment terminal. The payment terminal also has a wireless communication interface for communicating wireless signals. A processing unit of the payment terminal may monitor clock signals provided by the clock management unit and determine a phase and frequency difference between a clock signal provided to a component producing RF noise and a clock signal provided to a wireless communication interface of the payment terminal. When RF noise present in the received wireless signal falls below a threshold, the processing unit may sample the received wireless signal.

Abstract: A circuit for a single differential-inductor oscillator with common-mode resonance may include a tank circuit formed by coupling a first inductor with a pair of first capacitors; a cross-coupled transistor pair coupled to the tank circuit; and one or more second capacitors coupled to the tank circuit and the cross-coupled transistors. The single differential-inductor oscillator may be configured such that a common mode (CM) resonance frequency (FCM) associated with the single differential-inductor oscillator is at twice a differential resonance frequency (FD) associated with the single differential-inductor oscillator.

Abstract: A first radio frequency (RF) power amplifier (PA) stage, a second RF PA stage, and an alpha RF switch are disclosed. The first RF PA stage provides a first RF output signal. During a first alpha mode, the alpha RF switch forwards the first RF output signal to the second RF PA stage, such that the first RF PA stage functions as a driver stage and the second RF PA stage functions as a final stage. However, during one of a group of alpha modes, the alpha RF switch forwards the first RF output signal to provide a corresponding one of a group of alpha transmit signals, such that the first RF PA stage functions as a final stage. Further, the first alpha mode is not one of the group of alpha modes.

Abstract: Embodiments of the present disclosure use shared oscillator for cellular communications and location detection in a communication device. The communications device estimates a frequency offset of one of its subsystems. The communications device determines a frequency offset that results from drifting of this shared oscillator, typically caused by aging and/or changes in temperature, voltage, humidity, pressure, and/or vibration to provide some examples, from the frequency offset this subsystem. The communications device provides various compensation parameters to its various subsystems to compensate for the frequency offset that results from drifting of the oscillator.

Abstract: A wireless communication device for communicating in the near-field via active load modulation. The device including an antenna configured to receive a magnetic field, a recovery device configured to recover a clock from the magnetic field, and a multiplexer configured to receive the recovered clock and a reference clock, and to output one of the recovered clock and the reference clock based on a current operational state of the wireless communication device, The wireless communication device further including a shunt regulator configured to produce the active load modulation by modulating an impedance of the wireless communication device, a phase-locked loop (PLL) configured to receive one of the recovered clock and the reference clock and to utilize the received clock to control the active load modulation, and a driver configured to contribute to the active load modulation by adjusting an amplitude of a voltage across the antenna.

Abstract: A clock data recovery circuit (CDR) extracts bit data values from a serial bit stream without reference to a transmitter clock. A controllable oscillator produces a regenerated clock signal controlled to match the frequency and phase of transitions between bits and the serial data is sampled at an optimal phase. A phase detector generates early-or-late indication bits for clock versus data transition times, which are accumulated and applied to a second order feedback control with two distinct feedback paths for frequency and phase, combined for correcting the controllable oscillator, selecting a sub-phase and/or determining an optimal phase at which the bit stream data values are sampled. The second order filter is operated at distinct rates such that the phase correction has a latency as short as one clock cycle and the frequency correction latency occurs over plural cycles.

Abstract: One bit is a smallest increment of binary measurement in first and second digital values. The first digital value is converted into a first analog signal. The second digital value is converted into a second analog signal. The first analog signal is augmented by a first amount that equates to less than the smallest increment of binary measurement, so that the augmented first analog signal by definition does not equal the second analog signal. The second analog signal is augmented by a second amount that equates to less than the smallest increment of binary measurement, so that the augmented second analog signal by definition does not equal the first analog signal. The augmented first analog signal is compared to the second analog signal, and a first signal is output in response thereto. The augmented second analog signal is compared to the first analog signal, and a second signal is output in response thereto.

Abstract: A LTE compliant RF transceiver includes at least one transmit path and at least two receive paths. A switching arrangement connected between a transmit PLL synthesizer and at least one transmit path as well as between a receive PLL synthesizer and at least two receive paths allows the transmit PLL synthesizer to selectively be connected to the receive side of the transceiver as well as the receive PLL synthesizer to selectively be connected to the transmit side of the transceiver, thereby considerably increasing flexibility of the RF transceiver which enables both speed-up of handover procedures and power savings. A modem including the transceiver is also provided.

Abstract: Systems and methods according to embodiments of the present invention are provided for increasing the power efficiency of a communications device by allowing it to support dual-SIM functionality while issuing simultaneous wake ups for each SIM. Embodiments of the present invention leverage time sharing solutions to minimize the amount of circuitry needed in a communications device to issue wake ups while avoiding the drawbacks of other time sharing solutions that result in increased overhead due to requiring multiple transitions from an idle state to an active state.

Abstract: Integrated clock differential buffering. A first phase locked loop (PLL) circuit having a first clocking ratio is coupled to receive an input differential clock signal. The first PLL circuit generates a first reference clock signal. A second PLL circuit having a second clocking ratio is coupled to receive the input differential clock signal. The second PLL circuit to generate a second reference clock signal. A first set of clock signal output buffers are coupled to receive the first reference clock signal and to provide a first differential reference clock signal corresponding to the first reference clock signal. A second set of clock signal output buffers is coupled to receive the second reference clock signal and to provide a second differential reference clock signal corresponding to the second reference clock signal.

Abstract: An integrated circuit comprises frequency generation circuitry for controlling a frequency source for use in an automotive radar system. The frequency generation circuitry comprises low-path modulation circuitry arranged to generate a first, low-path control signal for providing lower frequency modulation of the frequency source, the low-path modulation circuitry comprising a Phase Locked Loop (PLL) arranged to generate the low-path control signal for controlling the frequency source and a fractional-N divider located within a feedback loop of the PLL, and frequency pattern control module operably coupled to the fractional-N divider and arranged to control the fractional-N divider, by way of at least a first, lower frequency pattern control signal. The frequency generation circuitry further comprises high-path modulation circuitry arranged to generate a second, high-path control signal for providing higher frequency modulation of the frequency source.

Abstract: Aspects of a method and system for compensating for using a transmitter to calibrate a receiver for channel equalization are provided. Various embodiments of the invention may be applicable wireless devices in TDM systems, Bluetooth, and/or WLAN applications, for example. Transmit tones may be generated by a transmitter PLL and the baseband response may be measured for each of the injected tones. The tones may be swept over a frequency range and a corresponding oscillator signal may be mixed with the received signal to determine the response of, for example, the receiver filters. Adjusting any of a plurality of receiver and/or transmitter parameters based on baseband measurements may provide appropriate channel compensation or calibration. Accordingly, the baseband circuitry may generate equalization signals, which may be utilized to adjust receiver and/or transmitter circuitry. This approach may be provide I/Q balancing and transmit filtering calibration after receiver calibration is completed.

Abstract: Adjusting a phase locked loop (PLL) clock source to reduce wireless communication (e.g., radio frequency (RF)) interference within a device. The PLL may be included in a high speed serial interface, e.g., coupled to a display, and may be initially driven by a first clock. Later, when a second clock is available and aligned with the first clock, the PLL may be driven by the second clock. The second clock may be configured to change its frequency over time such that the PLL does not lose lock and also does not interfere (or reduces interference) with wireless communication of the device. For example, the second clock may be programmable or may dynamically vary its operating frequency, thereby reducing its interference with the wireless communication of the device.

Abstract: Various embodiments are described herein for a universal television receiver that is capable of processing television channel signals broadcast according to a variety of analog and digital broadcast standards. Analog processing includes using coarse filtering with pass bands that are wide enough to accommodate frequency shifts in a desired television channel signal and analog circuitry variability and digital processing includes tracking a carrier frequency of the desired television channel signal to generate and apply a frequency shift feedback signal to compensate for frequency shifts in the carrier frequency.

Abstract: A semiconductor device comprises synthesized frequency generation logic arranged to receive a reference signal, and to generate a synthesized frequency signal from the reference signal. The synthesized frequency generation logic comprises programmable divider logic arranged to receive the reference signal and to generate a divided signal comprising a frequency with a period substantially equal to N times that of the reference signal, where N comprises a programmable integer value. The synthesizer frequency generation logic is arranged to generate the synthesized frequency signal comprising a frequency with a period substantially equal to 1/M that of the divided signal, where M comprises a further programmable integer value.

Abstract: An example wireless device includes a radio receiver to measure a signal quality of a data signal independent of a direct frequency measurement, the signal quality correlated to an offset between a transmitter reference frequency and a receiver reference frequency but not indicative of a direction of the offset. The example wireless device further includes a reference frequency generator to determine from the measured signal quality that a previous adjustment to the receiver reference frequency in a first direction has worsened the signal quality, and responsive to that determination adjust the receiver reference frequency in a second direction that is opposite to the first direction.

Abstract: A frequency synthesis system with self-calibrated loop stability and bandwidth, which outputs an output signal based on an input signal and includes a detector, a charge pump, a filter, a controllable oscillator and a programmable frequency divider. The detector produces a detection signal based on a logic level difference between the input signal and a feedback signal. The charge pump is connected to the detector in order to produce a control signal based on the detection signal. The filter is connected to the charge pump in order to produce a tuning signal based on the control signal. The controllable oscillator is connected to the filter in order to produce the output signal based on the tuning signal. The programmable frequency divider is connected to the controllable oscillator in order to produce the feedback signal based on the output signal. The filter is a discrete time loop filter.

Abstract: Aspects of a method and system for bandwidth calibration for a phase locked loop are presented. Aspects of the method may include generating one or more carrier signals based on one or more corresponding calibration signals. A pre-distortion function may be computed based on the generated one or more carrier signals for the phase locked loop circuit. An output radio frequency (RF) synthesized signal generated by the phase locked loop circuit may be modified based on the computed pre-distortion function and a subsequent output RF synthesized signal generated based on the modified output RF synthesized signal.

Abstract: An RF transceiver apparatus comprises transmitter circuitry arranged to convert signals from a baseband frequency to RF transmission frequencies and receiver circuitry arranged to convert signals from RF reception frequencies to the baseband frequency. The transmitter and receiver circuitry each comprise three mixers arranged to convert a signals between the baseband frequency, a first intermediate frequency; a second intermediate frequency that is higher than the transmission frequencies; and a second intermediate frequency to the transmission frequency.

Abstract: A frequency modulation (FM) transmitter implemented with a delta-sigma modulator and a phase-locked loop (PLL) is described. The delta-sigma modulator receives a modulating signal (e.g., an FM stereo multiplex (MPX) signal) and provides a modulator output signal. The PLL performs frequency modulation based on the modulator output signal and provides an FM signal. The FM transmitter may further include a gain/phase compensation unit and a scaling unit. The compensation unit may compensate the modulating signal for the closed-loop response of the PLL. The scaling unit may scale the amplitude of the modulating signal based on a gain to obtain a target frequency deviation for the FM signal. The PLL may operate in a transmit mode or a receive mode, may perform frequency modulation in the transmit mode, and may provide a local oscillator (LO) signal at a fixed frequency in the receive mode.

Abstract: Disclosed herein is a phase-locked circuit including: a phase-locked section including a voltage controlled oscillator having a capacitance bank and changing oscillation frequency according to voltage information, the phase-locked section phase-locking an oscillating signal of the voltage controlled oscillator to a reference signal; and a calibration section having a voltage correcting function for supplying an appropriate calibration voltage to the voltage controlled oscillator in performing frequency calibration for the voltage controlled oscillator; the calibration section including a counter circuit, a first storage circuit and a second storage circuit, a comparator circuit, a control circuit, a voltage generating circuit, and a processing circuit.

Abstract: A Radio Frequency Receiver on a Single Integrated Circuit (“RFSIC”) is described. The RFSIC may include a mixer, a phase-locked loop (“PLL”) in signal communication with the mixer, and an on-chip auto-tuned RF filter in signal communication with both the mixer and PPL, such that the same PLL simultaneously tunes the frequency of the VCO and the frequency response of the auto-tuned RF filter.

Abstract: The invention relates to an integrated circuit in a mobile radio transceiver. This circuit includes a radio-frequency assembly for producing a mobile radio signal and a modulator for converting transmission data into an analogue, modulated transmission signal which is broadcast in a frequency band outside the mobile radio frequency range.

Abstract: In various implementations, a re-configurable phase lock loop may have multiple signal paths, including a feedforward path to operate in a carrier frequency acquisition mode to obtain a carrier frequency estimate and a feedback loop path to operate in a carrier frequency tracking mode to translate an incoming signal to a baseband signal. The multiple signal paths may share most of the hardware to reduce implementation cost.

Abstract: According to an aspect of the invention, an oscillating circuit includes: a first MOS transistor having a first drain terminal and a first source terminal; a load element connected to the first drain terminal; and an oscillator connected to the first source terminal and outputs a fundamental signal and a harmonic signal, wherein the harmonic signal is amplified so that the amplified harmonic signal is output from the first drain terminal.

Abstract: Disclosed herein is a phase-locked loop circuit including: a voltage controlled oscillator; a variable frequency divider circuit for frequency-dividing an oscillating signal of the voltage controlled oscillator into a 1/N (N is an integer) frequency; a phase comparator circuit for comparing phases of a frequency-divided signal and a reference signal of a reference frequency with each other; a charge pump circuit for outputting a charge pump current changed in pulse width; a loop filter for being supplied with the charge pump current and outputting a direct-current voltage changed in level; and a control circuit for calculating a value of the charge pump current as a function of the oscillating frequency of the voltage controlled oscillator and a coefficient for setting a phase locked loop band, and setting the value of the charge pump current in the charge pump circuit.

Abstract: A two-point polar modulator for generating a polar-modulated signal based on an amplitude information and a phase information includes a two-point modulation phase-locked loop which is implemented to enable a frequency setting depending on a first control value via a feedback path of the two-point modulation phase-locked loop and to enable a frequency setting depending on a second control value, directly, bypassing the feedback path, wherein the two-point modulation phase-locked loop is implemented to provide a phase-locked loop output signal depending on the two control values.

Abstract: Disclosed herein is a carrier synchronizing circuit including at least frequency synchronizing means and phase synchronizing means. The phase synchronizing means includes residual frequency error detecting means for detecting a residual frequency error after a frequency synchronizing process by the frequency synchronizing means and supplying the residual frequency error to the frequency synchronizing means, and the frequency synchronizing means performs frequency pull-in for the residual frequency error supplied from the residual frequency error detecting means after first timing.

Abstract: A broad oscillation frequency range and good phase noise characteristic are achievable simultaneously by an oscillation circuit and a resonance circuit connected to the oscillation circuit. The resonance circuit includes an inductor element connected to the oscillation circuit, a first variable capacitance section connected to the inductor element, and a second variable capacitance section connected in parallel to the first variable capacitance section. The first variable capacitance section includes a first variable capacitive element connected to the inductor element, and a second variable capacitive element connected in parallel to the first variable capacitive element. The first variable capacitive element changes its capacity value based on a control voltage and a first reference voltage. The second variable capacitive element changes its capacity value based on the control voltage and a second reference voltage.

Abstract: An apparatus and a method for acquiring synchronization to support multi-frequency in a mobile communication terminal are provided. The apparatus includes a frequency generator, a control signal generator and at least two modems for operating respective Frequency Allocations (FAs) by sharing the frequency generator and the control signal generator. In an embodiment, the frequency generator respectively receives first reference frequency clock signals from an oscillator of each of the at least two modems and generates a second reference frequency clock signal and the control signal generator outputs a signal for controlling the oscillator of each of the at least two modems according to a frequency offset value estimated in each of the at least two modems.

Abstract: Aspects of a method and system for compensating for using a transmitter to calibrate a receiver for channel equalization are provided. Various embodiments of the invention may be applicable wireless devices in TDM systems, Bluetooth, and/or WLAN applications, for example. Transmit tones may be generated by a transmitter PLL and the baseband response may be measured for each of the injected tones. The tones may be swept over a frequency range and a corresponding oscillator signal may be mixed with the received signal to determine the response of, for example, the receiver filters. Adjusting any of a plurality of receiver and/or transmitter parameters based on baseband measurements may provide appropriate channel compensation or calibration. Accordingly, the baseband circuitry may generate equalization signals, which may be utilized to adjust receiver and/or transmitter circuitry. This approach may be provide I/Q balancing and transmit filtering calibration after receiver calibration is completed.

Abstract: An apparatus and method for audio conversion is provided to upgrade the resolution of transmission frequency of an FM (frequency modulation) transmitter and reduce the size of the FM transmitter by applying frequency coarse tune and fine tune. The apparatus comprises a digital FM modulator, a digital frequency synthesizer, a signal converter, and an analog frequency converter. The digital FM modulator modulates a digital audio input signal into a first digital audio signal. The digital frequency synthesizer converts the first digital audio signal into a second digital audio signal, whose frequency is determined according to a first frequency conversion parameter. The signal converter converts the second digital audio signal into an analog audio signal. The analog frequency converter generates an audio transmission signal with a predetermined frequency according to a second clock signal and the analog audio signal while the second clock signal is generated according to a first clock signal.

Abstract: An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Abstract: A Radio Frequency Receiver on a Single Integrated Circuit (“RFSIC”) is described. The RFSIC may include a mixer, a phase-locked loop (“PLL”) in signal communication with the mixer, and an on-chip auto-tuned RF filter in signal communication with both the mixer and PPL, such that the same PLL simultaneously tunes the frequency of the VCO and the frequency response of the auto-tuned RF filter.

Abstract: In the course of the channel presetting process, the central frequency is set by a step of 1 MHz within the range from the minimum frequency in the VHF band channel plan to the maximum frequency of the VHF band adopted in the place of destination for the scheduled shipment of the TV broadcast receivers, attempts are made to detect broadcast signals by changing frequency within a range of 1.5 MHz to the high frequency side and 0.5 MHz to the low frequency side from the central frequency, and the frequencies of the detected broadcast signals are stored in the semiconductor memory.

Abstract: In an exemplary embodiment, noise prediction-based data detection is described with respect to a SERDES (serializer/deserializer) backplane primary channel subject to inter-symbol interference (ISI) noise and added cross-talk noise from other channels. Noise prediction-based data detection combines an added error component from inter-symbol interference (ISI) noise and an added error component from cross-talk noise into an overall noise prediction error term and cancels effects of residual ISI and cross-talk for various components of the exemplary embodiment.

Abstract: When a power source of a digital broadcasting receiving apparatus is turned on, a microprocessor executes reading of a Read Data with specifying a Read Slave Address which is set by applying a prescribed electrical potential to an Address Select (AS) terminal, if the microprocessor confirms that an A/D converter (ADC) bit which is contained in the Read Data from a Mixer Oscillator PLL (MOP) IC is a ADC bit which is set by applying a prescribed electrical potential to an ADC terminal, the microprocessor transmits a tuning data of a format which corresponds to the MOP IC in which target channel is specified with specifying a Write Slave Address which is set by applying a prescribed electrical potential to the AS terminal.

Abstract: A technique for improving frequency synthesizer performance by frequency-compensating charge pump current in order to maintain a consistent loop bandwidth over a wide operating frequency range is described. A relationship between the capacitance value associated with a voltage controlled oscillator resonant tank and the magnitude of current pulses in a related charge pump is exploited to bound the loop bandwidth of the frequency synthesizer over both operating frequency and process variation. A control state machine generates digital coarse tune values that dynamically select a capacitance for the resonant tank, such that the voltage controlled oscillator operates within an optimal control voltage range. Each dynamically selected capacitance value is then used to determine the magnitude of current pulses in the charge pump.

Abstract: A method and apparatus for providing a dual-loop phase lock loop (PLL) for a radio-frequency (RF) receiver is provided. The dual-loop PLL may include coarse tuning circuitry and fine tuning circuitry. The coarse turning circuitry and fine tuning circuitry may be arranged in parallel. Both of the coarse tuning circuitry and fine tuning circuitry provide respective tuning signals to a voltage-controlled oscillator (e.g., a varactor tuned VCO). The coarse tuning circuitry and the fine tuning circuitry may provide the respective tuning signals simultaneously. In addition, coarse and fine tuning circuitry may be formed monolithically with other elements of the dual-loop PLL so as to provide a highly-integratable having a wide frequency lock range and high sensitivity.

Abstract: A clock and data recovery circuit including a phase synchronization loop including an oscillator, the oscillation frequency of which is variably controlled, the phase synchronization loop performing phase-synchronization of a clock signal output from the oscillator with an input data signal. The circuit also includes a discriminator circuit, responsive to a clock signal for discrimination, for discriminating the input data signal and outputting the discriminated signal. The circuit further includes a phase detector circuit for detecting the phase difference between an output data signal, discriminated and output by the discriminator circuit, and the input data signal. The circuit also includes a phase shift circuit for shifting the phase of the clock signal, output from the oscillator, based on a comparison result output from the phase detector circuit. The clock signal, which is output from the phase shift circuit, is supplied as the clock signal for discrimination to the discriminator circuit.

Abstract: A phase detector includes a plurality of phase detectors located in a phase correction loop, each phase detector configured to receive as input a radio frequency (RF) input signal and an RF reference signal, each of the plurality of phase detectors also configured to provide a signal representing a different phase offset based on the phase difference between the RE input signal and the RF reference signal; and a switch configured to receive an output of each of the plurality of phase detectors and configured to select the output representing the phase offset, that is closest to a phase of an output of an amplifier.

Abstract: A filter circuit arrangement for filtering of a radio-frequency signal has a first tunable filter and a phase regulation loop in order to hold the first tunable filter to a transmission phase constant relative to the frequency of the radio-frequency signal. The filter circuit arrangement has a second tunable filter arranged parallel to the first tunable filter in the phase regulation loop. The first tunable filter and the second tunable filter exhibit different attenuation characteristics and are fashioned and connected within the phase regulation loop so that: a capture range of the filter circuit arrangement, in which a tuning of the phase regulation loop to a radio-frequency signal to be filtered is possible is dominated by the attenuation characteristic of the second tunable filter, and so that the transmission behavior of the filter circuit arrangement in operation is dominated by the attenuation characteristic of the first tunable filter, given a tuned phase regulation loop.

Abstract: Embodiments of a millimeter-wave phase-locked loop with an injection-locked frequency divider (ILFD) are generally described herein. Other embodiments may be described and claimed. In some embodiments, the ILFD uses a quarter-wavelength transmission line. A method of calibrating an ILFD is also provided to allow the ILFD to operate at or near the center of its locking range for each of a plurality of VCO oscillating frequency bands.

Abstract: Circuits, architectures, systems and methods for facilitating data communications and/or reducing latency in data communications. The architecture includes a clock recovery loop receiving data from a host device and providing a recovered clock signal, a filter circuit receiving recovered clock signal information and providing a control signal that adjusts the transmitter clock in response to recovered clock signal information and the two clock signals, and a transmitter receiving the control signal and transmitting data to a destination device in accordance with the transmitter clock. The circuitry generally includes a clock alignment block receiving first and second periodic signals and providing a control signal in response thereto, a filter for first periodic signal information, and a logic circuit configured to combine the control signal and the filtered information, thereby providing an adjustment signal for the second periodic signal.

Abstract: A method and an apparatus for frequency synthesizing are provided for a wireless communication system. In a frequency synthesizer, a phase lock loop (PLL) circuit generates a first elemental frequency based on a reference frequency and a unity frequency. A first division module then divides the first elemental frequency to generate a second elemental frequency. A second division module divides the second elemental frequency a multiple of times to generate the unity frequency and a plurality of intermediate frequencies each having an exponential ratio to the unity frequency by a power of two. A second mixer is provided to mix one of the intermediate frequencies with the unity frequency to generate a step frequency, and a first mixer mixes the step frequency with one of the first and second elemental frequencies to generate an output frequency having a variety covering all frequency bands in an Ultra-Wide-Band (UWB) spectrum.

Abstract: An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Abstract: An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Abstract: The present disclosure relates generally to systems and methods for transmitter leak-over cancellation. In one example, a method includes transmitting a signal via a transmit chain in a wireless device, where a portion of the signal leaks over into a receive chain of the wireless device and generates higher order products that interfere with a signal being received by the wireless device. A portion of the signal from the transmit chain is diverted into cancellation circuitry coupled to the receive chain prior to a location in the transmit chain where leak-over occurs, and an amplitude and phase of the portion is manipulated. The manipulated portion is combined with the received signal and other portion to at least partially cancel interference caused by the portion leaking over into the receive chain.

Abstract: Aspects of a method and system for bandwidth calibration for a phase locked loop are presented. Aspects of the method may include generating one or more carrier signals based on one or more corresponding calibration signals. A pre-distortion function may be computed based on the generated one or more carrier signals for the phase locked loop circuit. An output radio frequency (RF) synthesized signal generated by the phase locked loop circuit may be modified based on the computed pre-distortion function and a subsequent output RF synthesized signal generated based on the modified output RF synthesized signal.