Abstract: A device and a method for processing high data rate serial data includes a VCO initial frequency calibration circuit. The circuit includes a frequency detection block for indicating a difference between a reference clock and a divided VCO clock, a frequency calibration block that produces a digital output signal based upon the difference between the reference clock and the divided VCO clock, and a digital-to-analog converter for producing an analog VCO adjust signal. The frequency detection block produces a plurality of signals based upon the reference clock and the divided VCO clock. A plurality of user selected inputs selects a frequency detection lock range and hysteresis range and a coarse loop open calibration lock and hysteresis range. The frequency calibration block implements a state machine for producing the digital output signal that sets the initial operating frequency then adjusts the frequency of the VCO clock.

Abstract: A phase tracking system includes a source of an input signal representing a received symbol. A phase rotator has a first input terminal which is responsive to the input signal, a second input terminal which is responsive to a phase correction signal, and an output terminal which produces a phase adjusted output signal. A decision element generates an ideal signal representing the received symbol in response to the phase adjusted output signal. A phase adjuster, which has full phase wrap-around capability, generates the phase correction signal in response to the phase difference between the phase adjusted output signal and the ideal signal.

Abstract: A dual path loop filter circuit for a phase lock loop is described. The filter circuit allows the filter to be integrated into a phase lock loop IC circuit without using active circuit components that may create additional noise and consume additional power. The filter circuit structure allows for a low capacitance capacitor to be used to filter out any undesired signals.

Abstract: The present disclosure relates generally to systems and methods for transmitter leak-over cancellation. In one example, a method includes transmitting a signal via a transmit chain in a wireless device, where a portion of the signal leaks over into a receive chain of the wireless device. A portion of the signal is diverted from the transmit chain into cancellation circuitry coupled to the receive chain to manipulate an amplitude and phase of the portion before combining the manipulated portion with the signal and other portion to at least partially cancel interference caused by the leak-over portion. After downconverting, a remainder portion is filtered from the received signal. A power level of the remainder portion is detected and compared to a threshold value. An amplitude and phase configuration of the cancellation circuitry is modified based on a result of comparing the power level to the threshold value.

Abstract: A wireless communication device is disclosed wherein the voltage swing of a local oscillator (LO) signal is controlled to prevent overstressing semiconductor devices in a mixer to which the LO signal is supplied. A quadrature divider supplies the LO signal to the mixer. Digital calibration methodology controls the current that the quadrature divider draws from a power supply to set the voltage swing of the LO signal that the quadrature divider generates.

Abstract: Television systems comprising tuners (1), controllers (2) for controlling tuners (1), and stages (3) for receiving tuned signals from tuners (1) and for supplying control signals to controllers (2), use time-consuming automatic fine tuning signals while high speed tuning. By using lock signals (53) from phase-locked-loops (31) in stages (3) as control signals, an indication whether a channel is active or not can now be got much quicker due to lock signals being much faster available than automatic fine tuning signals. By using synchronization signals (54) from synchronization generators (4) as further control signals, a further indication is got. In a fast tuning mode, frequencies nearby active channels are detected, and in a fine tuning mode, channel frequencies are identified.

Abstract: Using low impedance switches and coupling to a virtual ground, one or more capacitors are selectively switched into or out of an inductive-capacitive resonant circuit portion of an integrated circuit filter to alter the resonant frequency based on a phase difference between the resonant frequency and a reference frequency. The capacitors are sized for a sequence of total capacitances proceeding by halves or doubles between values corresponding to minimum and maximum desired frequency adjustments, allowing a binary count of pulses representative of the phase difference to address the correct combination of capacitors. An exact or ratioed replica of the inductive-capacitive resonant circuit, controlled by the same capacitance selection signal, may be used as a frequency-selective amplifier load or matching network, or to form a ladder filter.

Abstract: A wireless transmit-only apparatus (20) has a controller (21) that responds to a user interface 25 by correlating specific user input with a corresponding characterizing transmission parameter(s) as is stored in a memory (35) and by selecting a corresponding resonant device (31 and 32). The latter devices serve to drive the PLL control input of a phase locked loop (23) to thereby influence the transmission carrier frequency of a wireless transmitter (22). In a preferred embodiment, at least one of the resonant devices comprises a mechanically resonant device such as a surface acoustic wave device, a crystal resonator, or a ceramic resonator.

Abstract: A variable signal delaying circuit comprising an analog delay line having a control input for controlling the variable delay. A phase detector compares the input and output signals of the delaying circuit and supplies an output signal to a charge pump and integrator. A pulse stream generating arrangement produces pulse streams of different pulse widths and pulse control logic controls a selector for selecting any one of the pulse streams. In a first mode of operation, the control logic monitors the charge pump/filter output and selects the pulse stream which minimizes change in the output. The selection is fixed and the output of the charge pump/filter is then supplied as a correction signal to the control input of the analog delay line. Such an arrangement may be used to maintain minimum phase imbalance in I and Q signal paths of a quadrature frequency converter.

Abstract: Aspects of a method and system for compensating for using a transmitter to calibrate a receiver for channel equalization are provided. Various embodiments of the invention may be applicable wireless devices in TDM systems, Bluetooth, and/or WLAN applications, for example. Transmit tones may be generated by a transmitter PLL and the baseband response may be measured for each of the injected tones. The tones may be swept over a frequency range and a corresponding oscillator signal may be mixed with the received signal to determine the response of, for example, the receiver filters. Adjusting any of a plurality of receiver and/or transmitter parameters based on baseband measurements may provide appropriate channel compensation or calibration. Accordingly, the baseband circuitry may generate equalization signals, which may be utilized to adjust receiver and/or transmitter circuitry. This approach may be provide I/Q balancing and transmit filtering calibration after receiver calibration is completed.

Abstract: In a radio transmission system, a receiver comprises means for synchronizing the time on the side of the receiver with the time on the side of the transmitter by a PLL circuit on the basis of receiving intervals of a packet transmitted for each predetermined time interval from a transmitter, means for holding the received packet in a receiving buffer, and means for outputting, when the time on the side of the receiver coincides with the time on the side of the transmitter which is represented by the transmitter-side time information added to the packet held in the receiving buffer, the packet to a decoding device.

Abstract: An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Abstract: A calibration device for a phase locked loop arranged to generate an output frequency based upon a first frequency range of an input signal applied to a first input and a second frequency range of the input signal applied to a second input, the calibration phase locked loop synthesizer device comprising an estimator arranged to use a two dimensional estimation algorithm with a signal value indicative of a mismatch between the first input path and the second input path to determine an estimate of the mismatch to allow matching of the first input path and the second input path.

Abstract: A variable gain frequency multiplier comprises a multiplier circuit and a control circuit configured to receive a power control signal, the power control signal being proportional to a power output signal.

Abstract: An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Abstract: An LC-VCO includes a multivibrator which outputs a frequency signal, a fine tuning circuit which tunes the frequency signal by a first amount, a coarse tuning circuit which tunes the frequency signal by a second amount, and a control circuit which controls the fine and coarse tuning circuits. The coarse tuning circuit is formed from one or more capacitive arrays and the fine tuning circuit is formed from one or more varactors. The capacitive arrays are preferably controlled by a digital signal, where each bit selectively couples a respective capacitor to the multivibrator. An analog signal controls the value of the varactors. The capacitive arrays and varactors charge and discharge an inducator in the multivibrator to tune the frequency signal. The VCO may be incorporated within a phase-locked loop, where the capacitors may be assigned different weight and/or redundancy values to tune an output frequency signal.

Abstract: A device and a method for processing high data rate serial data includes circuitry for recovering a clock based on the high data rate input data stream. A transceiver includes a coarse loop of a phase-locked loop that selectively provides a clock having accuracy that is within a specified amount. In a sample mode of operation, only the coarse loop PLL is coupled to provide an error signal from which an oscillation signal and clock may be derived. In a second mode (lock) of operation, the transceiver may lock to the received serial data stream by coupling the fine loop PLL to provide an adjusted error signal. In a third mode of operation, (automatic) the transceiver initially performs coarse loop calibration by de-coupling the fine loop PLL and coupling the coarse loop PLL until a steady state has been reached.

Abstract: Circuits, architectures, systems and methods for facilitating data communications and/or reducing latency in data communications. The architecture includes a clock recovery loop receiving data from a host device and providing a recovered clock signal, a filter circuit receiving recovered clock signal information and providing a control signal that adjusts the transmitter clock in response to recovered clock signal information and the two clock signals, and a transmitter receiving the control signal and transmitting data to a destination device in accordance with the transmitter clock. The circuitry generally includes a clock alignment block receiving first and second periodic signals and providing a control signal in response thereto, a filter for first periodic signal information, and a logic circuit configured to combine the control signal and the filtered information, thereby providing an adjustment signal for the second periodic signal.

Abstract: A single chip GSM/EDGE transceiver comprises a fully differential receive chain, a subharmonic mixer in the receive chain, the subharmonic mixer configured to receive a radio frequency (RF) input signal and a local oscillator (LO) signal that is phase-shifted by a nominal 45 degrees, and a synthesizer having a voltage controlled oscillator and having at least one frequency divider to generate desired transmit and receive LO signals. The transceiver also comprises a transmitter having a closed power control loop, and a harmonic rejection modulator, the use thereof made possible by a frequency plan designed to allow the synthesizer to develop the transmit and receive LO signals without a frequency multiplier.

Abstract: A CATV tuner includes a metallic housing having first through fourth partitioned chambers. In the first through fourth partitioned chambers, a data circuit, an input filter circuit, a first mixer circuit, a first local oscillation circuit, a first intermediate frequency circuit, and other elements are housed. In the fifth partitioned chamber, a second intermediate circuit and an IC including a second local oscillation circuit are housed. With this configuration, the CATV tuner defines an up/down tuner. The third partitioned chamber in which the first local oscillation circuit is housed and the fifth partitioned chamber in which the second local oscillation circuit is housed are located adjacent to each other. Lines and terminals are used both for a first PLL circuit and a second PLL circuit.

Abstract: A polar transmitter that is configurable as either a closed loop polar transmitter or an open loop polar transmitter is provided. In general, the polar transmitter is configured as an open loop polar transmitter when operating at an output power level less than a predetermined threshold and as a closed loop polar transmitter when operating at an output power greater than the predetermined threshold.

Abstract: In a transmission signal generating apparatus according to the present invention, a voice signal is amplified by a variable amplifier which varies its amplification factor in accordance with an amplitude control signal, and the amplitude of the voice signal output from the variable amplifier is limited by a variable limiter which varies its amplitude limiting range in accordance with the amplitude control signal. The thus amplified and amplitude-limited voice signal is supplied as a modulating signal to a voltage controlled oscillator constituting part of a PLL circuit which generates a transmission signal. A control signal generating section generates the amplitude control signal for the variable amplifier and the variable limiter by detecting the f/v sensitivity of the voltage controlled oscillator based on an output of a low pass filter constituting part of the PLL circuit.

Abstract: A novel apparatus for a low noise, high isolation, all digital transmit buffer gain control mechanism. The gain control scheme is presented in the context of an all digital direct digital-to-RF amplitude converter (DRAC), which efficiently combines the traditional transmit chain functions of upconversion, I and Q combining, D/A conversion, filtering, buffering and RF output amplitude control into a single circuit. The transmit buffer is constructed as an array of NMOS switches. The control logic for each NMOS switch comprises a pass-gate type AND gate whose inputs are the phase modulated output of an all digital PLL and the amplitude control word from a digital control block. Power control is accomplished by recognizing the impairments suffered by a pseudo class E pre-power amplifier (PPA) when implemented in a CMOS process. Firstly, the NMOS switches of the array have significant on resistance and thus can only draw a limited current from the an RF choke when the input waveform is high.

Abstract: A front end for a radio frequency tuner, for example for connection to a cable distribution network, including an input connected to a signal path comprising an LNA connected via an AGC stage to a signal splitter. The input path has a bandwidth sufficiently wide to pass all of the channels in an input signal and has a substantially constant voltage standing wave ratio over the bandwidth. The splitter supplies identical signals to several filtering paths, each of which comprises a fixed filter. The paths are selectable one at a time and the filters divide the input frequency band into a plurality of contiguous or slightly overlapping sub-bands. The output of the front end is supplied to, for example, a double conversion arrangement comprising an upconverter and a downconverter with first and second IF filters.

Abstract: A transmitter has a signal generator, an amplifier, a detection circuit, a comparison circuit, a loop filter, and an adjustable clock. The signal generator produces a signal. The signal is produced with a first frequency characteristic and contains frequency-related information. The detection circuit detects the first frequency-related characteristic and generates an associated signal in response. A comparison circuit compares the signal from the detection circuit and another signal. It outputs a signal associated with the difference between the two. A loop filter receives the output of the comparison circuit and generates a signal to the signal generator in. The loop filter is clocked at a second frequency by a signal from a clock circuit. The clock circuit can compare the first frequency and the second frequency, and can change the second frequency based upon a relationship between the two frequencies.

Abstract: A ?? transmitter that permits setting of a loop filter LF, a charge pump current and other factors to the same conditions even if it is operated in a plurality of frequency bands, therefore allows the number of components to be reduced and at the same time enables the angle between the phases of local signals for reception use to be close to exactly 90°, which is a feature ensuring robustness against inter-element variations and accordingly suitable for large scale integration, is to be provided. The oscillation frequency of a VCO is set to an even-number multiple of the transmit frequency, and generates transmit signals via a divider. A device that varies the gain according to the amplitude component of modulating signals is added to an amplifier whose input is signals from the VCO, and the transmission of modulating signals involving amplitude modulation, such as EDGE, is thereby made possible.

Abstract: A system and method are provided for switching from one phase-locked loop feedback source to another in a radio frequency (RF) transmitter. The RF transmitter includes a phase-locked loop (PLL) that provides a phase-modulated RF input signal and power amplifier circuitry that amplifies the RF input signal to provide an RF output signal. The PLL includes switching circuitry that couples a feedback path of the PLL to an output of the PLL for open loop operation and couples the feedback path of the PLL to an output of the power amplifier circuitry for closed loop operation. Prior to switching the feedback path from the output of the PLL to the output of the power amplifier circuitry, time alignment circuitry operates to time-align feedback signals from the outputs of the PLL and the power amplifier circuitry such that switching from open loop operation to closed loop operation causes minimal phase disturbance.

Abstract: There is provided a flexible transmission device capable of automatically setting an optimal point for a signal decision making with high accuracy, so that highly reliable high-quality signal regeneration control is achieved. A clock timing extraction circuit dynamically sets a frequency-dividing ratio based on the transmission rate of an input signal to perform a phase synchronization control so that there is a fixed phase difference between the input signal and an oscillation output, whereby clock timing based on the transmission rate can be extracted. A regeneration control circuit sequentially sweeps a voltage threshold level and the phase of the extracted cock with respect to the input signal and determines whether the levels of adjacent monitor points match, whereby a decision point within the valid zone of the eye pattern can be automatically measured and used as the optimal point for regeneration control.

Abstract: An integrated circuit radio frequency (RF) transmitter includes a phase locked loop having a multi-mode loop filter that is operable to provide wide band response with a fast settle time in a startup mode of operation and a relatively more narrow response with a longer settle time but with improved filtering in a steady state mode of operation according to one embodiment of the invention. The multi-mode loop filter includes, in one embodiment, selectable resistance circuitry for selecting between a plurality of resistance values based upon a two-state multi-mode control signal to provide the selected resistance values and selectable capacitance circuitry for selecting between a plurality of capacitance values based upon the two-state multi-mode control signal and for operatively coupling selected capacitors to selected resistors to provide the selected capacitance values.

Abstract: A measuring apparatus employing a differential transformer includes a high-frequency oscillator which generates a high-frequency signal having a frequency higher than the excitation frequency of the differential transformer, a frequency divider which divides the high-frequency signal to generate a driving signal for the differential transformer, a multiplier or divider which reduces the frequency of the high frequency signal by the frequency of the driving signal, a mixer which mixes the output from the multiplier or the divider with the output from the differential transformer, a high-pass filter or a band-pass filter which cuts a low-frequency component of the output from the mixer, and a double balanced mixer which synchronously detects the output from the high-pass filter or the band-pass filter with the use of the high-frequency signal.

Abstract: A television tuner includes a tuning circuit having two first varactor diodes for changing a tuning frequency, a mixer for converting a television signal to an intermediate frequency signal, an oscillator having a second varactor diode, and a PLL circuit for outputting a tuning voltage for tuning the television signal. The tuning voltage is applied to cathodes of the first varactor diodes and the second varactor diode, and voltages of anodes of the first varactor diodes and the second varactor diode are higher at a time of receiving the television signal whose frequency is lower than or equal to a predetermined frequency than at a time of receiving a television signal whose frequency is higher than the predetermined frequency.

Abstract: A combined transmission unit for TMDS signals and LVDS signals. First (LVDS) and second (TMDS) transmission units are both coupled to a first set of input terminals. A switching controller, according to a mode selection signal, enables the first transmission unit to transmit the first data on the set of input terminals to first external input units through a pair of first signal lines or enables the second transmission unit to transmit the first data on the set of input terminals to the second external input units through a pair of second signal lines.

Abstract: A phase-locked-loop device includes a clock generator for generating a reference clock based on a binarized playback signal and a frequency of run-length data and for generating N-phase clocks using the reference clock, a pulse-length measuring device for measuring a pulse length of the binarized playback signal using the N-phase clocks to output pulse-length data, and a run-length-data extracting device for counting the pulse-length data based on a virtual channel clock to extract run-length data. Pulse-length data is generated using the N-phase clocks (e.g., 16-phase clocks). The pulse-length data is counted based on the virtual channel clock to extract run-length data. Thus, it is not needed to generate a high-frequency clock, and the operating frequency is maintained sufficiently low.

Abstract: A digital terrestrial tuner has an RF input connected to a filter arrangement, whose output signal is supplied to a zero intermediate frequency frequency changer. The filter arrangement comprises a plurality of signal paths of different frequency responses. The signal paths are selectable one at a time for insertion between the tuner input and the frequency changer. At least one of the signal paths comprises a non-tracking filter which provides attenuation of out-of-band signals so as to reduce harmonic mixing caused by harmonics of the frequency changer commutating signal or by harmonics of spurious signals at lower frequencies.

Abstract: A packet stream multiplexer may include one or more control loops (e.g., digital phase locked loops) for tracking the source clock frequency associated with a packet stream. A first control loop may slowly drive an error between a received timestamp and an estimated timestamp to zero. A second control loop may more quickly drive a first derivative of the error to zero. The second control loop may include a set of digital filters ordered according to tracking speed. The output of the slowest filter is initially selected for updating the source clock frequency estimate. As time progresses, the faster filters are selected in succession. The estimated source clock frequency is used to restamp packets of the packet stream as they are sent out onto an output channel.

Abstract: A broadband modulation PLL includes a PLL portion containing a voltage controlled oscillator (101), a frequency divider (105), a phase comparator (104) and a loop filter (103). A frequency-dividing ratio of the frequency divider (105) is controlled to apply modulation, and also an input voltage of the voltage controlled oscillator (101) is controlled to apply modulation. One of phase modulation data for controlling the frequency dividing ratio and phase modulation data for input voltage of the voltage controlled oscillator (101) is inverted in phase by using an inverter (113), and the delay control circuit (110) detects a timing error on the basis of a signal (133) achieved by adding the output signals (131) and (132) of the filter (106) and the loop filter (103), and the timing is controlled by the delay circuits (111) and (112) to correct, the timing error.

Abstract: A method of controlling a phase locked loop in a mobile station and a mobile station of a cellular telecommunications system are provided. The mobile station comprises an integrated phase locked loop for generating output frequencies; a frequency control unit for providing a frequency control word for the phase locked loop, according to which frequency control word an output frequency is generated; and a tuning unit for providing a synchronized tuning word for the phase locked loop, the tuning unit being configured to output the synchronized tuning word to the phase locked loop in synchronization with the output of the frequency control word. The invention reduces the settling time of a mobile station when an operating frequency is changed from one to another.

Abstract: An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Abstract: An electronic tuning system includes an electronic tuner for adjusting the predetermined control voltage of a voltage controlled oscillator (VCO) to tune the local frequency signal to radio waves on an arbitrary channel in accordance with channel selection information. A booster circuit boosts a source voltage to generate a boosted voltage in order to ensure the predetermined control voltage. A non-volatile memory stores the channel selection information in response to a predetermined write voltage. The boosted voltage of the booster circuit is utilized as the predetermined write voltage.

Abstract: An audio demodulating circuit in accordance with the present invention for demodulating audio signals in a plurality of broadcast systems of mutually different frequency deviations such as the NTSC and the PAL, is arranged such that a connection between a trap circuit for suppressing adjacent interference and an intermediate frequency signal line can be controlled without using an externally applied special signal, based on a control voltage applied from a phase comparator with respect to a voltage control oscillator which generates a local oscillation signal for extracting an audio signal from the intermediate frequency signal.

Abstract: In some embodiments of the present invention, multiple voltage controlled capacitor branches may be employed in a tuning circuit. Each of the multiple voltage controlled capacitors branches may be set to somewhat apart resonance frequency so that a composite resonance derivative curve forms an equi-ripple curve with an improved tuning sensitivity linearization.

Abstract: The apparatus measures timing variations, such as the jitter or wander in a timing signal (100) of a telecommunications network. A recovered clock signal is sampled and digitized to produce a series of digital clock samples which are then processed (135) with reference to a local digital reference signal to produce digital baseband frequency in-phase (I) and quadrature (Q) components (165, 170) these being further processed (145) to produce the digital phase information of said clock signal to determine (175) the required parameters of the network. The step of digitally processing said clock samples with reference to a local reference signal can be conveniently and cheaply implemented using a digital signal down-converter IC (135), for example of a type existing for digital radio receiver implementations. For jitter measurement, the local reference signal may be generated by a phase-locked loop (as in FIG. 2). For wander measurements an external reference clock is used (as in FIG. 3).

Abstract: A communication system for transmitting data between cores embedded in an integrated circuit on a silicon chip. Communication system includes transmitter circuitry for wirelessly transmitting data between cores and receiver circuitry for wirelessly receiving the transmission of data from other cores. Both transmitter circuitry and receiver circuitry may include of a phase-locked loop circuit having a voltage-controlled oscillator. Each core may transmit and receive data on a unique frequency with respect to other cores embedded in an integrated circuit on a silicon chip or transmit and receive data on the same frequency as other cores embedded in an integrated circuit on a silicon chip. Groups of cores may share transmitter and receiver circuitry.

Abstract: The invention provides a communication semiconductor integrated circuit device (RF IC) capable of pulling in the frequency of a PLL circuit to a desired set frequency at high speed even in the case where a frequency settable range of the PLL circuit is wide without providing a current source other than a current source for charging and discharging in an normal operation. An oscillator as a component of a PLL circuit is constructed so as to be operative in a plurality of bands. In a state where a control voltage of the oscillator is fixed to a predetermined value, an oscillation frequency of the oscillator is measured in each of bands and stored in a storing circuit. A set value for designating a band supplied at the time of PLL operation is compared with the stored measured frequency value. From a result of comparison, a band to be actually used in the oscillator is determined, and a frequency difference between the maximum frequency of the selected band and the set frequency is obtained.

Abstract: Receiver comprising an RF front end circuit for a selection and conversion of an RF input signal into a pair of quadrature IF (intermediate frequency) signals being supplied through in-phase and phase quadrature signal paths to signal inputs of quadrature phase detection elements, such as in-phase and phase quadrature phase detectors included in a (PLL) phase locked loop, an output of the quadrature phase detection elements being coupled through a loop filter to a control input of a quadrature IF oscillator supplying a pair of quadrature IF oscillator signals to carrier inputs of the quadrature phase detection elements.

Abstract: A combined transmission unit for TMDS signals and LVDS signals. A first (LVDS) transmission unit includes a set of first input terminals to receive first data, and a second (TMDS) transmission unit includes a set of second input terminals to receive second data. A phase locked loop (PLL) generates a first set of output clock signals to the first transmission unit in a first mode and a second set of output clock signals to the second transmission unit in a second mode according to a mode selection signal. The first and second transmission units are able to transmit the first data to the first and second external input units in the first and second modes respectively, according to the mode selection signal and the first and second sets of output clock signals.

Abstract: Adjustment circuitry in a phase-locked loop (PLL) adjusts a sampling point to any desired location within a bit period of each bit of received high-speed serial data. The adjustment circuitry, responsive to program control, selectively adds current portions to a charge pump error current output thereby adjusting a feedback signal frequency to shift the serial data sampling point. A plurality of current mirror devices is scaled, with respect to a reference current device, to provide ?I current portions. A current control module controls the current portions magnitude and a sign of the current portions. The adjustment circuitry further controls charge pump programmable current sources in order to set a desired operating point of the PLL. The programmable current sources are controlled by a bias voltage and a plurality of selectable serial and parallel coupled resistors.

Abstract: A device and a method for processing high data rate serial data includes circuitry for recovering a clock based on the high data rate input data stream. A transceiver includes a coarse loop of a phase-locked loop that selectively provides a clock having accuracy that is within a specified amount. In a sample mode of operation, only the coarse loop PLL is coupled to provide an error signal from which an oscillation signal and clock may be derived. In a second mode (lock) of operation, the transceiver may lock to the received serial data stream by coupling the fine loop PLL to provide an adjusted error signal. In a third mode of operation, (automatic) the transceiver initially performs coarse loop calibration by de-coupling the fine loop PLL and coupling the coarse loop PLL until a steady state has been reached.

Abstract: A reference signal enhancement device for phase lock loop oscillator. In the reference signal enhancement device, a band pass filtering unit is coupled to a reference signal to filter high frequency noise, low frequency noise, and harmonic components of the reference signal or components with frequency exceeding a predetermined frequency in the reference signal. A signal amplification device including three amplifiers connected in series is coupled to the band pass filter to convert the filtered reference signal.

Abstract: A power management circuit is arranged to apply power to and remove power from its own oscillator to conserve power. A power-on reset circuit provides a power-on-reset signal to a state machine. The state machine contains states that are programmed with information that is used to power up or down various subsystems within a device that includes the power management systems, including the oscillator of the state machine. The state machine assumes a known state and applies power to the oscillator in response to the power-on-reset signal. The state machine changes states in response to system events (e.g., a keypress). The state machine also maintains power to the oscillator during the period of time and which the state machine requires clock signal from the oscillator. The state machine can power down the oscillator to conserve power when the state machine does not require a clock signal from the oscillator.