Abstract: Methods and systems for clocking FM transmit, FM receive and near field communication functions using DDFS are disclosed. Aspects of one method may include generating a Bluetooth signal that may comprise, for example, I and Q components, or Bluetooth local oscillator (LO) signals, for use in Bluetooth communication. One of the two Bluetooth LO signals may then be used by a DDFS to generate I and Q LO signals for FM reception and/or transmission. One of the I and Q LO signals for FM communication may be used by another DDFS to generate at least one LO signal for near field communication (NFC) transmission and/or reception. While the Bluetooth LO signal may vary in frequency as Bluetooth frequency hopping occurs, the FM LO signals may remain constant for a specific channel frequency. Similarly, while the FM LO signals may be changed to tune to different FM channels, the NFC LO signals may remain at a constant frequency.

Abstract: The invention relates to a radio-frequency circuit comprising: a control unit; and a phase-locked loop; wherein the control unit is arranged to determine an offset between an actual value of a reference frequency at the input to the loop on the basis of a measurement of the signal output from the filter of the loop, and a theoretical value of said frequency known to the control unit, via a relation known to the control unit, and to control a correction of said offset.

Abstract: All-digital techniques for generating periodic digital signals having selectable duty cycles. In one aspect, a computation block is provided for computing the product of a selected duty cycle and a discrete ratio between a reference clock period and a high-frequency oscillator period. The computation block may be coupled to a pulse width generator for generating signals having pulse widths that are integer multiples of the high-frequency oscillator period. In another aspect, a pulse width generator may also accommodate mixed fractional multiples of high-frequency oscillator periods by tapping the individual inverter stages of a delay line matched to the individual inverter stages of a ring oscillator exemplary embodiment of the high-frequency oscillator.

Abstract: The present invention relates to a quadrature divider which may be used in a phase locked loop or frequency synthesizer or with a single side band mixer. According to a preferred embodiment the divider takes a quadrature input and has a quadrature output. The divider has four analog mixers 1, 2, 3 and 4. The first two mixers 1, 2 take the in-phase quadrature input, while the second mixers 3, 4 take the quadrature-phase quadrature input. The outputs and feedback loops of the mixers are properly arranged such that the in-phase and quadrature-phase outputs of the divider have a determinisitic phase sequence relationship based on the phase sequence relationship of the corresponding quadrature inputs. Third order harmonics may be minimized or reduced by addition or subtraction of the mixer outputs. As the divider is able to take a quadrature input, there is no need for a dummy divider in the phase locked loop, thus saving space and power.

Abstract: The transmitter of the transceiver includes: a transmitter-side mixers of a transmitter-side modulator; a transmitter-side voltage-controlled oscillator; and a transmitter-side divider. The divider having a dividing factor of a non-integral number is supplied with an oscillating output of the oscillator. A pair of non-quadrature local signals having a phase difference of 90° plus a predetermined offset angle is produced by the divider and supplied to the mixers. The transmitter includes a phase-shift unit which converts a pair of quadrature transmit signals having a phase difference of about 90° on an analog basis into a pair of non-quadrature shifted transmit signals. Consequently, quadrature modulation is performed by the mixers. Use of a similar configuration enables the reduction in interference of an RF signal with local signals supplied to receiver-side mixers of the receiver.

Abstract: A transmitter includes an input unit, a transmission phase locked loop PLL, a local PLL, and a synthesis unit. The input unit is configured to generate a division control signal based on an input signal and channel information. The transmission PLL is configured to generate a modulation signal having a frequency of a GHz band, which varies in response to the division control signal. The local PLL is configured to generate a local signal having the GHz band. The synthesis unit is configured to frequency-synthesize the modulation signal and the local signal to output a transmission signal of a MHz band.

Abstract: A method of controlling a transport mechanism allows a first mobile carrier to move based on a power source incorporated in the first mobile carrier when an instructions signal specifying an access to a cell defined in a storage is supplied to a controller. When a fault is detected in the first mobile carrier, the first mobile carrier is moved based on the action of a second mobile carrier. The method ensures the movement of the first mobile carrier with the assistance of the second mobile carrier even when the first mobile carrier suffers from a fault. The first mobile carrier can be moved out of the movable range of the second mobile carrier. The second mobile carrier is allowed to move in the own movable range without an interference to the first mobile carrier. The second mobile carrier keeps operating without an interruption.

Abstract: Techniques involving the generation of signals at particular frequencies are disclosed. For instance, an apparatus may include an oscillator module, a synthesizer module, and a control module. The oscillator module produces an oscillator signal having a first frequency. From the oscillator signal, the synthesizer module produces an output signal having a second frequency. A frequency multiplier corresponds to the first and second frequencies. The control module selects the first frequency and the frequency multiplier such that a difference between the second frequency and a nearest integer multiple of the first frequency is greater than a predetermined threshold. As a result, reductions in spurious outputs may be achieved.

Abstract: An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Abstract: A frequency plan is provided for particular use in a transceiver. Advantageously, a single oscillator may be used to generate desired frequency signals. One or more power splitters receive the signal and equally divide the signal into first and second signals having a frequency substantially equal to the original. Multipliers on each arm of the transceiver receive a signal and increase the frequency of the signal. In one exemplary embodiment, multiple signals having different frequencies may be transmitted over the same cable due in part to the generated frequency separation between the signals. In another exemplary embodiment, multiple signals may be transmitted over multiple cables. In another exemplary embodiment, the frequency plan may self correct a transmit signal based on a reference signal, such as the receive signal. Additionally, multiple signals over one or more cables may be transmitted at or below 3 GHz.

Abstract: A frequency plan is provided for particular use in a transceiver. Advantageously, a single oscillator may be used to generate desired frequency signals. One or more power splitters receive the signal and equally divide the signal into first and second signals having a frequency substantially equal to the original. Multipliers on each arm of the transceiver receive a signal and increase the frequency of the signal. In one exemplary embodiment, multiple signals having different frequencies may be transmitted over the same cable due in part to the generated frequency separation between the signals. In another exemplary embodiment, multiple signals may be transmitted over multiple cables. Additionally, multiple signals over one or more cables may be transmitted at or below 3 GHz.

Abstract: An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Abstract: A near field communication front-end includes an up conversion module, a plurality of coils, and a down conversion module. The up conversion module is coupled to convert an outbound symbol stream into a plurality of outbound signals based on a frequency-space encoding scheme. The plurality of coils is coupled to electromagnetically transmit the plurality of outbound signals and to electromagnetically receive a plurality of inbound signals in accordance with the frequency-space encoding scheme. The down conversion module is coupled to convert the plurality of inbound signals into an inbound symbol stream in accordance with the frequency-space encoding scheme.

Abstract: A method for operating an integrated transceiver, comprising coupling an operating transmitter and an operating receiver within the integrated wideband receiver, inputting a signal into the operating transmitter, performing a first conversion of the signal, wherein the signal is converted into a second signal, transmitting the second signal into the operating receiver, performing a second conversion of the signal, wherein the signal is converted into a third signal, transmitting the third signal into the operating transmitter, and adjusting the operating transmitter.

Abstract: A semiconductor device includes an antenna circuit for receiving a wireless signal, a power supply circuit generating power by the wireless signal received by the antenna circuit, and a clock generation circuit to which power is supplied. The clock generation circuit includes a ring oscillator which self-oscillates and a frequency divider which adjusts frequency of an output signal of the ring oscillator in an appropriate range. A digital circuit portion is driven by a clock having high frequency accuracy, so that a malfunction such as an incorrect operation or no response is prevented.

Abstract: The present invention provides architectures and methods which use multiple radio receive chains in mobile devices to boost performance of the mobile devices. While a first set of the receive chains are assigned to a serving base station, another set of receive chains are dynamically allocated to neighbor base stations and/or to the serving base station depending upon present or expected system conditions and timing. A first synthesizer is configured to provide signals to the first and second set of receive chains. Other synthesizers are also configured to provide signals to the second set of receive chains. Thus, depending on the mode of operation, the second set of receive chains utilizes signals from a given synthesizer as needed. A priori data may be used to allocate specific receive chains to the serving base station, neighboring base stations or both. Unused synthesizers may be turned off to conserve power.

Abstract: A far field radio frequency identification (RFID) reader includes a baseband processing module, a transmitter section, and a receiver section. The receiver section includes a low noise amplifier module, a down conversion module, and a current mode blocking circuit. The low noise amplifier module amplifies an inbound RF signal to produce an amplified inbound RF signal. The down conversion module converts the amplified inbound RF signal into the inbound baseband signal. The current mode blocking circuit substantial compensates for a blocking current component of the baseband inbound signal and passes, substantially unattenuated, a signal current component of the baseband inbound signal.

Abstract: A configurable transceiver includes an RF receiver section that generates at least one downconverted signal from a received RF signal. A receiver processing module processes at least one downconverted signal in a plurality of receiver stages to produce a stream of inbound data, wherein the receiver processing module is configurable in response to a control signal to selectively bypass at least one of the plurality of receiver processing stages. A transmitter processing module processes outbound data in a plurality of transmitter stages to produce at least one baseband signal, wherein the receiver processing module is configurable in response to the control signal to selectively bypass at least one of the plurality of transmitter processing stages. An RF transmitter section generates at least one RF signal from the at least one baseband signal.

Abstract: An oscillator circuit having a source of an oscillating signal, a tank circuit including an inductor and a capacitor, and a discretely switchable capacitance module configured to control an amount of capacitance in the oscillator circuit. The discretely switchable capacitance module includes, in one embodiment, a capacitor coupled between a first node and a second node, a switch, having a control node, coupled between the second node and a third node; and a DC feed circuit, having a first end coupled to the second node and a second end configured to receive a first or second control signal. The control node of the switch is tied to a predetermined bias voltage. When the first control signal is applied, the capacitor is coupled between the first node and the third node via the switch such that the capacitor is coupled in parallel with the capacitor of the tank circuit, and when the second control signal is applied the capacitor is decoupled from the tank circuit.

Abstract: The transmitter of the transceiver includes: a transmitter-side mixers of a transmitter-side modulator; a transmitter-side voltage-controlled oscillator; and a transmitter-side divider. The divider having a dividing factor of a non-integral number is supplied with an oscillating output of the oscillator. A pair of non-quadrature local signals having a phase difference of 90° plus a predetermined offset angle is produced by the divider and supplied to the mixers. The transmitter includes a phase-shift unit which converts a pair of quadrature transmit signals having a phase difference of about 90° on an analog basis into a pair of non-quadrature shifted transmit signals. Consequently, quadrature modulation is performed by the mixers. Use of a similar configuration enables the reduction in interference of an RF signal with local signals supplied to receiver-side mixers of the receiver.

Abstract: A balanced transmitter up-converts a baseband signal directly from baseband-to-RF. The up-conversion process is sufficiently linear that no IF processing is required, even in communications applications that have stringent requirements on spectral growth. In operation, the balanced modulator sub-harmonically samples the baseband signal in a balanced and differential manner, resulting in harmonically rich signal. The harmonically rich signal contains multiple harmonic images that repeat at multiples of the sampling frequency, where each harmonic contains the necessary information to reconstruct the baseband signal. The differential sampling is performed according to a first and second control signals that are phase shifted with respect to each other. In embodiments of the invention, the control signals have pulse widths (or apertures) that operate to improve energy transfer to a desired harmonic in the harmonically rich signal.

Abstract: In one example, a Bluetooth enabled navigation device pairs with a mobile phone and then sends a plurality of tuning transmissions, each at a different transmission power gain amount, to a remote server using the mobile phone. These tuning transmissions are encoded using frequency tones that synthesize speech for transmission through the mobile phone and a voice channel of its wireless telecommunications network. The navigation device then tunes transmit power settings according to a received response to the tuning transmissions and uses the tuned transmit power settings for subsequent transmission to the remote server using this particular mobile phone.

Abstract: Aspects of a method and system for a Multisystem Polar Transmitter may include a single integrated circuit comprising one or more Direct Digital Frequency Synthesizer (DDFS). The single integrated circuit may generate a plurality of signals compliant with at least a first wireless protocol and a second wireless protocol. At least one of the plurality of signals is polar modulated using the DDFS. The single integrated circuit may comprise a plurality of wireless transmitters. In another embodiment of the invention, a plurality of baseband signals compliant with the first and second protocols may be combined. The first protocol may be Bluetooth® and the second protocol may be Wireless LAN. The combined plurality of baseband signals may be modulated via a single wireless transmitter on the integrated circuit. The phase and frequency for polar modulation may be adjusted using the DDFS, while the amplitude may be adjusted using an amplifier.

Abstract: Techniques for generating oscillator signals in a wireless communication device are described. A phase-locked loop (PLL) may be used to generate an oscillator signal for a selected frequency channel. Different PLL settings may be used for the blocks in the PLL for different frequency channels. The different PLL settings may be for different PLL loop bandwidths, different amounts of charge pump current, different frequency equations associated with different sets of high and low divider ratios, different frequency division schemes associated with different prescaler ratios and/or different integer divider ratios, high side or low side injection for a super-heterodyne receiver or transmitter, and/or different supply voltages for one or more circuit blocks such as an oscillator. A suitable set of PLL settings may be selected for each frequency channel such that adverse impact due to spurs can be mitigated.

Abstract: Apparatus and methods for setting wakeup times in a communication device are disclosed where setting the wakeup times includes estimating the lock on time of a frequency synthesizer in order to minimize the wakeup time and extend sleep times for maximal energy savings. A disclosed apparatus includes an estimator to receive a current lock on time of a frequency synthesizer, which is the time taken by the frequency synthesizer to lock on to particular frequency after a wakeup signal has been issued to turn on the synthesizer after a sleep period. The estimator calculates a latest estimated lock on time based at least on the current lock on time of the frequency synthesizer and determines an enable signal timing information based on the estimated lock on time. The apparatus also includes a timer configured to receive the enable signal timing information and issue at least one enable signal to turn on other circuitry in the transceiver after the synthesizer lock on period based thereon.

Abstract: Methods and circuits for synthesizing two or more signals phase-locked to a common reference frequency signal are disclosed. In one embodiment, a method comprises generating first and second output signals phase-locked to a reference clock signal, using first and second phase-locked loop circuits. In response to a detected frequency error in the first output signal, the first output signal is corrected by adjusting a frequency-division ratio in the first phase-locked loop circuit. The second output signal is corrected, separately from the correction to the first output signal, by adjusting a frequency-division ratio in the second phase-locked loop circuit, using an adjustment parameter calculated from the detected frequency error. In another exemplary method, first and second output signals are generated as described above, using first and second phase-locked loop circuits.

Abstract: Disclosed is an oscillator circuit (10) for use in a local oscillator of an RF communications device (100) that communicates over an RF channel. The oscillator circuit includes an oscillator transistor coupled to a power supply voltage (Vcc) through a buffer transistor, and a biasing network having bias voltage outputs coupled to a control input of the oscillator transistor and to a control input of the buffer transistor. In one embodiment the bias voltage network is coupled to Vcc, while in another embodiment the bias voltage network is coupled to a separate voltage (Vbias). Circuitry is provided for setting a magnitude of Vcc and/or Vbias as a function of at least one of RF channel conditions, such as channels conditions determined from a calculation of the (SNR), or an operational mode of the RF communications device.

Abstract: A balanced transmitter up-converts I and Q baseband signals directly from baseband-to-RF. The up-conversion process is sufficiently linear that no IF processing is required, even in communications applications that have stringent requirements on spectral growth. In operation, the balanced modulator sub-harmonically samples the I and Q baseband signals in a balanced and differential manner, resulting in harmonically rich signal. The harmonically rich signal contains multiple harmonic images that repeat at multiples of the sampling frequency, where each harmonic contains the necessary information to reconstruct the I and Q baseband signals. The differential sampling is performed according to a first and second control signals that are phase shifted with respect to each other. In embodiments of the invention, the control signals have pulse widths (or apertures) that operate to improve energy transfer to a desired harmonic in the harmonically rich signal.

Abstract: A receiver for frequency down converting a radio frequency signal (10) using a multistage frequency (down) conversion. The radio frequency signal (10) having a center frequency that is comprised in one of at least two frequency bands, comprises oscillating means (20) for generating a first mixing signal (11) having a first frequency. And also a frequency divider (22) arranged to derive a second mixing signal (13) from the first mixing signal. The receiver further comprising a first mixer (12) arranged to down-convert the radio frequency signal (10) to a first lower frequency signal (15) using the first mixing signal (11) and a second mixer arranged to down-convert the first low frequency signal to a second lower frequency signal (18) using the second mixing signal (13). Wherein the division factor of the frequency divider and a ratio between the center frequency and the first frequency are determined by the one of at least two frequency bands.

Abstract: A wireless communication terminal includes a crystal oscillator, a transceiver and circuitry. The crystal oscillator belongs to a specified type of crystal oscillators in which a dependence of an output frequency as a function of temperature has one or more parameters that vary among the crystal oscillators belonging to the specified type. The transceiver is arranged to perform signal processing operations to a communication signal using the output frequency of the crystal oscillator. The circuitry is arranged to determine a characteristic of the output frequency of the crystal oscillator at one or more operating temperatures, to compute the one or more parameters for the crystal oscillator based on the determined characteristic and the operating temperatures, and to correct a frequency error in the output frequency of the crystal oscillator using the dependence and the computed parameters.

Abstract: Frequency conversion methods and systems for Bluetooth and FM radio communication are provided. FM data may be received and/or transmitted via the FM radio and Bluetooth data may be received and/or transmitted via the Bluetooth radio. With an integration of frequency conversion for Bluetooth and FM, both systems can operate from a single frequency source, thereby reducing part count and power consumption. Communication between Bluetooth and FM channels may be enabled via a single chip.

Abstract: A demodulation section 13 receives a TDMA-TDD based phase-modulated burst signal of mobile communications and demodulates the burst signal by a synchronous detection system (or a quasi-synchronous detection system). The demodulation section 13 includes a frequency deviation compensation section and a carrier recovery section each having a loop filter 14 with three or more stages of time constants. The time constants are switched by a selector switch 15 based on a control signal from a demodulation control section 16. This achieves quick pull-in and jitter after convergence is minimized, thereby allowing highly efficient performance of frequency deviation compensation, etc. that is required for synchronous detection (or quasi-synchronous detection) without increasing the size of circuit.

Abstract: In one embodiment, this disclosure describes a frequency synthesizer for use in a wireless communication device, or similar device that requires precision frequency synthesis but small amounts of noise. In particular, the frequency synthesizer may include a phase locked loop (PLL) and an integrated voltage controlled oscillator (VCO). The frequency synthesizer may implement one or more calibration techniques to quickly and precisely calibrate the VCO. In this manner, the analog gain of the VCO can be significantly reduced, which may improve performance of the wireless communication device. Also, the initial state of the PLL may be improved to reduce lock time of the PLL, which may enhance performance of the wireless communication device.

Abstract: A technique for agile region and band conscious frequency planning for wireless transceivers in which a comparison frequency is selected for generating a local oscillator signal. The comparison frequency (Fcomp) is selected for a frequency band of a particular communication standard or protocol, in order not to introduce harmonic components of the selected comparison frequency in a transmitted signal from the wireless device that generates spurious emissions restricted by the particular communication protocol or another protocol. The Fcomp selection may also take into consideration restrictive region-specific criteria for out-of band spurious emissions.

Abstract: An integrated circuit may enable transmission and reception of Bluetooth signals as well as FM signals. One or more clock signals may be generated via a phase-locked loop and may be utilized to enable Bluetooth transmission and reception. Bluetooth clock signals and frequency control words may be utilized by a direct digital frequency synthesizer to generate FM carrier signals that enable FM reception as well as digitally modulated signals for FM transmission. FM reception and transmission may be time division duplex. Frequency control words may be adjusted to compensate for variations in the Bluetooth clock signal frequency for FM carrier signals used in FM reception. Moreover, frequency control words may be adjusted to modulate a signal about the frequency of an FM carrier for transmission. Each of the Bluetooth clock signals, carrier signals and modulated signals comprise an in-phase component and a quadrature-phase component.

Abstract: A radio transceiver device includes circuitry for radiating electromagnetic signals at a very high radio frequency both through space, as well as through wave guides that are formed within a substrate material. In one embodiment, the substrate comprises a dielectric substrate formed within a board, for example, a printed circuit board. In another embodiment of the invention, the wave guide is formed within a die of an integrated circuit radio transceiver. A plurality of transceivers with different functionality is defined. Substrate transceivers are operable to transmit through the wave guides, while local transceivers are operable to produce very short range wireless transmissions through space. A third and final transceiver is a typical wireless transceiver for communication with remote (non-local to the device) transceivers. Additionally, a multi-mode transceiver is operable to configure transmit and receive circuitry based upon transmission path.

Abstract: Methods and systems for clocking FM transmit, FM receive and near field communication functions using DDFS are disclosed. Aspects of one method may include generating a Bluetooth signal that may comprise, for example, I and Q components, or Bluetooth local oscillator (LO) signals, for use in Bluetooth communication. One of the two Bluetooth LO signals may then be used by a DDFS to generate I and Q LO signals for FM reception and/or transmission. One of the I and Q LO signals for FM communication may be used by another DDFS to generate at least one LO signal for near field communication (NFC) transmission and/or reception. While the Bluetooth LO signal may vary in frequency as Bluetooth frequency hopping occurs, the FM LO signals may remain constant for a specific channel frequency. Similarly, while the FM LO signals may be changed to tune to different FM channels, the NFC LO signals may remain at a constant frequency.

Abstract: Aspects of a method and system for transmission or reception of signals utilizing a DDFS clocked are provided. A first oscillator signal utilized for transmission and/or reception of signals of a first wireless communication protocol may be generated, and a direct digital frequency synthesizer (DDFS) may be clocked by the first oscillator signal to generate one or more second oscillator signals. The one or more second oscillator signals may be modulated to generate a signal adhering to a second wireless communication protocol. The one or more second oscillator signals may be utilized to demodulate signals of the second wireless communication protocol. A control word input to the DDFS may control a frequency of the one or more second oscillator signals generated by the DDFS. Simultaneous transmission and reception of signals of the second wireless communication protocol may be simulated by switching the control word input to the DDFS between two values.

Abstract: An apparatus including a first circuit, a second circuit, a third circuit, and a fourth circuit. The first circuit may be configured to generate a demodulated signal in response to a modulated signal and a seed value selected in response to a first control signal. The second circuit may be configured to generate a second control signal in response to the demodulated signal. The third circuit may be configured to generate the first control signal in response to the second control signal, a compensation signal, and the first control signal, where generation of the first control signal includes adding the second control signal, the compensation signal, and a latched version of the first control signal. Generation of the latched version of the first control signal may include sampling the first control signal in response to a clock signal. The compensation signal may compensate for variation in the clock signal.

Abstract: A system and method providing variable-frequency IF conversion in a multimode communication device. Various aspects of the present invention provide a multimode communication device comprising at least one RF signal receiver adapted to receive at least a first RF signal corresponding to a first communication protocol and a second RF signal corresponding to a second communication protocol. A controllable frequency source may, for example, be adapted to output a mixing signal characterized by one of a plurality of selectable frequencies. Such selectable frequencies may, for example, comprise a first frequency corresponding to the first communication protocol and a second frequency corresponding to the second communication protocol. A mixer may, for example, receive a received RF signal from the RF signal receiver, receive a mixing signal from the controllable frequency source, and convert the received RF signal to an IF signal utilizing the received mixing signal.

Abstract: An object is to provide a PLL having a wide operating range. Another object is to provide a semiconductor device or a wireless tag which has a wide operating range in a communication distance or temperature by incorporating such a PLL. The semiconductor device or the wireless tag includes a first divider circuit; a second divider circuit; a phase comparator circuit to which an output of the first divider circuit and an output of the second divider circuit are provided; a loop filter to which an output of the phase comparator circuit is supplied and in which a time constant is switched in accordance with an inputted signal; and a voltage controlled oscillator circuit to which an output of the loop filter is supplied and which supplies an output to the second divider circuit.

Abstract: A mixer mixes respective signals of L1, L2C, and L5-E5a with a local oscillation signal where the frequency of the L1 signal has an image relationship with the frequencies of the L2C and L5-E5a signals to conduct frequency conversion. An image removal mixer mixes the respective position signals of 1stIF with a local oscillation signal where the frequency of the L1 signal of the 1stIF has an image relationship with the frequencies of the L2C signal and the L5-E5a signal of 1stIF to conduct frequency conversion. The image removal mixer then outputs the L1 signal of 2ndIF and the L2C and L5-E5a signals of 2ndIF, independently. A branching filter separates the L2C and L5-E5a signals of 2ndIF from each other, and outputs the separated signals.

Abstract: An electronic device includes a radio frequency (RF) modulator, a power amplifier, and a distortion correction circuit coupled between the RF modulator and the power amplifier. The distortion correction circuit includes a variable gain amplifier coupled between the RF modulator and the power amplifier, and an amplitude correction control loop. The amplitude correction control loop includes a first logarithmic converter having an input coupled to the RF modulator, a second logarithmic converter having an input coupled to an output of the power amplifier, and a difference circuit coupled to outputs of the first and second logarithmic converters for controlling the gain of the variable gain amplifier for correcting distortion in an output signal from the power amplifier.

Abstract: An RF transceiver apparatus comprises transmitter circuitry arranged to convert signals from a baseband frequency to RF transmission frequencies and receiver circuitry arranged to convert signals from RF reception frequencies to the baseband frequency. The transmitter and receiver circuitry each comprise three mixers arranged to convert a signals between the baseband frequency, a first intermediate frequency; a second intermediate frequency that is higher than the transmission frequencies; and a second intermediate frequency to the transmission frequency.

Abstract: A single sideband mixer circuit includes a voltage controlled oscillator operable a tunable frequency f1. The mixer circuit outputs a frequency signal at a frequency f1±f2. A tracking filter operates to filter the frequency signal and generate a first output signal at the frequency f1±f2. A resonance frequency fr of the tracking filter is tunable to substantially match the frequency f1±f2 of the frequency signal. The output signal of the tracking filter may be processed by a phase lock loop circuit to generate a control signal for controlling the setting of the tunable frequency f1 and resonance frequency fr. Alternatively, the output signal of the tracking filter may be divided and the divided signal processed by a phase lock loop circuit to generate the control signal for controlling setting of the tunable frequency f1 and resonance frequency fr.

Abstract: A configurable frequency conversion device includes an up-converter, which is arranged to convert an input transmit signal to an interim transmit signal at an intermediate transmit frequency and to convert the interim transmit signal to an output transmit signal at an output frequency. A down-converter is arranged to convert an input receive signal at an input frequency to an interim receive signal at an intermediate receive frequency and to convert the interim receive signal to an output receive signal. Local Oscillator (LO) generation circuitry is arranged to generate multiple LO signals having respective LO frequencies and is coupled to drive the up- and down-converter with the LO signals, and is externally configurable to modify one or more of the LO frequencies so as to modify any of the output frequency, the input frequency, and a separation between the output and input frequencies without changing the intermediate receive and transmit frequencies.

Abstract: A GPS RF Front End IC using a single conversion stage, which is immune from self jamming from clock signal harmonics generated internally or from dominant clock signal harmonics generated externally by the subsequent baseband GPS processor which uses a clock of 48?fo for GPS processing. The improved frequency plan reduces the problems of interference when the integration of the RF and Baseband functions is required in the form of a single-chip, or as 2 individual chips on a common substrate.

Abstract: A system is provided, the system includes a phase-locked loop (PLL) that multiplies a reference clock input to generate a communication link clock signal. The system also includes a transmitter/receiver (TX/RX) module coupled to the PLL, the TX/RX module is configured to transmit and receive data based on the communication link clock signal. The system also includes a divider coupled to the PLL, the divider receives the communication link clock signal and outputs a PLL-adjusted reference clock that approximates the reference clock input. The PLL-adjusted reference clock is used to generate at least one other communication link clock signal.

Abstract: A method for operating an integrated transceiver, comprising coupling an operating transmitter and an operating receiver within the integrated wideband receiver, inputting a signal into the operating transmitter, performing a first conversion of the signal, wherein the signal is converted into a second signal, transmitting the second signal into the operating receiver, performing a second conversion of the signal, wherein the signal is converted into a third signal, transmitting the third signal into the operating transmitter, and adjusting the operating transmitter.

Abstract: Disclosed is a recursive, direct digital synthesizer includes an accumulator module and a Coordinate Rotation Digital Computer (CORDIC) module coupled to the accumulator module. The CORDIC module rotates a signal according to a desired rotation angle specified by the accumulator module. An automatic gain control module is coupled to the CORDIC module. The automatic gain control module can apply a level of gain to the rotated signal.