Integrated Circuit Production Or Semiconductor Fabrication Patents (Class 700/121)
  • Patent number: 12242254
    Abstract: The disclosure relates to digital models of a production apparatus. The digital models can generate simulations of production sequences of the production apparatus, and a controller can access the simulation to improve operations of the production apparatus. The digital model uses data of a locating system to create the simulation. The locating system monitors carriers for transporting components. The controller can compare parameters of the simulation results with corresponding parameters of earlier simulation results and/or actually obtained parameters of earlier production sequences, which can be stored in a model library. The disclosure further relates to corresponding production control methods.
    Type: Grant
    Filed: November 3, 2021
    Date of Patent: March 4, 2025
    Assignee: TRUMPF Werkzeugmaschinen SE + Co. KG
    Inventors: Carina Mieth, Jens Ottnad
  • Patent number: 12237188
    Abstract: The current disclosure describes techniques for managing vertical alignment or overlay in semiconductor manufacturing using machine learning. Alignments of interconnection features in a fan-out WLP process are evaluated and managed through the disclosed techniques. Big data and neural networks system are used to correlate the overlay error source factors with overlay metrology categories. The overlay error source factors include tool related overlay source factors, wafer or die related overlay source factors and processing context related overlay error source factors.
    Type: Grant
    Filed: March 14, 2023
    Date of Patent: February 25, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tzu-Cheng Lin, Y. Y. Peng, Jerry Wang, Kewei Zuo, Chien Rhone Wang
  • Patent number: 12228910
    Abstract: Embodiments relate to a control method, apparatus, system, device and medium for production equipment. The method includes: receiving a recipe upload instruction, and generating a first control instruction in response to the recipe upload instruction to control the production equipment to upload first recipe data; receiving the first recipe data, and parsing the first recipe data to generate a corresponding first recipe file in a preset format; generating a second control instruction during parsing the first recipe data to control the production equipment to upload second recipe data; and receiving the second recipe data, and parsing the second recipe data to generate a corresponding second recipe file in a preset format.
    Type: Grant
    Filed: January 5, 2022
    Date of Patent: February 18, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Huan-Cheng Li
  • Patent number: 12222707
    Abstract: A production schedule estimation method and a production schedule estimation system are provided. The production schedule estimation method includes the following steps. Current-day work-in-process data, machine group cycle time data of a machine group, and productivity data of the machine group are obtained. The current-day work-in-process data, the cycle time data of the machine group, and the productivity data of the machine group are inputted into a prediction model. Current-day cycle time data and a current-day move volume for each of multiple stations in the machine group are calculated through the prediction model. And, current-day move data is calculated according to the current-day cycle time data and the current-day move volume for each of the multiple stations in the machine group.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: February 11, 2025
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Chih-Neng Liu, Chih-Chuen Huang, Chia-Jen Fu, Chih-Hsiang Chang
  • Patent number: 12222690
    Abstract: To facilitate evaluation of a predicted process shape in process recipe development using machine learning, a process recipe search apparatus that searches for an etching recipe that is a parameter of a plasma processing apparatus set so as to etch a sample into a desired shape displays, on a display device, the predicted process shape of the sample by a candidate etching recipe predicted by using a machine leaning model, by highlighting a difference between the predicted process shape and a target shape.
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: February 11, 2025
    Assignee: Hitachi High-Tech Corporation
    Inventors: Takashi Dobashi, Hiroyuki Kobayashi, Takeshi Ohmori
  • Patent number: 12225668
    Abstract: A production data creation device includes an input unit and a setting unit. The input unit receives an input of one application from among a plurality of applications displayed on a screen. The setting unit sets one or more operation parameters used by a component mounter to mount a component on a board, on the basis of the input application.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: February 11, 2025
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Eiji Shigaki, Taichi Shimizu, Takaaki Yokoi, Takuya Yamazaki
  • Patent number: 12216975
    Abstract: An aspect of the disclosed embodiments is a method for printed circuit board (PCB) component placement comprising: graphically displaying, on a display device, PCB design features of a PCB design; and providing a user interface control for designating one or more of the PCB design features as electrical contacts for a first selected electrical component. Other aspects are disclosed.
    Type: Grant
    Filed: December 28, 2023
    Date of Patent: February 4, 2025
    Assignee: Boardera Software 1nc.
    Inventors: Curtis Hunter, David Workman
  • Patent number: 12217986
    Abstract: A substrate treating apparatus for treating substrates includes a plurality of substrate treatment lines arranged vertically for carrying out plural types of treatment on the substrates while transporting the substrates substantially horizontally, and a controller for changing processes of treatment carried out on the substrates for each of the substrate treatment lines. By changing the processes of treatment carried out for the substrates for each substrate treatment line, the processes of treatment carried out for the substrates can be changed for each substrate conveniently. Thus, a plurality of different processes of treatment corresponding to the number of substrate treatment lines can be carried out in parallel for the respective substrates.
    Type: Grant
    Filed: January 8, 2021
    Date of Patent: February 4, 2025
    Assignee: SCREEN Semiconductor Solutions Co., Ltd.
    Inventors: Hiroyuki Ogura, Tsuyoshi Mitsuhashi, Yoshiteru Fukutomi, Kenya Morinishi, Yasuo Kawamatsu, Hiromichi Nagashima
  • Patent number: 12205061
    Abstract: A method for developing or improving a process for producing a product from a material comprising steps of acquiring the composition for at least two slurries as raw material data (17) for the CMP based manufacturing process and its relevant parameters (2) by using a Data Collecting computer (9); physically performing specific method steps of a CMP process; measuring relevant parameters of the used slurries and the physically performed CMP process to determine the CMP process performance by using the Data Collecting computer (9); analyzing the measured data about the relevant parameters with a specific software performed on an Analyzing computer (11) by creating for the software and applying with it a predictive model using Machine Learning to understand the intercorrelation of the different parameters and using the results to improve the CMP process performance and the resulting product quality of the CMP based manufacturing process.
    Type: Grant
    Filed: May 18, 2022
    Date of Patent: January 21, 2025
    Assignee: Versum Materials US, LLC
    Inventors: Cesar Clavero, Vid Gopal, Ryan Clarke, Esmeralda Yitamben, Hieu Pham, Anupama Mallikarjunan, Rung-Je Yang, Shirley Lin, Hongjun Zhou, Joseph Rose, Krishna Murella, Lu Gan
  • Patent number: 12204161
    Abstract: Methods and apparatuses for aligning and diagnosing the laser beam traversing an optical train in a highly space-efficient, lower cost and/or retrofit-friendly manner are disclosed. The optical components of the optical train are mounted such that one or more optical components can direct their exit laser beam to partially or wholly scan across one or more downstream sensors. Correlation data between physical disposition of optical components and the points of impact data and/or beam quality data are employed to, among others, align and/or diagnose the laser beam and/or localize failure sites and/or optimize maintenance schedule.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: January 21, 2025
    Assignee: Cymer, LLC
    Inventor: Donald Harrison Barnhart
  • Patent number: 12203828
    Abstract: The present disclosure relates to systems and methods for detecting anomalies in a semiconductor processing system. According to certain embodiments, one or more external sensors are mounted to a sub-fab component, communicating with the processing system via a communication channel different than a communication channel utilized by the sub-fab component and providing extrinsic sensor data that the sub-fab component is not configured to provide. The extrinsic sensor data may be combined with sensor data from a processing tool of the system and/or intrinsic sensor data of the sub-fab component to form virtual sensor data. In the event the virtual data exceeds or falls below a threshold, an intervention or a maintenance signal is dispatched, and in certain embodiments, an intervention or maintenance action is taken by the system.
    Type: Grant
    Filed: April 26, 2021
    Date of Patent: January 21, 2025
    Assignee: Applied Materials, Inc.
    Inventors: Ryan T. Downey, Hemant P. Mungekar, James L'Heureux, Andreas Neuber, Michael W. Johnson, Joseph A. Van Gompel, Gino Gerardo Crispieri, Tony H. Tong, Maxime Cayer, John L Koenig, Mike M. Huang
  • Patent number: 12197138
    Abstract: The current disclosure describes techniques for managing vertical alignment or overlay in semiconductor manufacturing using machine learning. Alignments of interconnection features in a fan-out WLP process are evaluated and managed through the disclosed techniques. Big data and machine learning are used to train a classification that correlates the overlay error source factors with overlay metrology categories. The overlay error source factors include tool signals. The trained classification includes a base classification and a Meta classification.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: January 14, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tzu-Cheng Lin, Chien Rhone Wang, Kewei Zuo, Ming-Tan Lee, Zi-Jheng Liu
  • Patent number: 12190418
    Abstract: One variation of a method for automatically generating a common measurement across multiple assembly units includes: displaying a first image—recorded at an optical inspection station—within a user interface; receiving manual selection of a particular feature in a first assembly unit represented in the first image; receiving selection of a measurement type for the particular feature; extracting a first real dimension of the particular feature in the first assembly unit from the first image according to the measurement type; for each image in a set of images, identifying a feature—analogous to the particular feature—in an assembly unit represented in the image and extracting a real dimension of the feature in the assembly unit from the image according to the measurement type; and aggregating the first real dimension and a set of real dimensions extracted from the set of images into a digital container.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: January 7, 2025
    Assignee: Instrumental, Inc.
    Inventors: Samuel Bruce Weiss, Anna-Katrina Shedletsky, John James Shedletsky, III, Isaac Sukin, Simon Kozlov
  • Patent number: 12190978
    Abstract: The present disclosure provides a memory test system, including a tester and a processor. The tester is configured to perform a final test to the memory device to obtain a test result, and read a read-only data of the packaged memory device. The processor is coupled to the tester, configured to perform a function to transform the read-only data to a chip ID of the packaged memory device when the memory device does not pass the final test according to the test result. When the packaged memory device does not pass the final test, the processor is further configured to obtain a process history of the packaged memory device according to the chip ID.
    Type: Grant
    Filed: October 19, 2023
    Date of Patent: January 7, 2025
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Cheng-Ting Hsu, Yung-Huang Liao
  • Patent number: 12190977
    Abstract: The present disclosure provides a memory test system, including a tester and a processor. The tester is configured to perform a final test to the memory device to obtain a test result, and read a read-only data of the packaged memory device. The processor is coupled to the tester, configured to perform a function to transform the read-only data to a chip ID of the packaged memory device when the memory device does not pass the final test according to the test result. When the packaged memory device does not pass the final test, the processor is further configured to obtain a process history of the packaged memory device according to the chip ID.
    Type: Grant
    Filed: March 29, 2023
    Date of Patent: January 7, 2025
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Cheng-Ting Hsu, Yung-Huang Liao
  • Patent number: 12189380
    Abstract: A method includes receiving first data associated with measurements taken by a sensor during a first manufacturing procedure of a manufacturing chamber. The method further includes receiving second data. The second data includes reference data associated with the first data. The method further includes providing the first and second data to a comparison model. The method further includes receiving a similarity score from the comparison model, associated with the first and second data. The method further includes performance of a corrective action in view of the similarity score.
    Type: Grant
    Filed: January 27, 2022
    Date of Patent: January 7, 2025
    Assignee: Applied Materials, Inc.
    Inventors: Sejune Cheon, Jeong Jin Hong, Mikyung Shim, Xiaoqun Zou, Jinkyeong Lee, Sang Hong Kim
  • Patent number: 12179112
    Abstract: Provided are a content playback program and a content playback device in which a character displayed on a display unit takes a predetermined reaction in response to a screenshot acquisition operation. When execution of a screenshot caused by a user's operation is detected in a state in which a character is displayed on the display unit, a content playback processing unit executes a production in which a facial expression of the character changes and/or a production in which the character speaks, immediately after completion of the screenshot.
    Type: Grant
    Filed: November 22, 2022
    Date of Patent: December 31, 2024
    Assignee: CYGAMES, INC.
    Inventor: Shuichi Kurabayashi
  • Patent number: 12174616
    Abstract: A control system operable to train a control tuner to generate temperature setpoint tracking improvements for a thermal processing system is provided. In one example implementation, temperature setpoint tracking improvements are achieved by generating system controller parameter adjustments based on a difference between a simulated workpiece temperature estimate and an actual workpiece temperature estimate. For example, a system model can generate a simulated workpiece temperature estimate simulating an actual workpiece temperature estimate, and based on the difference between the simulated and actual workpiece temperature estimates, generate clone controller parameter adjustments. The clone controller parameter adjustments can be used to generate system controller parameter adjustments, which can improve temperature setpoint tracking for the thermal processing system.
    Type: Grant
    Filed: May 8, 2023
    Date of Patent: December 24, 2024
    Assignees: Beijing E-Town Semiconductor Technology Co. Ltd., Mattson Technology, Inc.
    Inventors: Michael X. Yang, Markus Lieberer, Joseph Cibere
  • Patent number: 12173404
    Abstract: A method of depositing one or more epitaxial material layers, a device structure formed using the method and a system for performing the method are disclosed. Exemplary methods include coating a surface of a reaction chamber with a precoat material, processing a number of substrates, and then cleaning the reaction chamber.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: December 24, 2024
    Assignee: ASM IP Holding B.V.
    Inventors: Amir Kajbafvala, Caleb Miskin
  • Patent number: 12169674
    Abstract: This application discloses a computing system implementing a mask synthesis system to generate synthetic image clips of design shapes and corresponding mask data for the synthetic image clips. The mask data can describe lithographic masks capable of being used to fabricate the design shapes on an integrated circuit. The mask synthesis system can utilize the synthetic image clips of the design shapes and the corresponding mask data to train a machine-learning system to determine pixelated output masks from portions of the layout design. The mask synthesis system can identify one or more pixelated output masks for portions of a layout design describing an electronic system using the trained machine-learning. The mask synthesis system can synthesize a mask layout design for the electronic system based, at least in part, on the layout design describing the electronic system and the one or more pixelated output masks for the layout design.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: December 17, 2024
    Assignee: Siemens Industry Software Inc.
    Inventors: Nataraj Akkiraju, Ilhami Torunoglu
  • Patent number: 12158735
    Abstract: A method includes determining, by a processing device, whether a first process recipe including a set of Pareto efficient parameters is to be selected from a set of process recipes, wherein the set of Pareto efficient parameters fail to satisfy each target property of a set of target properties for processing the component, in response to determining that a first process recipe is not to be selected from a set of process recipes for processing the component, selecting, by the processing device from the set of process recipes, a second process recipe including a set of parameters satisfying each target property of the set of target properties, and causing, by the processing device, the component to be processed by a process tool using the second process recipe.
    Type: Grant
    Filed: September 8, 2023
    Date of Patent: December 3, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Dermot P. Cantwell, Taehun Kim
  • Patent number: 12148658
    Abstract: The present disclosure discloses a method for manufacturing an electronic device, including: setting a basic working area; a photoresist coating process; a development process; an etching process; an exposure process; a metal plating process; and a polishing process, wherein the photoresist coating process, the development process, the etching process, the exposure process, the metal plating process and the polishing process respectively have a maximum optimized process area, and a smallest one of the maximum optimized process areas is selected as the basic working area.
    Type: Grant
    Filed: December 5, 2022
    Date of Patent: November 19, 2024
    Assignee: InnoLux Corporation
    Inventors: Cheng-Chi Wang, Yeong-E Chen, Cheng-En Cheng
  • Patent number: 12147921
    Abstract: The disclosed is a system and production processes, comprising a processor to perform the steps: a) obtaining a long-term production schedule containing production operations for a set of production orders by using forecasted values for production operation durations; b) deriving dispatching recommendations for suitable order release dates, dispatching sequences and/or resource choices of all subsequent operational dispatching decisions from the obtained long-term production schedule; c) obtaining a released subset of the set of production orders having each a release date and a due date and including information of all possible dispatching sequences and logical dependencies between them to produce a requested product; d) iteratively calculating subsequent operational dispatching decisions based on operational constraints and on the derived dispatching recommendations which support a decision-making in favor of optimizing the overall production process with respect to long-term objectives; e) outputting each
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: November 19, 2024
    Assignee: Siemens Aktiengesellschaft
    Inventors: Corinna Gottschalk, Rafael Fink
  • Patent number: 12148638
    Abstract: An abnormality detection system includes a waveform acquisition unit configured to acquire waveform data that changes over time; an abnormality degree calculation unit, and an abnormality determination unit. The abnormality degree calculation unit is configured to calculate an abnormality degree based on a cumulative value obtained by accumulating absolute values of differences in data values for each unit time from the waveform data acquired by the waveform acquisition unit. The abnormality determination unit is configured to determine whether the waveform data is normal or abnormal based on the abnormality degree calculated by the abnormality degree calculation unit.
    Type: Grant
    Filed: December 10, 2021
    Date of Patent: November 19, 2024
    Assignee: DENSO CORPORATION
    Inventor: Satoshi Kojima
  • Patent number: 12142494
    Abstract: In a method of controlling a plasma beam of a plasma etcher a flow rate controller of the plasma etcher is set to generate one or more flow rates of an etching gas corresponding to one or more plasma beams of the plasma etcher. The emitted light generated by plasma discharge corresponding to the one or more plasma beams of the plasma etcher is monitored. The flow rate controller is calibrated based on the one or more flow rates and a corresponding emitted light of the plasma discharge.
    Type: Grant
    Filed: June 7, 2021
    Date of Patent: November 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Lung Hung, Yi-Tsang Hsieh, Yu-Hsi Tang, Chih-Teng Liao, Chih-Ching Cheng
  • Patent number: 12140938
    Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for optimizing a process of manufacturing a product. In one aspect, the method comprises repeatedly performing the following: i) selecting a configuration of input settings for manufacturing a product, based on a causal model that measures causal relationships between input settings and a measure of a quality of the product; ii) determining the measure of the quality of the product manufactured using the configuration of input settings; and iii) adjusting, based on the measure of the quality of the product manufactured using the configuration of input settings, the causal model.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: November 12, 2024
    Assignee: 3M Innovative Properties Company
    Inventors: Brian E. Brooks, Gilles J. Benoit, Peter O. Olson, Tyler W. Olson, Himanshu Nayar, Frederick J. Arsenault, Nicholas A. Johnson, Brett R. Hemes, Thomas J. Strey, Jonathan B. Arthur, Nathan J. Herbst, Aaron K. Nienaber, Sarah M. Mullins, Mark W. Orlando, Cory D. Sauer, Timothy J. Clemens, Scott L. Barnett, Zachary M. Schaeffer, Patrick G. Zimmerman, Gregory P. Moriarty, Jeffrey P. Adolf, Steven P. Floeder, Andreas Backes, Peter J. Schneider, Maureen A. Kavanagh, Glenn E. Casner, Miaoding Dai, Christopher M. Brown, Lori A. Sjolund, Jon A. Kirschhoffer, Carter C. Hughes
  • Patent number: 12124247
    Abstract: Techniques are presented for the application of neural networks to the fabrication of integrated circuits and electronic devices, where example are given for the fabrication of non-volatile memory circuits and the mounting of circuit components on the printed circuit board of a solid state drive (SSD). The techniques include the generation of high precision masks suitable for analyzing electron microscope images of feature of integrated circuits and of handling the training of the neural network when the available training data set is sparse through use of a generative adversary network (GAN).
    Type: Grant
    Filed: September 2, 2021
    Date of Patent: October 22, 2024
    Assignee: SanDisk Technologies LLC
    Inventors: Fei Zhou, Cheng-Chung Chu, Raghuveer Makala
  • Patent number: 12124254
    Abstract: A system for predictive analysis and/or process control, preferably including one or more communication and/or computing systems, and optionally including one or more entities and/or sensors. A method for predictive analysis and/or machine operation, preferably including receiving entity data and determining one or more latent features, and optionally including determining one or more response reconstructions, determining a processed representation of the entity data, determining entity information, and/or acting based on entity information.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: October 22, 2024
    Assignee: Arch Systems Inc.
    Inventors: Timothy Matthew Burke, Andrew Galen Scheuermann, Swamy Muddu
  • Patent number: 12124236
    Abstract: A computer system and method for the assisted setup of an instrumented computer-controlled machine tool table, which in principle manufactures only good parts, is disclosed. The invention allows a plurality of users, such as machinists, designers, administrators, and showroom operators, to access and share data related to computer-assisted setup (CAS) of an instrumented computer-controlled machine tool table in a manner that is interactive in real time and internal to the CAS infrastructure architecture.
    Type: Grant
    Filed: October 13, 2023
    Date of Patent: October 22, 2024
    Inventors: George Benedict, Surinder Badyal
  • Patent number: 12114083
    Abstract: Embodiments disclosed herein include a diagnostic substrate, comprising a baseplate, and a first plurality of image sensors on the baseplate, where the first plurality of image sensors are oriented horizontal to the baseplate. In an embodiment, the diagnostic substrate further comprises a second plurality of image sensors on the baseplate, where the second plurality of image sensors are oriented at a non-orthogonal angle to the baseplate. In an embodiment, the diagnostic substrate further comprises a printed circuit board (PCB) on the baseplate, and a controller on the baseplate, where the controller is communicatively coupled to the first plurality of image sensors and the second plurality of image sensors by the PCB. In an embodiment, the diagnostic substrate further comprises a diffuser lid over the baseplate, the PCB, and the controller.
    Type: Grant
    Filed: June 26, 2023
    Date of Patent: October 8, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Upendra Ummethala, Philip Kraus, Keith Berding, Blake Erickson, Patrick Tae, Devendra Channappa Holeyannavar, Shivaraj Manjunath Nara, Anandakumar Parameshwarappa, Sivasankar Nagarajan, Dhirendra Kumar
  • Patent number: 12106948
    Abstract: A plasma processing apparatus includes a chamber; an apparatus-side controller configured to control plasma processing in the chamber; and a monitoring unit configured to monitor a monitoring target that is disposed within the chamber, or is connected directly or indirectly to the chamber. The apparatus-side controller sets the monitoring target and a timing at which monitoring target information is to be acquired. The monitoring unit acquires the monitoring target information transmitted from the monitoring target to the apparatus-side controller, detects an occurrence of an abnormality in the chamber based on the monitoring target information, and controls the monitoring target for the chamber in which the abnormality occurs.
    Type: Grant
    Filed: February 1, 2022
    Date of Patent: October 1, 2024
    Assignee: Tokyo Electron Limited
    Inventors: Ken Hirano, Hiroki Endo
  • Patent number: 12093024
    Abstract: An evaluation value prediction unit predicts an evaluation value at a time point after a given time passes from a predetermined evaluation time based on input data related to an operation of a factory at the evaluation time using a learned prediction model. The prediction model is a learned model that is learned so that the evaluation value related to the operation of the factory at a time point after the given time passes from one time point is output by inputting a plurality of kinds of data related to the operation of the factory at one time point. An evaluation value output unit outputs information related to the evaluation value.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: September 17, 2024
    Assignee: MITSUBISHI HEAVY INDUSTRIES, LTD.
    Inventors: Hisashi Nishiki, Tomoyuki Enomoto, Hikaru Sawada
  • Patent number: 12092965
    Abstract: A defect prediction method for a device manufacturing process involving processing one or more patterns onto a substrate, the method including: determining values of one or more processing parameters under which the one or more patterns are processed; and determining or predicting, using the values of the one or more processing parameters, an existence, a probability of existence, a characteristic, and/or a combination selected from the foregoing, of a defect resulting from production of the one or more patterns with the device manufacturing process.
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: September 17, 2024
    Assignee: ASML NETHERLANDS B.V.
    Inventors: Venugopal Vellanki, Vivek Kumar Jain, Stefan Hunsche
  • Patent number: 12090577
    Abstract: A device for soldering, in particular for reflow soldering, of at least one assembly, having a process chamber arrangement, comprises at least two process chambers for preparing a soldering method and/or for carrying out a soldering method and/or for post-processing a soldering method, wherein the at least two process chambers are arranged above one another, in particular in a stack-like manner.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: September 17, 2024
    Assignee: SIEGFRIED HOFMANN GMBH
    Inventors: Daniel Feseker, Michael Deuerling, Michael Förste, Kai Fuhrmann, Johannes Günther, Benedikt Bechmann, Heinz Nolden
  • Patent number: 12093629
    Abstract: A method of manufacturing a semiconductor device, a corresponding layout diagram being stored on a non-transitory computer-readable medium, the layout diagram including layout cells, the method including generating the layout diagram including: for a candidate cell amongst the layout cells in the layout diagram, avoiding a discrete calculation of a corresponding parasitic capacitance (PC) description including, within a database which stores predefined cells and corresponding parasitic capacitance (PC) descriptions thereof, searching the database for one amongst the predefined cells (matching predefined cell) that is a substantial match to the candidate cell; and, when a substantial match is found, assigning the PC description of the matching predefined cell to the candidate cell.
    Type: Grant
    Filed: June 15, 2023
    Date of Patent: September 17, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ke-Ying Su, Ze-Ming Wu, Po-Jui Lin
  • Patent number: 12085916
    Abstract: A method and device for processing wafer detection tasks, a system, and a storage medium. The method includes that: the resource manager node receives the wafer detection task from the storage server, selects the target work node from the plurality of work nodes according to weight values of the work nodes connected to the resource manager node, and allocates the wafer detection task to the target work node. The target work node selects the idle GPU from the resource pool and allocates the wafer detection task to the idle GPU for execution. The GPU preprocesses the wafer map in the wafer detection task and inputs the processed wafer map into the wafer detection model to obtain the detection result.
    Type: Grant
    Filed: August 12, 2021
    Date of Patent: September 10, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Deqing Qu
  • Patent number: 12087074
    Abstract: A method for reading a digital graphical diagram representing an electric circuit is provided. The graphical diagram includes one or more diagram pages, each representing a portion of the electric circuit. The method includes for each diagram page detecting the graphical objects included in the diagram page, for each diagram page basing on the detected graphical objects, obtaining predictive information related to the components included in the portion of electric circuit represented in the diagram page, and for each diagram page harmonizing the predictive information related to the components of the portion of electric circuit represented in the diagram page to obtain an identification list of the components of the electric circuit.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: September 10, 2024
    Assignee: ABB S.p.A.
    Inventors: Antonello Antoniazzi, Matteo Matteucci, Gabriele Perrone
  • Patent number: 12086519
    Abstract: The present disclosure provides a method and an apparatus for setting wafer script, a device, and a storage medium. In response to the demand unit determining that the execution necessary condition of the script to be executed satisfies the business requirement based on the parameter information, the platform unit acquires the lot identification of the script to be executed and the corresponding production information. In response to the demand unit determining that the script to be executed is executed for the wafers corresponding to the script to be executed for the first time, the platform unit detects whether the first production information corresponding to the first wafers satisfies the execution necessary condition. If satisfied, the platform unit sets parameter information and assignment information for the first wafers, and synchronizes the first wafers with the set information to the material execution unit such that the material execution unit performs corresponding operation.
    Type: Grant
    Filed: September 17, 2021
    Date of Patent: September 10, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Sheng-Hua Su, Minghung Hsieh
  • Patent number: 12078935
    Abstract: A device manufacturing method, the method comprising: obtaining a measurement data time series of a plurality of substrates on which an exposure step and a process step have been performed; obtaining a status data time series relating to conditions prevailing when the process step was performed on at least some of the plurality of substrates; applying a filter to the measurement data time series and the status data time series to obtain filtered data; and determining, using the filtered data, a correction to be applied in an exposure step performed on a subsequent substrate.
    Type: Grant
    Filed: September 9, 2022
    Date of Patent: September 3, 2024
    Assignee: ASML NETHERLANDS B.V.
    Inventors: Rizvi Rahman, Hakki Ergün Cekli, Cédric Désiré Grouwstra
  • Patent number: 12072684
    Abstract: A system includes a first asset and a second asset disposed at an industrial system, and a server communicatively coupled to the first asset and the second asset. The server device is configured to receive a first set of stream-based data from the first asset and generate a model for the second asset based on the first set of stream-based data, wherein the model is configured to output an expected set of stream-based data associated with the second asset; receive a second set of stream-based data from the second asset; and send a command to the first asset or the second asset in response to the second set of stream-based data being outside of a threshold from the expected set of stream-based data.
    Type: Grant
    Filed: September 28, 2021
    Date of Patent: August 27, 2024
    Assignee: Rockwell Automation Technologies, Inc.
    Inventors: Edward A. Gray, Norman A. Weatherhead, Srikanth G. Mashetty
  • Patent number: 12074760
    Abstract: Embodiments relate to methods, systems, and computer program products for path management in a processing system. In a method, in response to receiving a request for adding a target controlling unit into a processing system, a plurality of network nodes in the processing system are divided into a group of subnets based on a topology of the plurality of network nodes, the plurality of network nodes being connected to at least one controlling unit in the processing system. A workload estimation is determined, the workload estimation representing a workload to be caused by the target controlling unit to the processing system. A target subnet is selected from the group of subnets for connecting the target controlling unit into the processing system based on the workload estimation. With these embodiments, the target subnet may be selected in an automatic way such that the performance of the processing system may be increased.
    Type: Grant
    Filed: September 16, 2021
    Date of Patent: August 27, 2024
    Assignee: International Business Machines Corporation
    Inventors: Yan Huang, Heng Wang, Kai Feng, Zheng Lei An, Shuang Shuang Jia, Xiao Ling Chen, Guang Han Sui, Lei Wang
  • Patent number: 12074176
    Abstract: A substrate processing method includes loading an operation list of a substrate, the operation list including an operation site bar, an inspection site bar, and an operation flag record enabling bar, the operation site bar including a plurality of operation site flags, and the inspection site bar including an inspection site flag; loading a substrate onto a production line; inquiring an operation site flag corresponding to the operation site at the operation site bar of the operation list, and judging whether the operation site flag is provided with an inspection site flag at the inspection site bar; if the operation site flag is provided with the inspection site flag at the inspection site bar, verifying whether a current operation flag of the substrate matches the inspection site flag; if the current operation flag of the substrate matches the inspection site flag, processing the substrate at the operation site.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: August 27, 2024
    Assignees: HKC CORPORATION LIMITED, CHONGQING HKC OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Posung Pan
  • Patent number: 12073475
    Abstract: A farming machine is configured to identify and treat plants in a field. The farming machine includes one or more light sensors for measuring a characteristic of light. The one or more light sensors are coupled to the farming machine and are directed a substantially upwards orientation away from the plants. A control system adjusts settings of an image acquisition system based on a characteristic of light measured by the one or more light sensors. The image acquisition system captures an image of a plant using one or more image sensors coupled to the farming machine, the one or more image sensors directed in a substantially downwards orientation towards the plants. The control system identifies a plant in the image and actuates a treatment mechanism to treat the identified plant.
    Type: Grant
    Filed: July 27, 2023
    Date of Patent: August 27, 2024
    Assignee: BLUE RIVER TECHNOLOGY INC.
    Inventors: Matthew Stephen Colgan, Charles McCauley Ross
  • Patent number: 12066815
    Abstract: There is provided a technique that includes: displaying a recipe editing screen including at least a selection screen area that displays a parameter list for selection of parameters included in a recipe of a substrate processing apparatus, and a parameter editing screen area that edits the parameters; receiving a selection operation that selects an editing target parameter from the parameter list; displaying, on the parameter editing screen area, in an editable manner, a timing chart that is changeable at a time of each process in a series of processes included in a substrate processing process; and editing the editing target parameter by receiving an operation instruction to edit the timing chart displayed on the parameter editing screen area and changing the timing chart according to the operation instruction.
    Type: Grant
    Filed: September 16, 2021
    Date of Patent: August 20, 2024
    Assignee: Kokusai Electric Corporation
    Inventor: Takatoshi Seki
  • Patent number: 12055912
    Abstract: The present disclosure provides a wafer repair method, system, apparatus and device, and a storage medium, relating to the field of semiconductor devices. The method includes: a laser equipment acquires test data for repairing a predetermined wafer; the laser equipment sending the test data to a processing server so that the processing server converts the test data into repair data in a predetermined format; and the laser equipment obtaining the repair data in the predetermined format to repair the predetermined wafer.
    Type: Grant
    Filed: June 11, 2021
    Date of Patent: August 6, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Yubin Lu
  • Patent number: 12046494
    Abstract: A chip matching system and a corresponding method are provided. The method defines a plurality of first electronic components in a first wafer as various grades of chips and defines a plurality of second electronic components in a second wafer as various grades of chips, and then grades of the first electronic components and the second electronic components are matched to generate target information, and finally the first and second electronic components are integrated in the same position according to the target information. Therefore, the highest-grade chips can be arranged in a multi-chip module to optimize the quality of the multi-chip module.
    Type: Grant
    Filed: November 16, 2022
    Date of Patent: July 23, 2024
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Wu-Hung Yen, Yi-Hsien Huang, Chun-Tang Lin, Shu-Hua Chen, Shou-Qi Chang
  • Patent number: 12045555
    Abstract: Substrates to be processed are partitioned based on pre-processing data that is associated with substrates before a process step. The data is partitioned using a partition rule and the substrates are partitioned into subsets in accordance with subsets of the data obtained by the partitioning. Corrections are applied, specific to each subset. The partition rule is obtained using decision tree analysis on a training set of substrates. The decision tree analysis uses pre-processing data associated with the training substrates before they were processed, and post-processing data associated with the training substrates after being subject to the process step. The partition rule that defines the decision tree is selected from a plurality of partition rules based on a characteristic of subsets of the post-processing data. The associated corrections are obtained implicitly at the same time.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: July 23, 2024
    Assignee: ASML NETHERLANDS B.V.
    Inventors: Vahid Bastani, Alexander Ypma, Dag Sonntag, Everhardus Cornelis Mos, Hakki Ergün Cekli, Chenxi Lin
  • Patent number: 12040167
    Abstract: In a diagnosis apparatus for diagnosing a state of a plasma processing apparatus, prior distribution information including a probability distribution function is previously obtained for each of first sensors by using first sensor values obtained by the first sensors in a first plasma processing apparatus, a probability distribution in each of second sensors corresponding to each of the first sensors is estimated based on the previously obtained prior distribution information and second sensor values obtained by the second sensors in a second plasma processing apparatus different from the first plasma processing apparatus, and a state of the second plasma processing apparatus is diagnosed by using the estimated probability distribution.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: July 16, 2024
    Assignee: HITACHI HIGH-TECH CORPORATION
    Inventors: Shota Umeda, Kenji Tamaki, Masahiro Sumiya, Masaki Ishiguro
  • Patent number: 12039249
    Abstract: A system and method for fixing DRC violations includes receiving a layout pattern having a design rule check (DRC) violation therein, determining that the layout pattern is an inlier based upon a comparison of the layout pattern with a plurality of previously analyzed layout patterns. The comparison may be performed by an anomaly detection algorithm. The system and method may also include selecting a recipe from a pool of recipes previously applied to the plurality of previously analyzed layout patterns for fixing the DRC violation in the layout clip upon determining that the layout pattern is an inlier.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: July 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yu-Chen Huang, Heng-Yi Lin, Yi-Lin Chuang
  • Patent number: 12038735
    Abstract: A method for qualifying a manufacturing process for a first component including a common geometric feature includes obtaining manufacturing data for the common geometric feature. The manufacturing data is associated with one or more qualified second components. The one or more qualified second components are different than the first component. Each of the one or more qualified second components include the common geometric feature. The method further includes modeling the manufacturing process for the common geometric feature of the one or more qualified second components using the manufacturing data, modeling the manufacturing process for the common geometric feature of the first component, obtaining manufacturing process parameters for the manufacturing process for the common geometric feature of the one or more qualified second components, and qualifying the manufacturing process for the common geometric feature of the first component.
    Type: Grant
    Filed: April 15, 2022
    Date of Patent: July 16, 2024
    Assignee: Pratt & Whitney Canada Corp.
    Inventors: Changsheng Guo, Serafettin Engin