Plural Processors Patents (Class 700/2)
  • Patent number: 7082346
    Abstract: A semiconductor manufacturing apparatus which continuously executes oxidation and CVD in a multiprocess apparatus includes an internal apparatus controller which selects the type of process and supplies a start signal and stop signal for the process to the multiprocess apparatus, and a process controller which calculates the process state for each process on the basis of the internal information of the apparatus. Upon receiving the stop signal from the controller, the controller sends the stop signal to the multiprocess apparatus to stop the current process by the multiprocess apparatus and switches to the next process.
    Type: Grant
    Filed: June 10, 2003
    Date of Patent: July 25, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuo Saki, Yukihiro Ushiku
  • Patent number: 7065688
    Abstract: In a system having a plurality of processing nodes, wherein each of the plurality of processing nodes has an assigned portion of system memory such that the assigned portion of system memory of each of the plurality of processing nodes is accessible by the plurality of processing nodes, a technique is presented that allows each of the plurality of processing nodes to perform a memory initialization and test of the processing node's assigned portion of system memory. One of the processing nodes can cause the others of the processing nodes to perform the memory initialization and test process or each processing node can automatically perform the memory initialization and test process.
    Type: Grant
    Filed: February 19, 2003
    Date of Patent: June 20, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: William A. Moyes, Michael V. Mattress
  • Patent number: 7062422
    Abstract: A PLC system construction support tool is provided wherein a display 31 of text and numeric values is produced at the left of a paste board 22. The display 31 is provided for each row of a system and whenever a unit is added or deleted, the numeric values are updated. The display 31 contains a character string of “WIDTH” meaning the total length of the units on the corresponding row and the numeric value of the width (mm units), a character string of “CURRENT CONSUMPTION” meaning the total current consumption of the units on the corresponding row and the numeric value of the current consumption (mA units), and a character string of “WEIGHT” meaning the total weight of the units on the corresponding row and the numeric value of the weight (g units).
    Type: Grant
    Filed: July 9, 2001
    Date of Patent: June 13, 2006
    Assignee: Keyence Corporation
    Inventors: Akihiro Inoko, Katsunari Koyama
  • Patent number: 7050867
    Abstract: A remote controlled system employs a computer-based remote control facilitator to facilitate remote control of a controlled device from a non-dedicated remote controller. The computer facilitator is coupled to the remote controller and controlled device via a wireless or wire-based network. The computer facilitator runs an application that corresponds to the controlled device. Neither the remote controller nor the controlled device need have any awareness of the other, or any knowledge as to how to communicate with one another. The computer tells the remote controller what options to present to a user and translates the selection entered by the user into a command that is sent to the controlled device.
    Type: Grant
    Filed: June 22, 2004
    Date of Patent: May 23, 2006
    Assignee: Microsoft Corporation
    Inventor: David M. Maymudes
  • Patent number: 7050860
    Abstract: The safe PLC1 and the safe slaves 2 are connected with each other via the safe network 3. The safe PLC has the function of transmitting a request of safety information by broadcast message to the safe slaves. The safe slaves are each provided with a safety information transmission function for transmitting safety information indicative of whether the safe slave is in a safe condition or not; and a changing function for changing a priority of a transmission frame which carries the safety information. As a result, when the safe slaves send back safe responses at once in response to the broadcast message, safety information (danger) with a higher priority is transmitted ahead of others to the safe PLC.
    Type: Grant
    Filed: June 21, 2002
    Date of Patent: May 23, 2006
    Assignee: Omron Corporation
    Inventors: Yasuo Muneta, Toshiyuki Nakamura
  • Patent number: 7051057
    Abstract: A general-purpose functional circuit for a programmable controller, comprising: an external connector which is connected to an external appliance to be controlled; an interconnecting connector which is connected to at least a CPU unit of the programmable controller; and an arithmetic processing member which has at least a function of transmitting to and receiving from the external appliance connected to the arithmetic processing member through the external connector, signals and performing a logical operation based on an external signal received from the external appliance so as to transmit to the CPU unit via the interconnecting connector, a logical operation signal corresponding to a result of the logical operation; wherein the CPU unit includes a CPU for executing a sequence program.
    Type: Grant
    Filed: November 28, 2001
    Date of Patent: May 23, 2006
    Assignee: Matsushita Electric Works, Ltd.
    Inventors: Koji Ohno, Hideki Noda, Kazuhiro Mishina
  • Patent number: 7047117
    Abstract: An integrated vehicle control system includes various functionalized networks, such as power train group, vehicle motion group, and power source group, each including a plurality of ECUs connected via an individual communication line. A managing ECU in each network determines operation directives to be supplied to individual ECUs belonging to its own network based on information obtained from these individual ECUs as well as information obtained from other ECUs of different networks via a host communication line L4. The determined operation directives are transmitted to corresponding ECUs to cause respective individual ECUs to operate subordinately according to the given operation directives, thereby realizing a collective control of specific functions. The managing ECU also executes abnormality detection processing for detecting abnormality occurring in the integrated vehicle control system.
    Type: Grant
    Filed: October 17, 2003
    Date of Patent: May 16, 2006
    Assignee: Denso Corporation
    Inventors: Susumu Akiyama, Tsutomu Tashiro
  • Patent number: 7035693
    Abstract: An arrangement operable to communicate with a fieldbus network and operate an attached relay and a method for implementing such arrangement is provided. The arrangement and method provide conventional discrete outputs from a fieldbus device using standard fieldbus function blocks, such as those used for Foundation® and Profibus® fieldbus networks. The arrangement and method may facilitate the integration of traditional discrete relay functions into these more advanced digital fieldbus networks, and also utilize additional functions available to standard Foundation® fieldbus and Profibus® fieldbus network devices.
    Type: Grant
    Filed: January 23, 2003
    Date of Patent: April 25, 2006
    Assignee: Smar Research Corporation
    Inventors: Cesar Cassiolato, Edson Emboaba De Oliveira, Libanio Carlos De Souza, Marcelo Luis Dultra
  • Patent number: 7024250
    Abstract: A method for the synchronous control of several manipulators, such as several industrial robots, is characterized in that control units of specific manipulators exchange control information according to the data structures contained in a corresponding control program, through which control units to be synchronized and synchronization points in the control programs taking place there can be clearly identified, and in that on reaching and synchronization points the program sequence in the control units to be synchronized is continued according to the contents of the data structures in conjunction with the already exchanged control information or stopped until corresponding information arrives from other control units to be synchronized.
    Type: Grant
    Filed: May 14, 2003
    Date of Patent: April 4, 2006
    Assignee: KUKA Roboter GmbH
    Inventors: Stefan Graf, Andreas Hagenauer, Michael Chaffee, Kenneth Stoddard
  • Patent number: 7020532
    Abstract: The invention provides improved methods and apparatus for control using field and control devices that provide a virtual machine environment and that communicate via an IP network. By way of non-limiting example, such field device can be an “intelligent” transmitter or actuator that includes a low power processor, along with a random access memory, a read-only memory, FlashRAM, and a sensor interface. The processor can execute a real-time operating system, as well as a Java virtual machine (JVM). Java byte code executes in the JVM to configure the field device to perform typical process control functions, e.g., for proportional integral derivative (PID) control and signal conditioning. Control networks can include a plurality of such field and control devices interconnected by an IP network, such as an Ethernet.
    Type: Grant
    Filed: January 13, 2004
    Date of Patent: March 28, 2006
    Assignee: Invensys Systems, Inc.
    Inventors: Alexander Johnson, Paul C. Badavas, T. Eric Christiansen, Peter D. Hansen, Thomas B. Kinney, Seyamak Keyghobad, Bo Ling, Richard L. Thibault
  • Patent number: 7004191
    Abstract: A mass flow controller includes an electronic controller that provides a web server that allows access to the web server through such interworking networks as the Internet.
    Type: Grant
    Filed: June 24, 2002
    Date of Patent: February 28, 2006
    Assignee: MKS Instruments, Inc.
    Inventors: Ali Shajii, Nicholas Kottenstette, Jesse Ambrosina
  • Patent number: 7003593
    Abstract: A computer system architecture and memory controller for close-coupling within a hybrid computing system using an adaptive processor interface port (“APIP”) added to, or in conjunction with, the memory and I/O controller chip of the core logic. Memory accesses to and from this port, as well as the main microprocessor bus, are then arbitrated by the memory control circuitry forming a portion of the controller chip. In this fashion, both the microprocessors and the adaptive processors of the hybrid computing system exhibit equal memory bandwidth and latency. In addition, because it is a separate electrical port from the microprocessor bus, the APIP is not required to comply with, and participate in, all FSB protocol. This results in reduced protocol overhead which results higher yielded payload on the interface.
    Type: Grant
    Filed: October 29, 2002
    Date of Patent: February 21, 2006
    Assignee: SRC Computers, Inc.
    Inventors: Jon M. Huppenthal, Thomas R. Seeman, Lee A. Burton
  • Patent number: 6993415
    Abstract: A control system for plumbing equipment includes a user interface and a main controller. Only the user interface is customized and unique to a specific model of the plumbing equipment, and stores main software program that is tailored to operate the particular components of that specific model. The main controller is generic and is able to be used on several different models of the plumbing equipment. Upon activation of the control system the main software program is transferred to the main controller which configures the main controller to operate the specific model of the plumbing equipment.
    Type: Grant
    Filed: April 8, 2004
    Date of Patent: January 31, 2006
    Assignee: Kohler Co.
    Inventors: Ronald A. Bauer, Richard J. Hackl
  • Patent number: 6990380
    Abstract: An object of the present invention is to grasp easily a process history of a target object such as a semiconductor wafer. The processing apparatus of the present invention includes: a processing apparatus body which includes a plurality of process units for executing a prescribed process to a target object, and transport mechanism for transporting said target object between the process units; a first controller for controlling the processing apparatus as a whole; a second controller for controlling the process units; an information storage section for taking in a signal transmitted and received between the first and second controllers; and a host computer for monitoring operation states of the process units. The present invention is extended to a processing system including a plurality of the processing apparatuses connected with a host computer which is further connected with a monitor computer through a communication network.
    Type: Grant
    Filed: December 21, 2001
    Date of Patent: January 24, 2006
    Assignee: Tokyo Electron Limited
    Inventors: Yuji Yoshimoto, Ryouichi Uemura, Kunie Ogata, Yoichi Deguchi
  • Patent number: 6986127
    Abstract: A debugging system and debugging techniques for configurable processors remove the requirement of foreknowledge of specific configurable processor information from components of the debugging system where obtaining that foreknowledge is costly. The system is part of an environment that generates a processor where the proper information is generated in the right forms for such use.
    Type: Grant
    Filed: October 3, 2000
    Date of Patent: January 10, 2006
    Assignee: Tensilica, Inc.
    Inventors: John Newlin, Albert Wang, Christopher M. Songer
  • Patent number: 6985780
    Abstract: A smart camera system provides focused images to an operator at a host computer by processing digital images at the imaging location prior to sending them to the host computer. The smart camera has a resident digital signal processor for preprocessing digital images prior to transmitting the images to the host. The preprocessing includes image feature extraction and filtering, convolution and deconvolution methods, correction of parallax and perspective image error and image compression. Compression of the digital images in the smart camera at the imaging location permits the transmission of very high resolution color or high resolution grayscale images at real-time frame rates such as 30 frames per second over a high speed serial bus to a host computer or to any other node on the network, including any remote address on the Internet.
    Type: Grant
    Filed: August 23, 2004
    Date of Patent: January 10, 2006
    Assignee: Adept Technology, Inc.
    Inventors: Edison T. Hudson, James McCormick, Ronald G. Genise, Jerome Dahl
  • Patent number: 6985778
    Abstract: An interface device and method thereof interfacing between a host processor and a NAND flash memory includes a register file, an internal memory, a flash interface portion, and a finite state machine. The register file receive a command from the host processor to control an operation of the NAND flash memory and an operation information to execute the command and storing the command and the operation information. The flash interface portion controls a control signal to operate the NAND flash memory, outputs the command, the operation information, or the host data, and controls an I/O signal wire through which the flash data is inputted to the NAND flash memory. The finite state machine extracts the command and the operation information from the register file and controls the internal memory and the flash interface portion to execute the command.
    Type: Grant
    Filed: May 28, 2003
    Date of Patent: January 10, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-soo Kim, Yong-je Kim, Jin-chul Pyo
  • Patent number: 6980868
    Abstract: A system and a method for integrating electronic apparatuses, e.g. information appliances, are provided. The present invention detects and stores the functions of each electronic apparatus in advance. When one of the electronic apparatuses transmits a signal to execute a particular function, the present invention determines which electronic apparatus is the most suitable to execute the function and sends the signal to the very electronic apparatus without manual operations.
    Type: Grant
    Filed: May 24, 2004
    Date of Patent: December 27, 2005
    Assignee: Autotools Group Co., Ltd.
    Inventors: C. J. Jason Huang, Jong-Min Deng
  • Patent number: 6973508
    Abstract: A versatile controller that can be used as either a stand-alone controller in a relatively small process plant or as one of numerous controllers in a distributed process control system depending on the needs of the process plant includes a processor adapted to be programmed to execute one or more programming routines and a memory, such as a non-volatile memory, coupled to the processor and adapted to store the one or more programming routines to be executed on the processor. The versatile controller also includes a plurality of field device input/output ports communicatively connected to the processor, a configuration communication port connected to the processor and to the memory to enable the controller to be configured with the programming routines and a second communication port which enables a user interface to be intermittently connected to the controller to view information stored within the controller memory.
    Type: Grant
    Filed: February 12, 2002
    Date of Patent: December 6, 2005
    Assignee: Fisher-Rosemount Systems, Inc.
    Inventors: Rusty Shepard, Ken Krivoshein, Dan Christensen, Gary Law, Kent Burr, Mark Nixon
  • Patent number: 6963814
    Abstract: Certain exemplary embodiments comprise a method for acceptance testing a fieldbus component configuration program. The method can comprise providing simulated input information to the fieldbus component configuration program. The method can further comprise comparing outputs from the fieldbus component configuration program to predetermined outputs. In certain exemplary embodiments, the method can comprise determining if the fieldbus component configuration program output is faulty.
    Type: Grant
    Filed: December 11, 2003
    Date of Patent: November 8, 2005
    Assignee: Siemens Energy & Automation, Inc.
    Inventors: John David Jones, Steven Michael Hausman
  • Patent number: 6961624
    Abstract: A two-wire field-mounted process device with multiple isolated channels includes a channel that can be an input channel or an output channel. The given input or output channel can couple to multiple sensors or actuators, respectively. The process device is wholly powered by the two-wire process control loop. The process device includes a controller adapted to measure one or more characteristics of sensors coupled to an input channel and to control actuators coupled to an output channel. The controller can be further adapted to execute a user generated control algorithm relating process input information with process output commands. The process device also includes a loop communicator that is adapted to communicate over the two-wire loop.
    Type: Grant
    Filed: January 20, 2004
    Date of Patent: November 1, 2005
    Assignee: Rosemount Inc.
    Inventors: William R. Kirkpatrick, Robert J. Karschnia, Marcos Peluso, Steven J. DiMarco, Gary A. Lenz
  • Patent number: 6930634
    Abstract: A shared memory architecture for a GPS receiver, wherein a processing memory is shared among the different processing functions, such as the correlator signal processing, tracking processing, and other applications processing. The shared memory architecture within the GPS receiver provides the memory necessary for signal processing operations, such as the massively parallel processing, while conserving memory cost by re-using that same memory for other GPS and non-GPS applications. The shared memory architecture for a GPS receiver provided in accordance with the principles of this invention thereby significantly minimize the costly memory requirement often required of extremely fast signal acquisition of a GPS receiver.
    Type: Grant
    Filed: December 4, 2002
    Date of Patent: August 16, 2005
    Assignee: SiRF Technology, Inc.
    Inventors: Leon Kuo-Liang Peng, Henry D. Falk
  • Patent number: 6928327
    Abstract: The process control system includes at least one master computer, at least one master system bus and at least one communication network, where the communications network is physically decoupled from the master system bus. The master computer is connected both to the master system bus and to the communications network and enables data exchange between the systems using Internet browser technology. At least one technical facility that is to be controlled can thus be advantageously controlled both by the master computer and by at least one computer connected to the communications network.
    Type: Grant
    Filed: March 20, 2002
    Date of Patent: August 9, 2005
    Assignee: Siemens Aktiengesellschaft
    Inventors: Dirk Albert, Uwe Gerk, Marcel Kellner
  • Patent number: 6925367
    Abstract: In a control method and a system for the automatic pre-processing of device malfunctions, first data about a device malfunction are sent to a central control device by means of first terminal equipment. On the basis of the first data and on the basis of stored second data, the central control device automatically selects a group of second terminal equipment that are allocated to various service technicians. A malfunction incident signal and at least a part of the data are then sent to the selected terminal equipment and output thereat. The terminal equipment respectively acquires preliminary diagnosis data relating to the malfunction and availability data from the respective service technician. These data are communicated to the central control device, which automatically evaluates the existing data, selects a specific second terminal equipment from the group and communicates an assignment signal to the selected second terminal equipment.
    Type: Grant
    Filed: May 21, 2003
    Date of Patent: August 2, 2005
    Assignee: Siemens Aktiengesellschaft
    Inventor: Joerg Fontius
  • Patent number: 6922664
    Abstract: Multi-sensor system for real-time embedded monitoring of object senses mixed-mode object conditions. Various sensors separately provide disparate analog signals representing different measurable attributes regarding sensed object. For example, such sensors may separately sense temperature, pressure, or other biometric value. Then, according to specified rule set or other qualifying parameters, a digital signal is generated by a processor or controller to indicate one or more condition of the sensed object according to certain sensor input values. Additionally, such multi-sensor scheme may be coupled to a digital network or otherwise coupled thereto for simulation and/or communication applications.
    Type: Grant
    Filed: September 7, 2001
    Date of Patent: July 26, 2005
    Inventors: Dennis S. Fernandez, Irene Y. Hu
  • Patent number: 6915170
    Abstract: A care management system in which the management of the administration of care for patients is automated. Hospital information systems are monitored and the information from those systems is used in verifying the administrations of care to patients. The care management system monitors ongoing administrations for progress and automatically updates records and provides alarms when necessary. The care management system is modular in nature but is fully integrated among its modules. Particular lists of data, such as the termination times of all ongoing infusions, provide hospital staff current information for increased accuracy and efficiency in planning. Features include the automatic provision of infusion parameters to pumps for accurate and efficient configuration of the pump, and providing an alarm when an unscheduled suspension of an infusion exceeds a predetermined length of time. A passive recognition system for identifying patients and care givers is provided.
    Type: Grant
    Filed: July 18, 2003
    Date of Patent: July 5, 2005
    Assignee: Alaris Medical Systems, Inc.
    Inventors: Joseph J. Engleson, Craig Chamberlain
  • Patent number: 6904325
    Abstract: A parallel flash programming system for use in motor vehicle assembly includes an input receptive of information relating to a predetermined number of processors connected to a system bus, processor flash programming attributes, and system bus attributes. An incremental flash programming times determination module is adapted, based on the information, to determine incremental flash programming times of a processor in relation to multiple interframe wait times respective of multiple parallel flash programming schema in accordance with the predetermined number of processors. A global flash programming time resolution module is adapted to determine, based on incremental flash programming times respective of multiple processors of the predetermined number, an assignment of the multiple processors to a number of parallel programming tracks yielding a global flash programming time in accordance with predetermined criteria.
    Type: Grant
    Filed: October 23, 2003
    Date of Patent: June 7, 2005
    Assignee: General Motors Corporation
    Inventors: Jianying Shi, Charles H. Rosa
  • Patent number: 6901352
    Abstract: A generic, scalable consumer subsystem/producer subsystem interface controller for exchanging data between at least one producer subsystem configured to produce a set of services characterized in a producer generated data set, and at least on consumer subsystem configured to consume the set of services, including an object-oriented producer application program interface configured for use on a multi-threaded, client-server operating system, wherein producer routines are configured to: initialize producer server objects maid producer client objects; receive requests for data from a consumer subsystem via the producer client objects; send acknowledgments to a consumer subsystem in response to requests from the consumer subsystem via the producer server objects; send data to a consumer subsystem in response to requests from the consumer subsystem via the producer server objects; and wherein consumer routines are configured to: initialize consumer server objects and consumer client objects; send requests for data
    Type: Grant
    Filed: June 30, 2003
    Date of Patent: May 31, 2005
    Assignee: Coe Newnes/McGehee ULC
    Inventors: Steve C. Woods, Michael McGuire, Harry Ogloff, Zvonimir Sko{hacek over (c)}ić, Emeric Johnson
  • Patent number: 6895289
    Abstract: Documents used for process control can be managed and maintained from a document server and a terminal. In order to update the documents quickly so that an operated process is always kept in the most preferable state of operation, the document server stores and manages production documents used for actually controlling and monitoring a control system plant, whereas the terminal system is used to refer and edit plant documents. The terminal can synchronize contents of the plant documents in the document server with those in the control system before storing the synchronized plant documents in the terminal.
    Type: Grant
    Filed: November 12, 2002
    Date of Patent: May 17, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Katsuhito Shimizu, Tooru Kimura, Yoshio Maruyama, Yukiko Mouri, Satoru Shimizu, Hidekazu Fujimura, Masao Furukawa, Yoshiharu Hayashi, Yasushi Hayasaka
  • Patent number: 6892129
    Abstract: A vehicle electronic control system has a control CPU and a monitor CPU. The control CPU performs a fail-safe processing thereby to reduce an engine output torque, when the monitor CPU monitoring the control CPU detects that the control CPU fails to perform throttle control for an engine. When the monitor CPU detects that the control CPU fails to perform the fail-safe processing, it performs a fail-safe processing in place of the control CPU. In this fail-safe processing, the monitor CPU continues to reset the control CPU so that the engine may be forcibly stopped.
    Type: Grant
    Filed: November 7, 2002
    Date of Patent: May 10, 2005
    Assignees: Denso Corporation, Toyota Jidosha Kabushiki Kaisha
    Inventor: Hidemasa Miyano
  • Patent number: 6888334
    Abstract: A reference variable having a linear relationship with the angular position of a master axis is set, and a correspondence between this reference variable and the displacement of a slave axis is stored in a data table. One execution stage is specified by setting a starting reference variable and an ending reference variable from this data table. A desired sequence is assigned to a plurality of execution stages thus specified. The reference variable corresponding to the angular position of the master axis is determined, slave axis displacement data corresponding to the reference variable is read out, and the slave axis is positioned in accordance with the position of the master axis on the basis of this displacement data.
    Type: Grant
    Filed: October 17, 2002
    Date of Patent: May 3, 2005
    Assignee: Fanuc LTD
    Inventors: Kentaro Fujibayashi, Tetsuo Hishikawa, Takashi Idei
  • Patent number: 6876888
    Abstract: A control system (60) controls a material handling system and has a first control module (120), a second control module (140), and a third control module (160). The first module (120) includes a first control cabinet (12) for providing primary control to the first module (120), a first external component (20) for controlling an equipment component of the material handling system, and a modular interconnectivity component (30) for interconnecting the first control cabinet (12) and the first external component (20) for control of the first external component (20). The control system (60) further includes a first internal component (20) for operating the first control cabinet (12) and a modular interconnectivity component (30). The first module (120) has primary control of the second module (140) and the third module (160).
    Type: Grant
    Filed: April 12, 2001
    Date of Patent: April 5, 2005
    Assignee: Lockheed Martin Corporation
    Inventor: Gary J. Locke
  • Patent number: 6871102
    Abstract: An apparatus for verifying memory coherency of a duplication processor having a symmetrical structure includes: an active processor in which a standby memory read command (SMRC) is generated and transmitted by hardware and then a read data of the standby memory which has been inputted corresponding to the SMRC is image-buffered to verify a memory coherency; and a standby processor in which the SMRC transmitted from the active processor is analyzed and a read command of a standby memory is outputted, and then the data read from the standby memory is transmitted to the active processor. A burst transaction can be performed both when the data is read from the standby memory and when the read data is transmitted, so that the use efficiency of the processor bus, the duplication bus and the duplication channel can be improved. Especially, a bad influence according to the operation of each processor and the duplication channel can be minimized.
    Type: Grant
    Filed: December 7, 2000
    Date of Patent: March 22, 2005
    Assignee: LG Electronics Inc.
    Inventor: Sang Ic Jeong
  • Patent number: 6868862
    Abstract: A mass flow controller includes an electronic controller for which a plurality of closed loop control codes sets may be uploaded. In a dual processor embodiment, one processor may upload a plurality of codes sets for another, with the selection of codes sets determined by the uploading processor either autonomously or through user interaction.
    Type: Grant
    Filed: June 24, 2002
    Date of Patent: March 22, 2005
    Assignee: MKS Instruments, Inc.
    Inventors: Ali Shajii, Nicholas Kottenstette, Jesse Ambrosina
  • Patent number: 6868309
    Abstract: A method and control system computing platform for a dialysis machine that uses Symmetric Multi-Processing (SMP) architecture. The SMP architecture tightly couples multiple (e.g., 2) independent processors by sharing memory between the processors. A single shared memory is used by both processors in order to facilitate communication between the processors and reduce cost by eliminating the expense of redundant memory. In this way, the two, or in general “N” processors, increase processor throughput by allowing the execution of N processes in parallel while without requiring extra memory and without having a single point of failure in the computer. In the event of a bus failure on the circuit card, the computer is reset using distributed hardware watchdogs. The watchdog reset signal is also sent to the hardware components of the dialysis machine in order to place the system in a safe.
    Type: Grant
    Filed: September 24, 2001
    Date of Patent: March 15, 2005
    Assignee: Aksys, Ltd.
    Inventor: Jamie Begelman
  • Patent number: 6864646
    Abstract: A multiple inverter system is powered from a common energy source such as a battery. First and second inverters are coupled to the common energy source and drive corresponding motors. First and second controllers provide pulse width modulated signals, modulated with respect to first and second clock signals, respectively, to the respective first and second inverters. A capacitor coupled between a power bus and a ground bus smoothes power bus ripples caused by simultaneous switching. To reduce the size needed for the capacitor, different modulation schemes, such as center based interleaved, and leading and lagging edge coincident, are used when both motors are in the motoring mode or both motors are in the regeneration mode. However, the same modulation scheme is used when one motor is in the motoring mode and the other motor is in the regeneration mode.
    Type: Grant
    Filed: February 14, 2003
    Date of Patent: March 8, 2005
    Assignee: General Motors Corporation
    Inventors: Khwaja M. Rahman, Silva Hiti, Scott D. Downer, Brian Welchko
  • Patent number: 6865644
    Abstract: A system and method for industrial control I/O forcing is provided. The invention includes a processor, shared memory and an I/O processor with cache memory. The invention provides for the cache memory to be loaded with I/O force data from the shared memory. The I/O processor performs I/O forcing utilizing the I/O force data stored in the cache memory. The invention further provides for the processor to notify the I/O processor in the event that I/O force data is altered during control program execution. The invention further provides for the I/O processor to refresh the cache memory (e.g., via a blocked write) after receipt of alteration of the I/O force data from the processor.
    Type: Grant
    Filed: July 25, 2001
    Date of Patent: March 8, 2005
    Assignee: Rockwell Automation Technologies, Inc.
    Inventors: Raymond R. Husted, Ronald E. Schultz, Dennis J. Dombrosky, David A. Karpuszka
  • Patent number: 6845277
    Abstract: Process and apparatus for communication between an Information Handling System (HIS) and a display having On “Screen Display” (OSD) capability. The HIS system includes a processor under control of an operating system, a graphics system and an electronic circuit which operates independently on the processor and the graphics system. The display receives a graphics channel with the graphics signals. An additional service channel is used for the interaction between the host and the display, and also for allowing the independent electronic circuit to have a direct access to the On Screen Display capability of the display. The service channel may be advantageously a DDC/CI communication link, and the electronic circuit may be a hardware monitoring circuit which is operational even before the booting process of the processor. No additional Liquid Crystal Display is thus required.
    Type: Grant
    Filed: March 20, 2000
    Date of Patent: January 18, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jacques Michelet, Claus Hirzmann, François Loison, Vincent Nguyen-Quang Do
  • Patent number: 6845410
    Abstract: A modular computer system includes at least two processing functional modules each including a processing unit adapted to process data and adapted to input/output data to other functional modules through at least two ports with each port including a plurality of data lines. At least one routing functional module is adapted to route data and adapted to input/output data to other functional modules through at least two ports with each port including a plurality of data lines. At least one input or output functional module is adapted to input or output data and adapted to input/output data to other functional modules through at least one port including a plurality of data lines. Each processing, routing and input or output functional module includes a local controller adapted to control the local operation of the associated functional module, wherein the local controller is adapted to input and output control information over control lines connected to the respective ports of its functional module.
    Type: Grant
    Filed: March 10, 2000
    Date of Patent: January 18, 2005
    Assignee: Silicon Graphics, Inc.
    Inventors: Michael Brown, Robert Cutler, Martin M. Deneroff, Kim Gustafson, Steven Hein, Richard T. Ingebritson
  • Publication number: 20040260410
    Abstract: Once attached to a slot of a personal digital assistant PDA, a card module CM executes an application-specific program and transmits a result obtained thereby to the personal digital assistant PDA. The thus received execution result is outputted from an output part. Accordingly, the output part can be provided for shared use among several card modules CM for output of the execution result.
    Type: Application
    Filed: July 8, 2004
    Publication date: December 23, 2004
    Inventor: Kiyomi Sakamoto
  • Publication number: 20040254651
    Abstract: A controller is disclosed for control operations in underground mining, especially for controllers to control support shields. The controller utilizes a central unit with a microprocessor and assigned, programmable memory devices for the storage and processing of software as well as a connector unit with connectors or circuits for communication between the controller and other controllers and/or actuators, sensors or the like, that are to be controlled with the controller. Both the central unit and the connector unit utilize a modular design. A collection of modules with different performances and/or functionalities are provided for both the central unit and the connector unit to form the hardware of a controller. The modules can be combined with one another and coupled together according to a modular concept.
    Type: Application
    Filed: May 7, 2004
    Publication date: December 16, 2004
    Applicant: DBT Automation GmbH
    Inventors: Ferdinand Uhlendorf, Wilfried Weigel, Johannes Wesselmann, Jens Titschert, Jurgen Tschope
  • Publication number: 20040254649
    Abstract: A system and a method for integrating electronic apparatuses, e.g. information appliances, are provided. The present invention detects and stores the functions of each electronic apparatus in advance. When one of the electronic apparatuses transmits a signal to execute a particular function, the present invention determines which electronic apparatus is the most suitable to execute the function and sends the signal to the very electronic apparatus without manual operations.
    Type: Application
    Filed: May 24, 2004
    Publication date: December 16, 2004
    Inventors: C. J. Jason Huang, Jong-Min Deng
  • Publication number: 20040254650
    Abstract: An electronic control system for cycles, for use with a set of sensors, a set of actuators, and a set of control members associated to a cycle. The system having a first processor unit for processing and displaying information; a second processor unit for communication and for interfacing with said set of control members; and a third processor unit for interfacing with said set of sensors and said set of actuators. The first processor unit, the second processor unit, and the third processor unit are connected together via asynchronous bi-directional communication channels.
    Type: Application
    Filed: June 29, 2004
    Publication date: December 16, 2004
    Applicant: Campagnolo Srl
    Inventors: Valentino Campagnolo, Gianfranco Guderzo
  • Patent number: 6832117
    Abstract: A processor core for realizing efficient operation processing by connecting an extended arithmetic unit to its exterior and a processor incorporating such a processing core are provided. The processor includes the processor core, a data memory accessed by the processor core, and the extended arithmetic unit connected to the exterior of the processor core for processing a particular instruction. The extended arithmetic unit executes an arithmetic operation by using arithmetic operation data retained in a register file in the processor core, and directly outputs an arithmetic operation result to the processor core. Then, the processor core saves the result of the arithmetic operation executed by the extended arithmetic unit and inputted therefrom in the register file in the processor core.
    Type: Grant
    Filed: September 21, 2000
    Date of Patent: December 14, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takashi Miyamori
  • Patent number: 6826438
    Abstract: A method for designing a control of a complete process (which can have a number of individual processes) can include: identifying functionalities of the individual processes; performing a validation by automatically verifying future interplay of the functionalities in accordance with an input to the complete process and producing a validation result; and determining data for future controlling of the complete process from the validation result. A process unit can be arranged to carry out such a method.
    Type: Grant
    Filed: January 3, 2001
    Date of Patent: November 30, 2004
    Assignee: Siemens Aktiengesellschaft
    Inventors: Bertil Brandin, Markus Kaltenbach
  • Publication number: 20040236438
    Abstract: A microprocessor system includes a plurality of modules, among them a microprocessor and at least one storage module for storing the code and/or data for the microprocessor. Stored, in a non-changeable manner, in at least one of the modules, referred to as exchange-protected module, is a serial number of this module. A control module is configured to receive a data value specified by the at least one serial number and to block, at least partially, the function of the microprocessor system if the received data value does not match an expected data value encoded in the control module.
    Type: Application
    Filed: March 10, 2004
    Publication date: November 25, 2004
    Inventors: Jochen Weber, Klaus Schneider, Axel Aue
  • Publication number: 20040225378
    Abstract: A method for processing data in a data processing system (1) which includes a number of data processing units (2), and operator and observation units (4), which are interconnected by way of a data transmission unit (6), whereby a respective data processing program (8) with corresponding function modules (FB1 to FBn) and data modules (DB 1 to DBn) is implemented in the data processing units (2). At least one identifier (K, KE, KI) for the function modules and data modules is stored in a respective conversion table (10) belonging to each data processing unit (2). When an external data processing unit (2) accesses a data module (DB1 to DBn) and/or a function module (FB1 to FBn) of another data processing unit (2), a conversion table (10) mediates by using an external identifier (KE) that characterizes the access and verifies whether a matching internal identifier (KI) is stored for the particular external identifier (KE).
    Type: Application
    Filed: January 2, 2004
    Publication date: November 11, 2004
    Applicant: SIEMENS AKTIENGESELLSCHAFT
    Inventors: Wilhelm Bollhoefer, Michael Dreher, Juergen Laforsch
  • Publication number: 20040225379
    Abstract: The configuration method for an installation comprising solar protection and/or lighting devices controlled by a central unit comprising a memory, computing means and a user interface, is characterized in that it comprises an iteration, over all of the solar protection and/or lighting devices, of the following steps:
    Type: Application
    Filed: January 21, 2004
    Publication date: November 11, 2004
    Applicant: SOMFY
    Inventors: Mattias Klasson, Dirk Mommaerts
  • Publication number: 20040210321
    Abstract: In an apparatus to be controlled 20 such as a USB-compatible peripheral device connected to a controlling apparatus such as a personal computer, when a specification change is detected such as a change in the apparatus to be controlled 20 itself and a change in the connection situation of an attached device 30 (S201: YES), identification information corresponding to the changed specification is extracted (S205) and the extracted identification information is set as identification information to be transmitted to the controlling apparatus 10 (S206). The identification information having been set is transmitted to the controlling apparatus 10, and the controlling apparatus 10 controls the apparatus to be controlled 20 having the changed specification, on the basis of the identification information.
    Type: Application
    Filed: March 16, 2004
    Publication date: October 21, 2004
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Motohiro Hayashi, Masahiro Inoue, Kazunori Miyamoto, Takeshi Yamaguchi, Yoshikazu Kondoh, Masakazu Suzuki, Kenji Ogasawara
  • Patent number: RE38911
    Abstract: Aspects for allowing variably controlled alteration of image processing of digital image data in a digital image capture device include forming an image processing chain with two or more image processors to process digital image data, and providing one or more parametric controls within each of the two or more image processors. The aspects further include accessing chosen controls of the one or more parametric controls to modify the two or more image processors for alteration of the image processing.
    Type: Grant
    Filed: November 21, 2001
    Date of Patent: December 6, 2005
    Assignee: Apple Computer, Inc.
    Inventors: Eric C. Anderson, Gary Chin