Including Program Set Up Patents (Class 702/123)
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Patent number: 8190392Abstract: A method and apparatus for determining a trigger in a test and measurement apparatus are provided. The method comprises the steps of loading a first trigger configuration to a first trigger element of the test and measurement apparatus and loading a second trigger configuration to a second trigger element of the test and measurement apparatus so that these trigger elements operate substantially simultaneously. It is then determined whether the input signal generates a trigger in accordance with the one or more trigger configurations.Type: GrantFiled: July 29, 2008Date of Patent: May 29, 2012Assignee: LeCroy CorporationInventors: Anthony Cake, Peter J Pupalaikis, David Graef, William Driver, Michael Hertz, Laxmikant Joshi
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Patent number: 8185339Abstract: The testing method of the present invention for testing a plurality of devices under test connected to a test module includes (a) determining combinations of devices under test that can theoretically be measured simultaneously from among the combinations of the plurality of devices under test based on at least the connection relationship between the test module and the plurality of devices under test. The testing method further includes (b) testing the plurality of devices under test by sequentially selecting the combinations of devices under test to be actually measured simultaneously from the combinations determined in (a).Type: GrantFiled: November 26, 2008Date of Patent: May 22, 2012Assignee: Advantest CorporationInventor: Hironori Maeda
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Patent number: 8180589Abstract: A semiconductor wafer inspection device which identifies an operator when an operation is performed and checks if the requested operation is permitted is provided. In a device that has already performed an operator authentication, the operator identification is further carried out when a particular operation is requested. If the operation requested is a permitted one, it is executed even if requested by an operator different from the one previously authenticated. The history of operations and the change history of in-device data are recorded and displayed. The operator authentication is performed only when necessary.Type: GrantFiled: September 23, 2008Date of Patent: May 15, 2012Assignee: Hitachi High-Technologies CorporationInventor: Yuko Toyoshima
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Patent number: 8155639Abstract: A system and method for antenna analysis and electromagnetic compatibility testing in a wireless device utilizes a “parent” device that undergoes rigorous conventional testing. A “child” device having similar components may thereafter undergo abbreviated testing. Because the Total Isotropic Sensitivity of the parent device is known, testing may be performed on the child device to infer equivalence to the parent's TIS performance using the abbreviated test techniques.Type: GrantFiled: March 20, 2008Date of Patent: April 10, 2012Assignee: AT&T Mobility II LLCInventor: Scott Dale Prather
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Patent number: 8156396Abstract: A system and method for reducing timing errors in automated test equipment (ATE) offering increased data rates for the testing of higher-speed integrated circuits. Embodiments provide an effective mechanism for increasing the data rate of an ATE system by delegating processing tasks to multiple test components, where the resulting data rate of the system may approach the sum of the data rates of the individual components. Each component is able to perform data-dependent timing error correction on data processed by the component, where the timing error may result from data processed by another component in the system. Embodiments enable timing error correction by making the component performing the correction aware of the data (e.g., processed by another component) causing the error. The data may be shared between components using existing timing interfaces, thereby saving the cost associated with the design, verification and manufacturing of new and/or additional hardware.Type: GrantFiled: October 5, 2010Date of Patent: April 10, 2012Inventors: Jean-Yann Gazounaud, Howard Maassen
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Publication number: 20120084043Abstract: A method can include providing spatial data for a base case of a subsurface geologic formation; providing spatial data for a simulation case of the subsurface geologic formation; performing box counting for the spatial data for the base case; performing box counting for the spatial data for the simulation case; based on the box counting for the spatial data for the base case, determining a fractal dimension for the base case; based on the box counting for the spatial data for the simulation case, determining a fractal dimension for the simulation case; comparing the simulation case to the base case based at least in part on the fractal dimensions; and, based on the comparing, adjusting one or more simulation parameters to generate spatial data for an additional simulation case of the subsurface geologic formation. Various other apparatuses, systems, methods, etc., are also disclosed.Type: ApplicationFiled: September 22, 2011Publication date: April 5, 2012Inventors: Sergio Fabio Courtade, Alina-Berenice Christ, Horacio Ricardo Bouzas
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Publication number: 20120072159Abstract: The present invention provides a method and a system for a universal software quality assurance automation framework. The three reusable components of this framework are composed of a test resource comprising of a test module-entity driver-entity communication. The test module provides an opportunity to create several case scenarios and test logics. The entity driver enables the test environment software entities to be accessible to the test module, without prior knowledge of where those entities are located. The entity communication enables the drivers to communicate with various entities inside the test environment. The combination of the three reusable components enable the framework to be product agnostic. Multiple tests may be performed in parallel. Test cases are presented in the integrated graphical user interface as a hierarchical managing structure. The framework is collaborative and multiple users may use it simultaneously.Type: ApplicationFiled: September 16, 2010Publication date: March 22, 2012Inventor: LINSONG WANG
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Publication number: 20120065921Abstract: Input/output interfaces of avionic modules of IMA type in a device including several modules is tested. A system includes at least one application employed by a set of computer modules. This set includes the computer module (a first module), and at least one other computer modul (at least one second module). A system test is associated with the at least one system for functionally testing the set of computer modules according to the system. The system test includes at least one elementary system test for functionally testing at least one input/output interface of the first module. The execution of the at least one elementary system test is independent of the at least one second module. At least one result of execution of the at least one elementary system test is transmitted to a maintenance computer distinct from the computer modules of the plurality of computer modules.Type: ApplicationFiled: July 28, 2011Publication date: March 15, 2012Applicant: AIRBUS OPERATIONS (S.A.S.)Inventors: Patrice Boucher, Nicolas Wacyk
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Publication number: 20120065922Abstract: A method of simulating an umbilical for use with a subsea fluid extraction well is provided. The method comprises using a programmed processing unit to condition an input electrical signal for producing an output signal characteristic of a signal which has passed through such an umbilical.Type: ApplicationFiled: September 12, 2011Publication date: March 15, 2012Inventor: Silviu Puchianu
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Patent number: 8135558Abstract: Embodiments herein present a method for automated simulation testbench generation for serializer/deserializer datapath systems. The method provides a database of transactors for generating and checking data within the datapath system, wherein the transactors are adaptable to arbitrary configurations of the datapath system. The database is provided with a single set of transactors per core. Next, the method automatically selects one set of transactors from the database for inclusion into the simulation testbenches. Following this, the method maps the first datapath and the second datapath through the datapath system by interconnecting the selected set of the transactors with the datapath system. The method further comprises setting control pins on the cores to facilitate propagation of the data through the cores of the datapath system. Subsequently, the control pins are traced to input ports and control registers.Type: GrantFiled: July 9, 2008Date of Patent: March 13, 2012Assignee: International Business Machines CorporationInventors: Francis A. Kampf, Jeanne Trinko-Mechler, David R. Stauffer
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Publication number: 20120035878Abstract: A method for obtaining an optimized process solution from a set of design of experiments in a cost effective manner is provided. An actual experiment is performed and data from the experiments is obtained. Through statistical analysis of the data, coefficients are obtained. These coefficients are input into an experiment simulator where input parameters and conditions are combined with the coefficients to predict an output for the input parameters and conditions. From simulated results, conclusions can be drawn as to sets of input parameters and conditions providing desired results. Thereafter, physical experiments utilizing the input parameters and conditions may be performed to verify the simulated results.Type: ApplicationFiled: October 17, 2011Publication date: February 9, 2012Applicant: INTERMOLECULAR, INC.Inventor: Prashant B. Phatak
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Patent number: 8112241Abstract: Methods and systems for generating an inspection process for a wafer are provided. One computer-implemented method includes separately determining a value of a local attribute for different locations within a design for a wafer based on a defect that can cause at least one type of fault mechanism at the different locations. The method also includes determining a sensitivity with which defects will be reported for different locations on the wafer corresponding to the different locations within the design based on the value of the local attribute. In addition, the method includes generating an inspection process for the wafer based on the determined sensitivity. Groups may be generated based on the value of the local attribute thereby assigning pixels that will have at least similar noise statistics to the same group, which can be important for defect detection algorithms. Better segmentation may lead to better noise statistics estimation.Type: GrantFiled: March 13, 2009Date of Patent: February 7, 2012Assignee: KLA-Tencor Corp.Inventor: Yan Xiong
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Patent number: 8103916Abstract: In an example embodiment, a method is provided for scheduling a check to detect anomalies in a computing system. An average time between the anomalies that are detectable by the check is identified and additionally, a runtime of the check is identified. A frequency of the check is then calculated based on the average time between the anomalies and the runtime of the check, and execution of the check may be scheduled based on the calculated frequency.Type: GrantFiled: December 1, 2008Date of Patent: January 24, 2012Assignee: SAP AGInventor: Udo Klein
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Patent number: 8086904Abstract: Detecting an anomaly is disclosed. An indication that a computer system monitoring instrument is desired to provide as output a subset of the output data that it would produce if it were to remain on throughout a relevant period with no limit being placed on its output at any point during the relevant period is received. The instrument is configured to provide as output only the desired subset.Type: GrantFiled: July 28, 2006Date of Patent: December 27, 2011Assignee: Apple Inc.Inventors: Theodore C. Goldstein, Stephen R. Lewallen, Maxwell O. Drukman
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Patent number: 8078423Abstract: A computer terminal retrieves pin data related to respective pins of a plurality of Field Programmable Gate Array that are mounted on a board. The computer terminal retrieves setting data related to a connection check. Upon retrieving the pin data and the setting data, the computer terminal assigns, as data for the connection check to all the pins that can output data, unique data that is unique to each pin. The computer terminal generates input pin data and output pin data containing the unique data, stores therein the input pin data and the output pin data, and generates checking circuits that check connections between output pins and input pins. The computer terminal generates checking data based on the checking circuits.Type: GrantFiled: September 21, 2007Date of Patent: December 13, 2011Assignee: Fujitsu LimitedInventors: Takakazu Tokunaga, Kouichi Tanda, Hiroaki Shiraishi, Yoshikatsu Kouhara, Koji Takatomi
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Patent number: 8078424Abstract: Provided is a test apparatus 10, which includes: a plurality of test modules 150, each of which is connected to any of the plurality of devices under test 100 to supply a test signal to the connected device under test 100; a plurality of site controllers 130 that control the plurality of test modules 150 to test the respective plurality of devices under test 100 simultaneously; a connection setting device 140 that sets a connection mode between the plurality of site controllers 130 and the plurality of test modules 150 so that each of the test modules 150 is connected to any of the plurality of site controllers 130; and a plurality of system controllers 110, each of which controls any of the plurality of site controllers 130, in which a predetermined system controller of the plurality of system controllers 110 assigns, in response to a request from another system controller of the system controllers, a site controller of the site controllers, which is to be controlled by the another system controller.Type: GrantFiled: September 29, 2008Date of Patent: December 13, 2011Assignee: Advantest CorporationInventor: Toshiaki Adachi
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Patent number: 8069011Abstract: A method for automatically creating a probability of detection (POD) curve of an entire network of transducers monitoring and detecting damage in a structure is based on the POD of each of the individual actuator-sensor paths. These individual path PODs may be generated in different ways, such as by experimentation or simulation. This technique makes it possible to create the POD curve of a structural health monitoring (SHM) system for the detection of damages in structures.Type: GrantFiled: April 15, 2008Date of Patent: November 29, 2011Assignee: Acellent Technologies, Inc.Inventors: Bao Liu, Fu-Kuo Chang
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Publication number: 20110288810Abstract: Provided is a test apparatus that tests a device under test, comprising a testing section that stores a program in which commands to be executed branch according to detected branching conditions and that tests the device under test by executing the program; and a log memory that stores test results of the testing section in association with command paths of the program executed to obtain the test results. The testing section sequentially changes a characteristic of a test signal supplied to the device under test, and judges pass/fail of the device under test for each characteristic of the test signal, and the log memory stores a test result of the testing section in association with a command path of the program, for each characteristic of the test signal.Type: ApplicationFiled: May 30, 2011Publication date: November 24, 2011Applicant: ADVANTEST CORPORATIONInventors: Shinichi ISHIKAWA, Tetsu KATAGIRI, Masaru GOISHI, Hiroyasu NAKAYAMA, Masaru TSUTO
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Patent number: 8065107Abstract: A method for obtaining an optimized process solution from a set of design of experiments in a cost effective manner is provided. An actual experiment is performed and data from the experiments is obtained. Through statistical analysis of the data, coefficients are obtained. These coefficients are input into an experiment simulator where input parameters and conditions are combined with the coefficients to predict an output for the input parameters and conditions. From simulated results, conclusions can be drawn as to sets of input parameters and conditions providing desired results. Thereafter, physical experiments utilizing the input parameters and conditions may be performed to verify the simulated results.Type: GrantFiled: October 9, 2008Date of Patent: November 22, 2011Assignee: Intermolecular, Inc.Inventor: Prashant B. Phatak
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Patent number: 8055467Abstract: A method of generating an IRF pattern for testing an IC and a test pattern generator are disclosed. In one embodiment, the method includes: (1) identifying a path of the integrated circuit for inline resistive fault pattern generation, (2) determining if the path is a minimal slack path of the IC and (3) generating, when the path is the minimal slack path, a restricted inline resistive fault pattern for the path using only a capture polarity having a minimal inherent margin.Type: GrantFiled: December 17, 2008Date of Patent: November 8, 2011Assignee: LSI CorporationInventors: Jeff S. Brown, Marek Marasch, John Gatt
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Patent number: 8050882Abstract: A system and method for online configuration of a measurement system. The user may access a server over a network and specify a desired task, e.g., a measurement task, and receive programs and/or configuration information which are usable to configure the user's measurement system hardware (and/or software) to perform the desired task. Additionally, if the user does not have the hardware required to perform the task, the required hardware may be sent to the user, along with programs and/or configuration information. The hardware may be reconfigurable hardware, such as an FPGA or a processor/memory based device. In one embodiment, the required hardware may be pre-configured to perform the task before being sent to the user. In another embodiment, the system and method may provide a graphical program in response to receiving the user's task specification, where the graphical program may be usable by the measurement system to perform the task.Type: GrantFiled: April 21, 2009Date of Patent: November 1, 2011Assignee: National Instruments CorporationInventors: Brian Sierer, Ganesh Ranganathan, John Pasquarette, David W Fuller, III, Joseph E. Peck, Matthew Novacek, Hugo A. Andrade
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Patent number: 8041979Abstract: A method of synchronizing respective state transitions in a group of devices including at least one responding device is disclosed. The group of devices is communicatively coupled to an initiating device via a communication network. The method includes the at least one responding device receiving a trigger message from the initiating device. The trigger message includes a state transition time or a time from which a state transition time is obtainable. The method further includes the at least one responding device jointly making a respective state transition at the state transition time. A responding device, and a system including the initiating device and the responding device are also disclosed.Type: GrantFiled: October 29, 2007Date of Patent: October 18, 2011Assignee: Agilent Technologies, Inc.Inventors: James Adam Cataldo, Bruce Hamilton
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Publication number: 20110251821Abstract: A method and a device for testing a computer core in a processor having at least two computer cores is described. The computer cores are connected to each other via an internal connecting system, both computer cores contributing toward the operating sequence of a machine. In the method for testing a computer core, with which a high error detection rate may be achieved in a minimum outlay of time, a test is run in one computer core, while a program for executing the driving operation of the motor vehicle is being processed in the other computer core at the same time.Type: ApplicationFiled: September 3, 2009Publication date: October 13, 2011Applicant: ROBERT BOSCH GMBHInventors: Bernd Mueller, Axel Aue
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Patent number: 8037109Abstract: Systems and methods are provided for the generation of synthetic repeatable data. In an illustrative implementation, an exemplary data environment comprises at least one computing application for the management, manipulation, and generation of data. The computing application operates on a predefined set of rules to generate a data set, having N elements, using a deterministic generator function which when executed always produces the same set of data. The seed is used to position the generator to a particular point in its sequence. To regenerate any particular entry in the data set, the generator, using the seed as an input, is executed and the desired data is re-generated. The illustrative implementation also contemplates that the generation of data may be parallelizable as each element is generated independently of any others.Type: GrantFiled: June 30, 2003Date of Patent: October 11, 2011Assignee: Microsoft CorporationInventors: Charles J. Levine, Jamie A. Reding, Sergey Vasilevskiy
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Patent number: 8036874Abstract: There is provided with a software executing device co-operating with a hardware circuit or a hardware simulator, including: a software executing unit configured to execute a software; an execution monitoring unit configured to monitor execution of the software by the software executing unit to sequentially obtain an execution state of the software; a determining unit configured to determine whether the software executing unit and the hardware circuit or the hardware simulator are to be synchronized based on an obtained execution state of the software; and a synchronization controlling unit configured to control synchronization between the software executing unit and the hardware circuit or the hardware simulator.Type: GrantFiled: June 20, 2008Date of Patent: October 11, 2011Assignee: Kabushiki Kaisha ToshibaInventor: Masato Igarashi
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Publication number: 20110224939Abstract: Architecture includes an integrated tool that allows a tester to automatically persist test plan information in association with related content while the tester is interacting with that content in an IDE. The tool further enables the tester to formally associate actions/expectations with specific items of content. In previous solutions, references to existing content are often lost due to inexact or missing descriptions. Formal associations allow for reuse of valuable content and avoid unnecessary recreation. The tool is integrated with the IDE, and thus, does not necessitate that the tester manually type or write descriptions of intent and expectations. This reduces the test plan cost significantly. The tool also persists information in a formal, self-describing format that enables easy consumption by either human testers or secondary software applications (e.g., for the purposes of identifying plans, performing associated actions and verifying expected behavior).Type: ApplicationFiled: March 10, 2010Publication date: September 15, 2011Inventors: Manish K. Jayaswal, Prakash Balasubramanian, Kevin Halverson, Sarika Calla, David Sterling, Murad Tariq, Eric Maino
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Patent number: 8019566Abstract: A system and method for using a single test case to test each sector within multiple congruence classes is presented. A test case generator builds a test case for accessing each sector within a congruence class. Since a congruence class spans multiple congruence pages, the test case generator builds the test case over multiple congruence pages in order for the test case to test the entire congruence class. During design verification and validation, a test case executor modifies a congruence class identifier (e.g., patches a base register), which forces the test case to test a specific congruence class. By incrementing the congruence class identifier after each execution of the test case, the test case executor is able to test each congruence class in the cache using a single test case.Type: GrantFiled: September 11, 2007Date of Patent: September 13, 2011Assignee: International Business Machines CorporationInventors: Vinod Bussa, Shubhodeep Roy Choudhury, Manoj Dusanapudi, Sunil Suresh Hatti, Shakti Kapoor, Batchu Naga Venkata Satyanarayana
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Patent number: 8019049Abstract: A method for generating reliability tests for a telephone system is based upon sampling an orthogonal array which covers various combinations of test parameters. Field data is collected of actual telephone activity on a telephone system. The field data is evaluated so as to determine call-mix characteristics. Probabilistic weights for the different call-mix characteristics are obtained, and then the probabilistic weights are used to sample the test case scenarios generated in the orthogonal array which have the same call-mix characteristics. These test case scenarios are used to run tests on the telephone system. These tests are preferably performed using automated test scripts. After the test data is collected, reliability metrics are calculated from the test data.Type: GrantFiled: March 27, 2007Date of Patent: September 13, 2011Assignee: Avaya Inc.Inventors: James J. Allen, Jr., Janet Kenny, John Yeager, Muharrem Umit Uyar, Linda Yeager
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Publication number: 20110213580Abstract: A buffer solution is made based on electrode features of a biological testing device. An interference agent for stabilizing measurement signals from the biological testing sheet is prepared. An enzyme is prepared based on parameters of the biological testing device and the electrode properties. An optimum electrode potential is determined and then the properties of the electrodes are reevaluated using potassium ferricyanide and potassium ferrocyanide. Enzyme from an incomplete biological testing sheet is retained, which is dried, covered and cut. The number of sets is determined and the steps repeated to find optimal ingredients and corresponding testing sheets. Sampling and testing of the biological testing sheets using different parameter codes is performed until all parameter codes are tested to determine process completion. Thus, biological testing sheets matching different biological testing devices from different manufactures or biological testing devices are provided.Type: ApplicationFiled: July 16, 2008Publication date: September 1, 2011Inventors: Chia-Nan Wang, Chi-Yuan Lin
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Publication number: 20110208469Abstract: The invention relates to a method of automatic testing of a software system through test driver code that classifies test data into equivalence classes and updates the available test data after using it against the software system. One embodiment of the invention is a Test Runner that monitors the effect of calling the software system on the available test data and uses this information to automatically determine the execution order of test cases to meet a number of objectives including to: Reuse data between calls, ensure all test cases are executed, perform parallelized testing, perform time dependent testing, perform continuous testing according to a probability distribution on test cases, perform automated management of complex test data and finally to provide an easy and concise way for a user to define a large sets of test cases.Type: ApplicationFiled: May 15, 2009Publication date: August 25, 2011Inventor: Simeon Falk Sheye
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Publication number: 20110208470Abstract: An operation verifying apparatus of a first embodiment acquires a log indicating the content of a sequence of operations performed on a predetermined device, identifies corresponding functions from the log, and automatically generates a program based on the identified functions. Input data, which is to serve as an argument of each of these functions, is set. Execution sets as well as test scenarios are each structured by combining a program and input data. Then each execution set is continuously executed. As a result, an operation test using a test program is executed.Type: ApplicationFiled: May 2, 2011Publication date: August 25, 2011Applicant: Nomura Research Institute, Ltd.Inventors: Mamoru Yasuda, Shunichi Matsumoto, Takaya Higashino, Eiji Nabika, Hayato Takabatake, Takuma Ishibashi, Takuharu Mizoguchi
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Publication number: 20110209124Abstract: Systems and methods of conducting interoperability assessments provide for generating a feature interoperability matrix based on feature data and interoperability data, wherein the feature data defines a plurality of features of a product and the interoperability data indicates levels of interoperability of the plurality of features. A validation set can be generated based on the feature interoperability matrix, wherein the validation set includes a plurality of feature combinations. A subfeature interoperability matrix can be used to convert the validation set into a test plan for the product, wherein the test plan minimizes test configurations for the product.Type: ApplicationFiled: April 22, 2010Publication date: August 25, 2011Inventor: Satwant Kaur
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Patent number: 8005639Abstract: A system and method (“utility”) for automated testing using a compact framework is provided. The utility includes a plurality of functionalities that include development of a test module, development of a test flow, and execution of a test flow. Each of these functionalities may be separated by the compact framework, such that automated testing functions may be divided into individual roles. The individual roles may include test developer, test flow designer, and test flow executor. The utility may also include an authenticator that is operable to determine the individual role of a user (e.g., using a GUI), and to provide the functionality that corresponds to that role. The utility may provide one or more displays that provide real time data feedback. Further, the utility may be operable to generate customized test results reports that enable a user to analyze the performance of one or more devices under test.Type: GrantFiled: September 4, 2008Date of Patent: August 23, 2011Assignee: Flextronics AP, LLCInventors: Ya Chao Ding, Guo Hua Zue
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Patent number: 8000928Abstract: A method and apparatus for data analysis according to various aspects of the present invention is configured to automatically select one or more outlier identification algorithms for identifying statistical outliers in test data for components.Type: GrantFiled: April 29, 2008Date of Patent: August 16, 2011Assignee: Test Advantage, Inc.Inventors: Michael J. Scott, Jacky Gorin, Paul Buxton, Eric Paul Tabor
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Patent number: 8000922Abstract: Methods and systems for generating information to be used for selecting values for parameter(s) of a detection algorithm are provided. One method includes without user intervention performing a scan of an area of a wafer using an inspection system and default values for parameter(s) of a detection algorithm to detect defects on the wafer. The method also includes selecting a portion of the defects from results of the scan based on a predetermined maximum number of total defects to be used for selecting values for the parameter(s) of the detection algorithm. The method further includes storing information, which includes values for the parameter(s) of the detection algorithm determined for the defects in the portion. The information can be used to select the values for the parameter(s) of the detection algorithm to be used for the inspection recipe without performing an additional scan of the wafer subsequent to the scan.Type: GrantFiled: May 29, 2008Date of Patent: August 16, 2011Assignee: KLA-Tencor Corp.Inventors: Hong Chen, Michael J. Van Riet, Chien-Huei (Adam) Chen, Jason Z. Lin, Chris Maher, Michal Kowalski, Barry Becker, Stephanie Chen, Subramanian Balakrishnan, Suryanarayana Tummala
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Publication number: 20110191057Abstract: A graphical representation of a feature and associated tolerance includes a graphical representation of a nominal definition of the feature; and a graphical representation of the tolerance zones, derived from the nominal definition of the feature.Type: ApplicationFiled: February 4, 2010Publication date: August 4, 2011Applicant: Quality Vision International, Inc.Inventor: Kenneth L. Sheehan
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Publication number: 20110184689Abstract: A method of automatic formulation by a computer of test cases for verifying at least one function of a piece of software in relation to a specification including requirements relating input values and output values of the software, the method including the steps of: distinguishing combinatorial requirements and sequential requirements; modeling combinatorial requirements by a truth table and sequential requirements by a finite state machine to obtain a modeled specification; establishing an operation matrix relating the input values of the software with a probability of them being in succession and a transition time between them; selecting the successions of input values to be tested by performing a Monte Carlo draw on the operation matrix; determining a test case including test rows relating each selected succession with the output values expected given the modeled specification; stopping the determination process when the test case being determined makes it possible to reach a predetermined threshold forType: ApplicationFiled: May 19, 2009Publication date: July 28, 2011Inventors: Roy Awedikian, Bernard Yannou, Philippe Lebreton, Line Bouclier, Mounib Mekhilef
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Patent number: 7983871Abstract: A method includes determining at least a first characteristic of a device during a first test insertion and storing the first characteristic. The device is identified during a second test insertion. The first characteristic is retrieved responsive to the identification of the device. A test program for the second insertion is configured based on the first characteristic. The configured test program is executed to test the device during the second test insertion.Type: GrantFiled: September 4, 2007Date of Patent: July 19, 2011Assignee: Advanced Micro Devices, Inc.Inventors: Douglas C. Kimbrough, Michael A. Retersdorf, Kevin R. Lensing
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Publication number: 20110153258Abstract: The objective of the present invention is to efficiently create a test table in a monitoring control system.Type: ApplicationFiled: June 9, 2010Publication date: June 23, 2011Applicant: MITSUBISHI ELECTRIC CORPORATIONInventor: Shinichiro TSUDAKA
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Publication number: 20110153259Abstract: A measuring system for determining a value of a physical or chemical, measured variable of a medium, comprises: a base unit; at least one relay unit connected with the base unit and a sensor unit connected with the relay unit. The relay unit is especially embodied to receive from the base unit, and to forward to the sensor unit, data, especially measurement data, operating data, commands or software modules, and/or to receive from the sensor unit, and to forward to the base unit, data, especially measurement data, operating data, commands or software modules wherein the sensor unit comprises a circuit having at least one microcontroller, at least a first memory region, in which a basic software of the sensor unit is stored, and a second memory region, in which an upload software of the sensor unit is stored.Type: ApplicationFiled: December 17, 2010Publication date: June 23, 2011Applicant: Endress + Hauser Conducta Gesellschaft fur Mess- und Regeltechnik mbH + Co. KGInventors: Ronny Michael, Hermann Günther, Sven-Matthias Scheibe, Hendrik Zeun
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Patent number: 7962314Abstract: A processor having one or more processor cores includes execution logic that may execute instructions including one or more processes. Each process may include one or more execution threads. The processor also includes a profiling mechanism that includes monitor logic and a monitor process. The monitor logic may monitor the one or more processes and provide access to performance data associated with the one or more processes without interrupting a flow of control of the one or more processes being monitored. The monitor process may gather the performance data. In addition, the monitor process may include program instructions executable by the one more processor cores while operating in user mode.Type: GrantFiled: December 18, 2007Date of Patent: June 14, 2011Assignee: GLOBAL FOUNDRIES Inc.Inventor: Anton Chernoff
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Publication number: 20110137606Abstract: Provided is a test apparatus that tests a device under test, comprising: a plurality of channels that output and receive signals to and from the device under test; a generating section that generates a packet data sequence transmitted to and from the device under test; and a channel selecting section that selects which of the channels is used to transmit the packet data sequence generated by the generating section.Type: ApplicationFiled: December 7, 2010Publication date: June 9, 2011Applicant: ADVANTEST CORPORATIONInventors: Shinichi ISHIKAWA, Masaru GOISHI, Hiroyasu NAKAYAMA, Masaru TSUTO
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Publication number: 20110131002Abstract: The invention relates to a method of automatic testing of a first software system using a test specification, the first software system comprising data and interacting with a third software system communicatively coupled to a database; the method comprising defining at least one operation; wherein an operation operates on at least one of at least one entity; defining at least one test condition; wherein a test condition defines at least one required value of a number of properties of at least one entity in order for the at least one entity to be passed on to the at least one operation and wherein said at least one test condition is defined by at least one condition generating expression in said test specification; operating, via said third software system, said at least one operation on said first software system, transmitting from the first software system to the third software system first data representing a result of said at least one operation operating on said first software system; if the first data saType: ApplicationFiled: May 15, 2008Publication date: June 2, 2011Inventor: Simeon Falk Sheye
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Patent number: 7949899Abstract: An electronic apparatus testing method is provided. The method includes the step of: reading a product ID of the electronic apparatus when the electronic apparatus is connected to a control apparatus; determining the device type ID from the product ID, wherein the product ID comprises basic information of the electronic apparatus, determining the script files of the functions of the electronic apparatus in the testing table according to the device type ID; obtaining the script files from a data storage and running the script files to test functions of the electronic apparatuses, sending a control instruction to the corresponding measuring device of the function to control the measuring device test the function during the process of running the script files; and displaying test results through a display of the control apparatus.Type: GrantFiled: July 17, 2008Date of Patent: May 24, 2011Assignees: Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.Inventors: Peng Chen, Yao Zhao, Hua-Dong Cheng, Wen-Chuan Lian, Han-Che Wang, Kuan-Hong Hsieh
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Publication number: 20110112790Abstract: The present invention relates to a system and a method for creating hardware and/or software test sequences and in particular, to such a system and method in which modular building blocks are used to create, sequence and schedule a large scale testing sequence using a matrix like platform.Type: ApplicationFiled: July 7, 2009Publication date: May 12, 2011Inventors: Eitan Lavie, Assaf Tamir, Moshe Moskovitch
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Publication number: 20110098963Abstract: In an embodiment, a method is provided. In this method, contexts used in a test are accessed, and these contexts are defined separate from the test. One of these contexts (a “first context”) defines a dependency to another context (a “second” context). A system of relationships between the contexts is constructed based on the dependency defined by the first context. The test is then executed using a number of contexts identified from the system of relationships.Type: ApplicationFiled: October 23, 2009Publication date: April 28, 2011Applicant: Cisco Technology, Inc.Inventor: Lakshmankumar Mukkavilli
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Publication number: 20110098964Abstract: A test system (1) comprises a system-on-chip with a memory (7) for storing sample data; and a dynamic test engine (4) to control input of dynamic test waveforms including sinusoidal waveforms to an ADC under test (15) and to determine device under test dynamic parameters by analysing the samples. A linear test engine (5) determines device under test (15) static parameters, and controls input of ramp input waveforms to the ADC. A test controller (2) performs finite sate machine control of testing including applying test waveforms, dumping samples to the memory (7), and retrieving static and dynamic results. A DAC (3) generates controlled waveform generation under instructions from the test engines, and an interface (10) communicates with an external host. The components are linked with a bus (11) and are modular.Type: ApplicationFiled: June 12, 2009Publication date: April 28, 2011Inventors: Brendan Mullane, Thomas Fleischmann, Vincent O'brien
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Patent number: 7930130Abstract: A system and method for reducing device test time are disclosed herein. A method for reducing device test time includes applying a linear program solver to select a first set of tests for testing a device from a second set of tests for testing the device. The first set of tests is selected to reduce the time required to test the device while allowing no more than a predetermined number of devices tested to pass the first set of tests and fail the second set of tests.Type: GrantFiled: July 2, 2008Date of Patent: April 19, 2011Assignee: Texas Instruments IncorporatedInventors: Charlotte Sakarovitch, Marielle Perrin, Laurent Zenouda
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Patent number: 7925456Abstract: A method and apparatus is disclosed that guides a user through a sequence of steps that will allow the user to complete a predefined task using the flow meter. The steps include: selecting a predefined task, displaying a sequence of steps that directs the user through a process for using the Coriolis flow meter to complete the predefined task, and operating the Coriolis flow meter in response to the sequence of steps to complete the predefined task.Type: GrantFiled: December 30, 2004Date of Patent: April 12, 2011Assignee: Micro Motion, Inc.Inventors: Craig B. McAnally, Andrew T. Patten, Charles P. Stack, Jeffrey S. Walker, Neal B. Gronlie
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Patent number: 7921248Abstract: A configuration facility is presented and specified, with at least one computer unit and a display device for the configuration of a time-triggered bus system. The bus system has at least two bus nodes and a data bus connecting the bus nodes. At least one node task and at least one transmission task can be executed at the bus nodes. The node tasks can be presented in time sequence in a node task field, the transmission tasks can be presented in time sequence in a transmission task field separate from the node task field, and the node tasks and the transmission tasks can be coordinated with each other by graphic allocation.Type: GrantFiled: November 20, 2008Date of Patent: April 5, 2011Assignee: dSpace digital signal processing and control engineering GmbHInventors: Kai Brinksmeier, Ralf Stolpe, Nico Loose