Including Program Set Up Patents (Class 702/123)
-
Patent number: 7912184Abstract: A method and system for testing a Telephony User Interface is disclosed. Voice prompts of the Telephony User Interface are converted into tone prompts that are representative thereof. Each tone prompt can have a predetermined frequency and/or duration, so that it is readily recognizable by a Telephony User Interface tester. Thus, automation of the testing of Telephony User Interface is enhanced.Type: GrantFiled: June 24, 2005Date of Patent: March 22, 2011Assignee: Cisco Technology, Inc.Inventor: Ravindra Koulagi
-
Patent number: 7912669Abstract: A process for a prognosis of faults in electronic circuits identifies parameters of a circuit under test. An upper and a lower limit is determined for one or more components of the circuit under test. A population of faulty and non-faulty circuits are generated for the circuit under test, and feature vectors are generated for each faulty and non-faulty circuit. The feature vectors are stored in a fault dictionary, and a feature vector for an implementation of the circuit under test in a field operation is generated. The feature vector for the implementation of the circuit under test in the field operation is compared to the feature vectors in the fault dictionary.Type: GrantFiled: March 27, 2007Date of Patent: March 22, 2011Assignee: Honeywell International Inc.Inventor: Sumit K. Basu
-
Patent number: 7904278Abstract: The present disclosure is directed towards methods and systems and methods for measuring the integrity of an operating system's execution and ensuring that the system's code is performing its intended functionality. This includes examining the integrity of the code that the operating system is executing as well as the data that the operating system accesses. Integrity violations can be detected in the dynamic portions of the code being executed.Type: GrantFiled: May 2, 2007Date of Patent: March 8, 2011Assignee: The Johns Hopkins UniversityInventors: Perry W. Wilson, J. Aaron Pendergrass, C. Durward McDonell, III, Peter A. Loscocco, David J. Heine, Bessie Y. Lewis
-
Patent number: 7903746Abstract: A mechanism uses in-situ bidirectional cable wrapping for determining different cable lengths. A calibration mechanism calibrates the high speed transmitter/receiver pair characteristics, and, thus, optimizes the transmission performance between subsystems. The calibration mechanism mitigates the need for frequent error correction and does not incur the performance degradation associated with error correction techniques.Type: GrantFiled: July 26, 2007Date of Patent: March 8, 2011Assignee: International Business Machines CorporationInventors: Brian James Cagno, Gregg Steven Lucas, Thomas Stanley Truman
-
Patent number: 7890808Abstract: A solution is proposed for testing a software application. The test includes the execution of a series of test cases, each one involving the application of a predefined test input to the software application. The software application generates a corresponding output in response to this test input. A result of the test case is determined by comparing the actual output provided by the software application with an expected output thereof. The expected output of the test case is determined automatically. For this purpose, multiple auxiliary sources are exploited, such as other software applications different from the one under test. Each auxiliary source receives a corresponding input, derived from the test input, which is intended to cause the auxiliary source to provide the same expected output as the software application. The expected output is then estimated according to the actual outputs provided by the different auxiliary sources.Type: GrantFiled: December 13, 2007Date of Patent: February 15, 2011Assignee: International Business Machines CorporationInventors: Salvatore Branca, Angela Molinari, Edoardo Turano
-
Patent number: 7890288Abstract: A method and system for optimizing a test plan of an Integrated Circuit (IC). The test plan includes two or more test sequences. A test sequence includes the measurement of a parameter of the IC. The total test time of the IC is reduced by performing one or more activities during a desired wait time associated with the measurement of the parameter. The test plan may be further optimized by modifying the one or more activities performed during the desired wait time.Type: GrantFiled: November 5, 2007Date of Patent: February 15, 2011Assignee: Anadigics, Inc.Inventor: Michael Joseph Raneri
-
Patent number: 7881887Abstract: A system and method for wireharness testing includes at least one probe attachable to a connector of a wireharness, the at least one probe in wireless communication with a controller to identify a potential lack of continuity in the wireharness therebetween.Type: GrantFiled: July 14, 2008Date of Patent: February 1, 2011Assignee: Sikorsky Aircraft CorporationInventor: William P. Kinahan
-
Patent number: 7870447Abstract: System and method for carrying out a process on an integrated circuit. The method includes reading a data key including subkeys, determining a process parameter set using a parameter directory in a manner dependent on the data key read in, and setting the parameters required for the process in accordance with the process parameter set determined. The parameter directory includes rule keys each having subkeys, which are each assigned predeterminable values from a plurality of values, and at least one subkey is assigned a wildcard, and a plurality of process parameter sets each respectively assigned at least one rule key. The step of determining a parameter set includes comparing the data key read in with the rule keys stored in the parameter directory, determining the rule key(s) whose subkeys match those of the data key read in, and outputting the process parameter set(s) assigned to the rule key(s) determined.Type: GrantFiled: November 28, 2005Date of Patent: January 11, 2011Assignee: Qimonda AGInventor: Thomas Grebner
-
Patent number: 7865335Abstract: Techniques are disclosed for integrating complexity analysis with procedure authoring (design and/or documentation). By way of example, a technique for authoring a procedure associated with a computing system operation based on a complexity analysis associated with the operation and the computing system implementing the operation comprises the following steps/operations. A procedure associated with a computing system operation is generated, wherein the generated procedure represents a new procedure or an edited existing procedure. A structured representation of the generated procedure is extracted from the generated procedure. The structured representation of the generated procedure is analyzed to produce complexity analysis results, wherein at least a portion of the complexity analysis results are fed back to a procedure author for use in selectively altering the generated procedure.Type: GrantFiled: December 28, 2007Date of Patent: January 4, 2011Assignee: International Business Machines CorporationInventors: Aaron B. Brown, Joseph Y. Kim
-
Patent number: 7865278Abstract: A diagnostic test sequence optimizer includes a diagnostic test selector that determines a group of diagnostic test procedures related to a specific symptom and vehicle type from a pool of diagnostic procedures. A failure mode analyzer then selects one or more factors that can affect resolution of a vehicle operational problem and performs a failure mode analysis to quantify a comparative utility of the individual tests, and a factor weighter assigns a weight to each of the factors. A vehicle receiver receives information regarding the history of the test subject vehicle, and a sequence optimizer places the diagnostic test procedures in an optimized sequence in accordance with the comparative utilities of the individual diagnostic procedures, user preferences and a Failure Mode and Effects Analysis compiled by the manufacturer of the vehicle.Type: GrantFiled: June 14, 2006Date of Patent: January 4, 2011Assignee: SPX CorporationInventors: Olav M. Underdal, Harry M. Gilbert, Oleksiy Portyanko, Randy L. Mayes, Gregory J. Fountain, William W. Wittliff, III
-
Patent number: 7853425Abstract: Provided is a method and system for testing a DUT. The system includes a plurality of testing devices for interacting with the DUT and conducting a plurality of different tests on the DUT, and a computer-readable memory for storing computer-executable instructions defining the plurality of tests to be conducted by the testing device on the DUT. A scheduler component designates at least a first test and a second test from the plurality of tests to be conducted on the DUT in parallel, wherein said designating is based at least in part on content of the computer-executable instructions defining the first test and the second test. And a controller initiates the first test and the second test to be conducted in parallel and initiating at least a third test sequentially relative to at least one of the first and second tests.Type: GrantFiled: July 11, 2008Date of Patent: December 14, 2010Assignee: Keithley Instruments, Inc.Inventors: Jerold A. Williamson, Michael Chao, Joseph N. Furio, Miao Lei
-
Patent number: 7844413Abstract: Self-generated automated tests can use a pseudo-random number generator to select one or more arguments that are passed to programs and scripts. The random arguments are driven by a configuration file where the limits for the parameters are defined. Multidimensional functions with multidimensional parameters can be tested. Test duration can be limited by time, number of iterations, or by any of the multidimensional functions or parameters. A pseudo-random seed for each test is recorded so that a test case can be reproduced if a failure is detected or otherwise.Type: GrantFiled: September 7, 2005Date of Patent: November 30, 2010Assignee: Broadcom CorporationInventors: Angela E. Overman, Eric S. Noya, Jeffrey T. Wong
-
Patent number: 7844412Abstract: Test systems and methodologies are provided and may include platforms for developing test programs for automated testing. In one example, tester and instruments are isolated from the tester OS, permitting any OS to be used. In another, a user layer is isolated from the physical layer, permitting hardware-independent development and usability among different tester platforms. In another, test program execution is isolated from tester platform OS, permitting test program function independent from tester platform. In another embodiment, functions are only added, existing links to functions are not broken, ensuring continued operation with new software, hardware and/or features. Systems may be non-deterministic. In one example, the non-deterministic computer is required to execute computer instructions within a constant execution time. A deterministic engine may be used to wait a variable amount of time to ensure constant execution time.Type: GrantFiled: July 10, 2007Date of Patent: November 30, 2010Inventors: Barry E. Blancha, Leszek Janusz Lechowicz, Stephen S. Helm, Sean Patrick Adam, Jorge Camargo, Carlos Heil, Paulo Mendes
-
Patent number: 7836426Abstract: System and method for generating an application domain specific graphical program. A graphical user interface (GUI) for specifying functionality of a graphical program in an application domain is displayed, where the GUI corresponds specifically to the application domain. User input to the GUI specifying the functionality of the graphical program is received, and the graphical program generated in response, where the graphical program is executable to perform the specified functionality, and comprises multiple interconnected graphical program nodes that visually represent the graphical program functionality. The GUI includes graphical interface elements operable to indicate and/or specify, e.g.Type: GrantFiled: February 7, 2006Date of Patent: November 16, 2010Assignee: National Instruments CorporationInventors: Joseph E. Peck, Matthew E. Novacek
-
Patent number: 7836398Abstract: Generated is a template edition screen on which to display components of a report as modules by OSD by use of icons. One of the icons is selected by use of a pointing device including a mouse. By a drag-and-drop operation, the icon is placed at a desired position in an output format setup area formed in the same screen. The icon is set in a desired size by another drag-and-drop operation. Details of a module shown by the icon thus placed can be set up in a detail setup area in the same screen. Information on a format thus set up is retained as a template through a retention function, and accordingly can be used easily by simply calling the information. Moreover, the retained template can be edited as well. This makes it possible not only to create a new template, but also to modify an existing template.Type: GrantFiled: January 29, 2007Date of Patent: November 16, 2010Assignee: Hitachi-High Technologies CorporationInventor: Takehiro Hirai
-
Publication number: 20100274520Abstract: Test plan to be utilized in a testing phase may be generated based on an initial test plan. A functional coverage model may be derived from the initial test plan. Modifications to the test plan may be automatically determined based on predetermined rules and parameters. Restrictions over possible combinations of values may be determined based on analysis of uncovered test activities in the initial test plan. Restrictions may be determined based on values of test activities in the initial test plan. Restrictions and modifications determined according to the disclosed subject matter may be indicated to a user for confirmation thereof.Type: ApplicationFiled: June 22, 2010Publication date: October 28, 2010Applicant: International Business Machines CorporationInventors: Shmuel Ur, Aviad Zlotnick
-
Patent number: 7810005Abstract: A system and method for reducing timing errors in automated test equipment (ATE) offering increased data rates for the testing of higher-speed integrated circuits. Embodiments provide an effective mechanism for increasing the data rate of an ATE system by delegating processing tasks to multiple test components, where the resulting data rate of the system may approach the sum of the data rates of the individual components. Each component is able to perform data-dependent timing error correction on data processed by the component, where the timing error may result from data processed by another component in the system. Embodiments enable timing error correction by making the component performing the correction aware of the data (e.g., processed by another component) causing the error. The data may be shared between components using existing timing interfaces, thereby saving the cost associated with the design, verification and manufacturing of new and/or additional hardware.Type: GrantFiled: October 31, 2007Date of Patent: October 5, 2010Assignee: Credence Systems CorporationInventors: Jean-Yann Gazounaud, Howard Maassen
-
Publication number: 20100235134Abstract: Methods and systems for generating an inspection process for a wafer are provided. One computer-implemented method includes separately determining a value of a local attribute for different locations within a design for a wafer based on a defect that can cause at least one type of fault mechanism at the different locations. The method also includes determining a sensitivity with which defects will be reported for different locations on the wafer corresponding to the different locations within the design based on the value of the local attribute. In addition, the method includes generating an inspection process for the wafer based on the determined sensitivity. Groups may be generated based on the value of the local attribute thereby assigning pixels that will have at least similar noise statistics to the same group, which can be important for defect detection algorithms. Better segmentation may lead to better noise statistics estimation.Type: ApplicationFiled: March 13, 2009Publication date: September 16, 2010Applicant: KLA-TENCOR CORPORATIONInventor: Yan Xiong
-
Patent number: 7797123Abstract: One embodiment of the present invention provides systems and techniques to extract assume properties from a constrained random test-bench. During operation, the system can receive a constrained random test-bench for verifying the design-under-test (DUT), wherein the constrained random test-bench includes a statement which assigns a random value to a random variable according to a constraint. Next, the system can modify the constrained random test-bench by replacing the statement with another statement which assigns a free input variable's value to the random variable. The system can also add a statement to the constrained random test-bench that toggles a marker variable to localize the scope of the statement. The system can then generate an assume property which models the constraint on the free input variable. The assume property can then be used by a formal property verification tool to verify the DUT.Type: GrantFiled: June 23, 2008Date of Patent: September 14, 2010Assignee: Synopsys, Inc.Inventors: Kaushik De, Eduard Cerny, Pallab Dasgupta, Bhaskar Pal, Partha Pratim Chakrabarti
-
Patent number: 7797136Abstract: A method and system to evaluate process objects for acceptability for use. New metrics that measure both object components and their relationships are used. The method selects metrics for the process objects that measure both the components and their relationships, compares measurements of the selected metrics with corresponding metric norms, and, based on the comparison, determines whether the process objects are acceptable. The system includes a memory to store metrics and process objects and a processor to select applicable metrics for the process objects, calculate the measurements of the selected metrics, compare the measurements to corresponding metric norms, and, based on the comparison, determine whether the process objects are acceptable.Type: GrantFiled: December 20, 2006Date of Patent: September 14, 2010Assignee: SAP AGInventors: Udo Klein, Thomas Gerhard Wieczorek, Daniel Zimmermann, Oliver Sievi, Guenter Pecht-Seibert
-
Patent number: 7792656Abstract: A test apparatus that tests a device under test is provided, including a plurality of testing units that are mapped to a control bus address space and that test the device under test; a control processor that executes a plurality of test control programs to control each testing unit corresponding to each test control program; a plurality of address registers that are mapped to a control processor address space and store an address in the control bus address space of one of the testing units when written thereon by the control processor; and a plurality of data registers that are mapped to the control processor address space, that are disposed to correspond one-to-one with the plurality of address registers, and that store data that is written thereto and read therefrom by the testing unit designated by the address stored in the corresponding address register.Type: GrantFiled: December 19, 2007Date of Patent: September 7, 2010Assignee: Advantest CorporationInventor: Norio Kumaki
-
Patent number: 7783437Abstract: An arc monitor system locates an arc based on optimal frames from a frame obtained before an arc discharge to a frame obtained immediately after the arc discharge. The arc monitor system, used to locate an occurred place of an arc discharge that occurred in an electric facility, includes multiple monitor cameras arranged at multiple places in the electric facility, an image processing device that processes images received from the respective monitor cameras, a control logic section that controls the image processing device, and an operation device that includes a display section and an operation section and is connected to the control logic section. The image processing device and the control logic section extract a change in the images received from the monitor cameras in response to a control signal generated from the electric facility on an occurrence of the arc discharge, and then locate an occurred place of the arc discharge.Type: GrantFiled: September 22, 2004Date of Patent: August 24, 2010Assignees: Mitsubishi Denki Kabushiki Kaisha, Chubu Electric Power Co., Inc.Inventors: Yoshihisa Oguchi, Kenichi Shimbo, Atsushi Suzuki, Toshiya Kumai, Hisaya Saitou
-
Publication number: 20100204950Abstract: A method for testing a consumer electronics (CE) product that wirelessly receives user commands from an IR remote control includes obtaining command codes from the remote and correlating the command codes to respective functions. A tester can generate a test script designating the functions but the tester is not required to designate the command codes. In this way, the script can be executed by wirelessly transmitting to the CE product command codes corresponding to the functions designated in the script. During script execution, the CE product is queried for health indicia such as memory usage. The CE product sends the product health indicia to a test computer over a USB debug port.Type: ApplicationFiled: February 10, 2009Publication date: August 12, 2010Inventors: Prisciliano Flores, Viral Mehta, Hung Nguyen, Manish Sharma, Christopher Walsh, True Xiong
-
Patent number: 7773015Abstract: To avoid the measurement disturbances occurring in a conventional, multi-channel measurement data acquisition apparatus there is proposed a multi-channel measurement data acquisition apparatus which includes at least one analog input assembly having a plurality of analog inputs, a controllable electronic analog signal switch device (12) and a central controllable analog-digital converter, wherein the channels of the analog inputs can be successively switched through by means of the analog signal switch device so that the analog signals at the inputs of the individual channels are successively applied as input signals to the central analog-digital converter, and wherein the electronic analog signal switch device and/or the analog-digital converter have control inputs connected to associated control lines.Type: GrantFiled: July 8, 2008Date of Patent: August 10, 2010Inventor: Peter Renner
-
Patent number: 7752583Abstract: A method of verifying a digital design is disclosed. The method comprises generating a reference model for a first digital design and creating an operational model for a second digital design, wherein the first digital design and the second digital design are intended to have a same logical function. A plurality of testcase types are then created by constraining one or more internal signals, and one or more test scripts representing the plurality of testcase types are produced. The method also includes verifying the second digital design with a testing simulation program by comparing results of the test scripts from the operational model and the reference model.Type: GrantFiled: November 26, 2007Date of Patent: July 6, 2010Assignee: International Business Machines CorporationInventors: Jason Raymond Baumgartner, Christian Jacobi, Viresh Paruthi, Kai Oliver Weber
-
Patent number: 7752006Abstract: Some demonstrative embodiments of the invention may include, for example, devices, systems and methods of performing functional verification of a hardware design. In some demonstrative embodiments, a test generator may include a transaction generator to automatically generate a plurality of manipulated transactions by manipulating one or more test case transactions resulting from a constraint-satisfaction-problem.Type: GrantFiled: June 19, 2007Date of Patent: July 6, 2010Assignee: International Business Machines CorporationInventors: Shady Copty, Alex Goryachev
-
Patent number: 7752004Abstract: A system on a circuit board includes a plurality of devices designed to access an electronic system on the circuit board, and a programmable logic device (PLD) connected to the plurality of devices. Each of the plurality of devices complies with a test port architecture. The PLD interfaces the plurality of devices with a test port. The PLD is capable of configuring different connectivity among the plurality of devices based on the program implemented and the assertion of input control signals. A method and apparatus configures a plurality of devices on a circuit board into a desired configuration using the PLD. The configuration includes (a) receiving a control signal at the PLD, (b) configuring at least one of the plurality of devices into a chain based on the control signal, and (c) coupling the configured chain to the test port via the PLD.Type: GrantFiled: January 9, 2004Date of Patent: July 6, 2010Assignee: Cisco Technology, Inc.Inventors: Indrajit Rajeev Gajendran, Biju Raghaven Nair, Kirk Dow Sanders
-
Publication number: 20100166942Abstract: A method for searching parameter codes of a biosensor and a method for producing a biosensor chip matching a biosensor, which utilize parameter codes to produce a biosensor which is applicable to the biosensor chips of different brands and a biosensor chip which is applicable to the biosensors of different brands.Type: ApplicationFiled: December 29, 2008Publication date: July 1, 2010Inventor: Chia-Nan WANG
-
Publication number: 20100153056Abstract: A method of generating an IRF pattern for testing an IC and a test pattern generator are disclosed. In one embodiment, the method includes: (1) identifying a path of the integrated circuit for inline resistive fault pattern generation, (2) determining if the path is a minimal slack path of the IC and (3) generating, when the path is the minimal slack path, a restricted inline resistive fault pattern for the path using only a capture polarity having a minimal inherent margin.Type: ApplicationFiled: December 17, 2008Publication date: June 17, 2010Applicant: LSI CorporationInventors: Jeff S. Brown, Marek Marasch, John Gatt
-
Patent number: 7739070Abstract: A test instrument and method for operating the same are disclosed. The data acquisition system within the instrument generates signals and couples the signals to a device and/or receives signals from the device. The data processor within the instrument includes measurement specific software that generates measurements from the received signals, a restricted software application that utilizes the measurement data, and a physics API that interfaces the measurement specific software with the data acquisition system. The physics API provides a plurality of internal physics functions that are used by the measurement specific software to access the measurement data. The instrument includes an external API that maps the physics functions to an external set of physics functions that are available to the restricted software application and that hide the internal physics functions from the restricted software while providing access to a portion of the measurement data.Type: GrantFiled: August 28, 2007Date of Patent: June 15, 2010Assignee: Agilent Technologies, Inc.Inventors: Thomas Ambler Rice, David William Grieve
-
Patent number: 7739071Abstract: System validation using validation programs for a plurality of root functions depicted using a markup language is disclosed. One embodiment of a method includes establishing a validation program template defining a style of input/output usable by a plurality of root functions to be performed by at least one of a plurality of systems; generating a validation program for each of the plurality of root functions based on the validation program template; establishing a markup language representation of each of the plurality of validation programs and corresponding root function; depicting a composite validation program for a composite function including a plurality of root functions using the markup language representation of the plurality of validation programs for the plurality of root functions in the composite function; and validating at least one of the plurality of systems by validating the composite function using the validation programs depicted in the composite validation program.Type: GrantFiled: August 30, 2007Date of Patent: June 15, 2010Assignee: International Business Machines CorporationInventor: Rakesh K. Parimi
-
Patent number: 7735064Abstract: A method and system for evaluating software includes generating a test deck (310), where the test deck is formulated to test the software for compliance with delivery system operation procedures (315), processing the test deck with the software, and grading the performance of the software for compliance with delivery system operation procedures (320).Type: GrantFiled: December 14, 2001Date of Patent: June 8, 2010Assignee: United States Postal ServiceInventors: Charles B. Hunt, Harry D. Jamieson
-
Publication number: 20100131224Abstract: The testing method of the present invention for testing a plurality of devices under test connected to a test module includes (a) determining combinations of devices under test that can theoretically be measured simultaneously from among the combinations of the plurality of devices under test based on at least the connection relationship between the test module and the plurality of devices under test. The resting method further includes (b) testing the plurality of devices under test by sequentially selecting the combinations of devices under test to be actually measured simultaneously from the combinations determined in (a).Type: ApplicationFiled: November 26, 2008Publication date: May 27, 2010Applicant: Advantest CorporationInventor: Hironori Maeda
-
Patent number: 7715960Abstract: A computer built into an automobile displays the owner's manual for the car. The user requests more information about the automobile through the computer, and the additional information is displayed to the user. Information may include a description of a specific function or device of the car, service history, and/or real time status of a component of the car.Type: GrantFiled: October 8, 2007Date of Patent: May 11, 2010Assignee: Intel CorporationInventor: Kelan C. Silvester
-
Patent number: 7711514Abstract: Various computer-implemented methods, carrier media, and systems for generating a metrology sampling plan are provided. One computer-implemented method for generating a metrology sampling plan includes identifying one or more individual defects that have one or more attributes that are abnormal from one or more attributes of a population of defects in which the individual defects are included. The population of defects is located in a predetermined pattern on a wafer. The method also includes generating the metrology sampling plan based on results of the identifying step such that one or more areas on the wafer in which the one or more identified individual defects are located are sampled during metrology.Type: GrantFiled: August 10, 2007Date of Patent: May 4, 2010Assignee: KLA-Tencor Technologies Corp.Inventors: Allen Park, Ellis Chang
-
Publication number: 20100102843Abstract: A semiconductor test head apparatus using a field programmable gate array (FPGA) is disclosed. A semiconductor test head apparatus using a field programmable gate array, includes a pattern generator for generating a predetermined memory test pattern, a driver/comparator unit comprising a first transceiver which performs a driver function capable of recording a memory test pattern generated from the pattern generator in a device under test and a comparator function capable of comparing a level of a signal read by the device under test with a predetermined high-level reference value, and a second transceiver which performs the driver function and a comparator function capable of comparing a level of a signal read by the device under test with a predetermined low-level reference value, and a connection unit for electrically connecting the first transceiver in parallel to the second transceiver, and connecting the first transceiver and the second transceiver to the device under test.Type: ApplicationFiled: October 24, 2008Publication date: April 29, 2010Inventors: Kyunghun Chang, Chulki Jang, Mangil Kang, Sekyung Oh
-
Patent number: 7702402Abstract: When, from a standby screen of a terminal device, a user depresses a motion key (S11) and performs a registered movement (S13), a sensor unit observes the movement of the terminal device, and a movement parameter calculation unit calculates a movement parameter. A movement parameter change decision unit decides (S15 and S16) whether or not a change of the movement parameter which is calculated, and a change of the movement parameter corresponding to a predetermined function registered in advance, agrees with one another. If the result of this decision is affirmative, a function control unit starts the corresponding function (S17). As a result, it is possible to set the terminal device to a state in which the predetermined function can be employed, with a simple and easily remembered actuation.Type: GrantFiled: April 19, 2007Date of Patent: April 20, 2010Assignee: Vodafone K.K.Inventors: Daisuke Tsujino, Hirohisa Kusuda, Yasuhiro Nishide, Jun Yamazaki
-
Patent number: 7698088Abstract: In some embodiments, an apparatus includes conductors, and a transmitter including transmitter test circuitry to embed test properties in test pattern signals, and transmit the test pattern signals to the conductors. In some embodiments, an apparatus includes conductors to carry test pattern signals with embedded test properties, and receiver test circuitry to receive the test pattern signals and extract the test properties and determine whether the extracted test properties match expected test properties. Other embodiments are described and claimed.Type: GrantFiled: April 30, 2007Date of Patent: April 13, 2010Assignee: Silicon Image, Inc.Inventors: Chinsong Sul, Heon C. Kim, Gijung Ahn
-
Publication number: 20100088194Abstract: A system and method for online configuration of a measurement system. The user may access a server over a network and specify a desired task, e.g., a measurement task, and receive programs and/or configuration information which are usable to configure the user's measurement system hardware (and/or software) to perform the desired task. Additionally, if the user does not have the hardware required to perform the task, the required hardware may be sent to the user, along with programs and/or configuration information. The hardware may be reconfigurable hardware, such as an FPGA or a processor/memory based device. In one embodiment, the required hardware may be pre-configured to perform the task before being sent to the user. In another embodiment, the system and method may provide a graphical program in response to receiving the user's task specification, where the graphical program may be usable by the measurement system to perform the task.Type: ApplicationFiled: December 7, 2009Publication date: April 8, 2010Inventors: Brian Sierer, Ganesh Ranganathan, John Pasquarette, David W. Fuller, III, Joseph E. Peck, Matthew Novacek, Hugo A. Andrade
-
Patent number: 7692106Abstract: An electronic scale having an integrated computer with an input unit for entering selection data, a memory for storing a plurality of parameter values, which can be assigned to function-specific parameters dependent on the entered selection data, a data processing unit for executing weighing applications dependent on a subset of the function-specific parameters and at least one interface for interacting with mechanical and/or electronic components dependent on a subset of function-specific parameters. A plurality of different profiles (24; 24?) can be stored as individual parameter value sets to adapt to user-specific and/or application-specific requirements. Selecting a specific profile (24; 24?) causes a joint assignment of the values contained therein to the corresponding parameters.Type: GrantFiled: September 12, 2008Date of Patent: April 6, 2010Assignee: Sartorius AGInventors: Rainer Rindermann, Jan Von Steuben, Thomas Pertsch, Apolonija Kordes
-
Publication number: 20100076717Abstract: A control and programming apparatus, in particular a measuring device control and/or programming apparatus, is provided for controlling and/or programming a measurement sequence for a tool. The control apparatus has a data processing unit having a data input unit provided for receiving and/or reading in a desired tool data record for the measurement sequence.Type: ApplicationFiled: February 12, 2009Publication date: March 25, 2010Applicant: E. Zoller GmbH & Co., KG Einstell- und MessgerateInventors: Felix Thiel, Christian Pfau
-
Patent number: 7685446Abstract: A method for scaling a dynamic voltage of a CPU is achieved by setting a voltage setting point for each of a plurality of code segments of a program, and profiling workload by measuring a workload variation of each of the code segments based on data that changes whenever measured, selecting a plurality of combinations, each having a plurality of voltage setting points, and calculating workload estimators corresponding to the voltage setting points of each of the selected combinations based on the workload variation measured in the workload profiling operation, selecting an optimal combination that consumes a least energy of the CPU based on the workload estimators, and determining whether a real time constraint is satisfied when an operating voltage is set based on the workload estimator corresponding to each of the voltage setting points of the optimal combination during runtime, and setting the operating voltage based on a result of the determination.Type: GrantFiled: November 13, 2006Date of Patent: March 23, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Pack Hong, Sung-Joo Yoo
-
Publication number: 20100070231Abstract: The invention disclosed relates to a system and method for test case management, wherein the final ‘product’ to be developed is an amalgamation of a variety of ‘modules’ under the ‘product’ umbrella. The variety of ‘modules’ undergo metamorphosis in relation to various phases (that is, from conceptualization to designing to development to testing). At each of these stages, a different team is engaged to perform the relevant functions on the abovementioned modules. Hence, there is a need for a coherent, synchronized and hierarchical classification of the constituents (the modules in relation to their designing parameters, functionality parameters, testing parameters, performance parameters and the like), so that the different teams involved in different phases have a common platform for transferring information and for understanding the transferred information, and essentially for gaining a cohesive overview of the product to be developed.Type: ApplicationFiled: September 8, 2009Publication date: March 18, 2010Inventor: Patil Suhas HANUMANT
-
Patent number: 7680621Abstract: A test instrument network for testing a plurality of DUTs includes a plurality of communicating script processors, the script processors being adapted to execute computer code; and a plurality of measurement resources controllable by the script processors in response to executed computer code, the measurement resources being adapted to test the DUTs. Each script processor and measurement resource may be arbitrarily assigned by the controller to one of at least two groups, only one script processor being assigned to be a master script processor, any other script processor being a slave script processor and any group not including the master script processor being a remote group. The master script processor is exclusively authorized to initiate code execution on any script processor in a remote group. Any slave script processor is only able to initiate operation of measurement resources in it own group.Type: GrantFiled: August 15, 2007Date of Patent: March 16, 2010Assignee: Keithley Instruments, Inc.Inventor: Todd A. Hayes
-
Publication number: 20100057395Abstract: A system and method (“utility”) for automated testing using a compact framework is provided. The utility includes a plurality of functionalities that include development of a test module, development of a test flow, and execution of a test flow. Each of these functionalities may be separated by the compact framework, such that automated testing functions may be divided into individual roles. The individual roles may include test developer, test flow designer, and test flow executor. The utility may also include an authenticator that is operable to determine the individual role of a user (e.g., using a GUI), and to provide the functionality that corresponds to that role. The utility may provide one or more displays that provide real time data feedback. Further, the utility may be operable to generate customized test results reports that enable a user to analyze the performance of one or more devices under test.Type: ApplicationFiled: September 4, 2008Publication date: March 4, 2010Inventors: Ya Chao Ding, Guo Hua Zue
-
Patent number: 7668684Abstract: In a sensor network system for transferring sensing data measured by a sensor node to a host server based upon a process condition, the process condition can be easily set. The host server (4) previously sets a transmission condition which is used to transmit only an event satisfying a preset condition to the host server (4). When the host server (4) receives a joined event from a PAN management server (2), the host server (4) transmits to the PAN management server (2) a transmission condition corresponding to an identifier of an ID of a sensor node (1) of a transmission source of the joined event, and the PAN management server (2) transfers only an observed event satisfying the transmission condition to the host server (4).Type: GrantFiled: April 30, 2007Date of Patent: February 23, 2010Assignee: Hitachi, Ltd.Inventors: Keiro Muro, Kei Suzuki
-
Publication number: 20100033200Abstract: Disclosed is a probing method including, when the probes are configured to make contact with a chip row including four chips continuously arranged in an oblique direction so that the probe card test four chips at a time, finding a first reference oblique chip row extending in the oblique direction and containing a center chip positioned at the center of the wafer and a plurality of first additional oblique chip rows arranged in parallel with the first reference oblique chip row at an upper side of the first reference oblique chip row, and setting contact positions between the probes and the first oblique chip rows wherein the contact positions are positions of the probes obtained by shifting the probes; setting contact positions between the probes and the second oblique chip rows in an opposite direction to a first step; and setting a plurality of index group and test order.Type: ApplicationFiled: August 6, 2009Publication date: February 11, 2010Applicant: TOKYO ELECTRON LIMITEDInventors: Hideaki Tanaka, Yukihiko Fukasawa
-
Publication number: 20100030509Abstract: Various embodiments of a system and method for performing a measurement application are described herein. The system may include a host computer having a processor, and a measurement device having a programmable hardware element. The programmable hardware element may be configured to perform a loop to acquire measurement data from a physical system. The host computer may be configured to perform another loop to read the measurement data from the programmable hardware element and use the measurement data in a measurement and control algorithm. The host computer may be further configured to perform a synchronization algorithm to keep the measurement data acquisition loop performed by the programmable hardware element synchronized with the measurement and control loop performed by the host computer.Type: ApplicationFiled: August 4, 2009Publication date: February 4, 2010Inventors: Charles E. Crain II, Adam H. Dewhirst, Robert L. Ortman
-
Publication number: 20100023294Abstract: An efficient automated testing system and method are presented. In one embodiment, an automated testing system includes a control component and an automated test instrument for testing a device or a plurality of devices (e.g., packages or wafers containing multiple independent different devices) under test. The automated test instrument component performs testing operation on the device or devices under test (DUT). The control component manages testing activities of a test instrument testing the device under test, including managing implementation of a plurality of test programs loaded as a group. In one exemplary implementation, the automated test system also includes a DUT interface and a user interface. The device under test interface interfaces with a device or devices under test.Type: ApplicationFiled: August 28, 2008Publication date: January 28, 2010Applicant: CREDENCE SYSTEMS CORPORATIONInventors: Yung Daniel Fan, David N. Grant, Mark Hanbury Brown, Jonathan David Godfree Pryce
-
Patent number: 7643959Abstract: Methods, systems, and computer readable media provide a softprocessor that is executed by a hardware processing device of a sensor monitoring system and provide an application that is executed by the softprocessor being executed by the hardware processing device. The softprocessor may be compiled for different hardware processing devices such that the customized programming remains independent of the particular hardware processing device present in the computer monitoring system. Tools for creating the custom programming for the softprocessor may be provided to entities purchasing the softprocessor so that the entities are not dependent upon the entity creating the softprocessor.Type: GrantFiled: January 9, 2004Date of Patent: January 5, 2010Assignee: American Megatrends, Inc.Inventors: Sanjoy Maity, Govind Kothandapani