Abstract: A test system for testing a device under test includes: a signal processor configured to generate a plurality of independent signals and to apply first fading channel characteristics to each of the independent signals to generate a plurality of first faded test signals; a test system interface configured to provide the plurality of first faded test signals to one or more signal input interfaces of the device under test (DUT); a second signal processor configured to apply second fading channel characteristics to a plurality of output signals of the DUT to generate a plurality of second faded test signals, wherein the second fading channel characteristics are derived from the first fading channel characteristics; and one or more test instruments configured to measure at least one performance characteristic of the DUT from the plurality of second faded test signals.

Abstract: A method of manufacturing an electrical system for reducing differential-to-differential far end crosstalk (DDFEXT) includes converting a first S parameter representative of a design of a first electrical system into a differential-only S parameter, generating a second differential-only S parameter configured to add even-mode propagation delay and odd-mode propagation delay of the differential-only S parameter of the electrical system such that a total even-mode propagation delay and odd-mode propagation delay of the differential-only S parameter are substantially equivalent, and reconfiguring a second electrical system from the differential-only S parameter and the second differential-only S parameter.

Abstract: In some examples, a converter circuit can be configured to operate in a buck-boost mode. The converter circuit can include a ramp generator that can be configured to generate first and second ramp signals that at least partially overlap respective portions of a buck-boost region during each intermediate clock cycle between clock cycles of a clock signal. By generating the first and second ramp signals during each intermediate clock cycle, first and second drivers can be provided to toggle switches of a power stage, such that an output voltage provided by the power stage can be averaged out over clock cycles of the clock signal to allow for a gradual transition between buck and boost modes of operation of the converter circuit. In some examples, the converter circuit can be configured to operate in a test mode and can be configured to implement trimming of a ramp signal.

Abstract: A system for analyzing faults in a transmission line includes a test signal generator, a coupler for injecting the test signal into the transmission line and sampling the signal back-propagated in the transmission line, a control unit for generating a calibration signal equal to the opposite of the test signal and controlling its phase and its amplitude, at least one combiner for combining the calibration signal and the signal sampled by the coupler into a corrected signal, an amplifier for amplifying the corrected signal and a correlator for correlating the corrected signal and the test signal to produce a reflectogram, the control unit being further configured to make the amplitude and the phase of the calibration signal vary so as to eliminate, in the signal sampled by the coupler, at least one echo of the test signal on at least one point of impedance mismatch of the transmission line.

Abstract: A test circuitry and a method for testing the same and a test system are provided. The test circuitry includes: a test signal input end, configured to input an initial test signal; a signal output end, configured to output a target test signal; and a signal shaping circuitry coupled to the test signal input end and the signal output end, configured to remove a noise signal from the initial test signal to obtain the target test signal.

Abstract: Technology is described for providing code modules for building a device. An indication of hardware components to be used when designing a device may be received. A use case for the device may be received. A list of code modules that are compatible with the hardware components may be provided. The list of code modules may be based on the use case for the device. A selection of code modules may be received from a list of code modules that are compatible with the hardware components. The code modules may be provided for use in designing the device.

Abstract: A noise reduction operation control method for a headset and an audio processor in a terminal device, where a pin of a universal serial bus (USB) Type-C interface is multiplexed. During implementation of the solutions in this application, a switch circuit corresponding to the pin of the USB Type-C interface is switched to ensure that a normal function of the pin of the USB Type-C interface is not affected. In addition, a digital microphone (DMIC) processor in a terminal device and a noise reduction microphone in a headset are coupled using the pin of the USB Type-C interface such that a noise reduction signal from the noise reduction microphone in the headset is received using the DMIC processor in the terminal device, thereby implementing noise reduction processing for the headset using the terminal device.

Abstract: Dynamic power-aware encoding method and apparatus is presented based on a various embodiments described herein. The experimental results confirmed that a desirable reduction in the toggling rate in the decompressed test stimulus is achievable by reasonable overhead (ATPG time, hardware overhead and pattern inflation) typically without degradation of a compression ratio. The performed experimental evaluation confirms that the described embodiments can support aggressive scan compression, efficient dynamic pattern compaction and a reduction of toggling rate in the decompressed test stimulus.

Abstract: A computer system verifies functional test patterns for diagnostics, characterization and manufacture testing. The system generates, by a system designer, verification sequences including initial trace traces selected from a verification sequence data to test system functional design. The system includes a trace module, an emulated pattern generator module, and a test pattern verification and debug module. The trace module adds custom information to the traces to generate modified traces and the system executes the verification sequences against a device to generate traces. The trace module further processes the modified traces by parsing the captured modified traces. The system verifies data integrity and summarizes statistics of the captured traces. The emulated pattern generator module generates emulated test patterns, which are based on the output of the trace module and have independent format streams compatible with a device test port.

Abstract: A test generator includes a computer programmed to receive at least one input instruction including a message to be transmitted by the test generator and an error command indicating errors to be introduced into the transmission. The computer is further programmed to generate a data frame formatted according to a single-edge-nibble-transmission protocol. The data frame includes the message and the errors. The computer is further programmed to transmit the data frame.

Abstract: The subject disclosure is directed towards providing a web application with access to hardware accelerated graphics. A rendering format for a set of video frames is established. A graphics component, which is coupled to a graphics device and associated with an unsupported file type, is identified. The graphics component generates image data compromising the hardware accelerated graphics. When the web application requests a set of video frames, the image data is transformed into the set of video frames in accordance with the format. Then, the set of frames is communicated to a display device.

Abstract: Embodiments of a digital-to-analog conversion system that utilizes a specialized clock signal to reshape an analog impulse response of a digital-to-analog converter (DAC) are disclosed. Preferably, a shape of the specialized clock signal is such that Nyquist images resulting from digital-to-analog conversion are controlled in a desired manner. In one embodiment, the digital-to-analog conversion system includes a DAC that converts a digital input signal into an analog output signal. A specialized clock signal is applied to the analog output signal of the DAC such that an analog impulse response of the DAC is reshaped according to a shape of the specialized clock signal, thereby providing a modified analog output signal. The specialized clock signal reshapes the analog impulse response of the DAC such that Nyquist images resulting from digital-to-analog conversion are controlled in a desired manner.

Abstract: A method is provided for generation of statistically uniform field distribution inside a test volume of a reverberation chamber. The method includes: generating complex independent and identically distributed random signals x, filtering signals x through a passage matrix P according to a linear transformation in order to determine correlated excitation signals “a” by “a”=Px, P being a passage matrix determined from H a complex transfer function H between the test volume and the antennas; and P is constructed such that E=HPx where E is independent and identically distributed, and generating the field E by applying simultaneously correlated excitation signals “a” to several antennas of the reverberation chamber.

Abstract: A time-interleaved RF triggering method and system on a test and measurement instrument includes an acquisition component that samples a waveform, which is converted into an amplitude, phase, frequency, in-phase (I), and quadrature (Q) waveform, any of which can be used for triggering an RF digital trigger, including triggering that uses demodulation and/or decoding of the down-converted complex IQ data samples for a given protocol. Aliasing caused by subsampled data in each of the interleaved acquisition components is cancelled out using a fractional time-shift filter.

Abstract: A method for quickly calibrating a memory interface circuit from time to time in conjunction with operation of a functional circuit is described. The method uses controlling the memory interface circuit with respect to read data capture for byte lanes, including controlling CAS latency compensation for the byte lanes. In the method control settings for controlling CAS latency compensation are determined and set according to a dynamic calibration procedure performed from time to time in conjunction with functional operation of a circuit system containing one or more memory devices connected to the memory interface circuit. In the method, determining and setting the control settings for controlling CAS latency compensation is performed independently and parallely in each of the byte lanes.

Abstract: A memory interface circuit for read operations is described. The circuit includes one or more controller circuits, one or more read data delay circuits for providing CAS latency compensation for byte lanes. In the system, control settings for the read data delay circuits for providing CAS latency compensation are determined and set using controller circuits according to a dynamic calibration procedure performed from time to time. In the system, determining and setting the control settings for the read data delay circuits for providing CAS latency compensation is performed independently and parallely in each of a plurality of byte lanes.

Abstract: A waveform acquiring unit acquires a time waveform of an electromagnetic wave. The time waveform is decomposed into wavelet expansion coefficients by wavelet transform. Influence levels of the respective wavelet expansion coefficients to a spectrum are calculated. The wavelet expansion coefficients are weighted based on at least the influence levels of the wavelet expansion coefficients to the spectrum. The weighted wavelet expansion coefficients are converted into time waveforms by inverse wavelet transform. Thus, the time waveforms that holds spectrum information needed for spectroscopic analysis and has a reduced noise is provided.

Abstract: Aspects of the invention relate to yield analysis techniques for generating root cause distribution information. Suspect information for a plurality of failing dies is first generated using a layout-aware diagnosis method. Based on the suspect information, potential root causes for the plurality of failing dies, and suspect feature weights and total feature weights for each of the potential root causes may then be determined. Next, the probability information of observing a particular suspect that is related to a particular root cause may be extracted. Finally, an expectation-maximization analysis may be conducted for generating the root cause distribution information based on the probability information and the suspect information. Heuristic information may be used to prevent the analysis from over-fitting.

Abstract: An embodiment of an electronic device having a plurality of trimmable operative parameters is provided. The electronic device includes a trimming circuit for applying a plurality of trimming actions to each parameter for causing a corresponding correction of the parameter, for at least one reference parameter, a measuring circuit for measuring the reference parameter responsive to the application of at least part of the trimming actions, and for forcing the application of the selected trimming action for the reference parameter. For each non-reference parameter different from the at least one reference parameter, the electronic device includes a selection circuit for selecting one of the trimming actions for the non-reference parameter corresponding to the selected trimming action for the at least one reference parameter, and a biasing circuit for forcing the application of the selected trimming action for each non-reference parameter.

Abstract: A waveform generator and a signal analyzer are respectively provided in electrical communication with an input transducer and an output transducer capable of conversion between electrical and acoustic signals, and in mechanical communication with a part. A processor coupled with the waveform generator and signal analyzer receives a set of parameters defining a frequency scan from which it determines a number of frequency sweeps to be performed by the waveform generator. Each of the frequency sweeps has a number of frequencies less than a maximum capacity of the waveform generator, and for each frequency sweep, the processor instructs the waveform generator to excite the input transducer and synchronously receiving a response signal with the signal analyzer at multiple frequencies.

Abstract: An apparatus for testing one or more transmission lines is disclosed. The apparatus comprises a processor capable of configuring the apparatus in one of a master mode and a slave mode. The apparatus when configured in the master mode controls the testing of the one or more transmission lines of a cable. The apparatus also includes one or more test modules associated with one or more tests to be performed on the one or more transmission lines. Further, one or more transceivers of the apparatus are capable of one or more of sending and receiving a plurality of signals through the one or more transmission lines. One or more signals of the plurality of signals are associated with the one or more test modules.

Abstract: Provided is a test apparatus that tests a device under test having a plurality of output terminals. The test apparatus comprises an executing section that executes a test command sequence for testing the device under test; a storage section that stores a plurality of pieces of setting data designating one or more output terminals among the plurality of output terminals; a detecting section that detects whether a value of an output signal from an output terminal designated by one of the pieces of setting data matches an expected value; and a selecting section that selects different pieces of setting data in the storage section when at least two detection commands, which change execution sequencing of the test command sequence according to the detection results of the detecting section, are executed, and supplies the selected pieces of setting data to the detecting section.

Abstract: This invention is to detect defective products of semiconductor devices with high accuracy even when the characteristics of the semiconductor devices vary according to their positions on each of wafers.

Abstract: A monitoring circuit for an integrated circuit comprises a non-temperature-inverted circuit and a temperature-inverted circuit. Operating parameters of the two circuits are measured, representing the propagation speed of signals in the respective circuits. In response to a change in temperature, the non-temperature-inverted circuit slows down and the temperature-inverted circuit speeds up. In contrast, in response to a change in operating voltage both circuits either speed up or slow down. This divergence in response to temperature and similar response to voltage enables the monitoring circuit to distinguish between changes in operating voltage and changes in operating temperature.

Abstract: The present invention provides a method and apparatus for testing a valve control system in an aircraft fuel supply system having a plurality of control valves, wherein the control system includes a processor adapted to receive feedback signals from each of the plurality of control valves, the method comprising the steps of: connecting a test device to the control system such that the test device is connected for signal transmission to the processor; outputting a signal to the processor simulating a feedback signal from at least one of the control valves; detecting a control signal which is output by the processor to the at least one of the control valves; and identifying the detected control signal which is output by the processor to the control valve.

Abstract: A method for calibrating a DDR memory controller is described. The method provides an optimum delay for a core clock delay element to produce an optimum capture clock signal. The method issues a sequence of read commands so that a delayed version of a dqs signal toggles continuously. The method delays a core clock signal to sample the delayed dqs signal at different delay increments until a 1 to 0 transition is detected on the delayed dqs signal. This core clock delay is recorded as “A.” The method delays the core clock signal to sample the core clock signal at different delay increments until a 0 to 1 transition is detected on the core clock signal. This core clock delay is recorded as “B.” The optimum delay value is computed from the A and B delay values.

Abstract: A measurement system includes a signal bus, an electronic control unit, and an emulated sensor. The electronic control unit is coupled to the signal bus. The sensor with emulated line adaptation is also coupled to the signal bus. The emulated sensor is configured to adapt current consumption according to a selected impedance and a selected frequency range.

Abstract: A test unit may generate a pulse signal based on a pulsatile profile and a frequency modulation component of a respiratory profile. A respiration modulated signal may be generated from the pulse signal, an amplitude modulation component, and a baseline modulation component. A patient modulated signal may be generated based on the respiration modulated signal and a patient profile. The artificial PPG signal may be generated based on the patient modulated signal and an artifact profile. The artificial PPG signal may be output to an electronic device.

Abstract: A standard EM wave field generator, includes a first tapered region configured to have a first port formed on its one side and be supplied with a source to generate EM field through the first port; and a first untapered region configured to have at least one or more slits in the form of a hole. Further, the standard EM wave field generator includes a second tapered region configured to have a third port formed on its one side and output the EM field generated from the first port through the third port.

Abstract: A system and method for checking a ground via of control chips of a printed circuit board (PCB) provides a graphical user interface (GUI) displaying a layout of the PCB. The control chip has a plurality of ground pins. The computer searches for signal path routing of each ground pin and ground vias along each signal path routing of each ground pin. If there are any ground vias having the same absolute coordinates, the computer determines that the ground vias are shared by more than one ground pin.

Abstract: A modulation error is detected every symbol data to generate a trigger signal. The present invention focuses that there are limited patterns of shifts from one symbol data to the next one of the digital modulation signal. Measured values of amplitude, phase and/or frequency of symbol data are latched and then values at the next symbol timing are predicted from the latched measured values using said feature. The predicted and measured values are compared at the following symbol timing. If the difference (error) is over an acceptable range, a trigger signal is provided which allows acquiring a modulation error by symbol data.

Abstract: A signal generator generates amplitude noise on a selected segment of a test signal. A user interface is used for selecting a segment of the test signal and an associated power level for applying amplitude noise at a selected power level to the test signal segment. A signal processing unit compiles the selected power level of the selected segment with the test signal to generate digital data representative of the test signal with selected segments having amplitude noise. A waveform generator receives the digital data and generating a test signal output having amplitude noise at selected segments of the test signal. The method includes the steps of: selecting a segment of the test signal to add amplitude noise; selecting a power level for the amplitude noise; and applying the amplitude noise at the selected power level to the selected segment of the test signal.

Abstract: A user equipment (UE) performs a transform domain (DFT) based method to detect the cyclic prefix (CP) length that is being used by a base station for cellular communications. The detected CP length is then used to reduce the amount of time required to complete the synchronization and cell search procedures. In particular, the UE uses the detected CP length information to obtain Cell Identification parameters (NID1, NID2) along with information including a Maximum energy Tap location and a reference signal receive power (RSRP) while completing the synchronization and cell search procedures.

Abstract: A system and method for receiving a plurality of pilot tones, generating an analytic signal in a frequency domain, the analytic signal including frequency components that when converted to a time domain include a preamble having a first half containing only non-zero data and a second half containing only zero data, converting the analytic signal from the frequency domain to the time domain, resulting in the preamble having the first half containing only non-zero data and the second half containing only zero data, generating a cyclic prefix based on the second half of the preamble, and attaching the cyclic prefix to the preamble to form a pilot signal, the cyclic prefix including only zero data.

Abstract: A device and method for generation of Intersymbol interference (ISI) effects on serial data by direct digital synthesis is described. The features of the present invention allow a user to set parameters such as data rate, voltage amplitude, encoding scheme etc. as per requirements. An ISI parameter value is selected and applied to the serial data to produce ISI effects in the serial data. Alternatively according to another feature the patterns may be set as per industry standards.

Abstract: Channel emulation in a PC computing platform including at least one general purpose parallel processor (GPPP) includes defining a plurality of fading channels in a GPPP and generating complex tap coefficients in a GPPP for the fading channels.

Abstract: A DDR memory controller is described wherein a core domain capture clock is created by programmably delaying the core clock of the memory controller. The delay of this capture clock is typically calibrated during a power on the initialization sequence in concert with a DDR memory in a system environment, thereby minimizing the effects of system delays and increasing both device and system yield. An additional embodiment also includes programmably delaying the incoming dqs signal. To compensate for voltage and temperature variations over time during normal operation, a runtime dynamic calibration mechanism and procedure is also provided.

Abstract: A signal generator produces a victim signal having crosstalk emulation by filtering and combining a victim signal waveform record file and an aggressor signal waveform record file generated using parameters selected by a user. A signal channel or a cascaded signal channel is characterized using one or more S-parameter arrays. The S-parameter array or arrays represent a mixed-mode multiple-port device under test. Coefficients of a NEXT filter, a FEXT filter and a forward transmission filter are derived from selected S-parameters of the S-parameter array. The aggressor signal is filtered individually by the NEXT and FEXT filters. The victim signal is summed with the filtered aggressor signal from the NEXT filter with the resulting summed signal being filtered by the forward transmission filter. The filtered signal from the forward transmission filter is summed with the filtered aggressor signal from the FEXT filter to generate a victim signal having crosstalk emulation.

Abstract: A temperature sensor includes a counting signal generation unit, a counting signal decoding unit, an input reference voltage selection unit, and a latch pulse generation unit. The counting signal generation unit is configured to generate one or more counting signals in response to an oscillation signal. The counting signal decoding unit is configured to decode the one or more counting signals and to generate one or more test selection signals and an end signal. The input reference voltage selection unit is configured to output a first selection reference voltage or a second selection reference voltage as an input reference voltage in response to the one or more test selection signals. The latch pulse generation unit is configured to generate one or more latch pulses in response to the one or more test selection signals.

Abstract: Radiowave environment data correction that uses the data measurement results obtained at measuring points in a base station peripheral area provided for a wireless communications system, is achieved accurately at a limited number of measuring points. A radiowave environment data correcting system includes correction data determining means that determines correction data for sub-areas, the sub-areas being regions into which an assessment area is divided, on the basis of data measurement results obtained at measuring points belonging to the sub-areas, wherein division into the area is based on an area usage division that is a division predefined according to a particular layout of objects or spaces in the assessment area.

Abstract: A device for adjusting the timing of at least one edge of an output pulse created in response to a reference pulse is disclosed. Such a device may include a first memory circuit having two or more first memory cells and a second memory circuit also having two or more second memory cells. The first memory circuit may be configured to periodically sample the reference pulse at the rising edges of a first sample clock while the second memory circuit may be configured to periodically sample the reference pulse at the falling edges of the first sample clock. A combinatorial logic circuit may also be included to produce the output pulse having at least one adjusted edge based on a set of timing instructions and timing information provided by the first and/or second memory circuits.

Abstract: A method of forming a compact model for an electrical device includes obtaining shape information for the device and obtaining nominal information for the device. The method also includes merging the shape information and the nominal information to form composite data, and fitting the compact model to the composite data.

Abstract: A waveform acquiring unit acquires a time waveform of an electromagnetic wave. The time waveform is decomposed into wavelet expansion coefficients by wavelet transform. Influence levels of the respective wavelet expansion coefficients to a spectrum are calculated. The wavelet expansion coefficients are weighted based on at least the influence levels of the wavelet expansion coefficients to the spectrum. The weighted wavelet expansion coefficients are converted into time waveforms by inverse wavelet transform. Thus, the time waveforms that holds spectrum information needed for spectroscopic analysis and has a reduced noise is provided.

Abstract: A method for testing the operating conditions of an electric network, including at least one operating state, including the steps of providing a voltage signal (v(t)) to a network load and measuring the instantaneous current signal (i(t)) circulating in the load, delaying the instantaneous current signal (i(t)) to generate an instantaneous current signal delayed ((i(t+?)) by a predetermined amount of time (?), the predetermined amount of time (?) being a function of the operating state of said load, the method including the steps of calculating, within a predetermined measurement time (Tm), an admittance ratio (G?(?)) between the mean of the product of the voltage signal (v(t)) and the delayed instantaneous current signal (i(t+?)), and the mean of the square of the voltage signal (v(t)), and to compare the value of the admittance ratio (G?(?)) with a range of predetermined values (Gmin,Gmax) to determine the operating state of the electric network.

Abstract: A method and apparatus for identifying ambient signal data in a test signal data set. A cumulative amplitude distribution of data elements is identified in the test signal data set in order by amplitude values. The data elements comprise frequency values and corresponding amplitude values. A subset of data elements from the test signal data set is identified. The subset of data elements comprises the data elements with the amplitude values greater than a first threshold value. The data elements in the subset of data elements are identified wherein a difference between the amplitude values of adjacent data elements in the cumulative amplitude distribution of data elements is greater than a second threshold value.

Abstract: A directional tap detection algorithm and a single tri-axis accelerometer are employed to extend the number of unique button less input commands available for a small mobile electronic device. The algorithm analyzes acceleration data from the tri-axis accelerometer to detect the direction and number of taps imparted to any of the six sides of a housing of the device, yielding 12 unique inputs. The algorithm employs a parameter referred to as the performance index (PI) to identify tap induced movements. The PI is determined by calculating the time derivative of each acceleration signal for each axis and then calculating the sum of the absolute values of the calculated acceleration derivatives. A tap is determined to have occurred if the sum exceeds a threshold value for a predetermined amount of time. If a second tap is detected within a predetermined time after the first tap, then a double tap is determined to have occurred.

Abstract: A method of filtering a signal sampled by a sampler, for example, in an equivalent time oscilloscope includes applying a correction to an actual frequency response of the sampler, with respect to a reference frequency response, to a first frequency range of the sampled signal, and transitioning across a second frequency range of the sampled signal from the correction applied to the first frequency range to no correction of the actual frequency response of the sampler, the second frequency range being higher than the first frequency range. The method further includes compensating in a third frequency range of the sampled signal for excess gain incurred while applying the correction and transitioning from the correction to no correction in the first and second frequency ranges, respectively, so that statistics of asynchronous components of the sampled signal are preserved, the third frequency range being higher than the second frequency range.

Abstract: A waveform generation and measurement module that may be used in automated test equipment. The waveform generation and measurement module includes high speed SERDES (or other shift registers) that are used to digitally draw a test waveform. Additional high speed SERDES may also be used to receive (in serial form) a response waveform from a device under test and convert it to parallel data for high speed processing. The waveform generation and measurement module may be implemented in field programmable gate array logic.

Abstract: A verification tool receives a finite precision definition for an approximation of an infinite precision numerical function implemented in a processor in the form of a polynomial of bounded functions. The verification tool receives a domain for verifying outputs of segments associated with the infinite precision numerical function. The verification tool splits the domain into at least two segments, wherein each segment is non-overlapping with any other segment and converts, for each segment, a polynomial of bounded functions for the segment to a simplified formula comprising a polynomial, an inequality, and a constant for a selected segment. The verification tool calculates upper bounds of the polynomial for the at least two segments, beginning with the selected segment and reports the segments that violate a bounding condition.

Abstract: A master CPU makes an execution interval b, during which CPUs are operated, common to CPUs including the master CPU and makes a stop interval a, during which the CPUs are stopped, different for each of the CPUs including the master CPU. As a result, the lengths of cycle intervals c of the CPUs constituted by the execution interval b and the stop interval a allow the ratio between the lengths of the cycle intervals c of any CPUs to be represented by two integers that are coprime to each other. Setting such lengths of the cycle intervals c of the CPUs achieves the synchronism between the shifts of all of the CPUs from a stopped state to an in-operation state and from the in-operation state to the stopped state.