Timing Signal Patents (Class 702/125)
  • Patent number: 11217287
    Abstract: In an embodiment, a differential strobe input squelch circuit includes a squelch sub-circuit that is configured to perform operations including receiving a true strobe signal, a complement strobe signal, and a strobe difference signal that is representative of a difference between the true strobe signal and the complement strobe signal; determining, based on the true strobe signal and the complement strobe signal, whether the strobe difference signal is defined or undefined; and outputting a modified strobe difference signal that is equal to the strobe difference signal when the squelch sub-circuit determines that the strobe difference signal is defined and that is instead equal to a constant strobe-level voltage when the squelch sub-circuit determines that the strobe difference signal is undefined.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: January 4, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Joel Scott Swanson
  • Patent number: 11184442
    Abstract: Systems and methods are described for securely monitoring a shipping container for an environmental anomaly using elements of a wireless node network of sensor-based ID nodes disposed within the container and a command node associated with the container. The method has the command node identifying which of the ID nodes are confirmed as trusted sensors based upon a security credential specific to each of the ID nodes; monitoring only the confirmed ID nodes for sensor data broadcast those ID nodes; detecting the anomaly based upon the sensor data from at least one of the confirmed ID nodes; automatically generating an alert notification related to the detected environmental anomaly for the shipping container; and transmitting the alert notification to the external transceiver to initiate a mediation response related to the detected environmental anomaly.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: November 23, 2021
    Assignee: FEDEX CORPORATE SERVICES, INC.
    Inventor: Ole-Petter Skaaksrud
  • Patent number: 11175325
    Abstract: A power analyzer system for correlating power consumption and RF signals of a device under test has a RF sensor unit, a power probe unit and an analysis device being a physically separate device from the RF sensor unit and the power probe unit. The analysis device has a standardized interface module by which the analysis device is connected to the RF sensor unit and the power probe unit. The analysis device is configured to control the RF sensor unit and the power probe unit and to synchronously display a representation of the RF signal of the device under test and a representation of the power consumption of the device under test. Further, a power analyzer setup is shown. The units or devices can comprise one or more circuits to carry out its respective or other functionality.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: November 16, 2021
    Assignee: Rohde & Schwarz GmbH & Co. KG
    Inventor: Michael Grimm
  • Patent number: 11164648
    Abstract: A circuit includes a glitch measurement circuit and a glitch profile circuit. The glitch measurement circuit includes a first comparator to compare a glitch in a power supply voltage to a first threshold voltage, a first counter to generate a first count indicative of a time duration the first comparator indicates that the glitch trips the first threshold voltage, a second comparator to compare the glitch in the power supply voltage to a second threshold voltage different than the first threshold voltage, and a second counter to generate a second count indicative of a time duration the second comparator indicates that the glitch trips the second threshold voltage. The glitch profile circuitry utilizes the first count and the second count to generate a multi-voltage profile of the glitch, wherein the multi-voltage profile includes indications of the time durations indicated by the first count and the second count.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: November 2, 2021
    Assignee: NXP USA, Inc.
    Inventors: Nihaar N. Mahatme, Srikanth Jagannathan
  • Patent number: 11035928
    Abstract: The disclosure provides a radar apparatus for estimating a position and a velocity of a plurality of obstacles. The radar apparatus includes a slave radar chip. A master radar chip is coupled to the slave radar chip. The master radar chip includes a local oscillator that generates a transmit signal. The slave radar chip receives the transmit signal on a first path and sends the transmit signal back to the master radar chip on a second path. A delay detect circuit is coupled to the local oscillator and receives the transmit signal from the slave radar chip on the second path and the transmit signal from the local oscillator. The delay detect circuit estimates a routing delay from the transmit signal received from the slave radar chip on the second path and from the transmit signal received from the local oscillator.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: June 15, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Karthik Subburaj, Brian Ginsburg, Karthik Ramasubramanian
  • Patent number: 10751846
    Abstract: A machine tool is equipped with a rotary table, and a clamp mechanism which clamps the rotary table in a manner so that the rotary table does not rotate. A clamping operation by the clamp mechanism is started after a standby time has elapsed from completion of indexing of the rotary table. The machine tool further includes a positional deviation calculating unit adapted to calculate a positional deviation of the rotary table when the clamping operation by the clamp mechanism is completed, and a standby time changing unit adapted to shorten the standby time in the case that an absolute value of the positional deviation is less than a threshold value, and to lengthen the standby time in the case that the absolute value of the positional deviation is greater than the threshold value.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: August 25, 2020
    Assignee: Fanuc Corporation
    Inventor: Hiroki Tezuka
  • Patent number: 10747119
    Abstract: A method of controlling a feedback system with a data matching module of an extreme ultraviolet (EUV) radiation source is disclosed. The method includes obtaining a slit integrated energy (SLIE) sensor data and diffractive optical elements (DOE) data. The method performs a data match, by the data matching module, of a time difference of the SLIE sensor data and the DOE data to identify a mismatched set of the SLIE sensor data and the DOE data. The method also determines whether the time difference of the SLIE sensor data and the DOE data of the mismatched set is within an acceptable range. Based on the determination, the method automatically validates a configurable data of the mismatched set such that the SLIE sensor data of the mismatched set is valid for a reflectivity calculation.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: August 18, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Chih Huang, Chi Yang, Che-Chang Hsu, Li-Jui Chen, Po-Chung Cheng
  • Patent number: 10591931
    Abstract: Techniques for controlling movement of a mobile drive unit within a workspace are described. In an example, a system may access a map of the workspace. The map defines a policy for the movement of the mobile drive unit within the workspace based on a volume of the workspace associated with a fire shutter. The fire shutter is located within the workspace and is operable to manage a spread of a fire within the workspace. The system may generate at least a portion of a movement path for the mobile drive unit within the workspace based on the map and on an event for transporting material from a location in the workspace. The portion of the movement path is in compliance with the policy defined in the map. The system provides at least the portion of the movement path to the mobile drive unit over a data network.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: March 17, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Aayush Aggarwal, Ryan Clarke, Anatoly Mitlin, James Plumley, Gregory Edward Tierney, Steven Augustine Wilson
  • Patent number: 10557564
    Abstract: Embodiments of the present disclosure describe both mechanically-operated and electrically-operated, locally-actuated partial stroke testing devices and systems for testing operation of an emergency isolation valve.
    Type: Grant
    Filed: January 7, 2017
    Date of Patent: February 11, 2020
    Assignee: Saudi Arabian Oil Company
    Inventor: Fawaz A. AlSahan
  • Patent number: 10255403
    Abstract: A view definition analyzer maps a plurality of timing views for a circuit design into compatibility groups having shared operating conditions of their respective process corners. An ETM generator then extracts an extracted timing model from a block of the circuit design for each compatibility group, containing timing arcs representing each combination of interface path in the circuit block and timing view in the compatibility group, where at least one timing arc in the ETM is a merged version of multiple timing arcs for an interface path across multiple timing views in the compatibility group. Timing arcs are merged when each timing characteristic in a first timing arc matches, within a tolerance threshold, a corresponding timing characteristic in a second timing arc. The ETM may then be used to model any timing view in the compatibility group. The ETM generator thus produces a minimal set of extracted timing models.
    Type: Grant
    Filed: January 6, 2016
    Date of Patent: April 9, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Sneh Saurabh, Naresh Kumar
  • Patent number: 9664738
    Abstract: A circuit, such as an integrated circuit or a die, has a first input pad configured to receive a multiplexed signal including scan data and a clock signal, a scan chain having a scan data input and a clock input and circuitry coupled between said first input pad and said scan chain. The circuitry is configured to extract the scan data and the clock signal from the received multiplexed signal, provide the extracted scan data to the scan data input of the scan chain, and provide the extracted clock signal to the clock input of the scan chain.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: May 30, 2017
    Assignee: STMicroelectronics (Research and Development) Limited
    Inventor: Gary Morton
  • Patent number: 9664539
    Abstract: Methods and devices for determining a timestamp that represents a time a sensor sample was generated are described. In one aspect, a method includes: obtaining a sampling rate estimate for the sensor; determining an expected sample time based on the sampling rate estimate; detecting a sensor sample and assigning a reporting time to the detected sensor sample, the reporting time representing the time when the sensor sample was detected; and determining the timestamp for the sensor sample based on the expected sample time and the reporting time.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: May 30, 2017
    Assignee: BlackBerry Limited
    Inventors: Christopher James Grant, Robert George Oliver, Nathan Daniel Pozniak Buchanan
  • Patent number: 9501245
    Abstract: A new approach is proposed that contemplates systems and methods to virtualize a physical NVMe controller associated with a computing device or host so that every virtual machine running on the host can have its own dedicated virtual NVMe controller. First, a plurality of virtual NVMe controllers are created on a single physical NVMe controller, which is associated with one or more storage devices. Once created, the plurality of virtual NVMe controllers are provided to VMs running on the host in place of the single physical NVMe controller attached to the host, and each of the virtual NVMe controllers organizes the storage units to be accessed by its corresponding VM as a logical volume. As a result, each of the VMs running on the host has its own namespace(s) and can access its storage devices directly through its own virtual NVMe controller.
    Type: Grant
    Filed: May 16, 2014
    Date of Patent: November 22, 2016
    Assignee: CAVIUM, INC.
    Inventors: Muhammad Raghib Hussain, Vishal Murgai, Manojkumar Panicker, Faisal Masood, Brian Folsom, Richard Eugene Kessler
  • Patent number: 9106201
    Abstract: A regulated, power supply system is described using multiphase DC-DC converters with dynamic fast-turnon, slow-turnoff phase shedding, early phase turn-on, and both load-voltage and drive-transistor feedback to pulsewidth modulators to provide fast response to load transients. In an embodiment, a system master can automatically determine whether all, or only some, slave phase units are fully populated. The programmable system includes fault detection with current and voltage sensing, telemetry capability, and automatic shutdown capability. In an embodiment, these are buck-type converters with or without coupled inductors, however some of the embodiments illustrated include boost configurations.
    Type: Grant
    Filed: June 23, 2011
    Date of Patent: August 11, 2015
    Assignee: Volterra Semiconductor Corporation
    Inventors: Sombuddha Chakraborty, Yali Xiong, Michael D. McJimsey, Anthony J. Stratakos, Giovanni Garcea, Ilija Jergovic, Andrew Burstein, Andrea Pizzutelli
  • Patent number: 9002672
    Abstract: According to the invention, a time synchronization of phase between measurement devices that do not share a same clock for their respective sampling of the signals is carried out by a time tagging of samples of the signals in time blocks followed by an adjustment of the phase values of components of interest of the signals in the regrouped time blocks so that the values refer to common time references between the measurement devices. The tagging is carried out with a synchronization signal available to the measurement devices, completed with count values provided by a counter operated by a reference clock for each measurement device.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: April 7, 2015
    Assignee: Hydro-Québec
    Inventors: Sylvain Riendeau, François Léonard, Patrick Picher, Michel Gauvin, Hugo Bertrand, Louis Dupont
  • Patent number: 8918295
    Abstract: A distributed reflectometry device for diagnosing a network is disclosed. According to one aspect, the device includes at least one transmission line and several reflectometers connected to the network. A transmission portion of the device includes a first memory configured to store at least one test signal and a second memory configured to store weighting coefficients. The transmission portion may also include a first multiplier of a test signal (s) with a coefficient ?m, for producing a measurement m and a digital-to-analog converter connected to the line. A reception portion of the device includes an analog-to-digital converter configured to receive a signal from the line and provide a vector for the measurement m, a second multiplier of configured to multiply the vector with the coefficient ?m, an averaging module, and a post-processing and analysis module.
    Type: Grant
    Filed: October 13, 2009
    Date of Patent: December 23, 2014
    Assignee: Commissariat à l'énergie Atomique et aux Énergies alternatives
    Inventor: Adrien Lelong
  • Patent number: 8887120
    Abstract: An on-chip timing slack monitor that measures timing slack at the end of a critical path includes a master-slave flip-flop having a tap on the Q output of the master and a logic module coupled to the flip-flop for producing a pulse whose width is a function of the slack. A pulse width shrinking delay line removes glitches on the flip-flop output and, in combination with a digital integrator and counter, also performs a time to digital conversion operation for determining a value for timing path slack. The determined value is used by a decision module for yield analysis. The monitor can discriminate a glitch from a slack pulse at the flip-flop output for any width of glitch up to one-half of a clock cycle.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: November 11, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Chetan Verma, Amit Kumar Dey, Amit Roy, Vijay Tayal
  • Patent number: 8874397
    Abstract: A user obtains a set of modules, inserts them into slots of a chassis, and interconnects the modules to form a modular instrument. A signal path extends through the modules. To support calibration of the signal path, a first of the modules (or the chassis or a calibration module) includes a calibration signal generator. A computer directs the first module to apply the calibration signal from the generator to the signal path, and measures the power (or amplitude) of the output of the signal path. The computer reads a factory-measured value A of the calibration signal amplitude from a memory of the first module (or the chassis or the calibration module). The value A and the measured output power of the signal path are used to determine a gain of the signal path. The system compensates for that gain when the signal path is used to measure live operational signals.
    Type: Grant
    Filed: January 14, 2011
    Date of Patent: October 28, 2014
    Assignee: National Instruments Corporation
    Inventors: Tamir E. Moran, Jatinderjit S. Bains, Daniel S. Wertz
  • Patent number: 8850394
    Abstract: A method and processor for debugging a target processor. The method comprises: executing code on the target processor to generate trace information for debugging; and during execution of that code, periodically incrementing a value of a counter on the target processor. The execution of the code includes executing a plurality of timestamp instructions on the target processor each to associate a respective timestamp with the trace information. The execution of each timestamp instruction comprises generating the respective timestamp by reading the value of the counter into a software accessible storage location and subsequently resetting the counter.
    Type: Grant
    Filed: May 7, 2009
    Date of Patent: September 30, 2014
    Assignee: Icera Inc.
    Inventor: David Alan Edwards
  • Patent number: 8843794
    Abstract: Techniques and mechanisms for evaluating I/O buffer circuits. In an embodiment, test rounds are performed for a device including the I/O buffer circuits, each of the test rounds comprising a respective loop-back test for each of the I/O buffer circuits. Each of the test rounds corresponds to a different respective delay between a transmit clock signal and a receive clock signal. In another embodiment, a first test round indicates a failure condition for at least one I/O buffer circuit and a second test round indicates the failure condition for each of the I/O buffer circuits. Evaluation of the I/O buffer circuits determines whether the device satisfies a test condition, where the determining is based on a difference between the delay corresponding to the first test round and the delay corresponding to the second test round.
    Type: Grant
    Filed: September 24, 2012
    Date of Patent: September 23, 2014
    Assignee: Intel Corporation
    Inventors: Christopher J. Nelson, Tak M. Mak, David J. Zimmerman, Pete D. Vogt
  • Patent number: 8762764
    Abstract: This invention relates to a method of receiving a first potentially unreliable clock signal having a first frequency; receiving a second reliable clock signal having a second frequency; wherein the first frequency and the second frequency have an expected relationship; determining whether the first potentially unreliable clock signal has changed with respect to the second reliable clock signal by: determining an actual relationship between the first potentially unreliable frequency and the second reliable frequency; and generating an alarm signal if the actual relationship is different to the expected relationship.
    Type: Grant
    Filed: January 5, 2011
    Date of Patent: June 24, 2014
    Assignee: STMicroelectronics (Research & Development) Limited
    Inventor: Mark Trimmer
  • Patent number: 8762096
    Abstract: A modulation error is detected every symbol data to generate a trigger signal. The present invention focuses that there are limited patterns of shifts from one symbol data to the next one of the digital modulation signal. Measured values of amplitude, phase and/or frequency of symbol data are latched and then values at the next symbol timing are predicted from the latched measured values using said feature. The predicted and measured values are compared at the following symbol timing. If the difference (error) is over an acceptable range, a trigger signal is provided which allows acquiring a modulation error by symbol data.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: June 24, 2014
    Assignee: Tektronix International Sales GmbH
    Inventor: Akira Nara
  • Patent number: 8707113
    Abstract: A method for operating a data processing system to generate a test for a device under test (DUT) is disclosed. The method utilizes a model of the DUT that includes a plurality of blocks connected by wires and a set of control inputs. Each block includes a plurality of ports, each port being either active or inactive. Each block is also characterized by a set of constraints that limit which ports are active. The active ports of at least one of the blocks are constrained by one of the control inputs. A test vector having one component for each port of each block and one component for each control input is determined such that each set of constraints for each block is satisfied. The test vector defines a test for the DUT.
    Type: Grant
    Filed: January 25, 2011
    Date of Patent: April 22, 2014
    Assignee: Agilent Technologies, Inc.
    Inventors: Douglas Manley, Randy A. Coverstone
  • Patent number: 8635041
    Abstract: Described herein are implementations of various technologies for a method for configuring a seismic data acquisition network. A first message may be received from a first node of the seismic data acquisition network over a first direct communication link. The first message may comprise a first precision quality of a first reference clock to which the first node may be synchronized. A second message may be received from a second node of the seismic data acquisition network over a second direct communication link. The second message may comprise a second precision quality of a second reference clock to which the second node may be synchronized. One of the first precision quality and the second precision quality may be determined to have a higher precision quality. A real time clock may be synchronized to one of the first reference clock and second reference clock having the higher precision quality.
    Type: Grant
    Filed: June 11, 2009
    Date of Patent: January 21, 2014
    Assignee: WesternGeo L.L.C.
    Inventors: Daniel Golparian, Anh Duc Dao
  • Patent number: 8635040
    Abstract: A signal measuring device, comprises one set, or a plurality of sets, of measuring unit(s) measuring an object of measurement in synch with a driving clock signal for measurement and outputting result of measurement as first data, and a timing identification unit which, in accordance with a measurement-start command, outputs a value, which differs every period, as second data in synch with a reference signal having a prescribed period and a speed lower than that of the driving clock signal; and a storage unit collecting and successively storing the first data and the second data as one set in synch with the driving clock signal.
    Type: Grant
    Filed: December 19, 2007
    Date of Patent: January 21, 2014
    Assignee: NEC Corporation
    Inventors: Koichi Nose, Masayuki Mizuno, Atsufumi Shibayama
  • Patent number: 8594962
    Abstract: A technique includes determining a first difference between a time that a first network element of a seismic acquisition network receives a first frame pulse from a second network element of the seismic acquisition network and a time that the first network element transmits a second frame pulse to the second network element. The technique includes determining a second difference between a time that the second network element receives the second frame pulse and a time that the second network element transmits the first frame pulse. The technique includes determining a transmission delay between the first and second network elements based on the first and second time differences.
    Type: Grant
    Filed: May 28, 2009
    Date of Patent: November 26, 2013
    Assignee: WesternGeco L.L.C.
    Inventor: Geir A. M. Drange
  • Patent number: 8552740
    Abstract: A method of measuring signal delay in a integrated circuit comprising applying a common clock signal at a circuit input and output, applying a test signal at the circuit input, detecting a corresponding output signal at the circuit output and detecting whether the test signal and output signal occur in a common part of the clock signal.
    Type: Grant
    Filed: December 10, 2008
    Date of Patent: October 8, 2013
    Assignee: Maxeler Technologies Limited
    Inventors: Peter Ying Kay Cheung, Nicholas Peter Sedcole, Justin Sung-Jit Wong
  • Patent number: 8542005
    Abstract: An apparatus includes a first oscilloscope having multiple channels, and a second oscilloscope having multiple channels. The first oscilloscope is configured to operate as a master or as a slave. The first oscilloscope operates as the master by using a first trigger signal and a first clock signal that are native to the first oscilloscope, and the first oscilloscope operates as the slave by using a second trigger signal and a second clock signal that are native to the second oscilloscope. The second oscilloscope is configured to operate as the master or as the slave. The second oscilloscope operates as the master by using the second trigger signal and the second clock signal, and the second oscilloscope operates as the slave by using the first trigger signal and the first clock signal.
    Type: Grant
    Filed: April 28, 2010
    Date of Patent: September 24, 2013
    Assignee: Teradyne, Inc.
    Inventors: Hamid Kharrati, Steven D. Roach, Joseph Sascha Willis
  • Patent number: 8452553
    Abstract: A device and a method. The device includes: (i) a processor, connected to the receiver, (ii) an interface adapted to receive a test vector and to output a test response, the test vector includes a first group of signals that include idle signals and at least one information frame and a second group of signals that include timing signals and data signals; and (iii) a receiver, connected to the interface. The receiver is adapted to receive the first group of signals and filter out the idle signals and at least one instruction frame delimiters to provide at least one instruction. The device is adapted to send the at least one instruction to at least one instruction buffer. The processor is adapted to execute at least one instruction stored in the at least one instruction buffer and to respond to the second group of signals such as to provide test responses.
    Type: Grant
    Filed: November 30, 2006
    Date of Patent: May 28, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Eran Glickman, Yaron Alankry, Erez Arbel-Meirovich, Erez Parnes
  • Patent number: 8448008
    Abstract: On-chip high speed clock control techniques for testing circuits with multiple clock systems are disclosed. The techniques allow certain (e.g. compatible) high speed clocks to be activated with predefined waveforms during a capture period of a logic test, based on a clock control signal. The clock control signal may be supplied via a JTAG control port or via a scan chain load port. The clock control signal may also be generated by a BIST controller. The techniques may ensure glitch-free transitions from slow speed clocks during a shift period to fast speed clocks during a capture period.
    Type: Grant
    Filed: March 29, 2010
    Date of Patent: May 21, 2013
    Assignee: Mentor Graphics Corporation
    Inventors: Friedrich Hapke, Michael Wittke, Sascha Ochsenknecht, Thomas H. Rinderknecht
  • Patent number: 8423315
    Abstract: A waveform generation and measurement module that may be used in automated test equipment. The waveform generation and measurement module includes high speed SERDES (or other shift registers) that are used to digitally draw a test waveform. Additional high speed SERDES may also be used to receive (in serial form) a response waveform from a device under test and convert it to parallel data for high speed processing. The waveform generation and measurement module may be implemented in field programmable gate array logic.
    Type: Grant
    Filed: March 3, 2010
    Date of Patent: April 16, 2013
    Assignee: Bini Ate, LLC
    Inventors: William F. Kappauf, Barry Edward Blancha, Tetsuro Nakao
  • Patent number: 8392145
    Abstract: A delay setting data generator generates delay setting data based on rate data. A variable delay circuit delays the test pattern data by a delay time determined by the delay setting data with reference to a predefined unit amount of delay. First rate data designates the period of the test pattern data with a precision determined by the unit amount of delay. Second rate data designates the period of the test pattern data with a precision higher than that determined by the unit amount of delay. The delay setting data generator outputs a first value and a second value in a time division manner at a ratio determined by the second rate data, the first and second values being determined by the first rate data.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: March 5, 2013
    Assignee: Advantest Corporation
    Inventors: Daisuke Watanabe, Toshiyuki Okayasu
  • Patent number: 8364290
    Abstract: A method of machine control can include providing at least a system master signal, selectively synchronizing at least sub-system master signal to the system master signal based on the value of the system master signal, and carrying out at least one operation based on the value of the other master signal. For example, a machine controller may provide a system virtual master signal and synchronize one or more module virtual master signals to the system virtual master based on the system virtual master count value. One or more components of the module may operate based on the count value of the module virtual master signal. The use of an asynchronous control method may advantageously increase the flexibility of the machine. Because the operation of the components of the machine may depend on respective virtual master signals, a machine using asynchronous control methods may advantageously continue operating one component or module in the event of a fault involving other components.
    Type: Grant
    Filed: March 30, 2010
    Date of Patent: January 29, 2013
    Assignee: Kimberly-Clark Worldwide, Inc.
    Inventor: Kenneth Allen Pigsley
  • Publication number: 20130006570
    Abstract: Employing RF or optical communication connecting links to oscilloscope probes—adds mobility and flexibility to oscilloscope test and measurement operation. Currently bound by cables to the oscilloscope control and display functions the probe systems are freed to communicate and send signal images over a wide range in local areas. The RF linking of unique address probe systems allows multiple individuals at distant test sites to participate in coordinated viewing and controlling test operations facilitating group and management cooperation. The test probe cable system adapted or replaced by an RF link is configured for the two general classes of oscilloscopes—the integrated bench oscilloscope instrument and the bifurcated oscilloscope instrument that employs a PC for display and control. Oscilloscope probes that are cable free enable the signal measurements to be collected conveniently—even from remote or otherwise inaccessible points.
    Type: Application
    Filed: June 29, 2012
    Publication date: January 3, 2013
    Inventor: Sidney J. Kaplan
  • Patent number: 8341477
    Abstract: A test board includes a plurality of test modules. Each test module stores a first control signal, a data signal, and a second control signal in response to a clock signal, and tests a corresponding device under test (DUT) using the first control signal and the stored data signal in response to the second control signal to generate an error signal indicating whether the DUT is defective. Each test module outputs the first control signal, the data signal, and the second control signal to a test module in a next stage, and each test module of a subsequent stage receives the error signal stored generated by a test module in a previous stage in response to the clock signal.
    Type: Grant
    Filed: March 11, 2010
    Date of Patent: December 25, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Won-Hyung Song
  • Publication number: 20120323519
    Abstract: A pattern generator PG generates control data which specifies a threshold voltage to be compared with a signal under test input to an I/O terminal, and generates expected value data which represents an expected value for the comparison result between the signal under test and the threshold voltage. A threshold voltage generator generates the threshold voltage having a voltage level that corresponds to the control data at every setting timing indicated by a first timing signal. A level comparator compares the voltage level of the signal under test with its corresponding threshold voltage. A timing comparator latches the output of the level comparator at a strobe timing indicated by a second timing signal so as to generate a comparison signal. A timing adjustment unit adjusts the phase of the first timing signal.
    Type: Application
    Filed: June 15, 2012
    Publication date: December 20, 2012
    Applicant: ADVANTEST CORPORATION
    Inventors: Masahiro ISHIDA, Kiyotaka ICHIYAMA
  • Publication number: 20120296598
    Abstract: A method for compensating for jitter during DDR3 delay line training may include using a computer or processor to perform the steps of executing a plurality of tests for each one of a plurality of delay values for an interconnect delay between a Double-Data-Rate Three (DDR3) memory controller and a DDR3 Synchronous Dynamic Random Access Memory (SDRAM); accumulating a plurality of test results for each plurality of tests for each one of the plurality of delay values; determining a plurality of final test results, where each final test result is associated with an accumulated plurality of test results; and determining a working window edge for the interconnect delay between the DDR3 memory controller and the DDR3 SDRAM utilizing the plurality of final test results.
    Type: Application
    Filed: May 18, 2011
    Publication date: November 22, 2012
    Applicant: LSI CORPORATION
    Inventors: Craig R. Chafin, William J. Schmitz, Carl E. Gygi
  • Patent number: 8244492
    Abstract: Delay-fault testing and parametric analysis systems and methods utilizing one or more variable delay time-base generators. In embodiments of the delay-fault testing systems, short-delay logic paths are provided with additional scan-chain memory elements and logic that, in conjunction with the one or more variable-delay time-base generators, provides the effect of over-clocking without the need to over-clock. Related methods provide such effective over-clocking. In embodiments of parametric analysis systems, test point sampling elements and analysis circuitry are clocked as a function of the output of the one or more variable-delay time-base generators to provide various parametric analysis functionality. Related methods address this functionality.
    Type: Grant
    Filed: March 9, 2011
    Date of Patent: August 14, 2012
    Assignee: DFT Microsystems, Inc.
    Inventor: Mohamed M. Hafed
  • Patent number: 8239158
    Abstract: Various embodiments of a system and method for performing a measurement application are described herein. The system may include a host computer having a processor, and a measurement device having a programmable hardware element. The programmable hardware element may be configured to perform a loop to acquire measurement data from a physical system. The host computer may be configured to perform another loop to read the measurement data from the programmable hardware element and use the measurement data in a measurement and control algorithm. The host computer may be further configured to perform a synchronization algorithm to keep the measurement data acquisition loop performed by the programmable hardware element synchronized with the measurement and control loop performed by the host computer.
    Type: Grant
    Filed: August 4, 2009
    Date of Patent: August 7, 2012
    Assignee: National Instruments Corporation
    Inventors: Charles E. Crain, II, Adam H. Dewhirst, Robert L. Ortman
  • Publication number: 20120197583
    Abstract: A method of testing a printed circuit board (PCB) acquires test points from a wiring diagram of the PCB. Frequency domain tested items for each test point and a standard value of each frequency domain tested item are preset. A distance between a preset fiducial point and each test point is computed to create a testing order of the test points according to the distances. The frequency domain tested items of each test point are computed according to the testing order. A pass or a failure of each test point is displayed according to a determination of if each of the computed frequency domain tested items within the corresponding standard value, and a test result of the PCB is output according to the passes or the failures.
    Type: Application
    Filed: November 7, 2011
    Publication date: August 2, 2012
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: HSIEN-CHUAN LIANG, SHEN-CHUN LI, PO-CHUAN HSIEH, YU-CHANG PAI, SHOU-KUO HSU
  • Publication number: 20120179415
    Abstract: A modulation error is detected every symbol data to generate a trigger signal. The present invention focuses that there are limited patterns of shifts from one symbol data to the next one of the digital modulation signal. Measured values of amplitude, phase and/or frequency of symbol data are latched and then values at the next symbol timing are predicted from the latched measured values using said feature. The predicted and measured values are compared at the following symbol timing. If the difference (error) is over an acceptable range, a trigger signal is provided which allows acquiring a modulation error by symbol data.
    Type: Application
    Filed: December 17, 2010
    Publication date: July 12, 2012
    Applicant: TEKTRONIX INTERNATIONAL SALES GMBH
    Inventor: Akira Nara
  • Patent number: 8219346
    Abstract: Various techniques are described for high resolution time measurement using a programmable device, such as a field programmable gate array (FPGA). The timing may be triggered by any event, depending on the applications of use. Once triggering has occurred, a START pulse begins propagating through the FPGA. The pulse is able to propagate through the FPGA in a staggered manner traversing multiple FPGA columns to maximize the amount of time delay that may be achieved while minimizing the overall array size, and thus minimizing the resource utilization, of the FPGA. The FPGA timing delay is calibrated by measuring for the linear and non-linear differences in delay time of each unit circuit forming the staggered delay line path for the timing circuit. The FPGA is able to achieve nanosecond and sub-nanosecond time resolutions.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: July 10, 2012
    Assignee: The Regents of the University of Michigan
    Inventors: Thomas Zurbuchen, Steven Rogacki
  • Patent number: 8214539
    Abstract: Command mapping systems that provide extended command functions to input devices in addition to translating between multiple APIs to provide compatibility between a user-selected input device and a user-selected program.
    Type: Grant
    Filed: February 9, 2010
    Date of Patent: July 3, 2012
    Inventor: Robert J. Kulanko
  • Publication number: 20120158348
    Abstract: A delay setting data generator generates delay setting data based on rate data. A variable delay circuit delays the test pattern data by a delay time determined by the delay setting data with reference to a predefined unit amount of delay. First rate data designates the period of the test pattern data with a precision determined by the unit amount of delay. Second rate data designates the period of the test pattern data with a precision higher than that determined by the unit amount of delay. The delay setting data generator outputs a first value and a second value in a time division manner at a ratio determined by the second rate data, the first and second values being determined by the first rate data.
    Type: Application
    Filed: February 29, 2012
    Publication date: June 21, 2012
    Applicant: Advantest Corporation
    Inventors: Daisuke Watanabe, Toshiyuki Okayasu
  • Publication number: 20120150479
    Abstract: A debug port configured to generate and provide a return clock is disclosed. In one embodiment, an integrated circuit (IC) includes one or more functional units and a debug port (DP). The DP is configured to enable access by an external debugger to the functional unit(s) of the IC for debugging purposes. The DP includes circuitry that may generate a first clock signal that is provided to the functional unit(s) during debug operations. Receiving test result data at the DP may require a return clock signal that is not provided by the functional unit(s). Accordingly, the IC may include a clock modifier coupled to receive the first clock signal. The clock modifier may generate a second clock signal based on the first, the second clock signal being provided to the DP as a return clock signal.
    Type: Application
    Filed: December 10, 2010
    Publication date: June 14, 2012
    Inventors: Deniz Balkan, Kevin R. Walker, Mitchell P. Lichtenberg,, JR.
  • Patent number: 8191033
    Abstract: Embodiments of the present invention provide a method/apparatus to measure the jitter of a timing signal used in an integrated circuit chip. The method/apparatus is used to send data from a launch element using a synchronous data path of the timing signal, receive the data at a capture element using the synchronous data path, wherein the launch element and the capture element are disposed on the same integrated circuit chip upon which the timing signal is generated and/or used, and gather statistics about whether a timing violation has occurred by comparing the sent data with the received data over the course of multiple launch/capture events as the timing is adjusted. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: November 6, 2009
    Date of Patent: May 29, 2012
    Assignee: Marvell International Ltd.
    Inventor: Thomas Page Bruch
  • Patent number: 8185338
    Abstract: A low pin interface module is provided for testing an integrated circuit. The interface module includes an input-output module, a controlling module, a processing module and a storage module specific to the integrated circuit to be tested. The interface module reduces the required number of hardware pins in the integrated circuit for a standalone testing without limiting the integrated circuit testing features. A methodology and a control mechanism achieved with the interface module can be used for the standalone testing of any integrated circuit without using a Joint European Test Action Group test logic interface JTAG implemented following the IEEE Standard 1149.1-1990. The interface module is not limited by a particular debugging platform and allows access to all test features in the integrated circuit with a reduced number of hardware pins and thereby leading to enhanced testing speeds on a tester in parallel and a shorter time-to-a market cycle and a lower development cost.
    Type: Grant
    Filed: December 24, 2008
    Date of Patent: May 22, 2012
    Assignee: STMicroelectronics International N.V.
    Inventors: Rahul Hakoo, Chilakala Ravi Kumar, Deepak Baranwal
  • Patent number: 8160835
    Abstract: A method for measuring unidirectional transmission properties, e.g., packet delay, delay-time fluctuations, and results derivable therefrom, in a telecommunications network. Test packets are transmitted from a first measuring computer via a measurement path to a second measuring computer. The first measuring computer records the departure time of the outgoing test packet. This clock time is transmitted along with the test packet. The second measuring computer records the arrival time of the test packet. In a subtraction operation between the departure time from the first measuring computer and the arrival time in the second measuring computer, the delay time of the test packet, i.e., the measuring result, is determined. To determine the measuring result, the two measuring computers are synchronized in time by satellite systems, e.g., GPS (global positioning system), in that the clock time is continuously transmitted to both measuring computers.
    Type: Grant
    Filed: July 13, 2001
    Date of Patent: April 17, 2012
    Assignee: Deutsche Telekom AG
    Inventors: Heinrich Doerken, Joachim Mende
  • Patent number: 8156396
    Abstract: A system and method for reducing timing errors in automated test equipment (ATE) offering increased data rates for the testing of higher-speed integrated circuits. Embodiments provide an effective mechanism for increasing the data rate of an ATE system by delegating processing tasks to multiple test components, where the resulting data rate of the system may approach the sum of the data rates of the individual components. Each component is able to perform data-dependent timing error correction on data processed by the component, where the timing error may result from data processed by another component in the system. Embodiments enable timing error correction by making the component performing the correction aware of the data (e.g., processed by another component) causing the error. The data may be shared between components using existing timing interfaces, thereby saving the cost associated with the design, verification and manufacturing of new and/or additional hardware.
    Type: Grant
    Filed: October 5, 2010
    Date of Patent: April 10, 2012
    Inventors: Jean-Yann Gazounaud, Howard Maassen
  • Patent number: 8150648
    Abstract: A delay setting data generator generates delay setting data based on rate data. A variable delay circuit delays the test pattern data by a delay time determined by the delay setting data with reference to a predefined unit amount of delay. First rate data designates the period of the test pattern data with a precision determined by the unit amount of delay. Second rate data designates the period of the test pattern data with a precision higher than that determined by the unit amount of delay. The delay setting data generator outputs a first value and a second value in a time division manner at a ratio determined by the second rate data, the first and second values being determined by the first rate data.
    Type: Grant
    Filed: December 26, 2008
    Date of Patent: April 3, 2012
    Assignee: Advantest Corporation
    Inventors: Daisuke Watanabe, Toshiyuki Okayasu