Abstract: A method and system for testing of base stations of a mobile telecommunications network having a plurality of cells. A base station at its antenna is connected to a testing system by a radio frequency cable. Mobile terminals of a cell are emulated. The mobile terminals transmit data and sends/receives calls within the cell via the base station. A separate channel emulator is provided for each emulated mobile terminal.

Abstract: Systems and methods for code caching are provided. A first indication of primary source code awaiting execution is received. A resource cache is checked for cached data corresponding to the primary source code. Upon a cache miss in the resource cache, a first executable code compiled from the primary source code is obtained. A secondary source code referenced in the primary source code is selected. A second executable code compiled from the selected secondary source code is obtained. The first executable code and the second executable code are serialized into serialized code. The serialized code is stored as cached data in the resource cache.

Abstract: The present disclosure pertains to systems and methods for simulating data packet routing within a software defined network (“SDN”), visualizing the results of the simulation, and permitting a user to search the resulting simulation. In one specified embodiment, a system may receive from a user a simulation parameter associated with a packet to be simulated in the SDN. A packet based on the at least one simulation parameter may be generated. A response of the SDN to the packet may be simulated by identifying applicable traffic routing rules and identifying a subsequent destination based on the applicable traffic routing rules. A record of the subsequent destination may be added to the simulation result, and the process may continue until a terminating condition is satisfied.

Abstract: Techniques for near-term data filtering, smoothing and forecasting are described herein. In one example, data is received from supervisory control and data acquisition (SCADA) measurements available in an electrical grid. The data may be filtered according to a two-stage Kalman filter, which may include a ramp rate filter test and a load level filter test. The filtered data may then be smoothed according to an augmented Savitzky-Golay filter. Within the filter, a lift multiplier may correct for bias, which may have been introduced by load changes (e.g., an early morning increase in load). In one example, the lift multiplier may be calculated as a ratio between a smoothed load from a centered Savitzky-Golay moving average and a right hand side constrained Savitzky-Golay moving average. The filtered and smoothed data may be used in forming near-term forecast(s), which may be performed by autoregressive model(s).

Abstract: A system for analyzing an environment to identify a security risk in a process, comprising a model engine to generate a model of the environment using multiple components defining adjustable elements of the model and including components representing a patching process for the environment, a risk analyzer to calculate multiple randomized instances of an outcome for the environment using multiple values for parameters of the elements of the model selected from within respective predefined ranges for the parameters, and to use a results plan to provide data for identifying a security risk in the patching process using the multiple instances.

Abstract: An information processing apparatus includes a hardware processor and a memory storing executable instructions that, when executed by the processor, cause the processor to extract a command from a command cache, complete a process by the command utilizing a predetermined method, input information, which indicates a final result of the process, onto a writing stage when the process by the command has been completed, compute, when operation of information input onto an execution stage for execution of the process by the command has been completed, power consumption required to execute the command stored in the execution stage in accordance with a status of a CPU (central processing unit) or a status of pertained parts around the CPU, and add, when operation of information input onto the writing stage has been completed, the computed power consumption to a current value of a power accumulating register that is a software visible register, so as to obtain accumulated power consumption.

Abstract: A device may receive information specifying a physical time delay of a computational node of a first computational graph. The first computational graph may include a group of computational nodes that are connected in a particular manner, and may represent at least a portion of a dynamic system. The device may further add an abstract node to a second computational graph based on the received information. The abstract node may correspond to the computational node and may implement the physical time delay when the second computational graph is executed. The second computational graph may include a group of abstract nodes that are connected in the particular manner. The device may also execute the second computational graph, and may obtain one or more behavioral characteristics of the at least the portion of the dynamic system based on executing the second computational graph.

Abstract: A method, system and computer-usable medium are disclosed for detecting the cause of a system hang in a verification environment. Hardware components associated with the design under test that are not included in the verification environment are replaced by software drivers. A dependency is set between a first driver and a second driver such that quiescing of the first driver is prevented until the second driver is quiesced. Each driver in a simulation test is designated to be either independent or dependent, with each dependent driver being associated with at least one independent driver. The independent driver is quiesced at a predetermined time. Dependent drivers do not quiesce until of their associated drivers have quiesced and completed all of their respectively issued instructions.

Abstract: Disclosed herein are representative embodiments of methods, systems, and apparatus for performing synthesis. For example, in one exemplary method disclosed herein, a high-level description of a complete circuit design is partitioned into a plurality of sections. Two or more synthesis engine configurations are selected for a respective one of the sections. The respective one of the sections is synthesized using the two or more selected synthesis engine configurations, thereby generating two or more gate-level descriptions. A gate-level description of the complete circuit design is generated that includes at least a portion of one of the gate-level descriptions. Computer-readable media storing instructions for causing a computer to perform any of the disclosed methods are also disclosed herein.

Abstract: A cache control device includes an area determination unit that determines an area of a cache memory which is allocated to each instruction flow on the basis of an allocation ratio of an execution time per unit time, which is allocated to each of a plurality of the instruction flows by a CPU. The area determination unit specifies the area allocated to the specified instruction flow in response to an access request from a memory access unit, and accesses the specified area in the cache memory.

Abstract: The method and system according to a preferred embodiment of the present invention allows ensuring consistency of the PNR record when it is handled within the subsystem controlled by the reservation interceptor module and including a plurality of OBEs. According to a preferred embodiment of the present invention the PNR context on open systems is centralized to avoid its fragmentation in the distributed environment, as gathering of all the context parts implies performance issues. In addition, instead of implementing a transaction session protocol to handle a start of transaction, intermediate updates and a final commit or rollback on the PNR context, the principle of the service interceptor architecture is to delegate the functional queries with the current user PNR context which will be modified in the central repository of PNR context only at response time when the whole functional use-case is finished.

Abstract: A network-based production service is configured to process client requests for the production service via a network, capture production request data defining the requests and store the production request data in a data store. A test system comprising one or more controllers creates test jobs according to a test plan for testing the production service. The test plan creates a test profile for using specified production request data to simulate a load on the production service. Each job created by the test plan specifies a portion of production request data. A job queue receives and queues test jobs from one or more controllers configured to add test jobs to the job queue according to the test plan. Workers access jobs from the job queue and the production request data from the data store as specified in each job and replay the production request data to the production service.

Abstract: A data processing apparatus supports operation in both a secure domain and a less secure domain. The secure domain has access to data that is not accessible when operating the less secure domain. Prediction circuitry generates a domain prediction indicating whether a given processing action (such as a memory access) is to be performed in association with the secure domain or with the less secure domain. In this way, an appropriate set of memory permission data for controlling access by different privilege levels in the domains may be selected and applied by an appropriate memory protection unit. If the domain prediction is incorrect, then the processing is stalled and the given processing action retried.

Abstract: An endian conversion method is executed by a CPU, and includes executing a program that includes endian conversion setting; and performing, when accessing an address of a main memory indicated in the endian conversion setting, endian conversion of data specified by the address of the main memory.

Abstract: A computer device and method are described for controlling access to a resource. An execution environment executes a user process with access privileges according to a user security context. A security unit controls access to resources according to the user security context, with the user process making system calls to the security unit. A proxy hook module embedded within the user process intercepts the system call and generates a proxy resource access request. A proxy service module in a privileged security context validates the proxy resource access request from the proxy hook module and, if validated, obtains and returns a resource handle that permits access to the desired resource by the user process.

Abstract: A method and system for enabling a designer to more easily convert a model of a dynamic system instantiated using floating-point representation such as has been created in a high level design language to fixed-point code suitable for execution in a programmable processor or logic array.

Abstract: A method for annotating video content for assisting language learning is shown. The method includes identifying one or more objects in a video content, generating one or more language tags for at least one of the one or more objects, and associating the one or more language tags with utilization information, wherein the utilization information comprises display information configured to be used by a user device in the displaying of at least one of the one or more language tags with the video content.

Abstract: A content management system synchronizes content items across client computing systems connected by a network. Each client device has a storage allocation for synchronized shared content items. If the storage allocation for shared content items on a client device is exceeded by the request to add or edit a content item such that it is enlarged, or open a large content item remote to the client device, a client application or the host of content management system selects content items to remove from residence on the client device but keep remotely on content management system. Upon removal of the selected content items, the client application creates shadow items, representing the content item but only containing the metadata of the content item. This creates sufficient space for the initial request to be completed while maintaining user access to all synchronized shared content items.

Abstract: A method of porting source code for use in a runtime environment including a tool chain with a compiler for building the source code, in which the method comprises obtaining a source code fragment associated with a build error during the source code build in the runtime environment; creating a signature of the source code fragment; automatically comparing the signature with entries in an error database constructed from a history of previous build errors in the runtime environment and their fixes in the form of source code and/or tool chain modifications; using the comparison to find one or more similar previous build errors to the build error and thus to identify one or more of the source code and/or tool chain modifications as candidate solutions to the build error; compiling the source code with each of the candidate source code and/or tool chain modifications in turn until the source code compiles without reproducing the build error; and storing the build error in the error database and storing the modific

Abstract: Systems and methods of using hardware to simulate software, specifically the semantic operations defined in HDL simulation languages. Traditional software HDL simulation kernel operations of advancing time, activating threads in response to notified events, and scheduling those threads of execution are handled via a simulation controller. The simulation controller is comprised of a timing wheel, an event-processor, a thread/process dispatch engine, a token processor, and a resource-allocator. These components work together with a control logic component to perform the semantic operations of an HDL software kernel.

Abstract: Disclosed are methods, circuits, apparatus, systems and associated software modules for dynamically evaluating code behavior in runtime. There is provided a code testing platform and/or framework which may include: (1) a code execution environment instancing module (CEEIM), (2) code execution resources, (3) executed code isolation logic, and (4) code call response logic. The CEEIM may instance, on a computing platform, a code execution environment (CEE) which is at least partially isolated from external resources functionally associated with the computing platform. The CEE may include code execution resources adapted to execute code whose behavior is to be evaluated, wherein a resource call generated from code execution may be analyzed by the code isolation logic and may under certain conditions be routed to the code call response logic.

Abstract: A device supporting the structural analysis of a module comprises: a storage means storing at least one module; and a conversion means that converts a prescribed target module among the modules stored by the storage means to a secondary module and stores same in the storage means. The conversion means reads the target module from the storage means and sequentially outputs to the secondary module each sentence written from a prescribed processing start location in the target module to a prescribed processing end location. The conversion means also recursively develops a sentence written in processing units etc., for execution, and outputs same to the secondary module, when the sentence is a module internal processing unit or a sentence that executes another module.

Abstract: A method and apparatus for transaction level modeling where communications occur between modules in the system that contain time annotations is described. An apparatus includes an initiator module, a target module, and a communications channel with each being modeled as an executable behavioral model. The communications channel transports burst information between the initiator module and the target module. The communications channel has a timing variable function to store timing variables and derive timing information associated with each individual transfer within a burst transaction during a simulation.

Abstract: An embodiment provides a method, including: detecting, using a processor, a volatile memory device of an information handling device; and designating, using a processor, at least a portion of the volatile memory device as simulated non-volatile memory. Other aspects are described and claimed.

Abstract: A building control system comprises a central control station and at least one control panel connected to the central control station over a network. At least one loop is connected to at least one control panel. The at least one loop comprises a plurality of installed building control devices connected in an electrical circuit. A simulator is also connected to the network and configured to simulate the operation of a plurality of uninstalled building control devices for the building control system. The simulator is further configured to communicate over the network with the plurality of installed building control devices. Simulation of the operation of the uninstalled building control devices occurs simultaneously with the communication between the installed building control devices and the simulator. Accordingly, the simulator may be used to test the entire building control system during the process of installation at a facility.

Abstract: An extension Cache Coherence protocol-based multi-level coherency domain simulation verification and test method. An extension Cache Coherence protocol-based multi-level coherency domain CC-NUMA (Cache Coherent Non-Uniform Memory Access) system protocol simulation model is built, a protocol table inquiring and state converting executing mechanism in a key node of a system ensures that a Cache Coherence protocol is maintained in a single computing domain and is simultaneously maintained among a plurality of computing domains, and accuracy and stability of intra-domain and inter-domain transmission are ensured; a credible protocol inlet conversion coverage rate evaluation driven verification method is provided, transactions are processed by loading an optimized transaction generator push model, a coverage rate index is obtained after the operation is ended, and the verification efficiency is increased in comparison with a random transaction promoting mechanism.

Abstract: A deployed configurable communication integrated circuit (IC) and/or chipset which may be integrated within a wireless communication and/or multi-media communication device may be operable to monitor its operating conditions, performance and/or utilization characteristics. It may send information via a wireless, optical and/or wired network to a remote analysis and/or development system and/or service, such as an engineering service, that may determine and return configuration parameters. The configuration parameters may be utilized to adjust antenna and/or MIMO, SIMO, MISO and beamforming configuration, power level, interference rejection, equalizer length, dynamic range, modulation, encoding and/or decoding, analog to digital conversion precision, error detection and/or correction parameters, MAC parameters such as timing thresholds, transmit window size and/or buffer space.

Abstract: Embodiments of apparatuses and methods for processing virtualization events in a layered virtualization architecture are disclosed. In one embodiment, an apparatus includes a event logic and evaluation logic. The event logic is to recognize a virtualization event. The evaluation logic is to determine whether to transfer control from a child guest to a parent guest in response to the virtualization event.

Abstract: Performance metrics related to the processing and propagation of messages related to select applications are collected during a simulation of a network. Each message associated with an application is tagged, and each simulated packet that contains some or all of a tagged message is correspondingly tagged to facilitate the creation of transmit records and receive records. A post processor is configured to collate transmit and receive records of each tagged message to identify delays associated with each node that processes the message, and each link that propagates the message from node to node within the network. The processed timing information is provided to the user via an interactive user interface that allows the user to view the timing information from an application layer perspective.

Abstract: A computer system that simulates a workload of a storage system including a non-transitory storage medium including instruction code for the computer system, wherein the instruction code, when executed on the computer system, performs steps as follows: obtaining configuration data regarding first components of the first storage system including at least one RAID group; obtaining performance data including workload information of the first storage system; configuring second components of a second storage system including at least one corresponding RAID group corresponding to the at least one RAID group of the first storage system, based on the obtained configuration data; and operating the second storage system using a simulated workload based on the obtained performance data, resulting in a front loading of the second storage system equivalent to a front loading of the first storage system.

Abstract: In an embodiment, an electrical-line-noise canceller includes a phase detector, a phase lock loop, a zero-crossing detector, and an adaptive filter. The phase detector is configured to receive a composite input signal including an input neural signal combined with electrical line noise and to detect a phase of the electrical line noise. The phase lock loop is coupled to the phase detector and is configured to lock to the phase of the electrical line noise. The zero-crossing detector is coupled to the phase lock loop and is configured to detect zero crossings of an output of the phase lock loop. The adaptive filter is coupled to the zero-crossing detector and is configured to remove the electrical line noise from the composite input signal and output a filtered neural signal that is substantially similar to the input neural signal.

Abstract: A system receives a model, internals associated with a target processor, and code information associated with the target processor, and obtains a bit-true model simulation for the target processor based on the model, the target processor internals, and the target processor code information.

Abstract: A host device may establish a connection with a physical device. The host device may receive physical device information from the physical device, based on establishing the connection with the physical device. The host device may determine, based on receiving the physical device information, a model element associated with the physical device. The host device may pair the physical device and the model element, based on determining the model element associated with the physical device.

Abstract: Executing a simulation of a computer platform, the simulation including simulation models. A dynamic quantum is accessed whose current value specifies a maximum number of units of execution a simulation model is allowed to perform without synchronizing with another simulation model. The dynamic quantum may be received from a user. Respective simulation models are invoked for execution with the current value of the dynamic quantum provided to each of the simulation models. The method also comprises modifying the value of the dynamic quantum based on a simulation event.

Abstract: Provided is a method for structuring hardware information in computer system, including: modeling Target Independent Model (TIM), which is independent from a hardware; structuring hardware information based on Meta Object Facility (MOF)-Hardware Component Modeling Language (HCML); and transforming the TIM into a Target Specification Model, which depends on the hardware, based on the structured hardware information and the model transformation language, wherein the step of structuring hardware information based on Meta Object Facility (MOF)-Hardware Component Modeling Language (HCML), comprises: defining a MOF-based Hardware Component Modeling Language (HCML) meta-model; and defining a model by using a meta-model of the HCML and representing architecture information on the model.

Abstract: An abstract trace may be defined based on a coverage goal. An execution of a System Under Test (SUT) is guided in accordance with the coverage goal. Non-deterministic decision, which correlates to receiving a stimulus to the SUT, is decided based on a probability function. After one or more executions, the probability function is modified based on a measurement of similarity between the abstract trace and each of the one or more executions. The modification of the probability function may be performed using on Cross-Entropy method. The modification is performed in order to cause determination of non-deterministic decisions in executions to better correlate with the abstract trace. In some exemplary embodiments, a determination whether the abstract trace is reachable is determined based on a rate of convergence of the executions to the abstract trace.

Abstract: A method for synchronizing different components of a computer network system using meta-commands embedded in normal network packets. The data communication channel between different components of a computer network system can be used to transport meta-commands piggybacked in normal network packets, without modifying or compromising the validity of the protocol message. Embodiments of the method can be used for embedding test synchronization and control commands into the network packets sent through a device or system under test. The device or system under test can be an edge device, with the data communication channel carrying normal packets containing meta-commands embedded in the packets to synchronize the test control of the test clients and the test servers connected to the edge device.

Abstract: A system and method of operating an integrated circuit (IC) having a fixed layout of one or more blocks having one or more current sources therein that draw electrical current from a power source. The method includes dynamically issuing to a block configured to perform operations responsive to an instruction received at the block, a reserve amount of tokens; determining for each issuance of instruction to the block whether that block's reserve token amount exceeds zero; and one of: issuing the instruction to the block if the token reserve for that block is greater than one, and decrementing, after issuance of the instruction, by one token the block's reserve token amount, or, preventing issuance of an instruction to the block. In the method, each block may be initialized to have: a reserve token amount of zero, a token expiration period; a token generation cycle and a token generation amount.

Abstract: A method and device for preserving the wired-OR nature of the clock signal connection between two devices without a direct analog connection between the lines and in an infinitely scalable fashion. The method includes detecting a logic state at a first connector and a second connector and driving an appropriate connector of the device to an active state in response to determining that a connector is driving an active state. The device includes first and second connectors for communicating logic states and driving active states in response to detected logic states.

Abstract: A method and mechanism for implementing a general purpose scripting language that supports parallel execution is described. In one approach, parallel execution is provided in a seamless and high-level approach rather than requiring or expecting a user to have low-level programming expertise with parallel processing languages/functions. Also described is a system and method for performing circuit simulation. The present approach provides methods and systems that create reusable and independent measurements for use with circuit simulators. Also disclosed are parallelizable measurements having looping constructs that can be run without interference between parallel iterations. Reusability is enhanced by having parameterized measurements. Revisions and history of the operating parameters of circuit designs subject to simulation are tracked.

Abstract: The present disclosure provides systems and methods for a simulation environment that simulates hardware at a fiber level, a data plane level, a card level, and a chassis level. The simulation environment may be utilized in development and testing of complex, real time, embedded software systems, such as, for example, routers, switches, access devices, base stations, optical switches, optical add/drop multiplexers, Ethernet switches, and the like. In an exemplary embodiment, the simulation environment operates on one or more workstations utilizing a virtual machine to operate a virtualized module, line card, line blade, etc. Further, a plurality of virtual machines may operate together to operate a virtualized chassis forming a network element and with a plurality of virtualized chassis forming a network. Advantageously, the present invention provides state of the art data plane traffic and control plane simulation that reduces development time and cost while increasing design flexibility.

Abstract: A computer-implemented method that simulates NPskew effects on a combination NFET (Negative Field Effect Transistor)/PFET (Positive Field Effect Transistor) semiconductor device using slew perturbations includes performing a timing test by a computing device, by: (1) evaluating perturb slews in Strong N/Weak P directions on the combination semiconductor device for a timing test result; (2) evaluation perturb slews in Weak N/Strong P directions on the combination semiconductor device for a timing test result; and (3) evaluating unperturbed slews in a balanced condition on the combination semiconductor device for a timing test result. After each test is performed, a determination is made as to which evaluation of the perturbed and unperturbed slews produces a most conservative timing test result for the combination semiconductor device. An NPskew effect adjusted timing test result is finally output based on determining the most conservative timing test result.

Abstract: A system and method for performing circuit simulation is described. The present approach provides methods and systems that create reusable and independent measurements for use with circuit simulators. Also disclosed are parallelizable measurements having looping constructs that can be run without interference between parallel iterations. Reusability is enhanced by having parameterized measurements. Revisions and history of the operating parameters of circuit designs subject to simulation are tracked. Mechanisms are provided that allow for viewing, measurement or other manipulation of signals at specific locations in a circuit design for simulation, such as parameters that include observation points which are implemented using probes. One approach to executing a measurement is via a controllable and flexible control statement, which in one embodiment is the “run” statement. Improved interfaces for viewing, controlling, and manipulating simulations and simulation results are also provided.

Abstract: An embodiment of a design of one or more devices such as e.g. integrated circuits is ported from a source design technology to a target design technology by: —producing a standardized set of porting rules which translate device information related to the device or devices from the source design technology to the target design technology, and—creating a migrated design for the device or devices resulting from porting the CAD design from the source design technology to the target design technology by applying the standardized set of rules to the device information related.

Abstract: A method for inserting characteristic extractor is provided. The method includes parsing a transaction level model (TLM) of an electronic device of a target system to find out at least one target point of an operation status of the electronic device; and inserting at least one characteristic extractor into the at least one target point.

Abstract: The graphics load of a virtual desktop is estimated to determine the capacity of a virtual desktop system. In one embodiment, the graphics load of a physical desktop is measured by a remoting agent installed on the physical desktop. The graphics load can be used as an estimate of the load that would be created by a deployed virtual desktop. The remoting agent on the physical desktop mimics host operations that are necessary to direct graphics data to a remote site. The remoting agent also measures the graphics load incurred by the host operations to determine a capacity of a virtual desktop system prior to deployment of the virtual desktop system.

Abstract: A method of configuring a hardware design for a pipelined parallel stream processor includes obtaining a scheduled graph representing a processing operation in the time domain as a function of clock cycles. The graph includes a data path to be implemented in hardware as part of the stream processor, an input, an output, and parallel branches to enable data values to be streamed therethrough from the input to the output as a function of increasing clock cycle. The data path is partitioned into a plurality of discrete regions, each region operating on a different clock phase and having discrete control logic elements. Phase transition registers to align data separated by a boundary between regions having different clock phases are introduced into the data path at the boundary. The graph and control logic elements define a hardware design for the pipelined parallel stream processor.

Abstract: The present invention provides a circuit simulation method of executing a high-precision circuit simulation. A voltage fluctuation analysis step at a gate level is executed (step S2). The voltage fluctuation analysis step at the gate level is executed on an entire chip TP. Next, a step of obtaining waveforms of power supply voltage and ground voltage (Vss) according to the voltage fluctuation analysis step is executed (step S4). Subsequently, a signal analysis step at a transistor level is performed (step S6). The signal analysis step at the transistor level is performed in an area narrower than the entire chip TP, for example, on one or more functional modules. After that, a step of obtaining a signal analysis result according to the signal analysis step is executed (step S8).

Abstract: A method for operating a data processing system to generate a test for a device under test (DUT) is disclosed. The method utilizes a model of the DUT that includes a plurality of blocks connected by wires and a set of control inputs. Each block includes a plurality of ports, each port being either active or inactive. Each block is also characterized by a set of constraints that limit which ports are active. The active ports of at least one of the blocks are constrained by one of the control inputs. A test vector having one component for each port of each block and one component for each control input is determined such that each set of constraints for each block is satisfied. The test vector defines a test for the DUT.

Abstract: Aspects of the invention relate to techniques for fault diagnosis based on circuit design partitioning. According to various implementations of the invention, a circuit design of a failing die is first partitioned into a plurality of sub-circuits. The sub-circuits may be formed based on fan-in cones of observation points. Shared gate ratios may be used as a metric for adding fan-in cones of observation points into a sub-circuit. Based on test patterns and the sub-circuits, sub-circuit test patterns are determined. Fault diagnosis is then performed on the sub-circuits. The sub-circuit fault diagnosis comprises extracting sub-circuit failure information from the failure information for the failing die. The sub-circuit fault diagnosis may employ fault-free values for boundary gates in the sub-circuits.