Abstract: A system and method provides for the formation of transparent links between subsystems or blocks within a graphical model. The transparent link allows marking one or multiple subsystems in the graphical model as the reference source that, similar to a library block, can be linked with other blocks in the graphical model. The referenced subsystem or block is not located in a separate file from the graphical model file. Changes made to a source block in the model can be propagated to linked destinations.

Abstract: A computer architecture includes a first operating system (COS), which may be a commodity operating system, and a kernel, which acts as a second operating system. The COS is used to boot the system as a whole. After booting, the kernel is loaded and displaces the COS from the system level, meaning that the kernel itself directly accesses predetermined physical resources of the computer. All requests for use of system resources then pass via the kernel. System resources are divided into those that, in order to maximize speed, are controlled exclusively by the kernel, those that the kernel allows the COS to handle exclusively, and those for which control is shared by the kernel and COS. In the preferred embodiment of the invention, at least one virtual machine (VM) runs via a virtual machine monitor, which is installed to run on the kernel. Each VM, the COS, and even each processor in a multiprocessor embodiment, are treated as separately schedulable entities that are scheduled by the kernel.

Abstract: There is disclosed an apparatus for designing and optimizing a memory for use in an embedded processing system. The apparatus comprises: 1) a simulation controller for simulating execution of a test program to be executed by the embedded processing system; 2) a memory access monitor for monitoring memory accesses to a simulated memory space during the simulated execution of the test program, wherein the memory access monitor generates memory usage statistical data associated with the monitored memory accesses; and 3) a memory optimization controller for comparing the memory usage statistical data and one or more predetermined design criteria associated with the embedded processing system and, in response to the comparison, determining at least one memory configuration capable of satisfying the one or more predetermined design criteria.

Abstract: An interactive voice response (IVR) system executes a call flow that references data objects holding information. The information within a data object includes a variable that holds a value utilized by the call flow, state information describing the state of the variable, and fulfillment type information that describes how to get a value for the variable or otherwise change the variable's state. Process and application objects in the call flow specify desired states of variables at given points in the call flow. A resolution module within the IVR system determines whether the variables are in the desired states and, if not, utilizes the fulfillment type information in the data objects to attempt to put the variables in the desired states. This dynamic resolution process provides a mechanism for resolving the values of variables in data objects as the values are required and eases the burden on the call flow developer.

Abstract: A computer system reads data corresponding to an IC layout target layer and performs an etch simulation on the target layer. Etch biases are calculated and the inverse of the etch biases are used to produce a new target layer. The new target layer is provided as an input to an optical process correction (OPC) loop that corrects the data for image/resist distortions until a simulation indicates that a pattern of objects created on a wafer matches the new target layer. In another embodiment of the invention, original IC layout data is provided to both the OPC loop and an etch simulation. Etch biases calculated by the etch simulation are used in the OPC loop in order to produce mask/reticle data that will be compensated for both optical and resist distortions as well as for etch distortions.

Abstract: The invention relates to a device for testing a packet-switched radio network. The device comprises a network traffic simulator for traffic in a radio access network; and a serving general packet radio service GPRS support node simulator connectable to a gateway GPRS support node for coupling the device to a service network. The device is connectable to a control computer for giving commands to the device. For testing packet-switched services, the device is connectable to a test computer, in which a user interface of a service is run on a given platform. A name server is connectable to the device, and a content server via the service network. The device is able to generate billing data records from traffic caused by the packet-switched service.

Abstract: Embodiments of the present invention are directed to the running of a virtual machine directly from a physical machine using snapshots of the physical machine. In one example, a computer system performs a method for running a virtual machine directly from a physical machine using snapshots of the physical machine. A snapshot component takes a snapshot of the physical system volume while the physical system volume is in an operational state. The virtual machine initializes using the physical system volume snapshot thereby allowing the physical system volume snapshot to be a virtual system volume snapshot representing an initial state of a virtual system volume. The physical system volume snapshot includes instances of all the files within the physical system volume at the time the snapshot was taken.

Abstract: A cache replacement system for extending the debugging capabilities of accelerated simulation by enabling enhanced cache data and state checking is provided. The system includes a Cell Broadband Engine Architecture (CBEA) compliant system implementing Replacement Management Tables in an accelerated simulation environment. The RMTs control cache replacement and allow the software to direct entries with specific address ranges at a particular subset of the cache. The RMTs further allow for locking data in the cache and are utilized to prevent overwriting data in the cache by directing data that is known to be used only once at a particular set. Using the locking mechanism in an accelerated simulation environment, a user is able to run code sets, which, when the microprocessor system being tested is correctly designed, generates identical and verifiable data and cache states in each of the different sets of the cache.

Abstract: A client-server semiconductor verification system is described. The system comprises a client device storing a test job having test vectors and configuration data for programmable logic for testing a design of a logic circuit. A server is coupled to the client device and receives the test job from the client device. Finally, a system under test coupled to the server and has programmable logic which is reconfigured. The system under test receives the test vectors and outputs result vectors to the client device by way of the server. Corresponding methods are also disclosed.

Abstract: Disclosed is a SCSI target device simulator consisting of a personal computer, a SCSI host adapter board, and simulator software. The SCSI target device simulator is employed to test SCSI host adapter systems by simulating multiple SCSI target devices for test purposes. The simulated SCSI target devices may be configured to imitate a wide variety of different SCSI target device types, with an equally wide variety of configuration settings within a single SCSI target device type. A user may quickly create and change simulated SCSI target devices for a test system. The SCSI target device simulator may also be configured so that the simulated SCSI target devices respond in a specified manner to SCSI commands and SCSI task management commands. Controlling the simulated SCSI target device responses to SCSI commands and SCSI task management commands allows a user to easily configure and test a SCSI host adapter device for specific operational scenarios.

Abstract: A method for determining polynomials to model circuit delay includes the step of determining one or more error areas in a characteristic map that exceed an error margin. Next, a current domain count is set to zero and selecting one error area of the one or more error areas is selected. A patch region that will contain the error area determined the patch region is then curve fitted and the current domain count is increased by one. The steps of repeating steps of selecting an error area, determine a patch, curve fitting within the patch, and increasing the domain count by one are repeated until there are no error area within the patch region.

Abstract: A verification environment is provided that co-verifies a software component 8 and a hardware component 10. Within the same environment using a common test controller 18 both hardware stimuli and software stimuli may be applied to their respective simulators. The response of both the software and the hardware to the simulation conducted can be monitored to check for proper operation.

Abstract: Embodiments of the present invention address deficiencies of the art in respect to pattern design and provide a novel and non-obvious method, system and computer program product for self-service creation and deployment of a pattern. In an embodiment of the invention, a method for creating a self-service reusable pattern can be provided. The method can include implementing an arrangement of re-usable assets into a set of self-service application components, extending at least one of self-service application components, and packaging the components for deployment in a target environment. The method further can include determining a target deployment environment and modeling the target environment to receive the deployment of the components. Thereafter, the packaged components can be deployed to a portal server or to a portal test environment.

Abstract: The invention relates to a system and a method for controlling jobs of a production device. The aim of the invention is to allow a current situation to be analyzed and the required operations to be planned, executed, and monitored irrespective of mathematical routines for optimizing the throughput. Said aim is achieved by the fact that a simulated image is formed starting from an initial situation based on real resources and real jobs, a potential sequence of jobs is optimized based on the initial situation regarding available resources and available jobs with the aid of an optimization algorithm, and the production device is controlled with the aid of a solution algorithm such that a target state is determined by simulating the required operations of the production device.

Abstract: A method and a system provide a reconfigurable platform for designing and emulating a user design. The method and system facilitates design and emulation of a system-on-a-chip type user design. The netlist of a user design may be included with netlists from customized or optimized third party circuits in an emulation using a platform including a number of field programmable devices. Various customized circuits for specific development activities, such as debugging, performance analysis, and simulator linkage may be configured to interact with the user design.

Abstract: Embodiments of the present invention include a system for accessing a memory device comprising a master device coupled to a first serial bus. The system further comprises a slave device coupled to a second serial bus wherein the slave device comprises a first memory. The system further includes a slave device simulator coupled to the first serial bus and coupled to a long distance system specific interconnection, wherein the slave device simulator comprises a first shadow memory of the first memory and wherein a master device simulator is coupled to the second serial bus and coupled to the system specific interconnection. The master device comprises a second shadow memory of the slave device. Data read operations of the master may be satisfied directly from the slave device simulator shadow memory. Data writes from the master are propagated to the slave device and data coherency routines update the shadow memories accordingly.

Abstract: A simulation system and A method for computer-implemented simulation and verification of a control system under development are provided, the simulation system having a host-target architecture. An operating system of the target representing at least a part of the control system is reconfigured by the host via a application programming interface dedicated to the operating system of the target.

Abstract: In this disclosure, based on change item definition information concerning system LSI development and design, software used for development and design of a system LSI that contains a processor having optional instructions defined therein is operated, and system LSI hardware description, verification environment and a development and design tools are generated, thus making it possible to develop a system LSI optimal to an application within a short period.

Abstract: A method, a system, and an apparatus for quantification of the quality of diagnostic software by applying a coverage tool are provided, wherein the diagnostic software is used for testing a computing system. The method involves executing the diagnostic software in an Integrated Circuit (IC) verification environment. The diagnostic software is executed by a Virtual Computer-processing Unit (V-CPU), which models (Central Processing Unit) CPU of the computing system to be tested.

Abstract: A hyperspectral imaging system is tested in the lab to allow a determination of its response to the emission from a simulated target, of certain wavelengths of radiation which the imaging system will be using during target determination. A broadband IR wavelength generator is used to generate a multiplicity of wavelengths representing the target and an emissions simulator is used to generate wavelengths representing target emission of hot gases. An AOTF is used to delete one or more target wavelengths, and to add one or more emission wavelengths, from and to the transmission path to the imaging system.

Abstract: An automated model componentization feature systematically converts duplicate or otherwise amenable patterns in a model into references. Multiple references are simplified to one unit that contains the otherwise duplicated functionality. Duplicated or selected functionality is identified based on a number of arguments that may be user supplied. These arguments include the level of polymorphism (i.e., which of the sample times, dimensions, and data types can be propagated in) but also the maximum size of the patterns to look for to address the general trade-off of generating few partitions with many blocks or many partitions with few blocks and which modeling constructs are used (e.g., whether Go To/From connections such as in Simulink® are present). Model conversions can result in potentially disjoint partitions.

Abstract: A laser scanning system can be used in construction projects to generate a field survey. An architect or engineer can use the field survey to create construction drawings. In addition, relevant points from the construction drawings can be identified at the construction site with the scanning system. Further, earth moving equipment can be controlled using the same information. The laser scanning system can be used to determine if two parts can be mated together by scanning and comparing the parts that are to be mated. The laser scanning system can further be used to determine if an object can be moved through an opening in a structure by comparing scan points of the structure with scan points from the object. The laser scanning system can be used to identify objects within the site, to build databases that have relevant information about the objects, and to guide reproducing machines.

Abstract: A storage medium is disclosed. The storage medium having stored on it a set of programming instructions defining a number of data objects and operations on the data objects for use by another set of programming instructions to enable the other set of programming instructions to be compilable into either a version suitable for use in a hardware/software co-simulation that effectively includes calls to hardware simulation functions that operate to generate bus cycles for a hardware simulator, or another version without the effective calls, but explicitly expressed instead, suitable for use on a targeted hardware.

Abstract: Estimates of a communication system configuration, such as a DSL system, are based on operational data collected from a network element management system, protocol, users and/or the like. The operational data collected from the system can include performance-characterizing operational data that typically is available in an ADSL system via element-management-system protocols. Generated estimates and/or approximations can be used in evaluating system performance and directly or indirectly dictating/requiring changes or recommending improvements in operation by transmitters and/or other parts of the communication system. Data and/or other information may be collected using “internal” means or may be obtained from system elements and components via email and/or other “external” means.

Abstract: A data-processing apparatus, method and program product generally includes a graphical user interface, which is provided to generate a simulation of one or more target devices based one or more user inputs to the graphical user interface. The simulation of the target device(s) can be automatically generated device based on the particular user input(s) to the graphical user interface. A topology of the target device(s) can then be compiled based on the simulation of the target device(s). Such a topology is utilized for testing of the target device(s). The simulation of the device(s) can also be utilized to modify the target device(s) on a per-device basis. A script of errors is also compiled for injection into the target device(s) for testing of the target device(s). The target device can be, for example, an SAS device, an SMP device and/or an SATA device.

Abstract: A method for displaying the results of predicted wireless communication system performance as a three-dimensional region of fluctuating elevation and/or color within a three-dimensional computer drawing database consisting of one or more multi-level buildings, terrain, flora, and additional static and dynamic obstacles (e.g., automobiles, people, filing cabinets, etc.). The method combines computerized organization, database fusion, and site-specific performance prediction models. The method enables a design engineer to visualize the performance of any wireless communication system as a three-dimensional region of fluctuating elevation, color, or other aesthetic characteristics with fully selectable display parameters, overlaid with the three-dimensional site-specific computer model for which the performance prediction was carried out.

Abstract: A method and apparatus for predicting the likelihood of an avatar under the control of a user in a virtual environment moving with a predetermined range of a boundary as disclosed in which the movement of the avatar in the virtual environment is monitored for a period of time, a model of avatar movement is determined using the monitor movement, and the likelihood of the avatar movement within the predetermined of a boundary is predicted using the model.

Abstract: Aspects of the subject matter described herein relate to simulating storage devices. In aspects, a test automation engine instructs a simulator to simulate a storage device having certain characteristics such as a storage area network. The test automation engine then tests an application against the simulated storage device. Tests may include storage management requests and storage access requests. A provider may translate a request to one or more operations suitable to perform the request on the underlying simulated device. Shadow copies and the results of other storage management-related operations may be shared across computers via aspects of a simulation framework described herein.

Abstract: A load simulator is used to apply access load on a web server device as a test target using a plurality of virtual web clients each of which transmits a request message and receives a response message in order according to a given scenario. The load simulator makes a computer function as search means for searching page data of a response message for predetermined character strings when a virtual web client receives the response message from the web server device through a communication device, source modifying means for overwriting the predetermined character string searched by the search means by replacing characters of a part of the string to disable a function provided by the original character string, and output means for passing the page data that is overwritten by the source modifying means to the viewer.

Abstract: The invention provides a method and system for switching in networks responsive to message flow patterns. A message “flow” is defined to comprise a set of packets to be transmitted between a particular source and a particular destination. When routers in a network identify a new message flow, they determine the proper processing for packets in that message flow and cache that information for that message flow. Thereafter, when routers in a network identify a packet which is part of that message flow, they process that packet according to the proper processing for packets in that message flow. The proper processing may include a determination of a destination port for routing those packets and a determination of whether access control permits routing those packets to their indicated destination.

Abstract: A method for visualizing and efficiently making comparisons of communication system performance utilizing predicted performance, measured performance, or other performance data sets is described. A system permits visualizing the comparisons of system performance data in three-dimensions using fluctuating elevation, shape, and/or color within a three-dimensional computer drawing database consisting of one or more multi-level buildings, terrain, flora, and additional static and dynamic obstacles (e.g., automobiles, people, filing cabinets, etc.). The method enables a design engineer to visually compare the performance of wireless communication systems as a three-dimensional region of fluctuating elevation, color, or other aesthetic characteristics with fully selectable display parameters, overlaid with the three-dimensional site-specific computer model for which the design was carried out.

Abstract: An open system for multiple discrete, geographically disperse simulation engines to communicate with each other across a distributed electronic network, such as the Internet, comprises a portal accessible to the simulation engines over the network. Local portions of the simulation may be run separately by each simulation engine, and the output data files are stored on and managed by the portal. A co-simulating engine may request an output data file stored by the portal and use that data as input for its downstream portion of the simulation. In this fashion, multiple geographically disperse simulation engines can test bench their designs in an open, network centric simulation environment.

Abstract: An electronic device and method are provided to enable simulation of a system while minimizing a requirement to reanalyze or recompile topology information during subsequent simulations of the system. Instructions representative of compiling a topology of the system and at least one relationship among a plurality of parameters of the system may be obtained. The instructions, including reading a data structure containing the plurality of parameters to create an intermediate representation representative of the system and the plurality of parameters may be executed. In some implementations, time and effort required to perform system simulations can be reduced, even when parameters that represent the system are changed during each execution of the simulation.

Abstract: A method for routing a message from a source node to a destination node, where the source node and the destination node are connected by a plurality of nodes in a cycle-based system, is disclosed. The method includes generating a maze data structure including the plurality of nodes, where each of the plurality of nodes is associated with a dimension corresponding to time, and routing the message from the source node to the destination node using the dimension corresponding to time.

Abstract: A method for generating a simulated network using a graphical user interface (GUI). A network topology generated at a GUI by a user is received, wherein the network topology includes a plurality of devices and at least one connection between devices. A build file describing the network based on the network topology is automatically generated. A user is able to create and edit a simulated network through the GUI, thereby obviating the need for manually coding a simulated network. Large simulated networks can be quickly created, edited and maintained.

Abstract: A method for modeling digital signal processors (DSP) in a C++ environment is disclosed. In particular, the method models and converts an operation (or function) from a floating-point model to a given DSP fixed-point processor model. The invention defines a vector space for each DSP fixed-point processor, as a direct sum of each distinct fixed bit length data representation sub-space. The direct sum of all DSP fixed-point processor vector sub-spaces forms a working vector space. Furthermore, the invention defines an operator projection to be performed on the working vector space such that redundancy in the operational behavior of the DSP's to be modeled may be exploited. In the preferred embodiment, the working vector space is in a C++ environment. A C++ class is defined for each distinct fixed bit length data representation of a given DSP fixed-point processor. The behavior of the given DSP fixed-point processor is then modeled in a C++ environment using the library of classes.

Abstract: A method for emulating a processor of a first endian type on a processor of a second endian type, wherein each memory access address B of string length L is transformed to the address A?B?L+S, wherein A is the total number of bytes allocated to a program, and S is the start address of the program.

Abstract: A remote control system includes: an electric home terminal device 11 having a control program; a server PC 12, for transmitting control data to the electric home terminal device 11 and for registering three-dimensional model data concerning the electric home terminal device 11; and client PCs 14, 15 and 16, for receiving the three-dimensional model data from the server PC 12, wherein the client PCs 14, 15 and 16 perform an additional operation upon the receipt of specific three-dimensional model data from the server PC 12, and transmit, to the server PC 12, update data for a three-dimensional model obtained by the additional operation, and wherein the server PC 12 transmits, to the electric home terminal device 11, the control data based on the update data for a three-dimensional model received from the client PCs 14, 15 and 16.

Abstract: A method for identifying predictable data sharing locations includes generating a testcase thread of code, creating a list of data lines used by the generated testcase thread of code, and generating a list of predictable data sharing locations based on the data line list.

Abstract: Dynamic cosimulation is implemented using a cosimulation bridge for data exchange between a primary simulator and a secondary simulator, and a plurality of user selected optimization control signals defined over the cosimulation bridge. At least one user selected optimization control signal is identified for disabling the cosimulation bridge. The primary simulator and secondary simulator are dynamically disengaged for ending data exchange responsive to disabling the cosimulation bridge. Responsive to optimization control signal going inactive, the primary simulator and secondary simulator are dynamically re-engaged for data exchange. The optimization control signals include a single sided disable; a two independent disable; a functional OR disable; a functional AND disable, and suspend signals. The single sided disable and the two independent disable enable disabling one side of the cosimulation bridge and not the other side.

Abstract: An application program that describes processing of a workpiece by the machine tool in form of instruction steps is disclosed. A computer executes the application program and step-by-step determines based on a simulation program machine-dependent control commands for a controller. The machine-dependent control commands depend on a virtual time base that is independent of an actual time base. The computer determines based on a computer-internal model of the machine tool and the determined machine-dependent control commands expected actual states of the machine tool, thereby simulating execution of the machine-dependent control commands by the machine tool. The simulation program is implemented as control software in the controller.

Abstract: A component, system and method for simulation of a PCI device's memory-mapped I/O register(s) are provided. The PCI simulation component has an initialization component, a configuration space simulator and a memory-mapped I/O space simulator. The initialization component can claim an amount of memory by modifying the amount of memory that an operating system has available to it. The initialization component further identifies to the operating system that at least some of the claimed memory resides on a PCI bus. The configuration space simulator causes the operating system to accept that the simulated PCI device is present in the system. The memory-mapped I/O space simulator simulates device and can comprise can comprise a thread that monitors the simulated memory-mapped I/O registers for a change in order to simulate behavior of the simulated PCI device.

Abstract: Method and apparatus for simulating operations of a circuit design that includes high-level components and HDL components. Groups of HDL components are associated with different co-simulation engines. The high-level components of the design are simulated in a high-level modeling system (HLMS), and the HDL components in each group are simulated on the associated co-simulation engine.

Abstract: The present invention provides methods for determining the level of protein activity in a cell by: (i) measuring abundances of cellular constituents in a cell in which the activity of a specific protein is to be determined so that a diagnostic profile is thus obtained; (ii) measuring abundances of cellular constituents that occur in a cell in response to perturbations in the activity of said protein to obtain response profiles and interpolating said response profiles to generate response curves; and (iii) determining a protein activity level at which the response profile extracted from the response curves best fits the measured diagnostic profile, according to some objective measure. In alternative embodiments, the present invention also provides methods for identifying individuals having genetic mutations or polymorphisms that disrupt protein activity, and methods for identifying drug activity in vivo by determining the activity levels of proteins which interact with said drugs.

Abstract: A method for verification includes providing an implementation model, which defines model states of a target system and model transitions between the model states, and providing a specification of the target system, including properties that the system is expected to obey. A tableau is created from the specification, the tableau defining tableau states with tableau transitions between the tableau states in accordance with the properties. The tableau transitions are compared to the model transitions to determine whether a discrepancy exists therebetween.

Abstract: Method and system for creating an electronic circuit design from a system-level environment. A plurality of user-selectable system-level design objects are provided in the system-level environment. Each system-level design object is defined by a system-level function and is selectable by a system-level designer. A plurality of hardware-level design objects are also provided. Each hardware-level design object is configured to generate a hardware definition of a hardware-level function. Each system-level design object maps to one or more hardware-level design objects. In response to selections made by the designer, a system-level design is instantiated in a system-level design file. The system-level design includes user-selected ones of the system-level design objects.

Abstract: A functional block for verifying correct interface operation of any functional block is generated from interface description and installed on a LSI chip. To accomplish this, from the interface description, hardware description of a synthesizable interface checker is generated. Means for selecting interface functions to be checked is provided, thereby making it possible to reduce the overhead of circuits to be installed on the LSI.

Abstract: In a predictive action determination apparatus (10), a state observation section (12) observes a state with respect to an environment (11) and obtains state data s(t). An environment prediction section (13) predicts, based on the state data s(t), a future state change in the environment. A target state determination section (15) determines, as a target state, a future state suitable for action determination with reference to a state value storage section (14). A prediction-based action determination section (16) determines an action based on a determined target state.

Abstract: A program product for use in generating test benches for verifying test structures embedded in a circuit, comprises a verification specification processor for parsing a verification specification containing test specifications for selected test structures and a test bench generator for each of one or more types of embedded test structures, each test bench generator being operable to process a test structure specification of a test structure of a corresponding test structure type and generate a test bench using data contained in said test specifications of said verification specification, data contained in said test structure specification and data contained in a test connection specification.

Abstract: A method for exposing the internal signals of a system model or software model of a dynamic system to a client application outside the original modeling environment is provided. A designer of the system model is provided with a way to select internal signals of the system model in order to expose those internal signals to other computer applications external to the modeling environment. Such computer applications are then able to access the internal signals by way of interfacing software while the system model is being exercised within the modeling environment, or while a software model based on the system model is executed outside of that environment.