Simulating Electronic Device Or Electrical System Patents (Class 703/13)
  • Patent number: 10691517
    Abstract: In one example in accordance with the present disclosure, a method for determining operating frequencies includes receiving a warranty period for a computer component. The method includes determining an operating frequency that will cause a predicted life cycle of the computer component operating at the operating frequency to fall within the warranty period. The method includes setting the computer component to operate at the operating frequency.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: June 23, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Vincent Nguyen, Robert E Van Cleve, Kevin G Depew, Scott P Faasse
  • Patent number: 10684936
    Abstract: Systems and methods validate the operation of a component of an executable model without inadvertently altering the behavior of the component. The model may be partitioned into a design space and a verification space. The component may be placed in the design space, while an observer for validating the component may be placed in the verification space, and linked to the component. During execution of the model, input or output values for the component may be computed and buffered. Execution of the observer may follow execution of the component. The input or output values may be read out of the buffer, and utilized during execution of validation functionality defined for the observer. Model compilation operations that may inadvertently alter the behavior of the component, such as back propagation of attributes, are blocked between the observer and the component.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: June 16, 2020
    Assignee: The MathWorks, Inc.
    Inventors: Mahesh Nanjundappa, S. M. Shahed Nejhum, Vijaya Raghavan, Krishna Balasubramanian, John P. Dirner
  • Patent number: 10685147
    Abstract: Areas of non-conformances in a manufactured object are electronically mapped within a coordinate system of the object. Boundary lines of the areas containing the non-conformances are displayed on a 3-D image of the product. Visualization of the boundary lines of areas containing multiple non-conformances allows tracking of non-conformances, identification of trends in non-conformances and correction of production processes in order to reduce non-conformances.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: June 16, 2020
    Assignee: The Boeing Company
    Inventors: Brian N. Slack, Thomas Alexander Brown, Jennifer Diane MacKay, Guy Stockie, Yanxin Emily Wang, Lori Lynne Woodbury
  • Patent number: 10685148
    Abstract: Disclosed aspects relate to managing a set of spatial zones associated with an architectural layout. A first spatial zone of the set of spatial zones is detected. The first spatial zone has a first spatial zone size value. By comparing the first spatial zone size value with a threshold spatial zone size value, it is determined to convert the first spatial zone. Based on proximity, a group of conversion candidates is identified from the set of spatial zones. Based on the first spatial zone and the group of conversion candidates, a second spatial zone is determined using an architectural criterion. Using the second spatial zone, a design-model of the architectural layout is established.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: June 16, 2020
    Assignee: MITEK HOLDINGS, INC.
    Inventors: William A. Wright, Michael G. Shnitman
  • Patent number: 10679228
    Abstract: Provided herein are methodologies, systems, and devices for simulating the performance of products a within a display area of a retail store. Data relating to a product's attributes, location within a display area, and historical performance can be used to create a model that can predict the impact on sales that will result from moving particular items from one location in a display area to another location. Once created, this model can predict a product's performance at various locations and assist in optimizing product placement within a display area. A GUI of an electronic device can display a virtual display area that allows a user to create various product placement scenarios. The model may also display product placement recommendations based on the predicted performance values of various products at different locations within a display area.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: June 9, 2020
    Assignee: Walmart Apollo, LLC
    Inventor: Murthy Narayana Kolluru
  • Patent number: 10678989
    Abstract: A method for timing optimization is disclosed. The method includes obtaining information on timing of paths in a chip, wherein the information includes a mean of slacks and a sigma of slacks of each of the paths, determining a sigma margin (SM) value each of the paths, the SM value being obtained by dividing the mean by the sigma, and determining that a first path of the paths is more critical than a second path of the paths, an SM value of the first path being smaller than that of the second path.
    Type: Grant
    Filed: January 18, 2018
    Date of Patent: June 9, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yen-Pin Chen, Tzu-Hen Lin, Tai-Yu Cheng, Florentin Dartu, Chung-Hsing Wang
  • Patent number: 10679735
    Abstract: Improved computer-implemented tools for use in modeling/simulating spatial charge distributions for electrophysiological systems are provided. The improvements are in three areas: (1) the use of solid angles to calculate quantities of free charge and/or bound charge in calculation cells and/or the movement of quantities of free charge across one or more faces of a calculation cell; (2) the use of flattened calculations cells having only two faces with substantial areas as seen from the free charge and/or the bound charge of the electrophysiological system; and (3) the use of at least two spatial charge distributions, specifically, at least one for bound charge and at least one for free charge, so as to include the effects of relative dielectric constants greater than 1.0 for part or all of an electrophysiological system. The three improvements can be used individually or in combinations.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: June 9, 2020
    Inventor: Maurice M. Klee
  • Patent number: 10678673
    Abstract: According to an aspect of an embodiment, a method may include executing multiple tests with respect to code under test of a software program to perform multiple test executions. The method may further include identifying one or more passing tests and one or more failing tests of the test executions. In addition, the method may include determining an aggregated score for each statement based on two or more of: the passing tests and the failing tests; a semantic similarity between one or more statement tokens included in the respective statement and one or more report tokens included in an error report; and an amount of time that has passed from when the respective statement received a change. Moreover, the method may include identifying a particular statement of the plurality of statements as a fault location in the code under test based on the aggregated scores of the plurality of statements.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: June 9, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Ripon K. Saha, Mukul R. Prasad
  • Patent number: 10671785
    Abstract: Simulating a hardware description language design including a core and a testbench can include performing, using a processor, a first compilation of the hardware description language design by generating a compiled core unit for the core, a compiled testbench for the testbench, and synchronization data describing signals crossing a compile checkpoint boundary. A subsequent compilation of the hardware description language design can be performed by reusing the compiled core unit from the first compilation and generating a new compiled testbench for the testbench using the synchronization data.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: June 2, 2020
    Assignee: Xilinx, Inc.
    Inventors: Valeria Mihalache, Kumar Deepak, Saikat Bandyopadhyay, Sandeep S. Deshpande, Feng Cai
  • Patent number: 10656528
    Abstract: In the embodiments disclosed herein, an approach based on a mask function M is disclosed. This approach meets the requirement of the Hopkins model and at the same time incorporates the incident angle effects of a given partially coherent illumination. The new mask function M is referred to as a partially coherent mask function (PCMF). In the embodiments disclosed herein, the incident angle effects of individual source points of a given partially coherent illumination are removed from the mask function M and incorporated into a source function G. As a result, use of the partially coherent mask function M does not require an integration over individual plane waves in the illumination, as would be the case with a rigorous mask function M. Therefore, the Hopkins model can be used with partially coherent mask function M and at the same time capture the incident angle effects.
    Type: Grant
    Filed: January 2, 2019
    Date of Patent: May 19, 2020
    Assignee: Synopsys, Inc.
    Inventor: Peng Liu
  • Patent number: 10649887
    Abstract: An apparatus, a computer program product and a method for co-verification of systems comprising software and hardware components. The method comprises obtaining an over-approximation of the system that over-approximates the software or the hardware by using a non-deterministic version thereof; performing simulation of the over-approximation of the system; and utilizing an outcome of the simulation to guide a co-simulation of the system. The co-simulation comprises instrumenting the software to identify whether the coverage goals are reached during execution, generating a test input for the system, simulating execution of the test input by the instrumented software, wherein during said simulating, stimuli provided from the instrumented software to underlying hardware is provided to a hardware simulator that is configured to simulate the hardware-under-test; determining a coverage of the execution of the test input, and utilizing the coverage information in a successive iteration of the method.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: May 12, 2020
    Assignee: International Business Machines Corporation
    Inventors: Fady Copty, Dov Murik, Sharon Keidar Barner
  • Patent number: 10650125
    Abstract: An electronic apparatus operated based on an OS is provided. The electronic apparatus includes a storage to store the OS, a virtual device program capable of generating a virtual device executed based on the OS, and at least one program; and at least one processor to execute the virtual device program to generate the virtual device, and to execute the OS to determine whether a first program having an administration authority assigned by the OS from among the at least one program has access authority to data about the virtual device in response to an attempt to access the data from the first program and to selectively permit the access to the data based on the determined access authority. With this, the electronic apparatus may restrain the access to the virtual device or the data thereabout according to a presence of the access authority, thereby safely protecting the virtual device or the data.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: May 12, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-hwa Jeong, Sung-kyu Lee, Hyun-cheol Park, Chang-woo Lee
  • Patent number: 10650174
    Abstract: The present disclosure relates to a system and method for use in an electronic design environment. Embodiments may include receiving, using at least one processor, an electronic design and generating a unique name for each hardware state element associated with the electronic design. Embodiments may further include generating a unique name for each software state element associated with the electronic design. Embodiments may also include combining a plurality of unique names into an arbitrary expression, wherein the plurality of unique names includes at least one software state unique name and at least one hardware state unique name. Embodiments may further include evaluating the arbitrary expression at one or more discrete time points. Embodiments may also include recording an evaluated expression in an electronic design database.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: May 12, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Andrew Robert Wilmot, Rohan Kangralkar, George Franklin Frazier, Neeti Khullar Bhatnagar
  • Patent number: 10643284
    Abstract: The present disclosure is directed to methods for providing insurance brokerage services for both a property owner and potential insurers. The methods provides for virtual websites and related mobile applications for estimating the value of a property based on current reconstruction costs. The methods also provide for aiding a property owner in procuring an insurer by compiling property valuation information in a format that is submitted to potential insurers to bid upon. The methods further provides for helping property owners manage changes to property value and updating insurance policy based on valuation changes to reconstruction costs as well as compiling information for reconstruction costs when damage does occur. Finally, disclosure provides for methods of maintaining important records for insurer, maintaining communications between insured and insurer, and providing emergency services related to the insured property in the time of emergencies related to the insured property.
    Type: Grant
    Filed: March 6, 2015
    Date of Patent: May 5, 2020
    Inventor: Christopher Rogers
  • Patent number: 10639547
    Abstract: A method of networked simulation during a multiplayer game for a server includes: simulating at the server at least a first interactive object of a virtual environment, detecting whether a user of a first client may interact with the first interactive object within the virtual environment, and if so, setting the server to a co-operative simulation mode in which the server is arranged to receive data corresponding to an outcome of a simulation by the first client of an interaction between the first interactive object and an avatar of the user; receiving data from the first client corresponding to the outcome of the simulation by the first client of the interaction between the first interactive object and the avatar of the user, and updating the server simulation of the first interactive object responsive to the received data.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: May 5, 2020
    Assignee: Sony Interactive Entertainment Inc.
    Inventor: Michael John Atkins
  • Patent number: 10634778
    Abstract: Camera-assisted tracking of point objects in a radar system is provided. An extended Kalman filter framework based on both radar and camera observations is used to track point objects detected in frames of radar signal data. This framework provides a minimum mean square estimation of the current state of a point object based on previous and current observations from both frames of radar signals and corresponding camera images.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: April 28, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Yucheng Liu, Vikram VijayanBabu Appia, Muhammad Zubair Ikram
  • Patent number: 10635765
    Abstract: Clusters of metrics in a system are stored. A display region is divided into n divided regions in such a way that an area of a divided region i (1?i?n) is equal to or larger than an area of a divided region i+1. Each cluster is allocated to the divided region i sequentially selected from i=1, in the decreasing order of the number of metrics contained in each of the clusters, in such a way that the number of the clusters allocated to the divided region i+1 is equal to or more than the number of clusters allocated to the divided region i. The cluster allocated to the divided region i is drawn in the divided region i.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: April 28, 2020
    Assignee: NEC CORPORATION
    Inventor: Masanao Natsumeda
  • Patent number: 10635577
    Abstract: A computer-implemented method may include: receiving a request to integrate a commit; obtaining analytics data of an author that developed the commit; executing a simulation using the analytics data of the author as inputs to the simulation; obtaining results from the simulation, wherein the results indicate error rates when one or more testing stages are omitted from a testing procedure of the commit; comparing the results of the simulation with a threshold; determining, by the computing the device, the testing procedure based on the comparing, wherein the testing procedure identifies the one or more testing stages that are omitted and one or more testing stages that are included in the testing procedure; and outputting information regarding the determined testing procedure, wherein the outputting causes an integration server to test the commit in accordance with the testing procedure as part of an integration process for integrating the commit to a project.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: April 28, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Aaron K. Baughman, Cameron McAvoy, Brian M. O'Connell
  • Patent number: 10635766
    Abstract: In a data processing system, a processor creating level qualifying logic within instrumentation of a hardware description language (HDL) simulation model of a design. The level qualifying logic is configured to generate a first event of a first type for a first simulation level and to generate a second event of second type for a second simulation level. The processor simulates the design utilizing the HDL simulation model, where the simulation includes generating the first event of the first type responsive to the simulating being performed at the first simulation level and generating the second event of the second type responsive to the simulating being performed at the second simulation level. Responsive to the simulating, the processor records, within data storage, at least one occurrence of an event from a set including the first event and the second event.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: April 28, 2020
    Assignee: International Business Machines Corporation
    Inventors: Guy L. Guthrie, Hugh Shen, Derek E. Williams
  • Patent number: 10630643
    Abstract: In some embodiments, a protected client operates a live introspection engine and an on-demand introspection engine. The live introspection engine detects the occurrence of certain events within a protected virtual machine exposed on the respective client system, and communicates the occurrence to a remote security server. In turn, the server may request a forensic analysis of the event from the client system, by indicating a forensic tool to be executed by the client. Forensic tools may be stored in a central repository accessible to the client. In response to receiving the analysis request, the on-demand introspection engine may retrieve and execute the forensic tool, and communicate a result of the forensic analysis to the security server. The server may use the information to determine whether the respective client is under attack by malicious software or an intruder.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: April 21, 2020
    Assignee: Bitdefender IPR Management Ltd.
    Inventors: Dan H. Lutas, Daniel I. Ticle, Radu I. Ciocas, Sandor Lukacs, Ionel C. Anichitei
  • Patent number: 10621386
    Abstract: A method, a system and a non-transitory machine-readable storage medium are provided. In one or more aspects, a computer-implemented method for bias temperature instability (BTI) calculation of a device includes simulating the device, using an electronic design automation tool. The simulation includes determining a first degradation value after applying a first sequence of stress values to the device for a first plurality of time steps. The simulation further includes determining a first degradation recovery value after the first plurality of time steps. The simulation further includes determining a first recovered degradation value after the first plurality of time steps by combining the first degradation value and the first degradation recovery value. The first degradation value, the first degradation recovery value, and the first recovered degradation value are associated with one or more model parameters of the device.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: April 14, 2020
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Alvin Chen, Jushan Xie, Si-Yu Liao, Chunyi Huang, Tianlei Guo, Yanhui Li, Runsheng Wang, Shaofeng Guo, Zhuoqing Yu, Ru Huang
  • Patent number: 10622932
    Abstract: A method for emulating a three-phase, brushless DC motor using a load emulator that is connected in a three-phase manner via load terminals to supply terminals of a motor control unit. The load emulator has emulator power electronics and an emulator control unit for controlling the emulator power electronics. The emulator control unit determines the supply terminals that are actuated by the motor control unit and the supply terminals that are not actuated, and the emulator power electronics are actuated by the emulator control unit in such a way that phase currents calculated by the emulator control unit on the basis of a motor model flow in the supply terminals that are actuated by the motor control unit and a phase voltage calculated by the emulator control unit on the basis of a motor model is applied to the supply terminal that is not actuated by the motor control unit.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: April 14, 2020
    Assignee: dSPACE digital signal processing and control engineering GmbH
    Inventor: Nils Holthaus
  • Patent number: 10614192
    Abstract: A method and apparatus for ranking combinations of mutants, test cases and random seeds in mutation testing, comprising obtaining, based on a signal of a test case target, logic gates related to the signal of the test case target and mutants on the related logic gates, for a compiled integrated circuit under test; calculating distances between the mutants and the signal of the test case target; performing a circuit simulation on the compiled integrated circuit under test to obtain activation cycle numbers corresponding to combinations of the mutants, test cases and random seeds; obtaining activation cycle number variances corresponding to combinations of the mutants and the test cases; and ranking the combinations of the mutants, the test cases and the random seeds based on the distances, the activation cycle numbers and the activation cycle number variances. The invention can reduce the probability that the mutation simulation selects equivalent mutants.
    Type: Grant
    Filed: January 18, 2018
    Date of Patent: April 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Peng Fei Gou, Bodo Hoppe, Yang Li, Dan Liu, Yang Liu
  • Patent number: 10614193
    Abstract: This application discloses a design verification tool implementing in a functional verification environment with a computing system, a hardware emulator, or a combination thereof. The design verification tool can identify, from a power intent specification of a circuit design, operational states of circuitry described in the circuit design, and generate code coverage bins based on the operational states of the circuitry. The operational states of the circuitry correspond to operational capabilities of the circuitry supported by each of the power modes for the circuitry. The code coverage bins are configured to store code coverage events occurring when the circuitry operates in different power modes. The design verification tool can utilize the code coverage bins to record the code coverage events performed by the circuitry during functional verification operations in a verification environment, and also can generate at least one coverage metric based on the records of the code coverage events.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: April 7, 2020
    Assignee: Mentor Graphics Corporation
    Inventors: Pankaj Kumar Dwivedi, Shweta Gulati
  • Patent number: 10609034
    Abstract: Case management systems and techniques are disclosed. In various embodiments, a hierarchical permission model is received, comprising for each of at least a subset of case nodes comprising a hierarchical data model associated with a case model a corresponding set of case roles to be afforded permissions with respect to that case node and for each such case role a set of permissions to be associated with that case role with respect to that case node. The hierarchical permission model is used to enforce with respect to one or more case instances associated with the case model the permissions defined in the hierarchical permission model.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: March 31, 2020
    Assignee: Open Text Corporation
    Inventors: Satyapal P. Reddy, Jeroen van Rotterdam, Muthukumarappa Jayakumar, Michael T. Mohen, Ravikumar Meenakshisundaram
  • Patent number: 10607117
    Abstract: The invention provides a method for recognition of information in digital image data, said method comprising a learning phase on a data set of example digital images having known information, and characteristics of categories are computed automatically from each example digital image and compared to its known category, said method comprises training a convolutional neural network comprising network parameters using said data set, in which via deep learning each layer of said convolutional neural network is represented by a linear decomposition of all filters as learned in each layer into basis functions.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: March 31, 2020
    Assignee: KEPLER VISION TECHNOLOGIES B.V.
    Inventors: Jorn-Henrik Jacobsen, Johannes Christianus Van Gemert, Reinier Van Den Boomgaard, Zhongyu Lou, Arnoldus Wilhelmus Maria Smeulders
  • Patent number: 10599799
    Abstract: Computer-implemented systems and methods for modeling low-dropout (LDO) regulators and charge pumps are provided. A relationship between an output voltage of an LDO regulator or charge pump and a loading condition is determined. A frequency-domain analysis is performed at multiple frequencies to determine an impedance function representative of an impedance of the LDO regulator or charge pump at each of the multiple frequencies. A vector-fitting algorithm is applied to approximate the impedance function using a plurality of poles and residues. A circuit is synthesized based on the plurality of poles and residues. A model for the LDO regulator or charge pump is generated, where the model includes the synthesized circuit and components that model the relationship between the output voltage and the loading condition.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: March 24, 2020
    Assignee: ANSYS, Inc.
    Inventors: Deqi Zhu, Yi Cao, Shan Wan, Norman Chang
  • Patent number: 10598730
    Abstract: A testing method is performed by at least one processor and includes following operations: converting first data associated with a scan test into a program, in which the program is configured to observe an untested part of a circuitry that is unable to be tested in the scan test; performing circuit simulations with the program according to a netlist file indicating the circuitry and testing patterns, in order to rank the testing patterns to generate second data; selecting at least one candidate testing pattern from the testing patterns according to the second data; and performing at least one fault simulation on the circuitry according to the netlist file and the at least one candidate testing pattern, in order to test the circuitry.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: March 24, 2020
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chihtung Chen, Yi-Te Yeh, Chia-Hsien Cheng, I-Chang Wu, Huai-Yu Yen
  • Patent number: 10600007
    Abstract: A method and system to perform spatio-temporal prediction are described. The method includes obtaining, based on communication with one or more sources, multi-scale spatial datasets, each of the multi-scale spatial datasets providing a type of information at a corresponding granularity, at least two of the multi-scale spatial datasets providing at least two types of information at different corresponding granularities. The method also includes generating new features for each of the multi-scale spatial datasets, the new features being based on features of each of the multi-scale spatial datasets and spatial relationships between and within the multi-scale spatial datasets. The method further includes selecting, using the processor, features of interest from among the new features, training a predictive model based on the features of interest, and predicting an event based on the predictive model.
    Type: Grant
    Filed: August 4, 2014
    Date of Patent: March 24, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Wei Shan Dong, Arun Hampapur, Hongfei Li, Li Li, Xuan Liu, Chun Yang Ma, Songhua Xing
  • Patent number: 10579508
    Abstract: A mechanism for interacting with code such as software code is provided, whereby the code is represented as a graph such as a finite state machine corresponding to the code, such that a user may define a path through the code for example by way of a gesture or cursor movement, and the representation of the graph being restructured to give prominence to the nodes belonging to the defined path, and their sequence as defined in the path. The underlying code associated with each node may be presented with each corresponding node, so that the code of the nodes in the path is aligned, and can be read through as a continuous text. Amendments made to the code as presented can be reintegrated, and the representation adjusted as necessary.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: March 3, 2020
    Assignee: ECOLE NATIONALE DE L'AVIATION CIVILE
    Inventor: Stéphane Conversy
  • Patent number: 10579761
    Abstract: A method for reconstructing a graph representation of a previously executed verification test, may include obtaining a truncated chronicle of start time and end time messages of actions of the verification test that were logged during execution of the verification test on a design under test (DUT); using a processor, parsing and analyzing the start time and the end time messages to determine an order of the actions; using a processor, determining an order of other actions of said verification test, based on a graph representation of a verified scenario from which the verification test was generated; and reconstructing the graph representation of the verification test based on the determined order of the actions and order of the other actions.
    Type: Grant
    Filed: December 25, 2018
    Date of Patent: March 3, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Meir Ovadia, Talia Leah Orztizer
  • Patent number: 10572540
    Abstract: A method, system and computer-usable medium are disclosed for using travel-related cognitive graph vectors.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: February 25, 2020
    Assignee: REALPAGE INC.
    Inventors: Kyle W. Kothe, Scott E. Goldberg, John N. Faith
  • Patent number: 10565541
    Abstract: A method and computer system executes a home loss prevention simulation to provide a user with information on home loss prevention. The method and system may allow the user to select and place one or more home sensors on items and/or in locations within a simulated home environment. Once the user has finished selecting and placing the home sensors in the simulated home, the method and system may begin the home loss prevention simulation by applying different loss-related simulation scenarios to the simulated home. Based the different loss-related scenarios, the method and system may evaluate the placement of the home sensors in the simulated home to determine one or more losses (e.g., fire, water or burglary) and any associated financial costs. At the end of the simulation, the method and system may provide instructional information regarding the simulation results in order to educate the user on how to improve or optimize home loss prevention.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: February 18, 2020
    Assignee: STATE FARM MUTUAL AUTOMOBILE INSURANCE COMPANY
    Inventors: Kevin William Payne, Duane Lee Marzinzik
  • Patent number: 10552184
    Abstract: Examples of techniques for emulating an application-specific integrated circuit (ASIC) array using a field programmable gate array (FPGA) are disclosed. In one example implementation according to aspects of the present disclosure, a method may include loading configuration information to the FPGA, wherein the configuration information is representative of configuration information of the ASIC. The method may further include emulating the ASIC using the FPGA loaded with the configuration information by applying a fast emulation clock signal to the FPGA. The fast emulation clock signal is a multiple of a system clock signal.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: February 4, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael J. Becht, Raymond Wong
  • Patent number: 10546724
    Abstract: A radio frequency power system includes a master RF generator and an auxiliary RF generator, wherein each generator outputs a respective RF signal. The master RF generator also outputs a RF control signal to the auxiliary RF generator, and the RF signal output by the auxiliary RF generator varies in accordance with the RF control signal. The auxiliary RF generator receives sense signals indicative of an electrical characteristic of the respective RF signals output by the master RF generator and the auxiliary RF generator. The auxiliary RF generator determines a phase difference between the RF signals. The sensed electrical characteristics and the phase are used independently or cooperatively to control the phase and amplitude of the RF signal output by the auxiliary RF generator. The auxiliary generator includes an inductive clamp circuit that returns energy reflected energy back from a coupling network to a variable resistive load.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: January 28, 2020
    Assignee: MKS Instruments, Inc.
    Inventors: Aaron T. Radomski, Ky Luu, Larry J. Fisk, II, Ross Reinhardt, Matthew G. Harrington, Amish Rughoonundon, Jesse N. Klein, Aaron M. Burry
  • Patent number: 10540462
    Abstract: A method includes providing a register transfer level (RTL) description of a circuit design, providing a plurality of RTL-to-gate-level mapping details by translating the RTL description into a gate-level netlist, providing one or more input/output (I/O) variables as stimulus to simulate the RTL description of the circuit design, capturing a plurality of internal operation values from the simulated RTL description at a beginning time of a specified period of time wherein the specified period of time is less than a time period required to compete a full-scale simulation, mapping the captured internal operation values to corresponding gate-level nodes of the gate-level netlist, capturing a plurality of I/O values from the I/O variables at the beginning time of the specified period of time, and simulating the circuit design in a gate-level for the specified period of time based on the mapped internal operation values and the captured I/O values.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: January 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Yuan Stephen Yu, Wenyuan Lee, Boh-Yi Huang, Brent Lui, Tze-Chiang Huang
  • Patent number: 10534079
    Abstract: A vehicle includes a Radar sensor configured to output Radar dot data with respect to an obstacle, a Lidar sensor configured to output Lidar dot data with respect to the obstacle, and a controller configured to match the Radar dot data to the Lidar dot data. The controller clusters one or more Lidar dots of the Lidar dot data, and clusters one or more Radar dots of the Radar dot data based on a distance between a cluster of Lidar dots and the one or more Radar dots.
    Type: Grant
    Filed: July 18, 2016
    Date of Patent: January 14, 2020
    Assignee: Hyundai Motor Company
    Inventor: Byoungkwang Kim
  • Patent number: 10534897
    Abstract: Method for processing data, in which a Petri net is encoded, written into a memory and read and executed by at least one instance, wherein transitions of the Petri net read from at least one tape and/or write on at least one tape symbols or symbol strings, with the aid of at least one head. [FIG. 1]. In an alternative, data-processing, co-operating nets are composed, the composition result is encoded, written into a memory and read and executed from the memory by at least one instance. In doing this, components can have cryptological functions. The data-processing nets can receive and process second data from a cryptological function which is executed in a protected manner. The invention enables processing of data which prevents semantic analysis of laid-open, possibly few processing steps and which can produce a linkage of the processing steps with a hardware which is difficult to isolate.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: January 14, 2020
    Assignee: Whitecryption Corporation
    Inventor: Wulf Harder
  • Patent number: 10516579
    Abstract: Techniques are disclosed herein for reconciling planned data for a network (such as a fiber optic network) with data describing the deployed network. Network probing and planning components obtain a snapshot of the deployed network and organize the snapshot into three “layers”: the “link layer,” which represents the physical links that underlie the network, the “digital layer,” which includes optical channel groups that divide the total capacity of the physical links, and the “service layer,” which includes the services delivered over the network. The techniques involve comparing the planned data to the deployed data in the order of link layer, digital layer, and service layer. Differences considered to be “minor” are reconciled automatically. Differences that are “major” are reconciled after receiving instructions from a planner or administrator regarding whether to update the planned data based on what was originally in the planned data or what is in the deployed network.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: December 24, 2019
    Assignee: Infinera Corporation
    Inventors: Jayaram Hanumanthappa, Naresh Kumar, Naresh Srinivasulu Jayam, Arijit Mandal, Gounda Mohammed Nabi Saheb, Alok Jain, Steven Joseph Hand
  • Patent number: 10509866
    Abstract: An apparatus includes a memory; and a processor coupled to the memory and configured to: specify a shape type of an opening including a series of planes detected from planes of a plurality of second virtual rectangular parallelepipeds obtained by dividing a first virtual rectangular parallelepiped internally containing a virtual object in a simulated space based on a first shape of a first line obtained by projecting the series of planes from a direction based on a specific plane of the first virtual rectangular parallelepiped onto a projection plane which is perpendicular to the direction and located at a position more distant from the specific plane than the series of planes, calculate a resonance frequency of a wave leaking through the opening, based on the specified shape type of the opening; and present the calculated resonance frequency on a display.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: December 17, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Koji Demizu, Kai Nojima
  • Patent number: 10503844
    Abstract: A Discrete Event System model created or provided in a time domain modeling and simulation environment and/or an event domain modeling and simulation environment may be divided into multiple independent regions, e.g. “subgraphs”, to achieve interleaved execution of the components from different domains. The subgraphs are automatically identified by the modeling and simulation environment during the compilation. Each subgraph consists of one or more interconnected event-driven components. Each subgraph is associated with an event calendar that controls the execution of the associated subgraph. Such multiple event calendar design enables multi-domain simulation, where event-driven components modeled by an event domain modeling environment and time-driven components modeled by a time domain modeling environment are simulated in an integrated fashion.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: December 10, 2019
    Assignee: The MathWorks, Inc.
    Inventors: Wei Li, John Edward Ciolfi, Michael I. Clune
  • Patent number: 10503855
    Abstract: Methods and systems for SDA of mixed signal electronic circuitry including embedded software designs for creating ASICs, sub-systems, and SoCs. The SDA system described extends IP reuse beyond the circuit and stand-alone verification capabilities that are common practice today which limit the benefits of reuse. By solving the integration problem first in a loosely coupled manner, complex mixed signal SoC devices may achieve higher levels of IP reuse with push button ease through the cloud, significantly improving time to market, design resource limitations, risks for first time silicon success, and the tasks of managing business multiple relationships of IP providers. SDA generated designs use a multi-agent method of operation, creating powerful and flexible designs that provide both NOC (Network on a Chip) and NBC (Network Beyond the Chip) for distributed system operation, and enhanced non-intrusive in-system monitoring for mission critical and safety related applications.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: December 10, 2019
    Inventors: Robert Charles Ledzius, Robert James Stoddard, Greg Allen Hupp, Shalini Batra Sahni
  • Patent number: 10504802
    Abstract: A method of overlay control in silicon wafer manufacturing comprises firstly locating a target comprising a diffraction grating on a wafer layer; and then measuring the alignment of patterns in successive layers of the wafer. The location of the target may be done by the pupil camera rather than a vision camera by scanning the target to obtain pupil images at different locations along a first axis. The pupil images may comprise a first order diffraction pattern for each location. A measurement of signal intensity in the first order diffraction pattern is then obtained for each location. The variation of signal intensity with location along each axis is then analyzed to calculate the location of a feature in the target.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: December 10, 2019
    Assignee: KLA-Tencor Corporation
    Inventors: Naomi Ittah, Nadav Gutman, Eran Amit, Vincent Immer, Einat Peled
  • Patent number: 10503851
    Abstract: In example implementations, a method executed by a processor is provided. The method receives a simulated photonic data input based on a theoretical photonic design that meets a target specification. A complementary metal-oxide semiconductor (CMOS) circuit design is designed based on the simulated photonic data input using a pre-layout simulation. An experimental photonic data input based on a fabricated photonics device that meets the target specification is received. The CMOS circuit is designed based on the experimental photonic data input using a post-layout simulation. A physical circuit CMOS circuit design and a layout that includes detailed physical dimensions associated with the physical CMOS circuit design that is based on the pre-layout and the post-layout are transmitted to a CMOS foundry.
    Type: Grant
    Filed: January 22, 2016
    Date of Patent: December 10, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Tsung-Ching Huang, Chin-Hui Chen, Marco Fiorentino, Raymond G. Beausoleil
  • Patent number: 10495691
    Abstract: A method, system, and architecture (100) for adaptively field testing for hardware faults on an integrated circuit device includes a central quality assurance server (121) which receives specified hardware metric data (131) monitored at an integrated circuit device (110) in the field, identifies prioritized built-in self-test (BIST) fault detection tests (134) based on the specified hardware metric data, securely downloads the prioritized BIST fault detection tests (132) to the integrated circuit device for execution to identify a first hardware fault at the integrated circuit device, and then receives diagnosis information (133) identifying the first hardware fault from the integrated circuit device which is used to update the prioritized BIST fault detection tests.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: December 3, 2019
    Assignee: NXP USA, Inc.
    Inventors: Xiao Sun, Wen Chen, Jayanta Bhadra
  • Patent number: 10488835
    Abstract: A method for configuring a tester equipped for testing an electronic control unit, wherein a software model of a technical system is executed on the tester and communicates electronically through an input/output interface of the tester with a device connected to the tester. A configuration system is coupled to a modeling system, and a software model characterized by function blocks that are connected to one another is present in the modeling system. The tester is configured in the configuration system by interconnected configuration elements such that physical characteristics of the input/output interface and/or the connection of the input/output interface with the software model are defined via the configuration elements. The configuration system is coupled to the modeling system such that the software model is provided to the configuration system via a coupling interface at the run time of the modeling system.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: November 26, 2019
    Assignee: dSPACE digital signal processing and control engineering GmbH
    Inventor: Joerg Hagendorf
  • Patent number: 10489039
    Abstract: An electronic device and an operation method for operating the electronic device are provided to display at least one condition line based on notification conditions; determine at least a part of a section as an activation section for activating at least one object in the at least one condition line; and configure the activation section corresponding to the notification conditions.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: November 26, 2019
    Assignee: Samsung Electronics Co., Ltd
    Inventor: Young-Jae Meen
  • Patent number: 10482194
    Abstract: Described are techniques for processing a request. Data storage system configuration information is provided which is used by a simulator that simulates a data storage system configuration of a data storage system. A request is received to perform an operation with respect to the data storage system configuration being simulated. The request identifies an object included in the data storage system configuration information used to simulate the data storage system configuration. First processing is performed to simulate servicing the request using the data storage system configuration information and the first processing includes determining, at run time while processing the request, whether the object includes a first object property that is a reference to an embedded object.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: November 19, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Donald E. Labaj, Norman M. Miles, Scott E. Joyce, Timothy J. Cox
  • Patent number: 10481990
    Abstract: Methods and apparatuses relating to a multiple master capable debug interface are described. In one embodiment, an apparatus includes a device circuit, a debug and test access port to debug and test the device circuit, and a switching circuit to switch a debug and test mastership between the debug and test access port and a data access port to the device circuit that is not dedicated to debug and test.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: November 19, 2019
    Assignee: Intel Corporation
    Inventors: Patrik Eder, Rolf H. Kuehnis, Enrico D. Carrieri
  • Patent number: 10481817
    Abstract: Methods, apparatus, systems and articles of manufacture to optimize dynamic memory assignments in multi-tiered memory systems are disclosed. An example computer readable storage medium comprises instructions to, during an offline profiling run of a computer application: responsive to a first malloc function call, perform a first backtrace to identify a first path preceding the first malloc function call and identify a size of a buffer in memory allocated to the first path; and determine an indicator corresponding to a temperature of the buffer allocated to the first path; and during runtime: responsive to a second malloc function call, perform a second backtrace to identify a second path preceding the second malloc function call; and responsive to the second path corresponding to the first path, allocate memory from a tier of memory based on the indicator.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: November 19, 2019
    Assignee: INTEL CORPORATION
    Inventors: Kshitij Doshi, Andreas Kleen, Harshad Sane