Simulating Electronic Device Or Electrical System Patents (Class 703/13)
  • Patent number: 11032063
    Abstract: An example operation may include one or more of obtaining data of a simulation, identifying checkpoints within the simulation data, generating a plurality of sequential data structures based on the identified checkpoints, where each data structure identifies an evolving state of the simulation with respect to a previous data structure among the sequential data structures, and transmitting the generated sequential data structures to nodes of a blockchain network for inclusion in one or more data blocks within a hash-linked chain of data blocks.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: June 8, 2021
    Assignee: International Business Machines Corporation
    Inventors: Ravi Kiran Raman, Kush R. Varshney, Roman Vaculin, Michael Hind, Sekou L. Remy, Eleftheria K Pissadaki, Nelson K. Bore
  • Patent number: 11025633
    Abstract: Disclosed herein are systems and methods configured to provide customized and guided instructions for the placement of multiple access points in a home envelope to optimize-coverage therein. The exemplified system and method facilitates the learning of the home envelope, the determining of placements of devices within different locations within the home envelope, and the guiding of the homeowner or occupant through the installation process of the devices at such placements. The provided information are customized and tailored for a given home envelope. In addition, the exemplified systems and methods simplifies the task of adding personal wireless devices to a network whereby no password is used.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: June 1, 2021
    Assignee: BRK Brands, Inc.
    Inventors: Paul Qantas Judge, Adam Wesley Allred, Michael Burkett Biggs, Daniel Jack Peck, Paul Harris Royal
  • Patent number: 11003811
    Abstract: Techniques for improving a quantum simulator are provided. In one example, a system includes a simulation component and a snapshot component. The simulation component determines a set of random numbers and simultaneously provides the set of random numbers to an arithmetic decoder to perform a stochastic simulation process. The snapshot component generates snapshot data indicative of a state of the stochastic simulation process based on data associated with a stochastic branching point for the stochastic simulation process.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: May 11, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lev Samuel Bishop, Christopher J. Wood
  • Patent number: 10996990
    Abstract: Embodiments include method, systems and computer program products for performing Spectre mitigation on a workload. The method includes starting, by at least one processor of a plurality of processors, a process. The at least one processor determines that the process is a kernel process. The at least one processor determines that an interrupt has occurred in response to the determination that the process is a kernel process. The at least one processor processes the interrupt in response to determining that an interrupt has occurred. The at least one processor suppresses a malware mitigation to be applied to the kernel process in response to interrupt being processed.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: May 4, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sreenivas Makineedi, Douglas Griffith, Srinivasa Rao Muppala, Anil Kalavakolanu, Shanna Beck
  • Patent number: 10997585
    Abstract: An apparatus comprises a processing platform including a plurality of processing devices. The processing platform receives a request to generate a checkout interface on a user device in connection with a transaction to purchase a product and/or a service being performed over one or more networks, wherein the checkout interface comprises a plurality of selectable indicators each respectively indicating a payment option of a plurality of payment options, and to generate the checkout interface on the user device responsive to the request. The plurality of selectable indicators are simultaneously displayed on the checkout interface. The processing platform is further configured to receive a selection of a selectable indicator from the user device, and to automatically display on the checkout interface details of a payment option corresponding to the selected indicator responsive to the selection. The details are simultaneously displayed with the plurality of selectable indicators on the checkout interface.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: May 4, 2021
    Assignee: Dell Products L.P.
    Inventors: Archana Krishnamurthy Rao, Anand R. Pandey
  • Patent number: 10997114
    Abstract: Systems, methods, and apparatus for improving throughput of a serial bus are described. A method performed at a device coupled to a serial bus includes detecting a transition in signaling state of a first wire of the serial bus while a first pair of consecutive bits is being received from the first wire of the serial bus, determining that no transition in signaling state of the first wire occurred while a second pair of consecutive bits is being received from the first wire, defining bit values for the first pair of consecutive bits based on direction of the transition in signaling state detected while the first pair of consecutive bits is being received, and sampling the signaling state of the first wire while the second pair of consecutive bits is being received to obtain a bit value used to represent both bits in the second pair of consecutive bits.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: May 4, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Lalan Jee Mishra, Richard Dominic Wietfeldt, Helena Deirdre O'Shea
  • Patent number: 10990713
    Abstract: Systems and methods are provided for generating a state space model of a physical system. A matrix decomposition module is configured to receive input data and determine a size of an input matrix based on the input data. When the input matrix size is below a threshold, a singular value decomposition of the input matrix is determined using a first technique. When the input matrix size is above the threshold the input matrix is subdivided into a plurality of subparts. For each subpart, a separability value of that subpart is determined. When the separability value indicates that the subpart is well separated, a singular value decomposition of that subpart is determined using a second technique. When the separability value indicates that the subpart is not well separated, data associated with that subpart is provided to the matrix decomposition module via a recursive call.
    Type: Grant
    Filed: August 12, 2015
    Date of Patent: April 27, 2021
    Assignee: Ansys, Inc.
    Inventor: Amit Hochman
  • Patent number: 10990283
    Abstract: A storage cluster is provided. The storage cluster includes a plurality of storage nodes, each of the plurality of storage nodes having nonvolatile solid-state memory and a plurality of operations queues coupled to the solid-state memory. The plurality of storage nodes is configured to distribute the user data and metadata throughout the plurality of storage nodes such that the plurality of storage nodes can access the user data with a failure of two of the plurality of storage nodes. Each of the plurality of storage nodes is configured to determine whether a read of 1 or more bits in the solid-state memory via a first path is within a latency budget. The plurality of storage nodes is configured to perform a read of user data or metadata via a second path, responsive to a determination that the read of the bit via the first path is not within the latency budget.
    Type: Grant
    Filed: February 18, 2019
    Date of Patent: April 27, 2021
    Assignee: Pure Storage, Inc.
    Inventors: John D. Davis, John Hayes, Hari Kannan, Nenad Miladinovic, Zhangxi Tan
  • Patent number: 10984150
    Abstract: This application discloses a system implementing tools and mechanisms to identify alterations made to a baseline harness design that describes a wire harness, and selectively modify a target harness design based, at least in part, on the alterations made to the baseline harness design. The tools and mechanisms can perform the selective modification of the target harness design through a three-way comparison of the baseline harness design, an altered version of the baseline harness design, and the target harness design. During the three-way comparison, the tools and mechanisms can compare the target harness design to the baseline harness design, and compare the altered version of the baseline harness design to the baseline harness design. The tools and mechanisms can then selectively modify the target harness design based on the alterations made to the baseline harness design and the differences between the target harness design to the baseline harness design.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: April 20, 2021
    Assignee: Siemens Industry Software Inc.
    Inventor: Vikas Maddukuri
  • Patent number: 10982525
    Abstract: A downhole drilling system for reducing impact of vibration comprises a drill string having a bottom hole assembly (BHA) and a controller configured to control the downhole drilling system. The BHA includes a measurement sub configured to measure one or more of lateral, torsional, and axial vibrations. In this system, the controller controls the downhole drilling system based on a drilling environmental profile including drilling parameters of one or more of the lateral, torsional, and axial vibrations and further based on a vibration mode and a vibration level of the one or more of the lateral, torsional, and axial vibrations determined from the drilling environmental profile.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: April 20, 2021
    Assignee: CHINA PETROLEUM & CHEMICAL CORPORATION
    Inventor: Sheng Zhan
  • Patent number: 10985775
    Abstract: A method and apparatus is provided for implementing combinatorial hypermaps (CHYMAPS) and/or generalized combinatorial maps (G-Maps) based data representations and operations, comprising: mapping term-algebras to tree-based numbers using a fast algorithm and representing a graph of the mapping structure as a CHYMAPS using reversible numeric encoding and decoding; generating a representation of CHYMAPS in a form optimized for sub-map (sub-graph) to map (graph) isomorphism and partial matching with a general matching process; performing operations on the CHYMAPS as operations on respective numerical representations; performing compression and decompression using a three bit self-delimiting binary code; and storing and retrieving codes.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: April 20, 2021
    Assignee: KYNDI, INC.
    Inventor: Arun Majumdar
  • Patent number: 10970438
    Abstract: A method of generating a layout diagram of an IC device includes assigning a leakage constraint to a first schematic net of the IC device and determining a violation of the leakage constraint based on a dummy gate region. The IC layout diagram includes the dummy gate region between a first component of the first schematic net and a second component of a second schematic net of the IC device. The method includes modifying the IC layout diagram in response to the leakage constraint violation, and generating a layout file based on the modified IC layout diagram.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: April 6, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Tien-Chien Huang
  • Patent number: 10944491
    Abstract: A method for positioning a device under test within a test area is provided. The method comprises the steps of determining shape and/or quality of a quiet zone with respect to the device under test, and using an augmented reality technique in order to optimize the positioning of the device under test in the quiet zone.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: March 9, 2021
    Assignee: ROHDE & SCHWARZ GMBH & CO. KG
    Inventor: Benoit Derat
  • Patent number: 10933311
    Abstract: Method for generating collectible media content items based on location information starts with processor receiving location information from location sensor coupled to first client computing device. Processor causes a map interface to be displayed that includes avatar of first user at a location based on the location information and a subset of a plurality of collectible items associated with geographical coordinates. When the first client computing device is determined to be within predetermined distance from a selected collectible item, processor causes front facing camera view to be displayed on the first client computing device, causes lens corresponding to selected collectible item to be applied to the front facing camera view, and causes the image of the selected collectible item displayed on the front facing camera view to change. Lens includes image of the selected collectible item that is overlaid on front facing camera view. Other embodiments are described herein.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: March 2, 2021
    Assignee: Snap Inc.
    Inventors: Jonathan Brody, Jill H. Cohen, Bryant Detwiller, Alexander Fung, Evan HK Lin, Walton Lin, Kimberly A. Phifer, Alexandre Valdetaro Porto
  • Patent number: 10929584
    Abstract: Environmental modification testing with a formal verification is implemented for language-specified hardware designs. A language-specified hardware design may be received. A reference copy of the language-specified hardware design may be created. A formal verification may be performed on both the language-specified hardware design and the reference copy with a same input data. Different environmental assumptions for processing the same input data through the reference copy and the language-specified hardware design may be applied. An output value of the language-specified hardware design may be compared with an output value of the reference copy to determine whether those output values match. Error indications may be provided based on a result of the comparison.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: February 23, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Benzi Denkberg, Uri Leder, Ori Weber
  • Patent number: 10926474
    Abstract: Certain examples described herein relate to build units that are physically connectable to at least one host apparatus of an additive manufacturing system. A build unit comprises at least one controllable device useable in an object building operation. In certain examples, the at least one device is controllable according to first control instructions originating from the at least one host apparatus when the build unit is physically connected to the at least one host apparatus. In certain examples, the at least one device is also controllable according to second control instructions generated independently of the at least one host apparatus when the build unit is not physically connected to the at least one host apparatus.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: February 23, 2021
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Anna Torrent, David Soriano Fosas, Vicente Granados Asensio
  • Patent number: 10924345
    Abstract: A method for changing the configuration of at least two connected networks which consist of components and which are interconnected via at least one component, wherein at least one of the at least two networks is configured as a communication network, where digital models of the at least two networks are created based on network analyses, digital component models are created for the at least one connecting component, deriving a sequence of the configuration change is derived based on the digital models of the at least two networks and the digital component models for the at least one connecting component, the sequence of the configuration change is disassembled into decentrally executable sequence units and the decentrally executable sequence units distributing and executing while taking temporal and spatial dependencies on at least one decentralized sequence control unit in at least one of the at least two networks into account.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: February 16, 2021
    Assignee: SIEMENS AKTIENGESELLSCHAFT
    Inventor: Florian Kintzler
  • Patent number: 10917288
    Abstract: Apparatus and methods for maintaining service during a communication network outage. The apparatus may include an outage monitor. The outage monitor may monitor conditions that may affect the performance or integrity of a WAN. The apparatus may include a digital switch that may be configured to switch, responsive to a state variable in the monitor, between: a regular-operations information machine at an edge location; and a contingency server disposed at the edge location. When the switch engages the contingency server, data on the contingency server may be available to one or more of banking associates, call center attendants, customers and other suitable enterprise personnel and systems.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: February 9, 2021
    Assignee: Bank of America Corporation
    Inventors: Sean Denton, Monika Kapur, Stephen T. Shannon
  • Patent number: 10915237
    Abstract: A computer programme product (10) for the configuration of a user-specific product (12) is stored on a mobile computer (2) and has a virtual library (14) with a plurality of selectable virtual components (16) for the compilation of a virtual model (12M) of the product (12) which can be shown on a display (4) of the mobile computer (2), wherein product information (I) for the creation of the actual user-specific product (12) is derivable on the basis of the components (16) selected for the displayed virtual model (12M). According to the invention, at least one functional device (36) is provided on the mobile computer (2), the device being controllable by means of touch operation of the virtual model (12M) on the display (4).
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: February 9, 2021
    Inventor: Thomas Haug
  • Patent number: 10909600
    Abstract: A method is disclosed that includes identifying an inventory item corresponding to a product configuration. The product configuration is defined using a feature map. The inventory item is also defined using the feature map. Each entry of the feature map corresponds to one of a number of features of a product.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: February 2, 2021
    Assignee: Versata Development Group, Inc.
    Inventors: Grant M. Emery, Arpan Shah
  • Patent number: 10908942
    Abstract: A virtualization device for composing a virtual network for implementation using physical network infrastructure, the virtualization device comprising; a node functionality and constraints module, configured to identify functionality and constraints of one or more nodes of the physical network infrastructure; a link constraints module, configured to identify constraints of one or more links of the physical network infrastructure; a network modeller module, configured to generate a model of the physical network infrastructure, based on the identified functionality and constraints of the nodes and on the identified constraints of the links; a virtual network composer module configured to receive a request for composition of a desired virtual network and to map the desired virtual network onto the physical network infrastructure based on the model generated by the network modelling module; and one or more node and link mapping modules for simultaneously mapping a virtual node of the desired virtual network onto
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: February 2, 2021
    Assignee: Zeetta Networks Limited
    Inventors: Vassilis Seferidis, Reza Nejabati
  • Patent number: 10903921
    Abstract: A method for providing a broadcast service, according to the present invention, comprises the steps of: if a broadcast service is provided by means of two or more networks, obtaining the maximum value among the fixed end-to-end delay of each network; and, on the basis of the maximum value, controlling an output point of a receiver which received packets of the broadcast service.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: January 26, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Koo Yang, Sung-Hee Hwang, Young-Kwon Lim, Kyung-Mo Park, Sung-Oh Hwang
  • Patent number: 10902175
    Abstract: Methods, systems and computer program products for providing cross-hierarchical block pin placement are provided. Aspects include designating potential pin placements by aligning output pins of each of a first set of bottom-level hierarchical blocks positioned within one or more middle-level hierarchical blocks to an edge of a respective middle-level hierarchical block. Responsive to determining that each of a first subset of a second set of bottom-level hierarchical blocks having input pins that correspond to the output pins of the first set of bottom-level hierarchical blocks are positioned within a respective middle-level hierarchical block that has a cross hierarchical alignment, aspects include placing pins at one or more of the potential pin placements. Aspects also include placing a set of pins based on aligning input pins of a second subset of the second set of bottom-level hierarchical blocks to an edge of a respective middle-level hierarchical block.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: January 26, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jesse Surprise, Gerald Strevig, III, Shawn Kollesar
  • Patent number: 10887778
    Abstract: In one example, the present disclosure describes a device, computer-readable medium, and method for proactively adjusting the infrastructure of a communications network in response to reporting of real-time network performance. For instance, in one example, a method includes obtaining real-time network performance metrics directly from a user endpoint device operated by a customer of a telecommunication service provider network, correlating the real-time network performance metrics with data from another data source, wherein the data includes data other than network performance metrics, and adjusting an infrastructure of the telecommunication service provider network in response to an insight gleaned through the correlating.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: January 5, 2021
    Assignee: AT&T Intellectual Property I, L.P.
    Inventors: Rajan Anand, Nimish Buch, Timothy Neville, Mark Cottrell, David Lu, Eshrat Huda, Sachin Lohe
  • Patent number: 10884055
    Abstract: A system for post-silicon leakage characterization is configured to apply a rail voltage to a hardware component; cause the hardware component to operate at a particular frequency; cause a cooling device, coupled to the hardware component, to operate at a cooling capacity; run a workload on the hardware component after applying the rail voltage, causing the hardware component to operate at a particular frequency, and causing the cooling device to operate at a particular cooling capacity; discontinue the workload and clocks of the hardware component after a temperature of the hardware component has reached a steady high point; continuously measure temperature and leakage power of the hardware component after discontinuing the workload until the temperature of the hardware component has reached a steady low point; and adjust a power management procedure for the hardware component based on measured temperature and measured leakage power of the hardware component.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: January 5, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Diyanesh B. Chinnakkonda Vidyapoornachary, Anand Haridass, Arun Joseph, Charles R. Lefurgy, Spandana V. Rachamalla
  • Patent number: 10878344
    Abstract: Systems, methods, computer-readable media, and apparatuses for identifying and executing one or more interactive condition evaluation tests to generate an output are provided. In some examples, user information may be received by a system and one or more interactive condition evaluation tests may be identified. An instruction may be transmitted to a computing device of a user and executed on the computing device to enable functionality of one or more sensors that may be used in the identified tests. A user interface may be generated including instructions for executing the identified tests. Upon initiating a test, data may be collected from one or more sensors in the computing device. The data collected may be transmitted to the system and may be processed using one or more machine learning datasets to generate an output.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: December 29, 2020
    Assignee: Allstate Insurance Company
    Inventors: John Rugel, Brian Stricker, Howard Hayes
  • Patent number: 10867087
    Abstract: Systems and methods for performing power analytics on a microgrid. In an embodiment, predicted data is generated for the microgrid utilizing a virtual system model of the microgrid, which comprises a virtual representation of a topology of the microgrid. Real-time data is received via a portal from at least one external data source. If the difference between the real-time data and the predicted data exceeds a threshold, a calibration and synchronization operation is initiated to update the virtual system model in real-time. Power analytics may be performed on the virtual system model to generate analytical data, which can be returned via the portal.
    Type: Grant
    Filed: August 16, 2018
    Date of Patent: December 15, 2020
    Assignee: Wavetech Global, Inc.
    Inventors: Kevin Meagher, Brian Radibratovic, Adib Nasle
  • Patent number: 10866505
    Abstract: Provided is a method for fabricating a semiconductor device including performing an OPC process to an IC layout pattern to generate a post-OPC layout pattern. In some embodiments, the method further includes applying an MPC model to the post-OPC layout pattern to generate a simulated mask pattern. By way of example, the simulated mask pattern is compared to a mask pattern calculated from a target wafer pattern. Thereafter, and based on the comparing, an outcome of an MPC process is determined.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsu-Ting Huang, Ru-Gun Liu
  • Patent number: 10862766
    Abstract: A controller is provided for a Cloud based service handling multiple types of traffic in a telecommunications network, the controller comprising: a first stage configured to automatically model use of Cloud resources allocated to the service for specific workloads of each of a plurality of traffic types, so as provide a variety of models for each traffic type; a second stage configured to automatically reduce the number of and generalise the models so as to provide generalised models for each traffic type applicable to other workloads than the specific loadings; a third stage configured to automatically evaluate accuracy of the generalised models for various combinations of given workloads, in each combination each of the given workloads being of a corresponding traffic type, and to select one of the generalised models dependent upon evaluated accuracy; and a fourth stage configured to control operation of the Cloud resources according to the selected model.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: December 8, 2020
    Assignee: Alcatel Lucent
    Inventors: Diego Lugones, Jesus Omana Iglesias, Thomas Voith, Stefanie Braun, Jordi Arjona Aroca, Joachim Riemer, Volker Hilt, Jurgen Sienel
  • Patent number: 10860768
    Abstract: Disclosed herein are embodiments of tools and techniques for computing the electric coupling in terms of parasitic admittance and capacitance values between a through silicon via (TSV) and surrounding interconnect of an integrated circuit layout design. In particular embodiments, a computation of one or more admittance and capacitance values between a through-silicon-via (TSV) structure and an interconnect structure of the three-dimensional integrated circuit layout design using two or more field solvers or rule-based engines that are different from one another is performed. In addition, electrical connectivity for the coupling parasitic between a TSV and an interconnect is established. Then, a parasitic netlist representation of the three-dimensional integrated circuit layout design that includes the above parasitic element values is generated.
    Type: Grant
    Filed: September 29, 2018
    Date of Patent: December 8, 2020
    Assignee: Mentor Graphics Corporation
    Inventors: Vasileios Kourkoulos, Georgios Manetas
  • Patent number: 10853111
    Abstract: Techniques for providing customer feedback related to virtual machine instance maintenance events are described herein. A customer is provided with an event message specifying a virtual machine maintenance operation and a proposed time to perform that virtual machine maintenance operation. A response that specifies the time that the customer wishes to perform the virtual machine maintenance operation is received and the virtual machine maintenance operation is scheduled based at least in part on that specified time.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: December 1, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Diwakar Gupta, Georgios Elissaios, Weili Zhong McClenahan, Alan Hadley Goodman
  • Patent number: 10853049
    Abstract: Enabling migration of code in a service oriented architecture executed in a distributed computing environment. A migration definition for generating migrations is received, the migration definition exposing a tangible set of matchers and filters configured to locate code constructs and codebase settings of the code to be migrated. The code to be migrated is user defined. A deterministic script is scaffolded from the tangible set of matchers and filters to find instances of code to update or settings to update within the distributed environment. The instances of the code settings are updated, whereby the code in the service oriented architecture is migrated.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: December 1, 2020
    Assignee: ADP, LLC
    Inventors: Joe Groseclose, Lohit J. Sarma, Darshan Kapadia
  • Patent number: 10845407
    Abstract: An apparatus of a multi-chip package (MCP) of a functional safety system, comprises a processor configurable as a master chip in a master-slave arrangement with a slave chip in the MCP, and a memory coupled to the processor to store one or more infield test scan patterns. The processor includes a block to couple the master chip to the slave chip via a high-speed input/output (IO) interface to retrieve the one or more infield test scan patterns from the memory via the master chip, and to provide the one or more infield test scan patterns to the slave chip via the high-speed TO interface in response to the functional safety system entering an infield test mode.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: November 24, 2020
    Assignee: Intel Corporation
    Inventors: Asad Azam, Amit K. Srivastava, Enrico Carrieri, Rajesh Bhaskar
  • Patent number: 10841026
    Abstract: An exemplary device for emulating a wireless channel(s) can be provided, which can include, for example, a first communication interface configured to receive a first data signal(s) from a transmitter unit(s), a hardware processor configured to receive the first data signal(s) from the first communication interface, and generate a second data signal(s) by modifying the first data signal(s) based on a test(s) being performed on the transmitter unit(s), and a second communication interface configured to receive the second data signal(s) from the hardware processor, and transmit the second data signal(s) to a receiver unit(s). A control interface can be included, which can be configured to receive a control signal(s) from the transmitter unit(s) or the receiver unit(s) and provide the control signal(s) to the hardware processor for determining the second data signal(s).
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: November 17, 2020
    Assignee: New York University
    Inventors: Aditya Dhananjay, Sundeep Rangan, Dennis Shasha
  • Patent number: 10839545
    Abstract: When three-dimensional audio is produced by using headphones particular HRTF-filters are used the sound for left and right channels of the headphone. As the morphology of every ear is different, it is beneficial to have HRTF-filters particularly designed for the user of headphones. Such filters may be produced deriving ear geometry from a plurality of images taken with an ordinary camera, detecting necessary features from images and fitting said features to a model that has been produced from accurately scanned ears comprising representative values for different sizes and shapes. Taken images are sent to a server that performs the necessary computations and submits the data further or produces the requested filter.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: November 17, 2020
    Assignee: OwnSurround Oy
    Inventors: Tomi Huttunen, Antti Vanne
  • Patent number: 10839124
    Abstract: Interactive compilation of software to a hardware language may be performed to satisfy formal verification constraints. Source code for software to be executed on a hardware design may be received. Intermediate code may be generated from the source code as part of translating the source code to a hardware language used to specify the hardware design. The intermediate code may be provided via an interface and updates to the intermediate code may be received. The updated source code may then be used to complete translation of the source code to the hardware language.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: November 17, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Uri Leder, Adi Habusha, Ofer Naaman, Tzachi Zidenberg, Ohad Gdalyahu
  • Patent number: 10832265
    Abstract: A computer-implemented method for prescriptive time-series forecasting, which combines both what-if analysis and goal-seeking analysis. The method comprises building a model for a target metric with a set of predictors, based on historical time-series data, and computing, using the model, a set of forecast values. Using the set of forecast values with respect to a forecasting period, both a set of goals for the target metric and a set of constraints for the predictors are analyzed. A set of updated forecasts based on the analyses with respect to the forecasting period is determined to meet the goals within the set of constraints. The updated set of forecasts is presented with respect to the forecasting period, e.g., using a table, a visualization, and/or an interactive user interface.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Yea-Jane Chu, Richard J. Oswald, Jean-Francois Puget, Jing-Yun Shyr
  • Patent number: 10826785
    Abstract: Methods, computing systems and computer program products implement embodiments of the present invention that include detecting, on a communications network in a computing facility including a first computer coupled to a second computer via the communications network, an input/output (I/O) request conveyed from the first computer to the second computer. Subsequent to detecting the I/O request, data traffic resulting from the second computer processing the I/O request is identified on the communications network, and network statistics are collected based on the I/O request and the data traffic. Upon detecting a performance degradation of the computing facility, the performance degradation greater than a predetermined amount, heuristics can be applied to the collected network statistics, to identify a cause of the performance degradation and to identify a remedy to the detected performance degradation. In some embodiments, the identified cause and the identified remedy can be presented to a user on a display.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: November 3, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jonathan Amit, Lior Chen, Vladislav Drouker, Osnat Shasha
  • Patent number: 10824948
    Abstract: A trigger element of a design-time flow plan is set so that the trigger element activates in response computing conditions being satisfied. A decision action element of the design-time flow plan executed at run-time in response to activation of the trigger element is set. The decision action element is implemented by a decision table that includes decision inputs and respective condition logic based on the decision inputs for each of a plurality of decision answers associated with the decision table. The decision table is external to the design-time flow plan. First and second decision answer action elements are defined to execute at run-time respectively when a decision answer served-up by the decision table corresponds to first and second decision answer paths in the design-time flow plan that are associated with a first and second one of the plurality of decision answers, respectively. The design-time flow plan is published.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: November 3, 2020
    Assignee: ServiceNow, Inc.
    Inventors: Harry Thomas Nelson, Jacob Samuel Burman, Juell Solaegui, Alberto Alvarado Jimenez, Rebecca Anita Dias
  • Patent number: 10818638
    Abstract: A set of the dies and the package are provided with a plurality of dies each including at least an accelerator core or a CPU core, an external interface, memory interfaces, and a die interface for connecting to another die. At least two dies of the set of dies include a first type die and a second type die each including both the accelerator core and the CPU core, and the core number ratio between the accelerator core and the CPU core in the first type die differs from that in the second type die. The memory interfaces include an interface conforming to TCI. The memory interfaces further include an interface conforming to HBM.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: October 27, 2020
    Assignee: Pezy Computing K.K.
    Inventor: Motoaki Saito
  • Patent number: 10812363
    Abstract: Some embodiments are associated with a data center cloud computing environment executing a plurality of virtual machines. A virtual machine data store may contain information about the plurality of virtual machines associated with the cloud computing environment. A virtual machine test platform may access the information in the virtual machine data store and periodically initiate a network test for each of the plurality of virtual machines based on the information in the virtual machine data store. The virtual machine test platform may then receive network test result signals from the virtual machines in response to the executed network tests and apply, for each virtual machine, a digital signal processing noise filter to successive network test result signals from that virtual machine. An output of the digital signal processing noise filters may then be transmitted from the virtual machine test platform.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: October 20, 2020
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Joseph Romeo, Vyjeyanthi Murthy, Shruti Ramesh, Anthony Howe, Ashutosh Dhiman
  • Patent number: 10810093
    Abstract: A distributed system implements initializing reliability data of a newly joined node of a cluster for purposes of leadership election. When a new node joins a cluster, the new node receives reliability data for one or more existing nodes of a cluster. The new node initializes its own reliability data based on the reliability data received from the existing nodes of the cluster. In some cases, the new node may calculate a median reliability of the existing nodes and then initialize its own reliability to be the median or slightly below the median. For example, if the median reliability is “two failures,” then the new node may set its reliability to be “three failures.” This may provide a more stable leadership election process, as the new nodes are unlikely to be elected as a leader node.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: October 20, 2020
    Assignee: Amazon Technologies, Inc.
    Inventor: Joseph Andrew Tucek
  • Patent number: 10795614
    Abstract: In a memory controller for controlling an operation of a memory device, the memory controller includes a buffer memory and a buffer management circuit. The buffer memory includes an input buffer for storing input data received from a host and an output buffer for storing output data received from the memory device. The buffer management circuit changes capacities of the input buffer and the output buffer, based on a use state of at least one of the input buffer and the output buffer.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: October 6, 2020
    Assignee: SK hynix Inc.
    Inventor: Ho Jung Yun
  • Patent number: 10791034
    Abstract: A method of simulating a scenario in a telecommunications network is provided. The method comprises: generating a network definition expressed in a common data model readable by first and second routing engines; generating a set of demand matrices describing demands on the network; incorporating a scenario definition into one or more of the network definition and the demand matrices; automatically determining a first aspect of a new network state associated with the scenario definition by determining a first optimised set of routes using the first routing engine based on the network definition and at least one of the demand matrices; and automatically determining a second aspect of the new network state by determining a second optimised set of routes using the second routing engine based on the first optimised set of routes and at least one other of the demand matrices.
    Type: Grant
    Filed: November 27, 2015
    Date of Patent: September 29, 2020
    Assignee: ARIA NETWORKS LIMITED
    Inventors: Jay Perrett, Arthur Wade, John Crickett
  • Patent number: 10788759
    Abstract: Prediction based systems and methods for optimizing wafer chucking and lithography control are disclosed. Distortions predicted to occur when a wafer is chucked by a chucking device are calculated and are utilized to control chucking parameters of the chucking device. Chucking parameters may include chucking pressures and chucking sequences. In addition, predicted distortions may also be utilized to facilitate application of anticipatory corrections. Controlling chucking parameters and/or applying anticipatory corrections help reducing or minimizing overlay errors.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: September 29, 2020
    Assignee: KLA-Tencor Corporation
    Inventors: Bin-Ming Benjamin Tsai, Oreste Donzella, Pradeep Vukkadala, Jaydeep Sinha
  • Patent number: 10782772
    Abstract: An energy-aware system, and method thereof are provided. The energy-aware system includes a microcontroller; an energy storage; a plurality of execution functions integrated in a system on chip (SoC); and a scheduler configured to schedule execution of operations based on available energy at the energy storage and energy requires to complete each of the operations.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: September 22, 2020
    Assignee: WILIOT, LTD.
    Inventors: Yaron Elboim, Dotan Ziv, Yuval Amran, Nir Shapira
  • Patent number: 10783061
    Abstract: A method for testing a user interface includes determining states and state transitions associated with the user interface. A first plurality of states and a first plurality of state transitions of the user interface may be explored. A subset of a second plurality of states and a second plurality of state transitions of the user interface may also be explored. Paths that lead to cycles within the subset of the second plurality of states and the second plurality of state transitions may be penalized.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: September 22, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Parag Nandan Paul
  • Patent number: 10783536
    Abstract: A computer-implemented method for prescriptive time-series forecasting, which combines both what-if analysis and goal-seeking analysis. The method comprises building a model for a target metric with a set of predictors, based on historical time-series data, and computing, using the model, a set of forecast values. Using the set of forecast values with respect to a forecasting period, both a set of goals for the target metric and a set of constraints for the predictors are analyzed. A set of updated forecasts based on the analyses with respect to the forecasting period is determined to meet the goals within the set of constraints. The updated set of forecasts is presented with respect to the forecasting period, e.g., using a table, a visualization, and/or an interactive user interface.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: September 22, 2020
    Assignee: International Business Machines Corporation
    Inventors: Yea-Jane Chu, Richard J. Oswald, Jean-Francois Puget, Jing-Yun Shyr
  • Patent number: 10769008
    Abstract: The present disclosure relates to a computer-implemented method for use in an electronic design. The method may include receiving, using at least one processor, an electronic design and analyzing the electronic design. The method may further include generating one or more preconditions representative of metastability effects at the output of at least one synchronizer associated with the electronic design. The method may also include generating, based upon, at least in part, the one or more preconditions, one or more properties configured to analyze a propagation of the metastability effects associated with the at least one synchronizer.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: September 8, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Alberto Manuel Arias Drake, Andrea Iabrudi Tavares, Artur Melo Mota Costa, Fabiano Cruz Peixoto, Laiz Lipiainen Santos, Lucas Ferreira de Melo Diniz, Nathália Peixoto Reis, Patricia Sette Câmara Haizer, Regina Mara Amaral Fonseca, Tamires Vargas Capanema Franco Santos
  • Patent number: 10755015
    Abstract: The disclosed embodiments include systems and methods of building an agnostic model of a physically-based semiconductor device. The embodiments may include implementing, in the agnostic model, an arbitrary voltage source in series between a node voltage and a zero value voltage source, implementing, in the agnostic model, a reference capacitor in series between the node voltage and a dummy voltage source, implementing, in the agnostic model, an arbitrary current source between a first node and a second node. The arbitrary current source may include the dummy voltage source divided by the reference capacitor, and the arbitrary current source may model the change in the any property, such as charge, over time within the semiconductor device.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: August 25, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: James Joseph Victory, Mehrdad Baghaie Yazdi