Simulating Electronic Device Or Electrical System Patents (Class 703/13)
  • Patent number: 10263106
    Abstract: A power mesh-on-die apparatus includes a solder trace that enhances current flow for a power source trace between adjacent power bumps. The solder trace is also applied between power drain bumps on a power drain trace.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: April 16, 2019
    Assignee: Intel IP Corporation
    Inventors: Bernd Waidhas, Sonja Koller, Georg Seidemann
  • Patent number: 10263879
    Abstract: An aspect includes input/output (I/O) stack modeling. A processor determines a client configuration of a client I/O stack that includes layers with configurable parameters to control storage and retrieval of data between an uppermost layer and lowest layer. A model of the client I/O stack is built on a layer basis that defines input workload characteristics, output workload characteristics, and layer configuration parameters for the layers of the model based on the client configuration. Workload characteristics of the uppermost layer of the client I/O stack are fed to the model. The processor determines a statistical distribution of workload characteristics associated with each of the layers of the client I/O stack. I/O performance results are captured for layers of the model based on feeding the workload characteristics of the uppermost layer.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: April 16, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dean Hildebrand, Ramani R. Routray, Vasily Tarasov
  • Patent number: 10254826
    Abstract: A system and method of operating an audio visual system generating a virtual immersive experience may include an electronic user device in communication with a tracking device that may track a user's physical movement in a real world space and translate the tracked physical movement into corresponding movement in the virtual world generated by the user device. The system may detect when a user and the user device are approaching a boundary of a tracking area and automatically initiate a transition out of the virtual world and into the real world. A smooth, or graceful, transition between the virtual world and the real world as the user encounters this boundary may avoid disorientation which may occur as a user continues to move in the real world, while motion appears to have stopped upon reaching the tracking boundary.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: April 9, 2019
    Assignee: GOOGLE LLC
    Inventors: Manuel Christian Clement, Alexander James Faaborg
  • Patent number: 10255163
    Abstract: Embodiments are disclosed for analyzing data storage devices. The present disclosure employs a “canary” test that selects multiple storage devices and tests the same for a predetermined period of time. By analyzing the statuses of the storage devices monitored and recorded during the applicable tests, the present disclosure can generate an analytical result regarding the characteristics of the storage devices. The analytical result can be presented to an operator in a meaningful way so as to enable him or her to make an informed decision when utilizing a storage device with characteristics similar to the tested storage devices.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: April 9, 2019
    Assignee: Facebook, Inc.
    Inventors: Darryl Edward Gardner, Yashar Bayani, Zhanhai Qin
  • Patent number: 10254395
    Abstract: A device and methods are provided for determining data points with an integrated radar sensor. In one embodiment, a method includes determining position of a device, scanning one or more objects, wherein scanning includes detecting data points by an integrated radar sensor of the device and capturing image data of the one or more objects, and determining data points for one or more objects based on the scanning. The method may also include correlating data points to one or more portions of the image data, assigning correlated data points to one or more portions of the image data, and storing, by the device, image data with data points. The device and methods may advantageously be employed for one or more of mapping, modeling, navigation and object tracking.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: April 9, 2019
    Assignee: Trimble Inc.
    Inventors: Mark Edward Nichols, Gregory Craig Wallace
  • Patent number: 10248977
    Abstract: A management server and method for performing resource management operations in a distributed computer system takes into account information regarding multi-processor memory architectures of host computers of the distributed computer system, including information regarding Non-Uniform Memory Access (NUMA) architectures of at least some of the host computers, to make a placement recommendation to place a client in one of the host computers.
    Type: Grant
    Filed: April 9, 2014
    Date of Patent: April 2, 2019
    Assignee: VMware, Inc.
    Inventors: Aashish Parikh, Puneet Zaroo, Ganesha Shanmuganathan
  • Patent number: 10248385
    Abstract: A mobile application workflow extraction method, system, and computer program product include extracting functional elements from a design file to create a database of design screens, generating a flow graph of the design screens and the functional elements in the design file, creating a transition graph that details how to move from each of the design screens to another, and analyzing, for each of the design screens, a relatability of each design screen to a previously analyzed design screen in the database and generating a tag that represents a workflow.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: April 2, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kyungmin Lee, David M. Lubensky, Marco Pistoia, Stephen Wood
  • Patent number: 10230325
    Abstract: Electrical component location is provided. Employed location techniques may include providing a cycling signal, having components to be located sense the cycling signal at the same time, report back the sensed signal, and determining relative locations for one or more of the components using the sensed signals reported by the components.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: March 12, 2019
    Assignee: Enphase Energy, Inc.
    Inventors: Patrick L Chapman, Fernando Rodriguez, Philip Rothblum, Anant K Singh
  • Patent number: 10222776
    Abstract: A motor control wizard implements a simple workflow for creating an application-specific program for operation of a motor control system. The wizard prompts for selection of an application area, which sensitizes the system to tune certain motor control parameters in accordance with the demands of the selected application area. The wizard also prompts for selection of a target devices, such as a particular type of motor with a set of basic operating parameters. With the target device and application area known, the wizard runs an automatic adaptation step without requiring additional user-settable parameters. The adaptation step yields an adapted motor control program based characteristics of the motor control system obtained via the adaptation step. The wizard then confirms operation of the motor using the adapted program. Additional features allow the user to fine tune parameters beyond this set of initial configuration parameters.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: March 5, 2019
    Assignee: LINESTREAM TECHNOLOGIES
    Inventors: Adam Reynolds, Chris Knaack, Boris Eligulashvili, David Stopher
  • Patent number: 10222852
    Abstract: In an approach for determining voltage and frequency pairs, the computer identifies an integrated circuit design. The computer identifies a timing model associated with the identified integrated circuit design. The computer identifies at least a nominal voltage, a nominal clock signal, and a voltage range associated with the integrated circuit design. The computer receives a number n that defines the number of at least one alternate voltage within the voltage range. The computer analyzes the identified integrated circuit based on the received number n for each number n for at least one alternate voltage within the voltage range. The computer calculates a nominal slack. The computer calculates one or more clock periods based on the calculated nominal slack. The computer provides a report based on the calculated one or more clock periods.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: March 5, 2019
    Assignee: International Business Machines Corporation
    Inventors: Eric A. Foreman, Stephen G. Shuma
  • Patent number: 10222850
    Abstract: In an approach for determining voltage and frequency pairs, the computer identifies an integrated circuit design. The computer identifies a timing model associated with the identified integrated circuit design. The computer identifies at least a nominal voltage, a nominal clock signal, and a voltage range associated with the integrated circuit design. The computer receives a number n that defines the number of at least one alternate voltage within the voltage range. The computer analyzes the identified integrated circuit based on the received number n for each number n for at least one alternate voltage within the voltage range. The computer calculates a nominal slack. The computer calculates one or more clock periods based on the calculated nominal slack. The computer provides a report based on the calculated one or more clock periods.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: March 5, 2019
    Assignee: International Business Machines Corporation
    Inventors: Eric A. Foreman, Stephen G. Shuma
  • Patent number: 10216877
    Abstract: The present embodiments relate to methods for simulating the behavior of an IP core that has an encrypted simulation model. The encrypted simulation model of the IP core may include a plurality of probes, which a debug option may activate selectively, if desired. The encrypted simulation model may collect data during a simulation as selected by the activated probes of the plurality of probes. The encrypted simulation model may perform smart diagnosis of the collected data based on a set of rules and generate feedback messages that may suggest corrective action in the event of a simulation failure.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: February 26, 2019
    Assignee: Altera Corporation
    Inventors: Vishwas Tumkur Vijayendra, Bo Zhou
  • Patent number: 10216252
    Abstract: In an approach for determining voltage and frequency pairs, the computer identifies an integrated circuit design. The computer identifies a timing model associated with the identified integrated circuit design. The computer identifies at least a nominal voltage, a nominal clock signal, and a voltage range associated with the integrated circuit design. The computer receives a number n that defines the number of at least one alternate voltage within the voltage range. The computer analyzes the identified integrated circuit based on the received number n for each number n for at least one alternate voltage within the voltage range. The computer calculates a nominal slack. The computer calculates one or more clock periods based on the calculated nominal slack. The computer provides a report based on the calculated one or more clock periods.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: February 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Eric A. Foreman, Stephen G. Shuma
  • Patent number: 10210070
    Abstract: A model checking apparatus able to reduce redundant search in a model checking is provided. The model checking apparatus is configured to: accept verification information representing a state transition model and a verification content; obtain an execution path by causing a transition in the state transition model; analyze, between transitions on the execution path, a dependence relation relating to data set determination processing for determining a data set being a set of representative values of data used in a transition with data use; perform a re-search using a data set in which data already used in a previous search in the transition is excluded from the data set obtained by the data set determination processing, when performing a re-search from a backtrack point based on the dependence relation relating to the data set determination processing; and provide a verification result of the verification content based on the search result.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: February 19, 2019
    Assignee: NEC CORPORATION
    Inventor: Yutaka Yakuwa
  • Patent number: 10211778
    Abstract: A photovoltaic power generation system includes at least one photovoltaic power generation microgrid and a central server configured to communicate with the photovoltaic power generation microgrid via Internet.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: February 19, 2019
    Assignees: HUBEI UNIVERSITY FOR NATIONALITIES, HUBEI YONGHENG SOLAR CO., LTD.
    Inventors: Jianjun Tan, Jinqiao Yi, Xianbo Sun, Yong Huang, Tao Hu, Shangyun Ding
  • Patent number: 10204025
    Abstract: Embodiments are generally directed to a mechanism to provide back-to-back testing of memory controller operation. An embodiment of an apparatus includes a test controller including a specialized self-testing mechanism for memory control testing, the memory control testing including testing with back-to-back transactions; and a memory controller, the memory controller including one or more transaction arbiters, one or more arbiter queues for memory transactions, an auto response mechanism to provide a response to a read transaction, and a switching mechanism to switch the memory control between a functional mode and an auto response mode. The test controller is to generate test transactions and transfer the test transactions to the memory controller. The memory controller is to block the one or more transaction arbiters, place the plurality of test transactions in the one or more arbiter queues, and to unblock the transaction arbiters upon an event.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: February 12, 2019
    Assignee: Intel Corporation
    Inventor: Lakshminarayana Pappu
  • Patent number: 10198539
    Abstract: Systems, methods, and products implementing a dynamic register transfer level (DRTL) monitor are disclosed. The DRTL monitor may be rapidly constructed and implemented in one or more emulator devices during the runtime of the emulation of a device under test (DUT). The systems may receive monitor modules and corresponding monitor instances in high level hardware description language and compile the monitor modules and instances to generate a monitor within the one or more emulator devices. The systems may then connect one or more input ports of the monitor to one or more signal sources in the DUT. The systems may further allow removal of the monitor, addition or more monitors, and/or modification of the monitor during the run time of the emulation of the DUT.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: February 5, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Tsair-Chin Lin, Jingbo Gao, Alon Kfir, Long Wang, Wei Zeng, Zhao Li
  • Patent number: 10198540
    Abstract: The present disclosure relates to a computer-implemented method for electronic design simulation using a profiler. The method may include simulating, using a computing device, an electronic design associated with a programming language. The method may further include recording a first time corresponding to a first user-defined point in the simulation. The method may also include recording a second time corresponding to a second user-defined point in the simulation. The method may further include determining a difference in time between the first and second times and displaying a visualization including at least one of the first time, the second time, a value of a variable at the first time, a value of the variable at a second time, and the difference in time.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: February 5, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventor: Daniel Asher Cohen
  • Patent number: 10196878
    Abstract: Embodiments of machines, systems, computer-implemented methods, and computer program products certify oil and gas well equipment. Embodiments identify a selected well equipment device, a device test specification, and testing sequences to be performed by a corresponding testing apparatus. Embodiments select a testing sequence responsive to the selected device. Embodiments control the testing apparatus for the selected testing sequence so that the corresponding testing apparatus performs the sequence responsive to the device test specification. Embodiments generate testing data for the selected testing sequence and link the testing data for the selected testing sequence to the device identifier for the device so that a certificate can be generated. Embodiments generate a certificate for the selected device responsive to the testing sequences having been performed upon the selected device and link the certificate for the selected device to the device identifier so that the certificate can be readily recalled.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: February 5, 2019
    Assignee: S.P.M. FLOW CONTROL, INC.
    Inventor: Scott Hunter
  • Patent number: 10182355
    Abstract: A method for testing an air interface device by simulating multi-UE uplink virtual MIMO includes receiving, by a multi-UE simulator, a downlink signal transmission from an air interface device under test. The method further includes decoding, by the multi-UE simulator, the downlink signal transmission to identify simulated UEs with uplink resource block grants. The method further includes assigning, by the multi-UE simulator, uplink data transmissions for the simulated UEs with uplink resource block grants to antennas or cables such that uplink data transmissions for simulated UEs with overlapping uplink resource block grants are assigned to different antennas or cables. The method further includes testing, by the multi-UE simulator, uplink virtual MIMO processing capability of the air interface device under test by generating and transmitting uplink signals from the simulated UEs with the overlapping uplink resource block grants to the air interface device under test using the different antennas or cables.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: January 15, 2019
    Assignee: KEYSIGHT TECHNOLOGIES, INC.
    Inventors: Zhiyong Yan, Roger Alan Slyk
  • Patent number: 10176285
    Abstract: The present disclosure relates to a method for electronic design verification. Embodiments may include receiving, using at least one processor, an electronic design and identifying at least one property violation associated with the electronic design. Embodiments may further include generating a sensitivity path from an input to the at least one property violation. Embodiments may also include analyzing the electronic design to identify one or more of a portion of the electronic design that caused the at least one property violation, a portion of the electronic design that did not cause the at least one property violation, and a portion of the electronic design that has not been analyzed. Embodiments may further include applying at least one of a depth analysis and a breadth analysis to the sensitivity path.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: January 8, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventor: Lars Lundgren
  • Patent number: 10177049
    Abstract: Techniques for measuring and testing a semiconductor wafer during semiconductor device fabrication include designating a test area on the top surface of the wafer and etching a first rectangular trench and a second rectangular trench on the top surface of the wafer in the test area. The trenches are oriented such that a length of the first trench is perpendicular to a length of the second trench, and positioned such that the length of the first trench, if extended, intersects the length of the second trench. A silicon-germanium compound is deposited into the first trench and the second trench, and a test pad is removed from the test area of the wafer. The test pad includes a side surface where both the first trench and the second trench are exposed. The side surface of the test pad is scanned with a transmission electron microscope to take measurements of the silicon-germanium.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: January 8, 2019
    Assignee: SHANGHAI HUALI MICROELECTRONICS CORPORATION
    Inventors: Haifeng Zhou, Jun Tan
  • Patent number: 10176078
    Abstract: The present disclosure relates to a system and method for capturing log messages in a post-processing debugging environment. Embodiments may include receiving a processor model associated with an electronic design and generating, using one or more processors and the processor model, a complete view of the state of the memory. Embodiments may further include writing, using one or more processors and the processor model, a log message whenever a designated message logging function is reached within the complete view of the state of the memory.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: January 8, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Vincent Motel, Andrew Robert Wilmot, Tal Tabakman, Yonatan Ashkenazi
  • Patent number: 10169545
    Abstract: Improved computer-implemented tools for use in modeling/simulating spatial charge distributions for electrophysiological systems are provided. The improvements are in three areas: (1) the use of solid angles to calculate quantities of free charge and/or bound charge in calculation cells and/or the movement of quantities of free charge across one or more faces of a calculation cell; (2) the use of flattened calculations cells having only two faces with substantial areas as seen from the free charge and/or the bound charge of the electrophysiological system; and (3) the use of at least two spatial charge distributions, specifically, at least one for bound charge and at least one for free charge, so as to include the effects of relative dielectric constants greater than 1.0 for part or all of an electrophysiological system. The three improvements can be used individually or in combinations.
    Type: Grant
    Filed: April 13, 2016
    Date of Patent: January 1, 2019
    Inventor: Maurice M. Klee
  • Patent number: 10164859
    Abstract: A method for implementing software application monitoring techniques is provided.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: December 25, 2018
    Assignee: salesforce.com, inc.
    Inventors: Christopher Patrick McNair, Tuhin Kanti Sharma
  • Patent number: 10164997
    Abstract: A first computer is selected for testing. Information sent from a second computer system to the first computer is intercepted. The information is modified to be noncompliant with a communication protocol, thereby producing noncompliant information. A determination is made whether the first computer device has failed to provide a particular response to receipt of the noncompliant information, and an operation is performed based at least in part on the determination.
    Type: Grant
    Filed: February 1, 2017
    Date of Patent: December 25, 2018
    Assignee: Amazon Technologies, Inc.
    Inventors: Nima Sharifi Mehr, Christopher Dunn, Alexis Floyd, David James Kane-Parry, Volker Helmut Mosthaf, Christopher Gordon Williams
  • Patent number: 10152305
    Abstract: Composite virtual service models can be defined to model various business transactions. A request of a particular component in a first transaction is identified and a composite virtual service model can be identified that corresponds to the particular component. The composite virtual service model models a plurality of transactions comprising the first transaction between the particular component and a first component and a second transaction between the particular component and a second component. The composite virtual service model defines a correlation between the first transaction and the second transaction. A first synthetic response is generated from the composite virtual service model based at least in part on the request, the first synthetic response simulating a response of the first component. A second synthetic response is generated from the composite virtual service model based at least in part on the correlation to simulate a response of the second component.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: December 11, 2018
    Assignee: CA, Inc.
    Inventors: John J. Michelsen, Christopher C. Kraus
  • Patent number: 10146942
    Abstract: Data to be stored at a firmware memory is received. A random symmetric encryption key is generated. The data is encrypted using the generated key to provide encrypted data. The encrypted data and the encryption key are both stored at the firmware memory.
    Type: Grant
    Filed: February 24, 2015
    Date of Patent: December 4, 2018
    Assignee: Dell Products, LP
    Inventors: Ricardo L. Martinez, Allen C. Wynn, Richard M. Tonry
  • Patent number: 10140396
    Abstract: A circuit is simulated by using distributed computing to obtain a real solution. The circuit may be an entire integrated circuit, portion of an integrated circuit, or a circuit block. A circuit simulation technique of the invention generates a system graph, finds a tree, and partitions the tree into two or more subtrees. The technique identifies global links and local links in the graph. Each subtree may be solved individually using distributed, parallel computing (e.g., using multiple processor cores or multiple processors). Using the results for the subtrees, the technique obtains a real solution, branch voltages and currents, for the circuit.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: November 27, 2018
    Assignee: Worldwide Pro Ltd.
    Inventor: William Wai Yan Ho
  • Patent number: 10140199
    Abstract: Systems, methods, computer-readable media, and apparatuses for identifying and executing one or more interactive condition evaluation tests to generate an output are provided. In some examples, user information may be received by a system and one or more interactive condition evaluation tests may be identified. An instruction may be transmitted to a computing device of a user and executed on the computing device to enable functionality of one or more sensors that may be used in the identified tests. A user interface may be generated including instructions for executing the identified tests. Upon initiating a test, data may be collected from one or more sensors in the computing device. The data collected may be transmitted to the system and may be processed using one or more machine learning datasets to generate an output.
    Type: Grant
    Filed: October 6, 2017
    Date of Patent: November 27, 2018
    Assignee: Allstate Insurance Company
    Inventors: John Rugel, Brian Stricker, Howard Hayes
  • Patent number: 10141087
    Abstract: The wiring harness production mounting, includes: at least one screen for displaying data aiding in the production of wiring harnesses, and at least one attachment surface associated with the at least one display screen, the at least one attachment surface being configured to receive at least one cable-routing element.
    Type: Grant
    Filed: May 2, 2014
    Date of Patent: November 27, 2018
    Assignee: LASELEC
    Inventors: Stephane Rougier, Michel Viault
  • Patent number: 10140412
    Abstract: A timing-matching method, executed by a timing analyzer, that includes computing a slew or load of a cell, determining whether the slew or load exists in an extrapolation region of a standard cell look-up table, and swapping the cell with a virtual standard cell of a virtual standard cell look-up table when the slew or load exists in the extrapolation region.
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: November 27, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Inyoul Lee, Jye-Hak Lee
  • Patent number: 10140414
    Abstract: A method and system to identify a region of a design block of an integrated circuit for redesign are described. The method includes dividing the design block into grids, each of the grids including a corresponding number of logic elements. The method also includes filtering each of the grids based on a specified criteria, the filtering including determining a number (B) of the corresponding logic elements among a total number (A) of the logic elements in each grid that meet the specified criteria. The region is a set of two or more of the grids based on a result of the filtering.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: November 27, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: George Antony, Christopher J. Berry, Ricardo H. Nigaglioni, Sridhar H. Rangarajan, Sourav Saha, Vinay K. Singh
  • Patent number: 10133835
    Abstract: A system and method are provided for reducing processing time in characterizing a programmably implemented cell. The cell is decomposed into a plurality of channel connected component portions (CCC's), each including a local output node and at least one switching device establishing a conduction channel within a channel path extending from the local output node to a power plane of the cell. A component characteristic function is generated for each CCC, which logically sums a locus of vectors for nodes electrically connected to the local output node. Each CCC's component characteristic function is expanded to form a local characteristic function relative to one or more other upstream CCC. Each local characteristic function is thereby formed exclusive of any upstream local output node electrically disconnected from its local output node. At least one feasible vector is selectively generated from the local characteristic functions according to requirements predefined for a parametric measurement.
    Type: Grant
    Filed: December 6, 2013
    Date of Patent: November 20, 2018
    Assignee: Cadence Design Systems, Inc.
    Inventor: Robert MacDonald
  • Patent number: 10120965
    Abstract: A disclosed system of an emulation environment performs a simulation to construct a waveform of a target signal based on signals traced by an emulator for a time frame including multiple clock cycles. In one embodiment, a simulation is performed in a manner that an input of the logic gate, in a first duration of the time frame at which an output of the logic gate depends on the input, is analyzed to obtain the output, and the input of the logic gate, in a second duration of the time frame at which the output of the logic gate is independent, is omitted. In one aspect, the input of the logic gate is simulated for the first duration based on a periodicity in a waveform of the input in the first duration.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: November 6, 2018
    Assignee: Synopsys, Inc.
    Inventors: Johnson Adaikalasamy, Gagan Vishal Jain, Stanislav Margolin
  • Patent number: 10120708
    Abstract: Systems and methods for configuring a virtual machine provided by a remote computing system based on the availability of one or more remote computing resources and respective corresponding prices of the one or more remote computing resources.
    Type: Grant
    Filed: January 18, 2016
    Date of Patent: November 6, 2018
    Assignee: Amazon Technologies, Inc.
    Inventor: Rajan Panchapakesan
  • Patent number: 10120785
    Abstract: An automatic test generator (ATG) parses a computer-executable design model of operational software of an aircraft electronic device to identify design model data coupling and design model control coupling between functional modules of the design model. The ATG generates a plurality of test conditions configured to test whether the operational software of the aircraft electronic device satisfies the design model data coupling and the design model control coupling. A test procedure that implements the plurality of test conditions is generated. The test procedure is executed on the operational software of the aircraft electronic device. An indication of whether the operational software of the aircraft electronic device satisfies each respective one of the plurality of test conditions is output.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: November 6, 2018
    Assignee: Rosemount Aerospace Inc.
    Inventor: Scott C. Meyers
  • Patent number: 10114847
    Abstract: A computer implemented method includes monitoring blocks of data on a storage device that are changing as the computer operates. On detecting a computer shut down event, a copy of changes to the monitored blocks are saved. Upon startup of the computer, a backup of the changed blocks of data is performed.
    Type: Grant
    Filed: October 4, 2010
    Date of Patent: October 30, 2018
    Assignee: CA, Inc.
    Inventors: Pratap Karonde, Prashant Parikh
  • Patent number: 10102101
    Abstract: Methods, systems, and computer readable mediums for determining a system performance indicator representative of the overall operation of a network system are disclosed. According to one example, a method includes obtaining, from a plurality of infrastructure elements included in a network system, performance metric data associated with a plurality of application processes being executed by the plurality of infrastructure elements. The method further includes consolidating analogous portions of the performance metric data into a plurality of performance metric data groups irrespective of the plurality of infrastructure elements and utilizing the plurality of performance metric data groups to determine a system performance indicator (SPI) value that represents an overall performance level of the network system.
    Type: Grant
    Filed: May 28, 2014
    Date of Patent: October 16, 2018
    Assignee: VCE IP HOLDING COMPANY LLC
    Inventor: Srinivasa Rao Velaga
  • Patent number: 10097372
    Abstract: A method for resource optimized network virtualization overlay transport in a virtualized data center environment includes an optimized virtualized transport mechanism based on MPLS-TP tunneling technology. The transport mechanism may include a usage monitoring and resource usage advertisement mechanism based on IGP-TE protocol extension. Also, the transport mechanism may include a path computation engine (PCE) based optimal path computation for a virtualized transport tunnel used to carry VM-to-VM traffic across the virtualized data center. Additionally, the transport mechanism may include a SDN controller for provisioning and control of virtualized machines and a virtualized transport system.
    Type: Grant
    Filed: January 9, 2014
    Date of Patent: October 9, 2018
    Assignee: Ciena Corporation
    Inventors: Somen Bhattacharya, Jaffar Hameed Abdul Kather Jilani
  • Patent number: 10095821
    Abstract: Electronic design automation systems, methods, and computer readable media are presented for the generation of power-related connectivity data by an analog simulator (for example, by propagating the power supply data and/or ground data through the circuit components of the analog design schematic). In some embodiments, the verification module determines consistency between different versions of power-related connectivity data, such as: (i) power-related connectivity data from the analog design schematic and (ii) power-related connectivity data from the power-related data characterizing the mixed-signal design. Such verification determines whether the mixed-signal design satisfies the low power specification as expressed in the power-related data characterizing the mixed-signal design.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: October 9, 2018
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Qingyu Lin, Nan Zhang, Kun Zhang
  • Patent number: 10094875
    Abstract: Disclosed are techniques for implementing graph-driven verification and debugging of an electronic design. These techniques identify a pair of interest that comprises a target signal and a clock cycle or an event associated with the target signal from a verification or simulation result of an electronic design or a portion thereof. A boundary for relevant driver identification (RDI) operations may be identified for normal termination of the performance of one or more RDI operations. A debug graph may then be generated and stored at least by performing one or more RDI operations for at least the pair of interest based in whole or in part upon the boundary for RDI operations.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: October 9, 2018
    Assignee: Cadence Design Systems, Inc.
    Inventors: Chien-Liang Lin, Andrea Iabrudi Tavares, Chung-Wah Norris Ip
  • Patent number: 10074055
    Abstract: In an approach to assisting database management, a computer generates one or more combinations of values of one or more database configuration parameters. The computer associates each of the one or more generated combinations of values with an incident probability. The computer defines relationships between the one or more generated combinations and the associated incident probabilities. The computer stores the defined relationships into an object representable as a multi-dimensional matrix, whose dimensions correspond to a plurality of database configuration parameters used to generate the combinations of values. The computer traverses the object to identify a path in the matrix. The computer returns the identified path for enabling subsequent interpretation thereof as a rule for passing from a first database configuration, corresponding to the first one of the one or more generated combinations, to a second database configuration, corresponding to the second one of the one or more generated combinations.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: September 11, 2018
    Assignee: International Business Machines Corporation
    Inventors: Jasmina Bogojeska, Ioana Giurgiu, George E. Stark, Dorothea Wiesmann
  • Patent number: 10069753
    Abstract: Contention for a resource in a computer system resource is managed by measuring a resource performance metric and, for each of a selected plurality of clients (for example, virtual machines), a client performance metric. For each of the selected clients, a relationship measure, such as correlation, is determined as a function of the resource performance metric and the respective client performance metric. A degree of resource contention effect is determined for each of the selected clients as a function of the respective relationship measure, and a resource-related action is taken according to the respective relationship measures. Clients may include virtualized components contending for storage. Example metrics include functions of I/O operation counts, latency or throughput measurements, pending I/O request counts, I/O throughput relative to I/O latency, a degree of change of the respective clients' I/O behavior, etc.
    Type: Grant
    Filed: March 17, 2015
    Date of Patent: September 4, 2018
    Assignee: Cloud Physics, Inc.
    Inventors: Nohhyun Park, Carl A. Waldspurger
  • Patent number: 10061886
    Abstract: A method for fabricating a circuit comprises identifying a target on the circuit with a transitional sensitivity, determining a test pattern that stresses the target, generating a verification model at the hierarchy of the target, creating a pattern and translating the pattern into a verification assertion, running the verification with the translated pattern, determining whether the verification assertion is a possible verification assertion following the running of the verification, obtaining a state of source laches and pin inputs responsive to determining that the formal verification assertion is a possible verification assertion following the running of the formal verification, translating the formal verification assertion into a coverage event, running a simulation with the coverage event, determining whether the coverage event occurred, and creating a manufacturing test responsive to determining that the coverage event occurred.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: August 28, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: William V. Huott, Kevin M. McIvain, Samir K. Patel, Gary A. Van Huben
  • Patent number: 10055184
    Abstract: A computer-implemented method for providing card-based interfaces for enumerable datasets may include (1) identifying computing resources within a computing environment subject to a unified administration, (2) identifying a request to display the computing resources within a graphical user interface, (3) portraying each computing resource within the graphical user interface as a card that includes (i) a button interface element on a front face of the card that, when invoked, presents a radial menu of actions to perform on the computing resource, (ii) a summary description of the computing resource on the front face of the card, (iii) a flipping interface element that, when invoked, flips the card between the front face of the card and a back face of the card, and (iv) a detailed description of the computing resource on the back face of the card. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: August 21, 2018
    Assignee: Veritas Technologies LLC
    Inventors: Timothy Ferrell, Kirk Freiheit, Victor Leon Terry, II
  • Patent number: 10055256
    Abstract: A processor includes a front end and a scheduler. The front end includes circuitry to determine whether to apply an acyclical or cyclical thread assignment scheme to code received at the processor, and to, based upon a determined thread assignment scheme, assign code to a static logical thread and to a rotating logical thread. The scheduler includes circuitry to assign the static logical thread to the same physical thread upon a subsequent control flow execution of the static logical thread, and to assign the rotating logical thread to different physical threads upon different executions of instructions in the rotating logical thread.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: August 21, 2018
    Assignee: Intel Corporation
    Inventors: Sebastian Winkel, Ethan Schuchman, Tyler Sondag, Girish Venkatasubramanian
  • Patent number: 10041511
    Abstract: A pneumatic drive and a method for acquiring the power of a pneumatic drive are specified. A piston is movably disposed in a working space and coupled to a path transducer. A pressure sensor is provided for acquiring an internal pressure of the working space. An evaluation unit of the pneumatic drive is adapted to process the value of a path distance of a movement of the piston acquired by the path transducer as well as a variation of the internal pressure in the working space acquired by the pressure sensor. The variation of the internal pressure is associated with the movement of the piston in the working space. Based on these values, a power of the pneumatic drive can be determined.
    Type: Grant
    Filed: April 10, 2014
    Date of Patent: August 7, 2018
    Assignee: BÜRKERT WERKE GMBH
    Inventors: Klaus Beck, Sebastian Frank, Andreas Ungerer
  • Patent number: 10036964
    Abstract: Prediction based systems and methods for optimizing wafer chucking and lithography control are disclosed. Distortions predicted to occur when a wafer is chucked by a chucking device are calculated and are utilized to control chucking parameters of the chucking device. Chucking parameters may include chucking pressures and chucking sequences. In addition, predicted distortions may also be utilized to facilitate application of anticipatory corrections. Controlling chucking parameters and/or applying anticipatory corrections help reducing or minimizing overlay errors.
    Type: Grant
    Filed: March 12, 2015
    Date of Patent: July 31, 2018
    Assignee: KLA-Tencor Corporation
    Inventors: Bin-Ming Benjamin Tsai, Oreste Donzella, Pradeep Vukkadala, Jaydeep Sinha
  • Patent number: 10032124
    Abstract: Case management systems and techniques are disclosed. In various embodiments, a hierarchical permission model is received, comprising for each of at least a subset of case nodes comprising a hierarchical data model associated with a case model a corresponding set of case roles to be afforded permissions with respect to that case node and for each such case role a set of permissions to be associated with that case role with respect to that case node. The hierarchical permission model is used to enforce with respect to one or more case instances associated with the case model the permissions defined in the hierarchical permission model.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: July 24, 2018
    Assignee: Open Text Corporation
    Inventors: Satyapal P. Reddy, Jeroen Van Rotterdam, Muthukumarappa Jayakumar, Michael T. Mohen, Ravikumar Meenakshisundaram