Abstract: A method may include receiving a first selection via a user interface comprising a hardware configuration for a simulated computer storage system, the hardware configuration including a plurality of hardware components. The method may also include receiving a second selection via the user interface comprising a storage configuration for the plurality of hardware components of the simulated computer storage system. Further, the method may include creating a storage configuration template utilizing the storage configuration. Additionally, the method may include associating the plurality of hardware components of the simulated computer storage system with the storage configuration template. Further, the method may include storing the plurality of hardware components of the simulated computer storage system and the associated storage configuration template.

Abstract: A system and method are provided including an interface circuit in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the plurality of memory circuits and the system for simulating at leas one memory circuit with at least one aspect that is different from at least one aspect of at least one of the plurality of memory circuits. The interface circuit is further operable to control refreshing of the plurality of memory circuits.

Abstract: A method for computing includes specifying a data processing system using a logical system definition, which defines logical system components having respective functionalities and a topology for interconnecting the logical system components. The logical system components are represented using respective logical objects in a hierarchical object model. Physical resources of a grid computer system are represented using physical objects in the hierarchical object model. The logical objects are automatically mapped to at least some of the physical objects, so as to allocate the physical resources to carry out the respective functionalities of the logical system components. The allocated physical resources are configured and activated so as to cause the grid computer system to function as the data processing system, in accordance with the logical system definition.

Abstract: A computer-implemented method, system and computer program product are presented for managing an Effective-to-Real Address Table (ERAT) and a Translation Lookaside Buffer (TLB) during test verification in a simulated densely threaded Network On a Chip (NOC). The ERAT and TLB are stripped out of the computer simulation before executing a test program. When the test program experiences an inevitable ERAT-miss and/or TLB-miss, an interrupt handler walks a page table until the requisite page for re-populating the ERAT and TLB is located.

Abstract: A simulation system includes a simulation interface and a virtual controller coupled to the simulation interface. The virtual controller includes an application layer that receives application layer inputs and provides outputs to the simulation interface and an input/output (I/O) layer coupled to the system model and the application layer. The I/O layer includes one or more I/O module models that receive the system model outputs and creates the application layer inputs in the same or similar manner as an I/O module in the system being simulated.

Abstract: Embodiments of apparatuses and methods for processing virtualization events in a layered virtualization architecture are disclosed. In one embodiment, an apparatus includes a event logic and evaluation logic. The event logic is to recognize a virtualization event. The evaluation logic is to determine whether to transfer control from a child guest to a parent guest in response to the virtualization event.

Abstract: A simulation model of BT instability of a transistor in a semiconductor integrated circuit, wherein a bias condition of at least one terminal among the drain terminal, the source terminal and the substrate terminal of the transistor is set up as an independent bias condition from other terminals; and then a model parameter of the transistor is changed in the set bias condition.

Abstract: Method, system and computer program product for estimating the overall energy efficiency of a data center over a period of time. In one embodiment, a computer processor coupled to computer readable memory is configured to receive time parameters indicating the period of time over which the overall energy efficiency of the data center is to be estimated, receive component parameters indicating the performance characteristics of data center components and the operational interactions between the data center components, simulate the operation and interaction of the data center components based, at least in part, on the component parameters for the period of time over which the energy efficiency is estimated, and output results of the simulation to estimate the overall energy efficiency of the data center.

Abstract: Systems and methods are provided for concurrently emulating multiple channel impairments. The systems and methods may include storing a plurality of channel impairment profiles, where each channel impairment profile corresponds to a respective channel impairment type; receiving a selection of two or more of the plurality of channel profiles; generating a composite impairment profile by combining the selected two or more channel profiles, the composite profile specifying time-variant impairments, the composite profile reflecting a combination of the respective impairment types of the selected channel profiles; and applying the time-variant impairments specified by the composite profile to an input real-time data stream to generate an impaired real-time data stream, where a timing of the application of the time-variant impairments is based at least in part upon timing data from a real-time clock.

Abstract: A high-level integrated circuit (“IC”) modeling system (400) includes a first co-simulator (418) modeling a first portion of an IC system and a second co-simulator (419) modeling a second portion of the IC system, each co-simulator operating according to initial simulation operating conditions (426). A co-simulation synchronization interface (424) is configured to automatically change at least one of the initial simulation operating conditions to a triggered operating condition (428) in response to a user-selected triggering signal.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for emulating a mass storage device and a file system of a mass storage device. In a first aspect, a human-portable data processing device that includes one or more data processors that perform operations in accordance with machine-readable instructions, an incoming message classifier configured to classify an incoming read command according to an address of the data requested by the incoming read command, and an emulation data generation component connected to respond to the classification of the incoming read command by the incoming message classifier to generate emulation data emulating that which would have been read by the incoming read command were the human-portable data processing device a mass storage device; and a bus controller configured to respond to the incoming read command with the emulation data generated by the emulation data generation component.

Abstract: The present invention provides a system model management and support system that is capable of facilitating the management of a system model by identifying any difference between the system model and a real system. Conversion means 6 converts configuration information indicative of the configuration and settings of the real system into a model having the same expression form as the system model. The real system is actually operated as a system. The system model is used as a model representing the real system during the development of the real system. Difference extraction means 7 extracts any difference between the system model and the model converted from the configuration information by comparing the system model with the model converted from the configuration information.

Abstract: Modeling systems and methods for constructing one or more models of a computing system using collected data. Certain model-based systems build topology models and/or model instances by transforming collected performance data into a collection-location independent form. In certain examples, systems include at least one agent for collecting performance data from monitored resource(s), canonical data transform (CDT) configurations, and a data transformation module for performing data transform operation(s) on the performance data based on at least one CDT configuration. The data transform operation may include generating and/or updating a topology model, assigning metrics to model object(s), updating properties of model object(s), creating associations between existing model objects, or the like. Certain systems and methods also allow for a single piece of data to be processed by multiple models or for pieces of data collected from different locations to be matched and/or associated with the same model object.

Abstract: A method for building a magnetic bead mathematical model includes defining component elements of the model of the magnetic bead, building the model of the magnetic bead, obtaining a characteristic curve of an impedance of a magnetic bead in a standard magnetic bead specification of the magnetic bead, ascertaining parameters of the component elements, simulating the model of the magnetic bead, and comparing the characteristic curve with the characteristic curve in the standard magnetic bead specification, to further optimize the mode of the magnetic bead.

Abstract: A method and system for determining benefits of outsourcing is provided in a computer system. The method includes calculating on the computer system a first set of resource requirements to conduct one or more of a plurality of processes within an entity. The first set of resource requirements are calculated by performing a predefined set of computations on a set of data associated with the entity. The method further includes simulating on the computer system a second set of resources requirements to conduct one or more of the plurality of processes using one or more offshore personnel. The method further includes rendering on the computer system one or more benefits of using the one or more offshore personnel based on the first set of resource requirements and the second set of resource requirements.

Abstract: A memory circuit system and method are provided in the context of various embodiments. In one embodiment, an interface circuit remains in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for performing various functionality (e.g. power management, simulation/emulation, etc.).

Abstract: Simulating a large number of users is described. A method may include receiving a test script including a plurality of commands and invoking a script interpreter. An application thread may be launched to execute the test script. A protocol engine may be invoked for each of the commands in the test script such that each protocol engine has an associated command. Each protocol engine may execute its associated command. A system on which the method may be executed may include one or more chassis or computing devices having one or more network cards. The chassis and/or computing devices may be connected to one or more networks.

Abstract: A system and method for managing a storage array using simulation is disclosed. In one example embodiment, in a computer implemented method for managing a storage array using simulation, a virtual storage array, including a plurality of virtual storage array objects, associated with a physical storage array is generated using a storage array simulator residing in a storage array management server. Then, configuration changes are performed on the virtual storage array to form a desired virtual storage array to simulate presence of changed storage array without underlying hardware using the storage array simulator. Performance of the formed desired virtual storage array is determined without the underlying hardware of the storage array using the storage array simulator. The desired virtual storage array including the plurality of virtual storage array objects is uploaded to the associated physical storage array based on the outcome of determination.

Abstract: A development system for developing new peripheral software code for new peripheral hardware that will be used in a new integrated system. The development system includes a legacy, or preexisting, integrated system substantially the same as the new integrated system. A model of the new peripheral hardware is made. Each I/O register of the model is mapped into memory-mapped I/O space. Development code corresponding to the new peripheral software code is executed on the preexisting hardware so as to interact with the model via the memory-mapped I/O space. In one embodiment, the model is executed as an embedded model on the preexisting integrated system. In another embodiment, the model is executed as a non-embedded model on a hardware descriptive language simulator.

Abstract: A correlation model which is appropriate for a system analysis can be generated with respect to each of fixed periods such as the dates on which the system analysis is performed, even if the information on modeling periods with respect to system characteristics is not available. A correlation model generation unit 102 generates a plurality of correlation models 122 each expressing correlations between different types of performance values in a predetermined period, which are stored in a performance information unit 111.

Abstract: The present invention discloses a cycle-count-accurate (CCA) processor modeling, which can achieve high simulation speeds while maintaining timing accuracy of the system simulation. The CCA processor modeling includes a pipeline subsystem model and a cache subsystem model with accurate cycle with accurate cycle count information and guarantees accurate timing and functional behaviors on processor interface. The CCA processor modeling further includes a branch predictor and a bus interface (BIF) to predict the branch of pipeline execution behavior (PEB) and to simulate the data accesses between the processor and the external components via an external bus, respectively. The experimental results show that the CCA processor modeling performs 50 times faster than the corresponding Cycle-accurate (CA) model while providing the same cycle count information as the target RTL model.

Abstract: Distributed hardware device simulation, including: identifying a plurality of hardware components of the hardware device; providing software components simulating the functionality of each hardware component, wherein the software components are installed on compute nodes of a distributed processing system; receiving, in at least one of the software components, one or more messages representing an input to the hardware component; simulating the operation of the hardware component with the software component, thereby generating an output of the software component representing the output of the hardware component; and sending, from the software component to at least one other software component, one or more messages representing the output of the hardware component.

Abstract: A method and mechanism for implementing a general purpose scripting language that supports parallel execution is described. In one approach, parallel execution is provided in a seamless and high-level approach rather than requiring or expecting a user to have low-level programming expertise with parallel processing languages/functions. Also described is a system and method for performing circuit simulation. The present approach provides methods and systems that create reusable and independent measurements for use with circuit simulators. Also disclosed are parallelizable measurements having looping constructs that can be run without interference between parallel iterations. Reusability is enhanced by having parameterized measurements. Revisions and history of the operating parameters of circuit designs subject to simulation are tracked.

Abstract: A mechanism is provided for determining fragmentation in a computing environment. A simulation of virtual machine requests for resources in the computing environment is run for a predetermined time. The simulation is scaled down when the predetermined time exceeds a threshold. The scaling down includes scaling down the resources in the computing environment and/or scaling down a number of the virtual machine requests. The scaled down simulation is run iteratively to estimate relative fragmentation of the virtual machine requests against the resources in the computing environment.

Abstract: A system receives a model, internals associated with a target processor, and code information associated with the target processor, and obtains a bit-true model simulation for the target processor based on the model, the target processor internals, and the target processor code information.

Abstract: Provided herein are methods and apparatuses for certifying computers for use in conjunction with medical devices. These methods may be used in conjunction with a computer that includes software for operating the medical device. To certify a particular computer, one or more testing algorithms or routines for processing data, e.g., data representative of a typical output generated by use of the medical device on a patient, may be executed and the results may be compared to an expected result. In particular embodiments, the certification process may use data stored on the device itself to determine certification or may use data stored with or bundled with the software for operating the device.

Abstract: Embodiments include methods, apparatus, and systems for monitoring windows on computers. In one embodiment, movement of a mouse or cursor in a focused window of the computer is analyzed to determine whether an application is properly executing in the computer.

Abstract: In some embodiments if a transaction is directed at existing hardware, then the transaction is directed to existing hardware. If the transaction is not directed at existing hardware, then the transaction is sent through a behavioral model. Other embodiments are described and claimed.

Abstract: A memory circuit system and method are provided in the context of various embodiments. In one embodiment, an interface circuit remains in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for performing various functionality (e.g. power management, simulation/emulation, etc.).

Abstract: A simulation apparatus and method for a multicore system are provided. The simulation apparatus may prevent the occurrence of a data collision during the communication between modules and may reduce the overhead generated during simulation. The simulation apparatus may select a plurality of modules to be synchronized in terms of function execution timing based on timing information and may configure a multicore system architecture model using the selected modules. The simulation apparatus may acquire function execution timing information of the modules, control the execution of functions by the modules based on the acquired function execution timing information, and output the results of the control of the execution of functions by the modules.

Abstract: Methods, devices, and systems are disclosed for simulating a large, realistic computer network. Virtual actors statistically emulate the behaviors of humans using networked devices or responses and automatic functions of networked equipment, and their stochastic actions are queued in buffer pools by a behavioral engine. An abstract machine engine creates the minimal interfaces needed for each actor, and the interfaces then communicate persistently over a network with each other and real and virtual network resources to form realistic network traffic. The network can respond to outside stimuli, such as a network mapping application, by responding with false views of the network in order to spoof hackers, and the actors can respond by altering a software defined network upon which they operate.

Abstract: In an embodiment, a graphical model may include a functional portion and a architectural portion. The architectural portion may describe a multiprocessor system. Inter-process communication blocks may be defined that describe the connectivity of functional blocks in the deployed version of the model. The IPC blocks may describe the connectivity of the blocks independent of the communication channel(s) that connect the processor nodes in the multiprocessor system.

Abstract: A power testing apparatus for a USB interface includes first and second USB interfaces, and a simulation apparatus. The simulation apparatus includes a first voltage regulator, first and second resistors, and a load resistor. The first USB interface is configured to connect to a circuit board. The second USB interface is configured to connect to a USB device. The first voltage regulator includes input, output, and adjusting terminals. The first resistor is connected between the output terminal and the adjusting terminal. The second resistor is connected between the adjusting terminal and ground. The load resistor is connected to the output terminal and ground. Signal pins of the first USB interface are connected to signal pins of the second USB interface. A voltage pin of the first USB interface is connected to a voltage pin of the second USB interface and the input terminal.

Abstract: A plant monitoring and control apparatus having a function to simulate an object to be monitored and controlled for verifying healthiness of a control processing unit is provided with an input separating operation unit and an output separating operation unit which separate DI data and DO data handled by the control processing unit by transforming the DI data and the DO data into a label format differing from a label format of PDI data and PDO data which are related to input and output between the object to be monitored and controlled and the plant monitoring and control apparatus. In test mode, a switching unit switches an input device of the control processing unit and an output device thereof to a simulator unit provided within the plant monitoring and control apparatus.

Abstract: Method and system for processing a management operation command received from a management entity is provided. The management operation command is received by an emulation module for a switch element operationally coupled to the management entity. The switch element includes a plurality of ports, each port having a plurality of components designated as managements devices. The emulation module determines if identification information for a management device in the command matches with identification information stored by the switch element to emulate the management device. If the information matches, then the management operation identified in the management operation command is performed by the emulation module interfacing with a switch element processor.

Abstract: A method for managing error information of a printed circuit board layout system is provided. The system provides an error file recording names of all the errors to be displayed in wiring diagrams, generates wiring diagram files, outputs a first user interface showing one wiring diagram. Each of the wiring diagram files includes an attribute table for describing error information. The attribute table comprises the names and the set of coordinates. The method comprises obtaining the error file and the attribute table, outputting a second user interface comprising a first display area and a second display area, outputting the name in the first display area, analyzing the obtained attribute table to provide a classifying table. Then outputting one selected name and at least one set of coordinates corresponding to the one selected name in the second display area according to the classifying table. A related system is also provided.

Abstract: Disclosed is a simulation apparatus for accident reduction measures which is capable of supporting the determination of measures to be applied. This apparatus (100) is a simulation apparatus for accident reduction measures in order to consider addition of an incidental facility on a road for the purpose of decreasing the number of accidents, and the apparatus includes: search section (160) that searches similar roads having a structure similar to that of a target road for consideration; and search result display section (190) that displays accident-related information on the similar roads searched by search section (160), so as to correspond to incidental facility statuses of the similar roads, wherein search result display section (190) displays the accident-related information to be comparable, relative to a plurality of different incidental facility statuses.

Abstract: A user interface to a network simulator facilitates the use of application layer parameters and application layer logic. The user interface is configured to allow the user to define the input in a graphic form, or a text/programming form, or a combination of both. Preferably, the user interface provides common graphic forms for both inputting the data to the simulator as well as for displaying the resultant data from the simulator, thereby easing the progression from the analysis of output from one simulation to the generation of new input for a subsequent simulation.

Abstract: A modeling system includes a processor with software that performs static timing analysis (STA) on a design model. STA software executes a static timing analysis (STA) run with shortened clock cycles to model full cycle clock variability. Designers or other entities interpret the results of the shortened STA run data by performing modeling on the output data to generate slack data for design model data paths. STA software executes an STA run with an extended clock cycle to automatically separate half cycle data path (HCDP) slack data from full cycle data path (FCDP) slack data. The full and half cycle clock variability method may automatically adjust slack data for all half cycle data paths (HCDP)s to account for the additional half cycle variation (AHCV) and half cycle clock edge variability that may penalize the design model results in a real hardware implementation.

Abstract: The cost necessary for introducing and maintaining a development environment that includes multiple simulators is suppressed, and a sharing of designing information is promoted, to make parameter adjustment of simulators easy. Provided is a service that unifies development environment on a computer provided with: a working computer system that can guarantee that there is no leaking of designing files; a user behavior monitoring system that collects utilization history of simulators or software, for each of the users, and selects development process of each of the users from the collected information; and a dynamic computational-resource distribution system that can conduct an automatic optimization of a complex simulation configuration, from information collected by the aforementioned user behavior monitoring system.

Abstract: An embodiment of a simulation tool includes a path determiner and a simulator. The path determiner is configured to identify a first communication path between first and second devices of a system, and the simulator is configured to simulate a routing of a first item from one of the first and second devices to the other of the first and second devices via the identified path. The path determiner may also be configured to identify the communication path before the simulator simulates the routing of the item, or to identify the communication path while the simulator is inactive.

Abstract: The disclosure includes a method of and associated system for placing nodes in a wireless local area network (WLAN). The method includes receiving user-specified parameters regarding the network. The parameters can include a layout of a building or other space, and requirements for the WLAN. An algorithm then employs these parameters to automatically create and optimized layout of multiple wireless access points for the WLAN. The method can display the layout and provide various types of information to the user.

Abstract: A method includes obtaining at least one measurement of one or more controlled variables associated with an industrial process. The method also includes obtaining a linearized approximation of a process model representing the industrial process. The method further includes estimating a state of the industrial process using the at least one measurement, the linearized approximation, and a window-based state estimator. The method also includes generating at least one control signal for adjusting one or more manipulated variables associated with the industrial process. Generating the at least one control signal includes using the estimated state and model predictive control (MPC) logic. In addition, the method includes outputting the at least one control signal.

Abstract: In a method for generating a resource management plan for an infrastructure, a resource supply available from a combination of resource sources is determined, an operation of the infrastructure in performing an objective using the determined supply of resources is simulated, in which the simulation is to simulate resource demand of a plurality of infrastructure components in performing the objective, a metric(s) associated with operating the infrastructure based upon the simulation is determined, a determination as to whether the metric(s) satisfies a predetermined goal(s) is made, the resources supplied and/or the simulation of the resource demand of the plurality of infrastructure components is modified in response to the at least one metric failing to satisfy the predetermined goal(s), and a resource management plan for the infrastructure that has been determined to result in the metric(s) satisfying the predetermined goal(s) is generated.

Abstract: Load testing an online game server environment using a web-based interface includes: configuring a load test with configuration parameters including client behavior parameters and server parameters, wherein the client behavior parameters provide settings for various behaviors such as cheating and aggressiveness, and wherein the server parameters provide a setup for server states and messages; building and deploying simulation client and game server binaries; scheduling and running the load test; and collecting test data output from the load test. Keywords include load test automation, load test service, load test resource management.

Abstract: A method for modeling and simulating a system comprising first and second interrelated components is disclosed. The method comprises modeling the behavior of said first and second components using first and second specifications. Each of said first and second specifications includes a functional specification and an associated simulation element. The method further comprises simulating the behavior of said first and second components using said first and second specifications. The simulation elements communicate with one another to provide a simulation system.

Abstract: The system comprises a component model for modelling aspects of the hardware component, and feature extraction logic for extending the component model to cause the component model, when executing, to output one or more features identifying execution behavior of the component model. A statistical model is then arranged to receive the one or more features output by the component model, and to generate the output dependent on one or more features. The component model may not explicitly model features that can be used to effectively predict values of the observable property, features that a statistical model depends on may still be captured in the underlying logic and implementation of the component model. By extracting features identifying execution behavior of the component model, this can provide a suitable input to the statistical model.

Abstract: A simulation apparatus is disclosed, including a hardware simulator and a CPU model. The hardware simulator activates one or more logical hardware models for verifying embedded software. The CPU model is one of the one or more logical hardware models which imitates a CPU which executes the embedded software, and to trigger the embedded software to operate without synchronization for each of instructions.

Abstract: A reflective process algebra called the ?-calculus facilitates the serialization of processes at the level of the reflective process algebra. The reflective process algebra because of its reflective properties, can be used on computing systems with finite resources. The reflective process calculus can be made to be sensitive to resources, such as memory and bandwidth, hence facilitating its use as a programming language at the machine level. The reflective process calculus causes the dual nature of a computation entity to be exposed. A name can be caused to become a process and a process can be caused to become a name.

Abstract: An object of the present invention is to provide a simulator for verifying plural products with common hardware configuration, in which peripheral hardware that can be reused are constituted by hardware and other peripheral hardware is constituted by software simulator, and simulation method. A simulator comprises: a hardware section that includes a peripheral hardware configuration with a structure required for a CPU and OS to operate alone; a software section that simulates the operation of peripheral hardware other than hardware constituting the hardware section as a peripheral hardware model; and an interface board that connects the hardware section and software section.