Abstract: A mechanism is provided for determining a modeled age of a set of interconnect groups in a set of cores in a set of multi-core processors. For each interconnect group in the set of interconnect groups in the set of cores on the set of multi-core processors, a determination is made of a current modeled age of the interconnect group. A determination is then made as to whether at least one current modeled age of the interconnect group for the set of interconnect groups is greater than an end-of-life value. Responsive to at least one current modeled age of the interconnect group being greater than the end-of-life value, an indication to take corrective action with the at least one associated interconnect group is sent.

Abstract: A model-based virtual power management driven multi-chip system simulator generates utilization data and performance data with a workload model that models one or more types of workloads based on parameters that characterize the one or more types of workloads. The simulator generates thermal data and power consumption data with a power model that models power consumption at a chip-level and a system-level. The simulator then generates performance counter information with a performance model that models change of performance counters over time and at least one of the generated utilization data and the generated performance data as input to the performance model. The simulator provides this generated data as input to a driver of the simulator.

Abstract: A model-based virtual power management driven multi-chip system simulator generates utilization data and performance data with a workload model that models one or more types of workloads based on parameters that characterize the one or more types of workloads. The simulator generates thermal data and power consumption data with a power model that models power consumption at a chip-level and a system-level. The simulator then generates performance counter information with a performance model that models change of performance counters over time and at least one of the generated utilization data and the generated performance data as input to the performance model. The simulator provides this generated data as input to a driver of the simulator.

Abstract: Embodiments of apparatuses and methods for processing virtualization events in a layered virtualization architecture are disclosed. In one embodiment, an apparatus includes a event logic and evaluation logic. The event logic is to recognize a virtualization event. The evaluation logic is to determine whether to transfer control from a child guest to a parent guest in response to the virtualization event.

Abstract: A deployed configurable communication integrated circuit (IC) and/or chipset which may be integrated within a wireless communication and/or multi-media communication device may be operable to monitor its operating conditions, performance and/or utilization characteristics. It may send information via a wireless, optical and/or wired network to a remote analysis and/or development system and/or service, such as an engineering service, that may determine and return configuration parameters. The configuration parameters may be utilized to adjust antenna and/or MIMO, SIMO, MISO and beamforming configuration, power level, interference rejection, equalizer length, dynamic range, modulation, encoding and/or decoding, analog to digital conversion precision, error detection and/or correction parameters, MAC parameters such as timing thresholds, transmit window size and/or buffer space.

Abstract: Method, apparatus, and product for performing incremental formal verification. A computer-implemented method performed by a computerized device. The method comprises: obtaining invariants with respect to a first model; determining a portion of the invariants that are invariants with respect to a second model, and utilizing the portion of the invariants to check that the second model holds a property.

Abstract: Performance metrics related to the processing and propagation of messages related to select applications are collected during a simulation of a network. Each message associated with an application is tagged, and each simulated packet that contains some or all of a tagged message is correspondingly tagged to facilitate the creation of transmit records and receive records. A post processor is configured to collate transmit and receive records of each tagged message to identify delays associated with each node that processes the message, and each link that propagates the message from node to node within the network. The processed timing information is provided to the user via an interactive user interface that allows the user to view the timing information from an application layer perspective.

Abstract: The invention relates to a method and apparatus for simulating a system in a communications network as a linear system in order to obtain a prediction of the load of a resource in the system. Measurements obtained at m different points in time of the event intensity aevent for a number n of key events occurring in a reference system are used to form the simulation model, together with measurements of the total load L in the reference system at the m different points in time. An optimization problem, defined by the simulation model and a set of event intensities of the system-to-be-predicted in a scenario to be simulated, is solved in order to obtain a prediction of the total load of the system in the simulated scenario.

Abstract: The present invention is achieved as software which operates on a computer system and which performs calculation by receiving various data as inputs, and which outputs values. The present invention is applicable to a coarse-grained system architecture model including the foregoing event-driven simulation and receives, as inputs, execution time T and the number of memory accesses, N, in the simulation step of the model. Thus, various estimates at the occurrence of memory access conflict are obtained at a simulation speed sufficient for evaluating the effect of the memory access conflict and comparing it with many alternative architectures without information on the correct timing of memory accesses in consideration of memory synchronous accesses and arbitration. The results of this simulation are estimated simulation-step execution time T? under memory access conflict and memory-bandwidth utilization factors {U?i} in individual simulation steps under memory access conflict.

Abstract: A non-transitory tangible computer-readable medium may include instructions executable by a processor in a simulation system to perform a simulation. The instructions may include to wait for a plurality of virtual controllers to complete a previous simulation step, write a result of the previous simulation step from each of the plurality of virtual controllers to a shared memory, read an input from the memory to each of the plurality of virtual controllers, initiate a simulation step on each of the plurality of virtual controllers, and upon initiation of the simulation step in each of the plurality of virtual controllers, indicate completion of the simulation, in which the plurality of virtual controllers include a controller model having a plurality of simulation steps and the instructions are configured to be executed by the processor in parallel.

Abstract: A system and method of testing, during development, the operation of a clustered storage server system and its associated storage operating system. The system includes at least one host computer having a host operating system, and at least one virtual computer having a simulated storage operating system, at least one simulated disk, a simulated NVRAM, and a simulated flashcard within a guest operating system hosted by the host operating system. The simulated storage operating system represents an actual storage operating system. Facilities of the simulated storage operating system including the simulated disk, the simulated NVRAM, and the simulated flashcard are mapped onto corresponding facilities of the host operating system via virtualization components of the virtual computer so that the simulated storage operating system operates substantially the same as the actual storage operating system on low cost host hardware platforms.

Abstract: A method and system for detection of intrusion in networked control systems, is provided. The method includes generating an operating model of a system being controlled. The operating model of the system comprises a relationship between a plurality of components in the system defined by a plurality of parameters. Further, the method includes calculating an estimated value of at least one parameter for at least one component in the system. The operating model is used to calculate the estimated value of the at least one parameter. Furthermore, the method includes measuring a latest value of at least one parameter at a predefined interval. The method also includes triggering an alert for intrusion for the at least one component based on an analysis of at least one of the latest value and the estimated value of at least one parameter.

Abstract: A method and a system are disclosed for simulation in a substation. The method can include acquiring substation data from substation condition data and base substation record; adapting the acquired substation data to suit a target substation; and administering the adapted substation data on a communication channel of the target substation. The substation system can include a base substation which is an existing, a pre existing, or a target substation, or a substation defined by a user or any combination thereof; a substation automation system; test equipment configured to test the system and perform simulation in a target substation; and a human machine interface for interfacing the substation system with a user.

Abstract: Example embodiments provide various techniques for modeling network storage environments. To model a particular storage environment, component models that are associated with the components of the storage environment are loaded. Each component model is programmed to mathematically simulate one or more components of the storage environment. A system model is then composed from the component models and this system model is configured to simulate the storage environment.

Abstract: Method, system and computer program product for estimating the overall energy efficiency of a data center over a period of time. In one embodiment, a computer processor coupled to computer readable memory is configured to receive time parameters indicating the period of time over which the overall energy efficiency of the data center is to be estimated, receive component parameters indicating the performance characteristics of data center components and the operational interactions between the data center components, simulate the operation and interaction of the data center components based, at least in part, on the component parameters for the period of time over which the energy efficiency is estimated, and output results of the simulation to estimate the overall energy efficiency of the data center.

Abstract: Methods for classifying and correlating simulation components to functional models. A method includes receiving a simulation component library comprising a plurality of simulation components into a memory of the data processing system, parsing the plurality of simulation components from the simulation component library, analyzing a plurality of extracted functions into a plurality of function graphs for each of the plurality of simulation components, composing an extracted functions graph with the plurality of extracted functions of the plurality of function graphs, and storing the extracted functions graph of the plurality of extracted functions in a components-to-function database.

Abstract: The present invention provides a method for efficient resource-oriented power evaluation. By mapping instructions to microarchitecture components, both advantages of high-level simulation performance and fine-grained power model are obtained. The present invention effectively reduces simulation runtime overhead and provides an accurate power estimation result. The present invention is nearly as accurate as gate-level simulators, with an error rate of less than 1.2 while achieving simulation speeds of up to 20 MIPS, five orders faster than a commercial gate-level simulator. By using the present invention, it is easy to analyze power consumption profile and peak power.

Abstract: Described herein are methods, systems and machine-readable media for simulating a FIFO cache using a Bloom filter ring, which includes a plurality of Bloom filters arranged in a circular log. New elements are registered in the Bloom filter at the head of the circular log. When the Bloom filter at the head of the circular log is filled to its capacity, membership information associated with old elements in the Bloom filter at the tail of the circular log is evicted (simulating FIFO cache behavior), and the head and tail of the log are advanced. The Bloom filter ring is used to determine cache statistics (e.g., cache hit, cache miss) of a FIFO cache of various sizes. In response to simulation output specifying cache statistics for FIFO cache of various sizes, a FIFO cache is optimally sized.

Abstract: A method for modeling a test space comprising defining a coverage model including: one or more variables, wherein respective values for the variables are assigned, and restrictions based on which valid variable value combinations are determined for the purpose of testing the model, wherein at least two values that are assignable to the one or more variables are merged to reduce number of variable values in the coverage model.

Abstract: Techniques for tuning systems generate configurations that are used to test the systems to determine optimal configurations for the systems. The configurations for a system are generated to allow for effective testing of the system while remaining within budgetary and/or resource constraints. The configurations may be selected to satisfy one or more conditions on their distributions to ensure that a satisfactory set of configurations are tested. Machine learning techniques may be used to create models of systems and those models can be used to determine optimal configurations.

Abstract: At least some of the illustrative embodiments are methods including: executing a test program on a computer system coupled to a server, the test program emulating virtual users by instantiating a first user instance by calling a first reentrant function, the first user instance exiting the first reentrant function upon encountering a blocking statement in the first reentrant function; instantiating a second user instance by calling the first reentrant function, the second user instance exiting the first reentrant function upon encountering a blocking statement in the first callable function; reentering the first user instance by again calling the first reentrant function, the first reentrant function resuming execution within the reentrant function after the first blocking statement; and reentering the second user instance by calling the first reentrant function, the first reentrant function resuming execution within the reentrant function after the second blocking statement.

Abstract: A system and method are provided for simulating an aspect of a memory circuit. Included is an interface circuit that is in communication with a plurality of memory circuits and a system. Such interface circuit is operable to interface the memory circuits and the system for simulating at least one memory circuit with at least one aspect that is different from at least one aspect of at least one of the plurality of memory circuits. In accordance with various embodiments, such aspect may include a signal, a capacity, a timing, and/or a logical interface.

Abstract: Methods, systems, and computer-readable media for providing a rule based exchange simulator are presented. A plurality of rules may be received at an exchange simulator that define how orders should be processed at the exchange simulator. The received rules may be stored, for instance, at a rules engine. For example, rules may comprise a fill rule, a cancel rule, a reject rule, a no acknowledgment rule, and a market data rule. An order that comprises a stock exchange order may be received at the exchange simulator. For example, an order may comprise a buy or sell order for a particular instrument, such as a stock, and may comprise a particular quantity. Based on the one or more rules stored in the rules engine, the received order may be fully filled, partially filled, or not filled.

Abstract: A system receives a model, internals associated with a target processor, and code information associated with the target processor, and obtains a bit-true model simulation for the target processor based on the model, the target processor internals, and the target processor code information.

Abstract: In order to achieve tasks, according to an embodiment of the present invention, an arithmetic unit including one or more ASIPs includes two or more processors, and an execution unit that is connected to the two or more processors and executes instructions received from the processors. According to an embodiment of the present invention, it is possible to provide a low-power, high-integration, high-performance arithmetic unit through resource sharing using the arithmetic unit including the one or more ASIPs, and it is possible to provide a method of designing an arithmetic unit that may be applied to a specific application.

Abstract: A computer-implemented method may include receiving transition information indicative of transition rates associated with a plurality of communication links in a network, wherein the network includes a plurality of nodes, the plurality of communication links, and a communication path between a first node and a second node of the plurality of nodes. In one embodiment, the communication path uses at least two of the plurality of communication links. The method may include generating biased transition information indicative of biased transition rates, wherein the biased transition rates are greater or less than the indicated transition rates and simulating the network, based on the biased transition information, until a transition associated with one of the communication links causes the communication path to transition to a different state. A network reliability parameter may be determined based on the simulation of the network.

Abstract: Systems and methods comprise a network in which a mobile device is configured as an input/output interface for a user such that actual processing, storage and network interfaces are performed or provided by a remote server.

Abstract: A method for generating a power model for a device includes identifying a device-level set of power contributors for a given state of the device, wherein each power contributor in the device-level set of power contributors contributes to power dissipation when the device is in the given state, and generating the power model for the device based on the device-level set of power contributors, wherein the power model is independent of process, voltage, and temperature.

Abstract: A Portable Maintenance Aid (PMA) having multiple applications for the electrical testing and data acquisition for various air/ground vehicle platforms is disclosed. The PMA includes an interface adapter that has a number of electrical testing interfaces and data collection ports in addition to a stray voltage detector. The portable testing aid also includes a user interface that transmits data to the interface adapter and a display that communicates the testing and maintenance information to the user. The portable testing aid also includes a communication system for transferring information between the user interface, the display, and the interface adapter. The PMA provides a preload tester/stray voltage tester that is sustainable, less replaceable and has capability of filling the test voids.

Abstract: According to exemplary embodiments, a computer implemented method for functional testing of a processor design includes accessing a test template from a library of test templates, wherein the test template is configured to test a first selected function of the processor and inputting the test template to an automated test generation tool executed by a computer. The method further includes generating an instruction sequence based on the test template by the automated test generation tool and injecting an event instruction to the instruction sequence during the generating of the instruction sequence by the automated test generation tool, the injecting of the event instruction preserving testing of the first selected function of the processor and the event instruction being configured to test a second selected function of the processor. The method includes verifying a function of the processor by analyzing responses of the processor to the instruction sequence.

Abstract: Executing a simulation of a computer platform, the simulation including simulation models. A dynamic quantum is accessed whose current value specifies a maximum number of units of execution a simulation model is allowed to perform without synchronizing with another simulation model. The dynamic quantum may be received from a user. Respective simulation models are invoked for execution with the current value of the dynamic quantum provided to each of the simulation models. The method also comprises modifying the value of the dynamic quantum based on a simulation event.

Abstract: A system includes tracing logic to parse trace information into time varying segments and model traces based on segments of time varying I/O (input/output) and/or workload behavior. The logic can detect segments that represent statistically similar system behavior and reduce the number of segments based on detecting segments representing similar system behavior. The logic can leverage Mutual Information techniques to eliminate redundant workload dimensions and build a concise workload model. The logic can also use HAC to segregate similar workload patterns represented by multiple non-redundant workload attributes. The logic can use ePDF to regenerate distributions of workload attribute values during trace regeneration. The logic can generate segment models from the segments, which can be combined into a test trace that represents a period of system behavior for simulation.

Abstract: An ECU (Electronic Control Unit) evaluation apparatus, for use in vehicle design, allocates functions appropriately to respective ECUs of a vehicle. The function allocation can be performed based on user-specified priority aspect(s) in conjunction with stored information concerning the respective functions and information concerning the ECUs, such as installation positions on the vehicle, mechanical and electrical specifications of component parts of ECUs, etc.

Abstract: A computer-based analysis of an enterprise computer system is utilized to remove bottlenecks that cause the enterprise computer system to operate in a non-optimal or risky manner. Contents of e-mails are examined to identify bottlenecks in the enterprise computer system. Upon identifying the bottlenecks, the enterprise computer system is simulated, and simulations of replacement components, which the computer-based analysis has deemed appropriate for curing the bottlenecks, are installed in the simulated system. If the computer simulation with the replacement components cures the bottlenecks and causes no new problems for the enterprise computer system, then corresponding actual replacement components are installed in the enterprise computer system.

Abstract: A method for providing a virtual optical disk drive (ODD) is provided. The method can comprise: simulating a PCI IDE controller through PCI configuration space IO trap and simulating the ODD through IDE device IO trap.

Abstract: A method and system for simulating a plurality of devices are disclosed. A simulator configured to simulate a plurality of devices may output simulated device data for the plurality of devices, where the output of the simulated device data may be performed based upon execution of commands by the simulator. The commands may be received from a device abstraction layer in response to a request from the simulator for any commands associated with the plurality of devices. Additionally, the simulated device data may be communicated to a component coupled to the simulator, where a result of the processing of the simulated device data by the component may be used to analyze the performance of the component. Further, other commands may be executed by simulator for changing the frequency at which simulated device data is output, for performing another operation defined during configuration of the simulator, etc.

Abstract: A simulation apparatus is disclosed, including a hardware simulator and a CPU model. The hardware simulator activates one or more logical hardware models for verifying embedded software. The CPU model is one of the one or more logical hardware models which imitates a CPU which executes the embedded software, and to trigger the embedded software to operate without synchronization for each of instructions.

Abstract: A method for generating software for a hardware component of a measuring, control, or regulating system having a processor, an FPGA, and a plurality of I/O channels. The I/O channels are connected to the FPGA and the FPGA is connected to the processor via a communications interface. The method includes the steps of selecting a first subset of the I/O channels for operation by the FPGA, generating a first application for execution in the FPGA, selecting a second subset of the I/O channels for operation by the processor, and generating a second application for execution on the processor. The step of generating a first application comprises generating code for connecting the second subset of I/O channels to the communications interface. The invention relates in addition to a method for operating a hardware component.

Abstract: Example embodiments provide various techniques for modeling network storage environments. To model a particular storage environment, component models that are associated with the components of the storage environment are loaded. Each component model is programmed to mathematically simulate one or more components of the storage environment. A system model is then composed from the component models and this system model is configured to simulate the storage environment.

Abstract: Systems and methods for modeling test space for verifying system behavior, using one or more auxiliary variables, are provided. The method comprises implementing a functional coverage model including: one or more attributes, wherein respective values for the attributes are assigned according to a test plan, and one or more constraints defining restrictions on value combinations assigned to the attributes, wherein the restrictions are Boolean expressions defining whether said value combinations are valid; determining a set of valid value combinations for the attributes that satisfy the restrictions to define the test space for verifying the system behavior; and determining relevant auxiliary variables and a corresponding function for said auxiliary variables to reduce the complexity associated with modeling the test space.

Abstract: A method includes presenting multiple memory circuits to a system as a virtual memory circuit having at least one characteristic that is different from a corresponding characteristic of one of the physical memory circuits; receiving, at an interface circuit, a first command issued from the system to the virtual memory circuit; and in response to receiving the first command, 1) directing a copy of the first command to a first physical memory circuit of the multiple physical memory circuits, and 2) performing a power-saving operation on at least one other physical memory circuit of the multiple physical memory circuits.

Abstract: A system, method, and computer program product are provided for providing validation of network model objects within a network model design process. In use, a request to create a design of at least a portion of a network model is received via an interface utilized for creating a network model design. Additionally, at least one object of the network model capable of being utilized to create the design of the at least a portion of the network model is identified, in response to the request. Furthermore, it is determined whether at least one discrepancy has been identified for the at least one object. Moreover, a response to the request to create the design of the at least a portion of the network model is provided that is based on the determination of whether the at least one discrepancy has been identified for the at least one object.

Abstract: A simulator is partitioned into a functional component and a behavior prediction component and the components are executed in parallel. The execution path of the functional component is used to drive the behavior prediction component and the behavior prediction component changes the execution path of the functional component.

Abstract: A quantum annealer simulator approximates unitary quantum dynamics of a quantum annealer on a non-quantum computing device such as a conventional computing device. The quantum annealer simulator may utilize algorithms that may efficiently approximate unitary time evolution of a quantum system, where the quantum system corresponds to a problem for which an optimized solution is sought.

Abstract: A dynamic predictive model of a computing system fabrication test is constructed. The computing system fabrication test is conducted over test sectors. Each test sector corresponds to a different type of the computing system fabrication test, and includes test operations that are individually performed to effectuate the test sector. The dynamic predictive model generates a predicted completion time of each test operation of each test sector. Production output of the computing system fabrication test is forecast for a scenario corresponding to a particular computing system to undergo fabrication testing, by applying the dynamic predictive model to the scenario. The production output is forecast in that a total time remaining until the particular computing system to which the scenario corresponds has completed the fabrication testing is predicted.

Abstract: The exemplary embodiments of the invention provide at least a method, apparatus and system to perform operations including receiving context data from an electronic device, causing, at least in part based on the received context data, an identification of at least one context model compatible with the electronic device, and causing, at least in part, provision of the electronic device with the at least one compatible context model. In addition, the exemplary embodiments of the invention further provide at least a method, apparatus and system to perform operations including causing, at least in part, a provision of context data associated with an electronic device to a context inference service, in response, receiving a context model from the context inference service, and causing adaptation of the received context model as a current context model of the electronic device.

Abstract: A system is configured to: identify a block of a model; represent the block as a group of sub blocks; and establish connections for the group of sub blocks. The block includes an input signal and two or more output signals. The group of sub blocks include a state block that provides a state, and two or more output blocks for receiving the state.

Abstract: A system and methods to simulate a power profile of an electrical system are disclosed. A combination of electrical devices operable to be electrically coupled to a common power source is virtually assembled, and empirically derived dynamic power requirements associated with each of the electrical devices are modeled. Power profiles for at least one electrical system configuration comprising the combination of electrical devices are generated using the empirically derived dynamic power requirements.

Abstract: A method and device for calibrating a power model for a multi-state device. The device includes a processor and a computer readable medium containing instructions to instruct the processor to perform the method. The method includes receiving a device state log comprising a time-based representation of multi-state device states for a first period of time and a power trace comprising a time-based representation of power consumed by the multi-state device for the first period of time; eroding the device state log to reduce potential noise present at state transitions within the device state log, thereby producing an eroded device state log; determining energy consumption for each state transition in the eroded power state log; creating an updated power model for the multi-state device based upon the eroded power state log; and storing the updated power model in a non-transitory computer readable medium operably connected to the multi-state device.

Abstract: A method is presented to verify correctness of computer system software and hardware components. The method includes: operating a test environment with a verified system software and hardware version; monitoring and recording each hardware access during operation of the test environment with the verified system software and hardware version to generate a corresponding verified trace file; operating the test environment with a modified system software and/or hardware version; monitoring and recording each hardware access to generate a corresponding new trace file during operation of the test environment with the modified system software and/or hardware version; defining an arbitrary order for target chips in the verified and the modified hardware model or hardware system version; sorting sequences of entries in both trace files according to the target chip order; and comparing the sorted trace files by comparing their entries each by each and outputting a corresponding comparison result.