Abstract: The present invention discloses a system and method for management of test or non-production environment. The method comprises planning the non-production environment design, wherein planning is based on plurality of inputs. The planning stage is preceded by engagement wherein engagement with functional groups takes place. The planned non-production environment design is analyzed based upon the requirements wherein analysis consists of reviewing plurality of non-production environment designs. This stage is followed by creation of non-production environment wherein non-production environment is built on analyzed design. After this stage the non-production environment is deployed. After deployment there is provision for on-going supports to test services via established Information Technology service management processes. Non-production environment services manage the on-going booking and allocation of the non-production environment through various in-house and third party tools.

Abstract: A channel emulator generates radio channel conditions of live cellular base station signals in a simulation of a radio environment of a fielded cellular network, based on a record of captured radio signal data of a plurality of cellular base stations in the fielded cellular network. A generates a simulation of a fielded cellular network. In one aspect, the radio channel conditions in the simulation of the radio environment are synchronized with events in the simulation of the fielded cellular network. In another aspect, an event handling state machine directs configurable events in the simulation of the fielded cellular network in response to radio channel conditions in the simulation of the radio environment.

Abstract: Method, apparatus, and system for monitoring performance within a processing resource, which may be used to modify user-level software. Some embodiments of the invention pertain to an architecture to allow a user to improve software running on a processing resources on a per-thread basis in real-time and without incurring significant processing overhead.

Abstract: A nonvolatile storage or memory device is accessed over a memory bus. The memory bus has an electrical interface typically used for volatile memory devices. A controller coupled to the bus sends synchronous data access commands to the nonvolatile memory device, and reads the response from the device bus based on an expected timing of a reply from the nonvolatile memory device. The controller determines the expected timing based on when the command was sent, and characteristics of the nonvolatile memory device. The controller may not need all the electrical signal lines available on the memory bus, and could issue data access commands to different groups of nonvolatile memory devices over different groups of electrical signal lines. The memory bus may be available and configured for either use with a memory controller and volatile memory devices, or a storage controller and nonvolatile memory devices.

Abstract: A complete end-to-end modeling system is provided that includes data sampling, feature engineering, action labeling, and model learning or learning from models built based on collected data. The end-to-end modeling process is performed via an automatic mechanism with minimal or reduced human intervention. A processor-readable medium is disclosed, storing processor-executable instructions to instantiate an automated data sampling and prediction structure training component, the automated data sampling and prediction structure training component being configured to automatically collect user event data samples, and use the collected user event data samples to train multiple prediction structures in parallel.

Abstract: A simulation apparatus that performs parallel execution of multiple logical processes obtained by modeling a plurality of components included in a system to be simulated. The apparatus includes: (i) a condition generating unit configured to generate, on the basis of communication delays between the multiple logical processes, constraint conditions to be satisfied by initial time shifts given to the multiple logical processes and look-ahead times each to be permitted by a message sent from a logical process serving as a communication source to a logical process serving as a communication destination to permit look-ahead; and (ii) a solver unit configured to solve an optimization problem that satisfies the constraint conditions and minimizes overhead in communication of messages between the multiple logical processes, and obtain the initial time shifts of the multiple logical processes and the look-ahead times between the multiple logical processes.

Abstract: The disclosed technology provides a manufacturing method of a target comprising obtaining an initial mass and a residual mass of the target sample, and calculating an etching mass; determining a relative etching depth of the target sample; calculating a relative etching mass based on the etching mass and the relative etching depth; determining a utilization parameter of the target sample based on the relative etching mass and the initial mass of the target sample before being used; and performing a simulation and optimization process on the utilization parameter of the target sample, obtaining target parameters corresponding to a preset value of the utilization parameter, and outputting the target parameters to a manufacturing control center for manufacturing a target. The disclosed technology also provides a manufacturing system of a target.

Abstract: Disclosed herein is a computer implemented method and system for analyzing load responsive behavior of infrastructure components in an electronic environment for proactive management of the infrastructure components. Transaction data on multiple application transactions is collected. Load patterns are identified from the collected transaction data for generating load profiles. Data on infrastructure behavior in response to the application transactions is collected. Infrastructure behavior patterns are identified from the infrastructure behavior data for generating behavior profiles. The generated load profiles and the generated behavior profiles are correlated to create a load responsive behavior model. The created load responsive behavior model predicts behavior of the infrastructure components for different load patterns. A live data stream from current application transactions is analyzed using the load responsive behavior model to determine current load responsive behavior.

Abstract: The cost necessary for introducing and maintaining a development environment that includes multiple simulators is suppressed, and a sharing of designing information is promoted, to make parameter adjustment of simulators easy. Provided is a service that unifies development environment on a computer provided with: a working computer system that can guarantee that there is no leaking of designing files; a user behavior monitoring system that collects utilization history of simulators or software, for each of the users, and selects development process of each of the users from the collected information; and a dynamic computational-resource distribution system that can conduct an automatic optimization of a complex simulation configuration, from information collected by the aforementioned user behavior monitoring system.

Abstract: Methods and systems are provided for executing a simulation of an operation in a data processing system. In one implementation, the method includes executing an operation under a first set of conditions, determining a characteristic associated with the execution of the operation under the first set of conditions, and executing a simulation of the operation under a second set of conditions different from the first set of conditions. The simulation of the operation is constrained by the determined characteristic. The method can further include determining a cost/benefit of executing the operation under a set of conditions different from the first set of conditions based at least in part on the simulation.

Abstract: Exemplary embodiments allow users to interactively formulate and solve multivariable feedback control problems. For example, users can solve problems where a plurality of control elements are distributed over one or more feedback loops and need to be jointly tuned to optimize overall performance and robustness of a control system. Embodiments allow users to specify design requirements and objectives in formats familiar to the user. Embodiments can operate on tunable parameters to solve the control problem in a manner that satisfies the design requirements and/or objectives provided by the user.

Abstract: A customization environment uses a customization system that models customizations to a base computer system. The customization system receives developer inputs that customize the design time behavior of a form control by modeling it with an extension model. Based on the developer inputs, the customization system generates an extension expression that expresses the design time behavior of the form control. The extension expression can express the design time behavior through the addition of attributes representing the design time behavior or through code authored in an extensibility framework.

Abstract: A system for visualizing and optimizing the operation of a system of systems. A Design of Experiments is conducted for a particular system of systems architecture using a simulation engine based upon a predefined set of inputs. The results are stored in a database as real data. Surface Response Models are built based upon the results and simulation data is generated and stored based on the Surface Response Models for data not present in the results. The results of the Design of Experiments are filtered to identify key variables. Values and rankings are selected for the key variables. An interim output is generated and displayed based on the selected values and rankings. The interim output is determined based on the real and simulation data. The results are verified by performing a simulation based on the selected values and comparing the simulation output with the interim output.

Abstract: A method and apparatus for performing a simulation by using a plurality of N processors in parallel include dividing the simulation scenario into N parts to distribute a simulation scenario to each of the processors; performing a high-detail simulation by using a first processor to which a part that includes a beginning part of the divided simulation scenario is distributed, from among the N processors; performing a fast simulation by using each of N?1 processors, other than the first processor; and performing a high-detail simulation based on a snapshot that is generated after the fast simulation is finished, by using each of the N?1 processors.

Abstract: A simulation environment verifies processor-sparing functions in a simulated processor core. The simulation environment executes a first simulation for a simulated processor core. During the simulation, the simulation environment creates a simulation model dump file. At a later point in time, the simulation environment executes a second simulation for the simulated processor core. The simulation environment saves the state of the simulated processor core. The simulation environment then replaces the state of the simulated processor core by loading the previously created simulation model dump file. The simulation environment then sets the state of the simulated processor core to execute processor-sparing code and resumes the second simulation.

Abstract: A method, computer program product, and computer system for analyzing code to improve efficiency of simulating a hardware system. A computer identifies one or more functions calling an application programming interface of a hardware simulator simulating the hardware system. In response to determining that left hand sides of respective one or more Boolean expressions are associated with the one or more functions calling the application programming interface and right hand sides are not associated with the one or more functions calling the application programming interface, the computer identifies the respective one or more Boolean expressions as one or more improvement points in source code for verifying a hardware model of the hardware system.

Abstract: Embodiments of the present invention relate to an arrangement for analyzing transmission line properties. Measurement data providing means provide data of a first frequency dependent line property, line property calculation arrangement with model handling means, a Hubert transform handler and line property determination means calculate said first property based on model parameters, line resistance at 0 frequency, roc, a cut-off frequency, v, a line capacitance C? and a line inductance L?H. The line model handling means calculates the line inductance L(f) via a Hubert transform of a function of Q(f/v), wherein the function Q(f/v) relates the line resistance R(f) to roc as R(f)=roc·Q(f/v). The Hilbert transform values are calculated using a parameterized closed form expression for the Hubert transform or they are tabulated.

Abstract: A method and a system for automated test and result comparison, suitable for a client computer to control a management server to test sensors in a server to be tested, are provided. In the method, an operating interface of a management program of the management server is logged in through a network, and operating actions of a user testing the sensors by using the operating interface are simulated to generate keyboard and mouse control instructions corresponding to the operating actions by using a keyboard-and-mouse automation program. The keyboard and mouse control instructions are executed to operate the operating interface, so as to control the management program to test the sensors. The test parameters obtained by the management program testing the sensors are captured, and compared with predetermined parameters in a database to obtain a test result. Finally, the test result is stored as a test file.

Abstract: A method and system is provided for determining a viable containment design of a data center and systematic implementation of the determined containment design in the data center. Particularly, disclosed is a method and system for collecting data pertaining to the design and operational parameters of the data center; enabling various containment design options using CFD based methodology; and providing recommendations for a viable containment design and assisting systematic implementation of the recommendations of in the data center following an iterative procedure.

Abstract: A method for error simulation in a data storage subsystem providing abstractions of one or more storage devices. The method includes dividing the data storage subsystem into two or more hierarchically organized subsystems, wherein the subsystems interact using IO Request Packets (IORPs), such that relatively higher level subsystems create and populate IORPs and pass them to relatively lower level subsystems for corresponding processing. The method further includes defining an IORP modifier configured to attach to matching IORPs based on one or more attributes of the IORP modifier and to modify at least one of the processing and one or more attributes of the IORP in order to simulate errors in the data storage subsystem.

Abstract: A mechanism is provided for determining a modeled age of a set of interconnect groups in a set of cores in a set of multi-core processors. For each interconnect group in the set of interconnect groups in the set of cores on the set of multi-core processors, a determination is made of a current modeled age of the interconnect group. A determination is then made as to whether at least one current modeled age of the interconnect group for the set of interconnect groups is greater than an end-of-life value. Responsive to at least one current modeled age of the interconnect group being greater than the end-of-life value, an indication to take corrective action with the at least one associated interconnect group is sent.

Abstract: A model-based virtual power management driven multi-chip system simulator generates utilization data and performance data with a workload model that models one or more types of workloads based on parameters that characterize the one or more types of workloads. The simulator generates thermal data and power consumption data with a power model that models power consumption at a chip-level and a system-level. The simulator then generates performance counter information with a performance model that models change of performance counters over time and at least one of the generated utilization data and the generated performance data as input to the performance model. The simulator provides this generated data as input to a driver of the simulator.

Abstract: A model-based virtual power management driven multi-chip system simulator generates utilization data and performance data with a workload model that models one or more types of workloads based on parameters that characterize the one or more types of workloads. The simulator generates thermal data and power consumption data with a power model that models power consumption at a chip-level and a system-level. The simulator then generates performance counter information with a performance model that models change of performance counters over time and at least one of the generated utilization data and the generated performance data as input to the performance model. The simulator provides this generated data as input to a driver of the simulator.

Abstract: Embodiments of apparatuses and methods for processing virtualization events in a layered virtualization architecture are disclosed. In one embodiment, an apparatus includes a event logic and evaluation logic. The event logic is to recognize a virtualization event. The evaluation logic is to determine whether to transfer control from a child guest to a parent guest in response to the virtualization event.

Abstract: Method, apparatus, and product for performing incremental formal verification. A computer-implemented method performed by a computerized device. The method comprises: obtaining invariants with respect to a first model; determining a portion of the invariants that are invariants with respect to a second model, and utilizing the portion of the invariants to check that the second model holds a property.

Abstract: A deployed configurable communication integrated circuit (IC) and/or chipset which may be integrated within a wireless communication and/or multi-media communication device may be operable to monitor its operating conditions, performance and/or utilization characteristics. It may send information via a wireless, optical and/or wired network to a remote analysis and/or development system and/or service, such as an engineering service, that may determine and return configuration parameters. The configuration parameters may be utilized to adjust antenna and/or MIMO, SIMO, MISO and beamforming configuration, power level, interference rejection, equalizer length, dynamic range, modulation, encoding and/or decoding, analog to digital conversion precision, error detection and/or correction parameters, MAC parameters such as timing thresholds, transmit window size and/or buffer space.

Abstract: The present invention is achieved as software which operates on a computer system and which performs calculation by receiving various data as inputs, and which outputs values. The present invention is applicable to a coarse-grained system architecture model including the foregoing event-driven simulation and receives, as inputs, execution time T and the number of memory accesses, N, in the simulation step of the model. Thus, various estimates at the occurrence of memory access conflict are obtained at a simulation speed sufficient for evaluating the effect of the memory access conflict and comparing it with many alternative architectures without information on the correct timing of memory accesses in consideration of memory synchronous accesses and arbitration. The results of this simulation are estimated simulation-step execution time T? under memory access conflict and memory-bandwidth utilization factors {U?i} in individual simulation steps under memory access conflict.

Abstract: The invention relates to a method and apparatus for simulating a system in a communications network as a linear system in order to obtain a prediction of the load of a resource in the system. Measurements obtained at m different points in time of the event intensity aevent for a number n of key events occurring in a reference system are used to form the simulation model, together with measurements of the total load L in the reference system at the m different points in time. An optimization problem, defined by the simulation model and a set of event intensities of the system-to-be-predicted in a scenario to be simulated, is solved in order to obtain a prediction of the total load of the system in the simulated scenario.

Abstract: Performance metrics related to the processing and propagation of messages related to select applications are collected during a simulation of a network. Each message associated with an application is tagged, and each simulated packet that contains some or all of a tagged message is correspondingly tagged to facilitate the creation of transmit records and receive records. A post processor is configured to collate transmit and receive records of each tagged message to identify delays associated with each node that processes the message, and each link that propagates the message from node to node within the network. The processed timing information is provided to the user via an interactive user interface that allows the user to view the timing information from an application layer perspective.

Abstract: A non-transitory tangible computer-readable medium may include instructions executable by a processor in a simulation system to perform a simulation. The instructions may include to wait for a plurality of virtual controllers to complete a previous simulation step, write a result of the previous simulation step from each of the plurality of virtual controllers to a shared memory, read an input from the memory to each of the plurality of virtual controllers, initiate a simulation step on each of the plurality of virtual controllers, and upon initiation of the simulation step in each of the plurality of virtual controllers, indicate completion of the simulation, in which the plurality of virtual controllers include a controller model having a plurality of simulation steps and the instructions are configured to be executed by the processor in parallel.

Abstract: A system and method of testing, during development, the operation of a clustered storage server system and its associated storage operating system. The system includes at least one host computer having a host operating system, and at least one virtual computer having a simulated storage operating system, at least one simulated disk, a simulated NVRAM, and a simulated flashcard within a guest operating system hosted by the host operating system. The simulated storage operating system represents an actual storage operating system. Facilities of the simulated storage operating system including the simulated disk, the simulated NVRAM, and the simulated flashcard are mapped onto corresponding facilities of the host operating system via virtualization components of the virtual computer so that the simulated storage operating system operates substantially the same as the actual storage operating system on low cost host hardware platforms.

Abstract: A method and system for detection of intrusion in networked control systems, is provided. The method includes generating an operating model of a system being controlled. The operating model of the system comprises a relationship between a plurality of components in the system defined by a plurality of parameters. Further, the method includes calculating an estimated value of at least one parameter for at least one component in the system. The operating model is used to calculate the estimated value of the at least one parameter. Furthermore, the method includes measuring a latest value of at least one parameter at a predefined interval. The method also includes triggering an alert for intrusion for the at least one component based on an analysis of at least one of the latest value and the estimated value of at least one parameter.

Abstract: A method and a system are disclosed for simulation in a substation. The method can include acquiring substation data from substation condition data and base substation record; adapting the acquired substation data to suit a target substation; and administering the adapted substation data on a communication channel of the target substation. The substation system can include a base substation which is an existing, a pre existing, or a target substation, or a substation defined by a user or any combination thereof; a substation automation system; test equipment configured to test the system and perform simulation in a target substation; and a human machine interface for interfacing the substation system with a user.

Abstract: Example embodiments provide various techniques for modeling network storage environments. To model a particular storage environment, component models that are associated with the components of the storage environment are loaded. Each component model is programmed to mathematically simulate one or more components of the storage environment. A system model is then composed from the component models and this system model is configured to simulate the storage environment.

Abstract: Method, system and computer program product for estimating the overall energy efficiency of a data center over a period of time. In one embodiment, a computer processor coupled to computer readable memory is configured to receive time parameters indicating the period of time over which the overall energy efficiency of the data center is to be estimated, receive component parameters indicating the performance characteristics of data center components and the operational interactions between the data center components, simulate the operation and interaction of the data center components based, at least in part, on the component parameters for the period of time over which the energy efficiency is estimated, and output results of the simulation to estimate the overall energy efficiency of the data center.

Abstract: Methods for classifying and correlating simulation components to functional models. A method includes receiving a simulation component library comprising a plurality of simulation components into a memory of the data processing system, parsing the plurality of simulation components from the simulation component library, analyzing a plurality of extracted functions into a plurality of function graphs for each of the plurality of simulation components, composing an extracted functions graph with the plurality of extracted functions of the plurality of function graphs, and storing the extracted functions graph of the plurality of extracted functions in a components-to-function database.

Abstract: The present invention provides a method for efficient resource-oriented power evaluation. By mapping instructions to microarchitecture components, both advantages of high-level simulation performance and fine-grained power model are obtained. The present invention effectively reduces simulation runtime overhead and provides an accurate power estimation result. The present invention is nearly as accurate as gate-level simulators, with an error rate of less than 1.2 while achieving simulation speeds of up to 20 MIPS, five orders faster than a commercial gate-level simulator. By using the present invention, it is easy to analyze power consumption profile and peak power.

Abstract: Described herein are methods, systems and machine-readable media for simulating a FIFO cache using a Bloom filter ring, which includes a plurality of Bloom filters arranged in a circular log. New elements are registered in the Bloom filter at the head of the circular log. When the Bloom filter at the head of the circular log is filled to its capacity, membership information associated with old elements in the Bloom filter at the tail of the circular log is evicted (simulating FIFO cache behavior), and the head and tail of the log are advanced. The Bloom filter ring is used to determine cache statistics (e.g., cache hit, cache miss) of a FIFO cache of various sizes. In response to simulation output specifying cache statistics for FIFO cache of various sizes, a FIFO cache is optimally sized.

Abstract: Techniques for tuning systems generate configurations that are used to test the systems to determine optimal configurations for the systems. The configurations for a system are generated to allow for effective testing of the system while remaining within budgetary and/or resource constraints. The configurations may be selected to satisfy one or more conditions on their distributions to ensure that a satisfactory set of configurations are tested. Machine learning techniques may be used to create models of systems and those models can be used to determine optimal configurations.

Abstract: A method for modeling a test space comprising defining a coverage model including: one or more variables, wherein respective values for the variables are assigned, and restrictions based on which valid variable value combinations are determined for the purpose of testing the model, wherein at least two values that are assignable to the one or more variables are merged to reduce number of variable values in the coverage model.

Abstract: At least some of the illustrative embodiments are methods including: executing a test program on a computer system coupled to a server, the test program emulating virtual users by instantiating a first user instance by calling a first reentrant function, the first user instance exiting the first reentrant function upon encountering a blocking statement in the first reentrant function; instantiating a second user instance by calling the first reentrant function, the second user instance exiting the first reentrant function upon encountering a blocking statement in the first callable function; reentering the first user instance by again calling the first reentrant function, the first reentrant function resuming execution within the reentrant function after the first blocking statement; and reentering the second user instance by calling the first reentrant function, the first reentrant function resuming execution within the reentrant function after the second blocking statement.

Abstract: A system and method are provided for simulating an aspect of a memory circuit. Included is an interface circuit that is in communication with a plurality of memory circuits and a system. Such interface circuit is operable to interface the memory circuits and the system for simulating at least one memory circuit with at least one aspect that is different from at least one aspect of at least one of the plurality of memory circuits. In accordance with various embodiments, such aspect may include a signal, a capacity, a timing, and/or a logical interface.

Abstract: Methods, systems, and computer-readable media for providing a rule based exchange simulator are presented. A plurality of rules may be received at an exchange simulator that define how orders should be processed at the exchange simulator. The received rules may be stored, for instance, at a rules engine. For example, rules may comprise a fill rule, a cancel rule, a reject rule, a no acknowledgment rule, and a market data rule. An order that comprises a stock exchange order may be received at the exchange simulator. For example, an order may comprise a buy or sell order for a particular instrument, such as a stock, and may comprise a particular quantity. Based on the one or more rules stored in the rules engine, the received order may be fully filled, partially filled, or not filled.

Abstract: A system receives a model, internals associated with a target processor, and code information associated with the target processor, and obtains a bit-true model simulation for the target processor based on the model, the target processor internals, and the target processor code information.

Abstract: In order to achieve tasks, according to an embodiment of the present invention, an arithmetic unit including one or more ASIPs includes two or more processors, and an execution unit that is connected to the two or more processors and executes instructions received from the processors. According to an embodiment of the present invention, it is possible to provide a low-power, high-integration, high-performance arithmetic unit through resource sharing using the arithmetic unit including the one or more ASIPs, and it is possible to provide a method of designing an arithmetic unit that may be applied to a specific application.

Abstract: Systems and methods comprise a network in which a mobile device is configured as an input/output interface for a user such that actual processing, storage and network interfaces are performed or provided by a remote server.

Abstract: A computer-implemented method may include receiving transition information indicative of transition rates associated with a plurality of communication links in a network, wherein the network includes a plurality of nodes, the plurality of communication links, and a communication path between a first node and a second node of the plurality of nodes. In one embodiment, the communication path uses at least two of the plurality of communication links. The method may include generating biased transition information indicative of biased transition rates, wherein the biased transition rates are greater or less than the indicated transition rates and simulating the network, based on the biased transition information, until a transition associated with one of the communication links causes the communication path to transition to a different state. A network reliability parameter may be determined based on the simulation of the network.

Abstract: A method for generating a power model for a device includes identifying a device-level set of power contributors for a given state of the device, wherein each power contributor in the device-level set of power contributors contributes to power dissipation when the device is in the given state, and generating the power model for the device based on the device-level set of power contributors, wherein the power model is independent of process, voltage, and temperature.

Abstract: A Portable Maintenance Aid (PMA) having multiple applications for the electrical testing and data acquisition for various air/ground vehicle platforms is disclosed. The PMA includes an interface adapter that has a number of electrical testing interfaces and data collection ports in addition to a stray voltage detector. The portable testing aid also includes a user interface that transmits data to the interface adapter and a display that communicates the testing and maintenance information to the user. The portable testing aid also includes a communication system for transferring information between the user interface, the display, and the interface adapter. The PMA provides a preload tester/stray voltage tester that is sustainable, less replaceable and has capability of filling the test voids.

Abstract: According to exemplary embodiments, a computer implemented method for functional testing of a processor design includes accessing a test template from a library of test templates, wherein the test template is configured to test a first selected function of the processor and inputting the test template to an automated test generation tool executed by a computer. The method further includes generating an instruction sequence based on the test template by the automated test generation tool and injecting an event instruction to the instruction sequence during the generating of the instruction sequence by the automated test generation tool, the injecting of the event instruction preserving testing of the first selected function of the processor and the event instruction being configured to test a second selected function of the processor. The method includes verifying a function of the processor by analyzing responses of the processor to the instruction sequence.