In-circuit Emulator (i.e., Ice) Patents (Class 703/28)
  • Patent number: 10249178
    Abstract: A condition monitoring sensor system having a power supply; a condition monitoring sensor; a processor; a permanently powered power-on timer; and a watchdog timer. The permanently powered power-on timer is set for a first predetermined duration and is configured to wake the processor by connecting the processor to the power supply if the power-on timer elapses. Upon waking up, the processor is configured to reset the power-on timer to the first predetermined duration and is configured to control at least the condition monitoring sensor. The condition monitoring sensor may take condition monitoring data. Upon waking up, the processor is configured to set the watchdog timer for a second predetermined duration. The watchdog timer is powered via the power supply, which forces the processor and the watchdog timer to enter a sleep mode by disconnecting the processor and the watchdog timer from the power supply if the watchdog timer elapses.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: April 2, 2019
    Assignee: Aktiebolaget SKF
    Inventors: Julian Franchitti, Mark Rhodes
  • Patent number: 10185794
    Abstract: A computer-implemented method for configuring a hardware verification system is presented. The method includes receiving a first data representative of a first design including a first sequential element configured to be evaluated in accordance with a first signal. The method further includes transforming the first data into a second data representative of a second design. The second data includes a third data associated with a second sequential element including functionality of the first sequential element and a fourth data associated with a first logic circuit. The evaluation of the second sequential element at cycle i of the hardware verification system is performed in accordance with the first logic circuit and a value of the first signal as computed during cycle i?1 of the hardware verification system when the second data is compiled for programming into the hardware verification system, where i is an integer number.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: January 22, 2019
    Assignee: SYNOPSYS, INC.
    Inventors: Xavier Guerin, Alexander Rabinovitch
  • Patent number: 10180925
    Abstract: An integrated circuit (IC) having multiple cores controls write access to its input/output (I/O) pins. The IC includes a pin-control circuit, a memory, and a set of I/O pins. The pin-control circuit allows a core to independently control individual ones of the I/O pins. A set of pin-control values are defined that correspond to the set of I/O pins to indicate a type of core that can access an I/O pin. The pin-control circuit receives the pin-control values, a source ID, and write data generated by a core, and updates a pin data bit stored in the memory with a corresponding bit of the write data when the core is allowed to access the I/O pin. The pin-control circuit does not change the pin data bit when the core is denied write access to the I/O pin.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: January 15, 2019
    Assignee: NXP USA, INC.
    Inventors: Rajan Srivastava, Girraj K. Agrawal
  • Patent number: 10102050
    Abstract: In a debugging method for an integrated circuit device which has multiple processing cores, a debugging breakpoint is activated at a first processor core in the integrated circuit device. Upon activation, the debugging breakpoint stops execution of instructions in the first processor core and the debugging breakpoint is communicated to a second processor core in the integrated circuit device.
    Type: Grant
    Filed: February 1, 2016
    Date of Patent: October 16, 2018
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Bryan Kris, Mike Catherwood, Dave Mickey, Brian Fall, Calum Wilkie, Vincent Sheard, Alex Dumais
  • Patent number: 10067845
    Abstract: A method of monitoring operations of a set of ICs. The method loads a first set of configuration data into a first IC for configuring a group of configurable circuits of the first IC to perform operations of a user design. The method receives a definition of an event based on values of a set of signals in the user design and a set of corresponding actions to take when the event occurs. The set of signals includes at least one signal received from a second IC. The method generates an incremental second set of configuration data based on the definition of the event and the set of corresponding actions. While the first IC is performing the operations of the user design, the method loads the incremental second set of configuration data into the first IC and monitors the signals received from the second IC at the first IC.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: September 4, 2018
    Assignee: Altera Corporation
    Inventors: Andrea Olgiati, Matthew Pond Baker, Steven Teig
  • Patent number: 10067852
    Abstract: In one or more embodiments, one or more systems, method, and/or processes described herein can change/switch from a first trace mode to a second trace mode without halting a system under development and/or under test. For example, a debug/trace unit can switch a trace mode without halting a processing unit of a system under development and/or under test. For instance, a debug/trace unit can switch a trace mode that can occur on a change of flow boundary of program instructions executable by a processing unit, at a branch instruction, if a region of program instructions is entered or exited, and/or if a capacity of a buffer changes. In one or more embodiments, Nexus messages can be utilized, and trace mode switches can include switches to and/or from traditional and history traces modes.
    Type: Grant
    Filed: October 29, 2013
    Date of Patent: September 4, 2018
    Assignee: NXP USA, Inc.
    Inventors: Jonathan J. Gamoneda, William C. Moyer
  • Patent number: 10007590
    Abstract: Embodiments include methods, computing systems and computer program products for identifying and tracking frequently accessed registers in a processor of a computing system. Aspects include: creating a list of top accessed registers of certain registers in processor, each register having a corresponding register usage counter, initializing each register usage counter, starting a register usage monitoring mode, examining each register usage counter, and updating list of top accessed registers, stopping register usage monitoring mode, and updating a register file partition assignment when the list of top accessed registers is identified. Once the list of top accessed registers is identified, stopping the programs and bring its threads of execution to quiescent, moving registers between register file partitions until all registers on the list of top accessed registers are in the fully-ported register file partition, and resuming executions of the program and its threads.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: June 26, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Pratap C. Pattnaik, Jessica H. Tseng
  • Patent number: 9983894
    Abstract: An application such as a virtual machine are executed securely using a software-based, full-system emulator within a hardware-protected enclave, such as an SGX enclave. The emulator may thereby be secure even against a malicious underlying host operating system. In some cases, paging is used to allow even a large application may run within a small enclave using paging. Where the application itself uses enclaves, these guest enclaves may themselves be emulated within an emulator enclave such that the guest enclave(s) are nested as sibling enclaves by the emulator.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: May 29, 2018
    Assignee: Facebook, Inc.
    Inventors: Oded Horovitz, Stephen A. Weis, Sahil Rihan, Carl A. Waldspurger
  • Patent number: 9817067
    Abstract: A testbench for testing a device under test (DUT), wherein the testbench has a verification environment including a reference model, a scoreboard and a customized agent for each interface that the DUT needs to receive input from and/or transmit output on. The testbench system is able to be generated by a testbench builder that automatically creates a scoreboard, a reference model, a dispatcher and generic agents including generic drivers, loopback ports, sequencers and/or generic monitors for each interface and then automatically customize the generic agents based on their corresponding interface such that the agents meet the requirements of the interface for the DUT.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: November 14, 2017
    Assignee: Cavium, Inc.
    Inventors: Saurin Patel, Nimalan Siva, Keqin Kenneth Han
  • Patent number: 9778946
    Abstract: A facility is described for optimizing the copying of virtual machine storage files. In various embodiments, the facility refrains from copying portions of the virtual machine storage file that do not contain any meaningful data for the purposes of the guest file system within the virtual machine storage file. In some embodiments, the facility refrains from copying portions of the file that are in use by the guest file system, but are of no practical value.
    Type: Grant
    Filed: August 7, 2009
    Date of Patent: October 3, 2017
    Assignee: Dell Software Inc.
    Inventor: Dilip Naik
  • Patent number: 9779831
    Abstract: An electronic apparatus and a data verification method using the same are provided. The electronic apparatus includes a first read-only memory having first data, a second read-only memory having second data and a controller. A correspondence relation exists between the first data and the second data. The controller is coupled to the first read-only memory and the second read-only memory. The controller reads first sub-data of the first data from the first read-only memory, and reads second sub-data of the second data corresponding to the first sub-data from the second read-only memory according to the correspondence relation. The first sub-data includes to-be-verified data. The controller perfoi ins a verification operation to the to-be-verified data according to the first sub-data, the second sub-data and the correspondence relation.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: October 3, 2017
    Assignee: Wistron Corporation
    Inventors: Jeng-Shiun Liu, Chun-Chih Lin, Tung-Lin Lu
  • Patent number: 9742796
    Abstract: Techniques for automatic repair of corrupt files (e.g., malware sample files) for a detonation engine are disclosed. In some embodiments, a system, process, and/or computer program for automatic repair of corrupt files for a detonation engine includes receiving a malware sample from a network device; determining whether the malware sample includes a corrupt file; and in an event that the malware sample is determined to include the corrupt file, repairing the corrupt file for the detonation engine.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: August 22, 2017
    Assignee: Palo Alto Networks, Inc.
    Inventor: Ryan C. Salsamendi
  • Patent number: 9702933
    Abstract: Methods and systems for concurrent diagnostics in a functional verification system are disclosed and claimed herein. The methods and systems enable testing the interconnections of a functional verification system while the system implements a hardware design. In one embodiment, a first emulation chip of the functional verification system generates an encoded data word comprising a data word and error correction code (ECC) check bits. The ECC check bits enable a second emulation chip receiving the encoded word to determine whether the data word was received without error. In another embodiment, test patters may be transmitted along the unused interconnections while the functional verification system implements a hardware design in other interconnections. In another embodiment, a dedicated pattern generator generates test patterns to transmit across the interconnection.
    Type: Grant
    Filed: October 22, 2015
    Date of Patent: July 11, 2017
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Charles R. Berghorn, Barton L. Quayle, Mitchell G. Poplack
  • Patent number: 9639639
    Abstract: A logic circuit emulator comprises multiple sub-systems, in which each sub-system outputs to another one of the sub-systems a permission notification to permit the another sub-system to proceed to next emulation clock cycle depending on whether or not the state of an own sub-circuit has advanced. In case a signal that is output from an own sub-circuit and that is to be sent to a sub-circuit of the other sub-system has changed, each sub-system outputs a transfer request to transfer the signal to the another sub-system before the next emulation clock cycle. In case a signal is not being sent from the own sub-circuit to the sub-circuit of the another sub-system, and a permission notification is received but no transfer request is being received from the other sub-system, a clock signal is output for the own sub-circuit to advance the own sub-circuit to the next emulation clock cycle.
    Type: Grant
    Filed: April 26, 2011
    Date of Patent: May 2, 2017
    Assignee: NEC CORPORATION
    Inventor: Noriaki Suzuki
  • Patent number: 9632914
    Abstract: Troubleshooting data can be collected to debug a computer appliance running in a production environment. A computer system can record inbound and outbound transactions and monitor for the occurrence of an error. Upon detection of an error, transactional data associated with the error can be copied to a container. The relevant transactions and user sessions can be run in the container on debug firmware and rich troubleshooting data can be collected from the execution. If the same error occurs again during this simulated execution, then the troubleshooting data that was collected, as well a product key, can be encrypted and included in an error report. The container can then be deleted from the appliance.
    Type: Grant
    Filed: May 21, 2015
    Date of Patent: April 25, 2017
    Assignee: International Business Machines Corporation
    Inventors: Chin-Teng Cheng, Ying-Hsien Lee, Chih-Hsiung Liu, Min-Tsung Wu
  • Patent number: 9607583
    Abstract: A display controller device for processing image data has a data processor for generating a display signal. The device has a writeback unit having an input coupled to the display signal and an output coupled to a debug interface. The writeback unit has a slice controller for defining a set of slices of the image and consecutively selecting slices of the set, and a slice selector for sampling pixel data from a selected slice. A slice buffer is coupled between the slice selector and the debug output for temporarily storing the selected pixel data. The slice controller transfers the selected pixel data to the debugger and subsequently selects a next slice until all slices of the set have been transferred. The debug system receives the slices and regenerates and displays the image.
    Type: Grant
    Filed: February 5, 2015
    Date of Patent: March 28, 2017
    Assignee: NXP USA, INC.
    Inventors: Michael Andreas Staudenmaier, Vincent Aubineau, Yves Briant
  • Patent number: 9513728
    Abstract: A touch sensor includes a substrate, a touch sensing layer, a first processor and a second processor. The substrate includes a first area and a second area. The first area and the second area are on the same surface of the substrate. The touch sensing layer is disposed on the substrate, and includes a first group of conductive patterns and a second group of conductive patterns. The first group of conductive patterns is disposed on the first area, and includes a plurality of first conductive patterns. The second group of conductive patterns is disposed on the second area, and includes a plurality of second conductive patterns. The first processor is electrically connected to the first conductive patterns. The second processor is electrically connected to the second conductive patterns.
    Type: Grant
    Filed: July 8, 2013
    Date of Patent: December 6, 2016
    Assignee: E Ink Holdings Inc.
    Inventors: Yun-Nan Hsieh, Lin-An Chen
  • Patent number: 9372947
    Abstract: The present patent document relates to a method to compact trace data generated by emulation processors during emulation of a circuit design, and a hardware functional verification system that compacts trace data. Compaction logic within emulation processor clusters accumulated data bits output from the emulation processors and compacts them into trace data bytes in registers based on enable bits identifying valid trace data according to a compaction scheme. Trace data bytes are further accumulated and compacted into larger trace data bytes in higher level processor clusters of the emulation chip according to a compaction hierarchy, with the compacted trace data bytes stored into a trace array of the emulation chip.
    Type: Grant
    Filed: September 29, 2014
    Date of Patent: June 21, 2016
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Beshara Elmufdi, Mitchell G. Poplack, Viktor Salitrennik
  • Patent number: 9350360
    Abstract: A system for configuring a semiconductor device to generate an output signal. The system includes a temperature sensor configured to sense a plurality of operating temperatures of the semiconductor device, the plurality of operating temperatures including at least a first operating temperature and a second operating temperature. A controller is configured to determine a plurality of operating frequencies of the output signal at respective operating temperatures of the plurality of operating temperatures. The plurality of operating frequencies include a first operating frequency of the output signal when the semiconductor device is at the first operating temperature and a second operating frequency of the output signal when the semiconductor device is at the second operating temperature. Memory is configured to store calibration information that associates each of the plurality of operating temperatures of the semiconductor device with respective operating frequencies of the plurality of operating frequencies.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: May 24, 2016
    Assignee: Marvell World Trade Ltd.
    Inventor: Sehat Sutardja
  • Patent number: 9323648
    Abstract: An automatic test apparatus for embedded software and an automatic testing method thereof, the automatic testing apparatus for embedded software, includes an output detector which collects interface status information in accordance with data transmission/reception from at least one of first and second electronic devices respectively loaded with first and second embedded software and exchanging data therebetween, and extracts a keyword from the collected interface status information, a scenario composer which uses identification information about the first and second embedded software and the extracted keyword, and composes a scenario corresponding to a predetermined event status and a control command generator which generates a control command to reproduce the event status based on the composed scenario.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: April 26, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byeong-hu Lee, Tai-ryong Kang, Sang-deok Kim, Yong-hee Park, Sang-rae Lee, Jae-hoon Lee
  • Patent number: 9300716
    Abstract: Timings of data traffic in a test system are modified by introducing dependencies that would arise in response to data requiring access to a resource comprising a buffer for storing pending data related to an access to the resource that cannot currently complete. A maximum value of a counter is set to a value corresponding to the buffer size. Data traffic is input, and the counter is updated in response to the data requiring the resource and being stored in the buffer and in response to the data traffic indicating a buffer entry has become available. Where the data requires the buffer and the counter is at its maximum value indicating the buffer is full, a timing of the data access requiring the buffer is modified indicating that the data is stalled until the buffer has capacity again, and the data traffic is updated with the modified timing.
    Type: Grant
    Filed: September 20, 2012
    Date of Patent: March 29, 2016
    Assignee: ARM Limited
    Inventor: Andrew David Tune
  • Patent number: 9286424
    Abstract: An emulation environment includes a host system and an emulator. The host system configures the emulator to emulate a design under test (DUT) and the emulator emulates the DUT accordingly. During emulation, the emulator traces limited signals of the DUT and stores values of the traced signals. When values of certain signals of the DUT are needed for analysis or verification of the DUT but the signals were not traced by the emulator, the host system simulates one or more sections of the DUT to obtain values of the signals. Signals traced by the emulator are used as inputs to simulate the one or more sections.
    Type: Grant
    Filed: May 4, 2015
    Date of Patent: March 15, 2016
    Assignee: Synopsys, Inc.
    Inventors: Ludovic Marc Larzul, Alexander Rabinovitch
  • Patent number: 9283748
    Abstract: A printhead includes a plurality of element substrates, each including a plurality of printing elements, arranged in the arrayed direction of the printing elements. Each element substrate includes a temperature detection element for detecting the temperature of the element substrate. The printhead includes a head control IC connected to each element substrate and configured to control driving of the printing elements integrated on the element substrates. The head control IC and the element substrates are connected via a head terminal by a signal wire for transferring a signal between the head control IC and each element substrate. A temperature detection signal output from the temperature detection element and an image data signal are multiplexed on part of the signal wires.
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: March 15, 2016
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kengo Umeda, Nobuyuki Hirayama
  • Patent number: 9244805
    Abstract: A method of managing a debug trace data stream by detecting conditions where the trace data generated exceeds the available transmission bandwidth, and inserting a trace data gap into the trace data stream. The gap may contain additional information relating to the amount and type of data that is being lost during the overflow condition. In an alternate embodiment the generated trace may be throttled to ensure the available bandwidth is not exceeded.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: January 26, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Jason L. Peck
  • Patent number: 9218258
    Abstract: Roughly described, an integrated circuit chip comprises a plurality of peripheral circuits, each peripheral circuit connected to a respective debug unit, the respective debug unit configured to generate debug information of that peripheral circuit; and a plurality of separate stores for receiving debug information, storing debug information, and outputting debug information; wherein in response to a single trigger signal, the debug units are configured to stream their generated debug information to the plurality of separate stores; and wherein each of the plurality of separate stores is configured to receive debug information at a higher stream rate than it outputs debug information.
    Type: Grant
    Filed: July 9, 2013
    Date of Patent: December 22, 2015
    Assignee: ULTRASOC TECHNOLOGIES LTD.
    Inventor: Andrew Brian Thomas Hopkins
  • Patent number: 9213947
    Abstract: Ancestry deconvolution includes obtaining unphased genotype data of an individual; phasing, using one or more processors, the unphased genotype data to generate phased haplotype data; using a learning machine to classify portions of the phased haplotype data as corresponding to specific ancestries respectively and generate initial classification results; and correcting errors in the initial classification results to generate modified classification results.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: December 15, 2015
    Assignee: 23andMe, Inc.
    Inventors: Chuong Do, Eric Durand, John Michael Macpherson
  • Patent number: 9213944
    Abstract: Performing trio-based phasing includes: obtaining a set of preliminary phased haplotype data of an individual; establishing a dynamic Bayesian network based at least in part on the set of preliminary phased haplotype data of the individual and phased haplotype data of at least one parent of the individual; and determining, based on the dynamic Bayesian network, a set of refined haplotype data of the individual.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: December 15, 2015
    Assignee: 23andMe, Inc.
    Inventors: Chuong Do, Eric Durand, John Michael Macpherson
  • Patent number: 9201479
    Abstract: Disclosed is a debug system that suppresses the supply of extra electrical power for functions disused in the future while maintaining the performance of communication between an electronic control unit and an external unit for development. The debug system includes an electronic control unit that has a microcomputer for controlling the operation of a control target, a transceiver circuit that is capable of communicating data with the microcomputer, and an external unit for development that is capable of rapidly communicating data with the transceiver circuit. The electronic control unit includes a power supply unit for supplying electrical power to the microcomputer. The transceiver circuit operates on electrical power supplied from an external power supply unit, which differs from the power supply unit included in the electronic control unit.
    Type: Grant
    Filed: October 18, 2012
    Date of Patent: December 1, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Takahiro Shiina
  • Patent number: 9176570
    Abstract: One particular example implementation may include an apparatus that includes logic, at least a portion of which is in hardware, the logic configured to: determine that a first device maintains a link to a platform in a selective suspend state; assign a first latency value to the first device; identify at least one user detectable artifact when a second device exits the selective suspend state; and assign, to the second device, a second latency value that is different from the first value.
    Type: Grant
    Filed: December 29, 2012
    Date of Patent: November 3, 2015
    Assignee: Intel Corporation
    Inventor: Jaya L. Jeyaseelan
  • Patent number: 9141512
    Abstract: A system and method of cluster debugging includes detecting debug events occurring in one or more first virtual machines, storing debug records, each of the debug records including information associated with a respective debug event selected from the debug events and a timestamp associated with the respective debug event, merging the debug records based on information associated with each timestamp, starting one or more second virtual machines, each of the one or more second virtual machines emulating a selected one of the one or more first virtual machines, synchronizing the one or more second virtual machines, retrieving the merged debug records, and playing the merged debug records back in chronological order on the one or more second virtual machines. In some examples, the method further includes collecting clock synchronization records. In some examples, merging the debug records includes altering an order of one or more of the debug records based on the clock synchronization records.
    Type: Grant
    Filed: May 21, 2013
    Date of Patent: September 22, 2015
    Assignee: Red Hat, Inc.
    Inventors: Filip EliĆ”{hacek over (s)}, Filip Nguyen
  • Patent number: 9143083
    Abstract: A crystal oscillator emulator having a plurality of predetermined operating configurations. The crystal oscillator emulator includes a measurement circuit configured to measure a value of an impedance connected to a select pin of the crystal oscillator emulator, wherein the impedance is external to the crystal oscillator emulator, and generate an output having a value corresponding to the value of the impedance. The storage circuit is configured to store a plurality of values corresponding to the plurality of predetermined operating configurations and select one of the plurality of values based on the output of the measurement circuit. A controller is configured to set an output frequency of the crystal oscillator emulator based on the selected one of the plurality of values.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: September 22, 2015
    Assignee: MARVELL WORLD TRADE LTD.
    Inventor: Sehat Sutardja
  • Patent number: 9094014
    Abstract: In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.
    Type: Grant
    Filed: April 2, 2014
    Date of Patent: July 28, 2015
    Assignee: Altera Corporation
    Inventors: Andy L. Lee, Cameron R. McClintock, Brian D. Johnson, Richard G. Cliff, Srinivas T. Reddy, Christopher F. Lane, Paul Leventis, Vaughn Betz, David Lewis
  • Patent number: 9047959
    Abstract: According to one embodiment, a data storage device comprises a buffer memory and a controller. The buffer memory stores a data group including sector unit data with addresses specified by a host, the data group in unit of page includes a plurality of addresses. The controller comprises an adding module configured to be operative, if the sector unit data with addresses specified by the host as valid addresses for write targets are stored in the buffer, to add information that identifies a last address included in valid addresses belonging to the same page addresses and specified by the host and starting with a start address, to a single sector unit data with the last address.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: June 2, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Nobuyuki Myouga
  • Patent number: 9047180
    Abstract: Disclosed are a system, method and computer-readable medium related to processing debug information from an embedded system. Source code of an application program to be used in an embedded system may be compiled by a computing system. The application program may include a debug code line. A minimum amount of debug information is stored in an embedded system, reducing memory overhead and waste of clock cycles of a processor.
    Type: Grant
    Filed: October 12, 2010
    Date of Patent: June 2, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae Don Lee, Shi Hwa Lee, Seung Won Lee, Chae Seok Im, Min Kyu Jeong
  • Patent number: 8997034
    Abstract: Techniques for emulation-based functional qualification are disclosed that use an emulation platform to replace simulation in mutation-based analysis. A method for functional qualification of an integrated circuit design includes receiving an integrated circuit design having one or more mutations. Emulation setup and activation simulation are performed in parallel to maximize computing resources. A prototype board can then be programed according to the integrated circuit design and a verification module. A set of test patterns and response generated by a simulation of the integrated circuit using the set of test patterns are stored in a memory of the prototyping board allowing enumeration of mutants to occur at in-circuit emulation speed.
    Type: Grant
    Filed: July 30, 2013
    Date of Patent: March 31, 2015
    Assignee: Synopsys, Inc.
    Inventors: Ying-Tsai Chang, Yu-Chin Hsu
  • Patent number: 8977921
    Abstract: A system for providing a test result from an integrated circuit to a status analyzer. A deserializer is configured to deserialize, into data frames, messages received from the integrated circuit. The messages include the test result and are received from the integrated circuit in a serial data format. A frame sync module is configured to synchronize the data frames, output the synchronized data frames, and generate a clock signal. A gateway module is configured to receive the synchronized data frames from the frame sync module in accordance with the clock signal, convert signal levels and signal timings associated with the synchronized data frames from a first format used by the frame sync module to a second format used by the status analyzer, and provide the synchronized data frames to the status analyzer in accordance with the signal levels and the signal timings in the second format used by the status analyzer.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: March 10, 2015
    Assignee: Marvell International Ltd.
    Inventors: Saeed Azimi, Son Hong Ho, Daniel Smathers
  • Patent number: 8959010
    Abstract: A method and apparatus for redundant communication channels in an emulation system is disclosed. A processor-based emulation system has a plurality of emulation chips on an emulation board. The emulation chips have a plurality of processor clusters. Signals are sent over one or more communication channels between processor clusters, including from a processor cluster on one emulation chip to a processor cluster on another emulation chip. Copies of the same signal may be sent in duplicate over separate communication channels. If a communication channel failure is detected, instruction memory is modified so that a processor cluster's instructions no longer address a first cluster memory location, but instead address a second cluster memory location of a non-failed communication channel. By using redundant communication channels, emulation system interconnect reliability is increased and recompilation of the design under verification may be avoided.
    Type: Grant
    Filed: December 8, 2011
    Date of Patent: February 17, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventors: Mikhail Bershteyn, Mitchell G. Poplack, Viktor Salitrennik
  • Patent number: 8954312
    Abstract: The invention provides for the interaction of an emulator emulating an electronic design having a communication bus communicating with a software application over the emulated communication bus. The interaction is facilitated in such a manner as to provide an appropriate latency for the emulated communication bus. According to various implementations of the invention, a protocol proxy is provided. The protocol proxy is designed to be emulated along with an electronic design and configured to communicate to software executing on a computer connected to the emulator. The protocol proxy includes a protocol module that communicates to the electronic design being emulated in the emulator environment. Furthermore, the protocol proxy includes a software control module that communicates to the software outside the emulator through proxy communication channels. Further still, the protocol proxy includes a data storage component.
    Type: Grant
    Filed: June 13, 2011
    Date of Patent: February 10, 2015
    Assignee: Mentor Graphics Corporation
    Inventors: Luis Lloret Portillo, Georges Antoun Elias Ghattas, Noah Wagdy Shawky Tadros
  • Patent number: 8903706
    Abstract: The invention is system for emulating a target application comprises a computer, and a capsular including a microcontroller, a programmable non-volatile memory, a numeric display, a transceiver for transmitting and receiving data, a real time clock and at least one input device interacting with a program run on the microcontroller. The capsular is couplable to the computer and adapted to fit in a housing. The input device is operable both when the capsular is inside the housing and when the capsular is outside the housing.
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: December 2, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Frank Forster, Markus Pfeiffer
  • Patent number: 8868829
    Abstract: A method includes presenting multiple memory circuits to a system as a virtual memory circuit having at least one characteristic that is different from a corresponding characteristic of one of the physical memory circuits; receiving, at an interface circuit, a first command issued from the system to the virtual memory circuit; and in response to receiving the first command, 1) directing a copy of the first command to a first physical memory circuit of the multiple physical memory circuits, and 2) performing a power-saving operation on at least one other physical memory circuit of the multiple physical memory circuits.
    Type: Grant
    Filed: February 6, 2012
    Date of Patent: October 21, 2014
    Assignee: Google Inc.
    Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber
  • Patent number: 8850381
    Abstract: The present patent document relates to a method and apparatus for an automatic clock to enable conversion for FPGA-based prototyping systems. A library or netlist is provided having a plurality of state elements of a chip design to be prototyped by a user. The chip design can have dozens of different user clocks and clock islands using these different user clocks. The state elements of an element library or netlist are converted to a circuit having one or more state elements and other logic that receive both a user clock as well as a fast global clock. With the disclosed transformations, the functionality of the original state element is maintained, and a single or low number of global clocks can be distributed in an FPGA of the prototype with user clocks generated locally on the FPGA.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: September 30, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Subramanian Ganesan, Philip Henry Nils Anthony De Buren, Jinny Singh, David Abada
  • Patent number: 8843357
    Abstract: An electrical connection defect simulation test method is provided. The electrical connection state simulation test method includes the steps as follows. A device under test is provided, wherein the device under test includes a plurality of pin groups each having a plurality of signal pins. A zero-frequency signal is transmitted from a signal-feeding device to each of the signal pins to simulate an open condition. An open test is performed on each of the signal pins. The signal pins of the device under test are connected to a relay matrix. The relay matrix is controlled to make any two of the signal pins in one of the pin groups electrically connected to simulate a short condition. A short test is performed on any two of the electrically connected signal pins. An electrical connection state simulation test system is disclosed herein as well.
    Type: Grant
    Filed: March 3, 2011
    Date of Patent: September 23, 2014
    Assignee: TEST Research, Inc.
    Inventors: Su-Wei Tsai, Ming-Hsien Liu
  • Patent number: 8812287
    Abstract: A method and device for preserving the wired-OR nature of the clock signal connection between two devices without a direct analog connection between the lines and in an infinitely scalable fashion. The method includes detecting a logic state at a first connector and a second connector and driving an appropriate connector of the device to an active state in response to determining that a connector is driving an active state. The device includes first and second connectors for communicating logic states and driving active states in response to detected logic states.
    Type: Grant
    Filed: February 8, 2011
    Date of Patent: August 19, 2014
    Assignee: International Business Machines Corporation
    Inventor: Daniel J Barus
  • Patent number: 8812286
    Abstract: A method for modeling power management in an integrated circuit (IC) includes: specifying a circuit design and a power architecture for the IC, the power architecture including a plurality of power domains for specifying power levels in different portions of the IC; determining an emulation module for the IC by including one or more hardware elements for modeling the power architecture in the emulation module; and using the emulation module to simulate changing power levels in one or more power domains of the IC including a power shutoff in at least one power domain.
    Type: Grant
    Filed: January 8, 2013
    Date of Patent: August 19, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Tsair-Chin Lin, Bing Zhu, Platon Beletsky
  • Patent number: 8812289
    Abstract: Approaches for simulating an electronic system. In one approach, a software co-simulation platform is configured to produce a first time sequence of values of a plurality of input ports of a design block of the electronic system, consume a second time sequence of values of a plurality of output ports of the design block, and generate access transactions for transferring the first and second sequences of values. The software co-simulation platform generates a plurality of reconfiguration transactions for transferring reconfiguration data for the design block. A PLD is configured to implement a communication block and a control block. The communication block receives the reconfiguration and access transactions from the software co-simulation platform, and the control block reconfigures programmable logic and interconnect resources of the PLD in response to the reconfiguration transactions. The control block also controls the emulation of the design block in response to the access transactions.
    Type: Grant
    Filed: April 4, 2007
    Date of Patent: August 19, 2014
    Assignee: Xilinx, Inc.
    Inventors: Chi Bun Chan, Jonathan B. Ballagh, Nabeel Shirazi
  • Publication number: 20140156253
    Abstract: According to one embodiment, a self-test system integrated on a chip is provided, the chip including a functional logic module for performing a selected application. The self-test system includes a primary interface a primary interface to the functional logic module, the primary interface configured to interface with a primary device, an input interface protocol generator for generating a pattern to be inserted into the primary interface and a secondary interface to the functional logic module, the secondary interface configured to interface with a secondary device. The system also includes an emulator engine coupled to the secondary interface, the emulator engine for testing a function of the functional logic module based on the inserted patterns, the function being configured to communicate with a secondary device coupled to the secondary interface, wherein the emulator engine tests the function when no secondary device is coupled to the chip.
    Type: Application
    Filed: December 4, 2012
    Publication date: June 5, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kevin M. McIlvain, Robert B. Tremaine, Gary Van Huben
  • Patent number: 8744832
    Abstract: A hybrid electronic design system and a reconfigurable connection matrix thereof are disclosed. The electronic design system includes a virtual unit, a hybrid unit and a communication channel. The virtual unit further includes a plurality of proxy units, a plurality of virtual components and a driver. The virtual components are connected with the driver via the proxy units. The hybrid unit further includes an emulate unit, a physical unit and a chip level transactor. The chip level transactor is connected with the emulate unit and the physical unit. The communication channel is connected with the driver of the virtual unit and the chip level transactor of the hybrid unit.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: June 3, 2014
    Assignee: Global Unichip Corporation
    Inventor: Peisheng Alan Su
  • Patent number: 8713391
    Abstract: A system for testing an integrated circuit, in which the system includes a deserializer, a frame sync module, and a diagnostic module. The deserializer is external to the integrated circuit and is configured to receive messages in a serial data format, wherein the messages include test results associated with the integrated circuit, and deserialize the messages into data frames. The frame sync module is configured to provide control code based on the data frames, wherein the control code includes, in a digital format, status information associated with the messages deserialized into the data frames. The diagnostic module is configured to generate, based on the control code, diagnostic data associated with states of the integrated circuit.
    Type: Grant
    Filed: October 28, 2013
    Date of Patent: April 29, 2014
    Assignee: Marvell International Ltd.
    Inventors: Saeed Azimi, Son Ho, Daniel Smathers
  • Patent number: 8706454
    Abstract: Disclosed are various embodiments for transmission evaluation. In one embodiment, among others, a method includes evaluating a plurality of contingencies to generate a plurality of contingency results, where at least one of the contingency results includes an overload condition. The evaluation is based at least in part upon a case associated with a transmission network. The method further includes sorting the plurality of contingency results based upon corresponding overload-contingency pairs and determining a potential remediation solution to the overload condition based at least in part upon the overload-contingency pair. In another embodiment, a system includes a transmission evaluation application executed in a computing device.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: April 22, 2014
    Assignee: Southern Company Services, Inc.
    Inventor: Joseph E. Sneed, III
  • Patent number: 8707113
    Abstract: A method for operating a data processing system to generate a test for a device under test (DUT) is disclosed. The method utilizes a model of the DUT that includes a plurality of blocks connected by wires and a set of control inputs. Each block includes a plurality of ports, each port being either active or inactive. Each block is also characterized by a set of constraints that limit which ports are active. The active ports of at least one of the blocks are constrained by one of the control inputs. A test vector having one component for each port of each block and one component for each control input is determined such that each set of constraints for each block is satisfied. The test vector defines a test for the DUT.
    Type: Grant
    Filed: January 25, 2011
    Date of Patent: April 22, 2014
    Assignee: Agilent Technologies, Inc.
    Inventors: Douglas Manley, Randy A. Coverstone