Abstract: Methods and systems include a hardware abstraction layer to provide control of two or more network switch controllers as a single network switch controller.

Abstract: A cloud-based operator training system includes a snapshot management architecture, which provides a hybrid system for generation of control system level scenarios and system-state snapshots, and which can improve the fidelity of a training simulation. By implementing the simulation system on a cloud platform, the system can generate a large and growing set of snapshot files representing various control states and corresponding process states. These files can then be leverage during operator training sessions to yield high fidelity simulated system operation.

Abstract: The present invention monitors read data or write data of a CPU without generating any influences on an execution operation of a program. An LSI includes: a processing unit, executing a program; a storage unit, capable of performing a read operation or a write operation; and an internal bus, connected to the processing unit and the storage unit; and a monitoring unit (21). The processing unit is capable of performing a read access or a write access, the read access is outputting a read enable signal (RE) and an address signal (ADD) to the internal bus, and the write access is outputting write data (WD), a write enable signal (WE) and the address signal to the internal bus. The storage unit outputs the read data to the internal bus in response to the read access and stores the write data in response to the write access. The monitoring unit latches the read data or the write data to be sent through the internal bus when an access meeting a set monitoring condition is present.

Abstract: A hardware emulation system for emulating an integrated circuit design under test (DUT) includes a switch system, FPGAs and serial transmitter and receiver circuitry. The switch system has input and output ports and is configurable to change which ports are connected to each other. The FPGAs are configurable to emulate a functionality of the DUT. The functionality of the DUT is partitioned across multiple FPGAs. The serial transmitter circuitry transmits data from the FPGAs on serial lines to the ports of the switch system. The serial receiver circuitry receives data for the FPGAs on serial lines from the ports of the switch system.

Abstract: A power usage estimation system for a design emulated on a field programmable gate array (FPGA) comprising a periodic dump unit implementing statistical data sampling to generate a periodic dump without emulation stops and interactions with a host, and without affecting the emulation performance.

Abstract: An FPGA chip-based handler simulation test system is provided. The FPGA chip-based handler simulation test system includes a handler simulator, a PC and a tester. The handler simulator includes an FPGA, an RS232 interface, a GPIB interface, a RAM, a LED, a keypad and a soft-core processor. The soft-core processor includes a CPU, an SDRAM, a PIO, a UART and a JTAG. The firmware of the soft-core processor establishes the communication of the RS232 interface and the GPIB interface, as well as the display of the LED and reception of the keypad. The test system of the present invention simulates handler communication by using a small-sized and low-cost hardware circuit, and is easy to carry. In this way, an operator can debug the handler in the laboratory without damaging the handler, thus protecting the expensive handler.

Abstract: Systems and methods to implement performance monitoring of a device under test involve defining one or more sequences. Each of the one or more sequences includes two or more events, each of the two or more events being defined by one or more hardware signals that include a hardware register value, transmission of a message or signal, or a wire voltage change. A method includes initiating a simulation of the device under test by inputting one or more signals at one or more inputs of the device under test for propagation across the device under test, and monitoring completion of the two or more events defining each of the one or more sequences. Performance of the device under test is reported. Reporting includes providing latency of each of the one or more sequences. A final design of the device under test is provided for fabrication based on the performance monitoring.

Abstract: An emulation system may have a built-in self-test circuit to generate one or more built-in self-test instructions. The one or more built-in self-test instructions may be pseudorandom. The one or more built-in self-test instructions may cause one or more emulation processors of the emulation system to generate one or more deterministic outputs. A testing processor of the emulation system may compare the one or more deterministic outputs to detect a faulty emulation processor, a faulty emulation processor cluster, or a faulty emulation chip of the emulation system.

Abstract: A debug-enabled processing device includes a processor, a communication transceiver circuit, and a debug support unit. The debug support unit has a plurality of dedicated debug registers to facilitate debugging a software program under execution by the processor. One of the plurality of debug registers is a control register having at least four bits, which are used to enable/disable a plurality of debugging operations. Others of the debug registers include a set of index registers that may be configured to pass data to and from the processor.

Abstract: A system and method for multicast delivery of messages using a configurable directional 2D router for Networks on Chips (NOCs) is disclosed. The router is well suited for implementation in programmable logic in FPGAs and achieves theoretical lower bounds on FPGA resource consumption. A NOC comprising a plurality of routers may be configured as a directional 2D torus, or in diverse ways, network sizes and topologies, data widths, routing functions, performance-energy tradeoffs, and other options. The NOC may transmit a unicast message from one source client core to one destination client core, or a multicast message from one source client core to a plurality of destination client cores, or an arbitrary mix of unicast and multicast messages, simultaneously. A multicast message destination may include all client cores of routers with a particular first or second dimension coordinate, or all client cores, or some arbitrary subsets of client cores.

Abstract: Systems and methods described herein provide for testing and debugging different subsystems of an embedded controller using a testing architecture. The testing architecture can simulate messaging interfaces between internal subsystems of the embedded controller and external subsystems the controllers interacts with to integrate various types of software. A method includes generating test support models for one or more subsystems and establishing a communications network between the test support models and a control module of the embedded controller. A clock signal is generated to initiate processing within the testing architecture between the control module and the test support models. An event model is executed at the test support models using the clock signal and data is generated at one or more of the test support models responsive to the event model. The data can correspond to operational parameters of a respective system the embedded controller.

Abstract: A system and method for Controller Pilot Data Link Communication (CPDLC) chat is disclosed. The system receives CPDLC signals and displays CPDLC messages sent and received from both ownship aircraft and optionally other nearby aircraft on the ownship aircraft display. Not to interfere with a traditional CPDLC display, the system is an additional display of all CPDLC data and highlights messages to and from the ownship on the aircraft display. The system allows a declutter option to limit displayed data to that of a current data authority (CDA) as well as a limit in range, geography, altitude, aircraft type, etc.

Abstract: Embodiments of the present invention are directed to a computer-implemented method for generating and verifying hardware instruction traces including memory data contents. The method includes initiating an in-memory trace (IMT) data capture for a processor, the IMT data being an instruction trace collected while instructions flow through an execution pipeline of the processor. The method further includes capturing contents of architected registers of the processor by: storing the contents of the architected registers to a predetermined memory location, and causing a load-store unit (LSU) to read contents of the predetermined memory location.

Abstract: Disclosed approaches involve at least one processor executing a program and a debug interface circuit coupled to the processor. The debug interface circuit is configured to transmit first trace data from the first processor. A debug access port is coupled to the debug interface circuit. A fault detection circuit is coupled to the debug access port and is configured to receive the first trace data via the debug access port and compare the first trace data to second data. The fault detection circuit generates an error signal to the first processor in response to a discrepancy between the first trace data and the second data.

Abstract: An integrated circuit includes a plurality of tiles. Each tile includes a processor, a switch including switching circuitry to forward data over data paths from other tiles to the processor and to switches of other tiles, and a switch memory that stores instruction streams that are able to operate independently for respective output ports of the switch.

Abstract: Related semiconductor devices have a problem in which analysis processing with high defect reproducibility cannot be performed. According to an embodiment, a semiconductor device includes a first arithmetic core that executes a first program stored in a first code area using a first local memory area and a second arithmetic core that executes a second program stored in a second code area using a second local memory area. In an analysis mode, the semiconductor device performs first analysis processing that causes both the first arithmetic core and the second arithmetic core to execute the first program and second analysis processing that causes both the first arithmetic core and the second arithmetic core to execute the second program, and compares a plurality of arithmetic result data pieces acquired from the first and second analysis processing to thereby acquire analysis information used for defect analysis.

Abstract: Data processing apparatus comprises a processing element having an instruction pipeline to execute instructions and trace circuitry to generate items of trace data indicative of processing activities of the processing element. The trace circuitry generates items of event trace data in response to events initiated by execution of corresponding instructions by the instruction pipeline and also generates items of waypoint trace data in response to instructions, in a set of waypoint instructions, reaching a predetermined stage relative to the instruction pipeline. The trace circuitry generates position data, indicating a relative position with respect to execution of the corresponding instructions by the instruction pipeline, of one or more items of event trace data and one or more items of waypoint trace data.

Abstract: Examples of the disclosure enable the recalculation of device chaining in a user interface. In some examples, a first element representing a first hardware device is received at a design surface of a computing device user interface. A second element representing a second hardware device is received at the design surface. A selection of an output associated with the first element is received. A function that binds a property of the second element to a property of the output associated with the first element is automatically generated. Aspects of the disclosure enable the automatically generated function to be displayed at the design surface.

Abstract: Embodiments relate to the emulation of circuits, and tracking states of signals in an emulated circuit for performing power analysis. A host system incorporates power analysis logic into a design under test (DUT). An emulator emulates the DUT along with the incorporated power analysis logic. Based on the power analysis logic, during a power analysis clock cycle, the emulator selects a signal from a plurality of signals of the DUT. The emulator determines whether a state event is detected for the selected signal. If the state event is detected, a state count is updated for the selected signal that indicates a number of state events detected for the selected signal during emulation of the DUT. If the state count reaches a threshold number based on the update, the emulator transmits a count update signal to the host system indicating that the state count reached the threshold number.

Abstract: A method is provided for verifying functional correctness of a device driver for a controller hardware component being emulated in an emulation environment including a virtual processor. The method includes providing a communication device in the emulation environment. The communication device receives at least one execution condition and an error injection command from a communication device driver associated with the communication device. The controller hardware component executes device operation commands received from the device driver. Based on the communication device determining that the at least one execution condition is fulfilled while the device operation commands are executed, the method provides for the communication device to: halt the operation of the virtual processor; inject an error into the controller hardware component by executing the error injection command; and resume the operation of the virtual processor.

Abstract: Diagnostic operations upon a target apparatus 2 having a target transaction master 8 which initiates memory transactions with one or more target transaction slaves 12, 14, 16 are provided by halting operation of the target transaction master 8 while permitting continued operation within the target apparatus 2 of at least some of the target transaction slaves 12, 14, 16. Opening state data representing an operating state of the target transaction master 8 is transferred to a model transaction master 32. Further operation of the target transaction master 8 is emulated using the model transaction master 32 using the opening state data. Diagnostic operations are performed upon the model transaction master 32. When the model transaction master 32 emulates initiation of a memory transaction with a memory address mapped to one of the target transaction slaves 12, 14, 16, this initiates the memory transaction to be performed with the target apparatus 2.

Abstract: The present disclosure describes systems and methods for controlling access to secure debugging and profiling features of a computer system. Some illustrative embodiments include a system that includes a processor, and a memory coupled to the processor (the memory used to store information and an attribute associated with the stored information). At least one bit of the attribute determines a security level, selected from a plurality of security levels, of the stored information associated with the attribute. Asserting at least one other bit of the attribute enables exportation of the stored information from the computer system if the security level of the stored information is higher than at least one other security level of the plurality of security levels.

Abstract: A configurable directional 2D router for Networks on Chips (NOCs) is disclosed. The router is well suited for implementation in programmable logic in FPGAs, and achieves theoretical lower bounds on FPGA resource consumption for various applications. The router may employ an FPGA router switch design that consumes only one 6-LUT or 8-input ALM logic cell per router per bit of router link width. A NOC comprising a plurality of routers may be configured as a directional 2D torus, or in diverse ways, network sizes and topologies, data widths, routing functions, performance-energy tradeoffs, and other options. System on chip designs may employ a plurality of NOCs with different configuration parameters to customize the system to the application or workload characteristics. A great diversity of NOC client cores, for communication amongst various external interfaces and devices, and on-chip interfaces and resources, may be coupled to a router in order to efficiently communicate with other NOC client cores.

Abstract: A method of monitoring operations of a set of ICs. The method loads a first set of configuration data into a first IC for configuring a group of configurable circuits of the first IC to perform operations of a user design. The method receives a definition of an event based on values of a set of signals in the user design and a set of corresponding actions to take when the event occurs. The set of signals includes at least one signal received from a second IC. The method generates an incremental second set of configuration data based on the definition of the event and the set of corresponding actions. While the first IC is performing the operations of the user design, the method loads the incremental second set of configuration data into the first IC and monitors the signals received from the second IC at the first IC.

Abstract: A data processing apparatus is provided comprising data processing circuitry and debug circuitry. The debug circuitry controls operation of the processing circuitry when operating in a debug mode. The data processing circuitry determines upon entry into a debug mode a current operating state of the data processing apparatus. The data processing circuitry allocates one of a plurality of instruction sets to be used as a debug instruction set depending upon the determined current operating state.

Abstract: Described herein are various technologies pertaining to confirming an integrity of a FPGA. A verifier circuit is placed into an FPGA bitstream to enable external verification of the FPGA configuration in real time without requiring readout of the FPGA configuration itself. Number generators are utilized to generate a key which is shared between the FPGA and an external verification component (VC). The key is utilized to configure an initial state of sequence registers respectively located on both the FPGA and the VC. When the FPGA is operating with an approved configuration, output from the sequence registers at the FPGA and the VC are the same.

Abstract: A condition monitoring sensor system having a power supply; a condition monitoring sensor; a processor; a permanently powered power-on timer; and a watchdog timer. The permanently powered power-on timer is set for a first predetermined duration and is configured to wake the processor by connecting the processor to the power supply if the power-on timer elapses. Upon waking up, the processor is configured to reset the power-on timer to the first predetermined duration and is configured to control at least the condition monitoring sensor. The condition monitoring sensor may take condition monitoring data. Upon waking up, the processor is configured to set the watchdog timer for a second predetermined duration. The watchdog timer is powered via the power supply, which forces the processor and the watchdog timer to enter a sleep mode by disconnecting the processor and the watchdog timer from the power supply if the watchdog timer elapses.

Abstract: A computer-implemented method for configuring a hardware verification system is presented. The method includes receiving a first data representative of a first design including a first sequential element configured to be evaluated in accordance with a first signal. The method further includes transforming the first data into a second data representative of a second design. The second data includes a third data associated with a second sequential element including functionality of the first sequential element and a fourth data associated with a first logic circuit. The evaluation of the second sequential element at cycle i of the hardware verification system is performed in accordance with the first logic circuit and a value of the first signal as computed during cycle i?1 of the hardware verification system when the second data is compiled for programming into the hardware verification system, where i is an integer number.

Abstract: An integrated circuit (IC) having multiple cores controls write access to its input/output (I/O) pins. The IC includes a pin-control circuit, a memory, and a set of I/O pins. The pin-control circuit allows a core to independently control individual ones of the I/O pins. A set of pin-control values are defined that correspond to the set of I/O pins to indicate a type of core that can access an I/O pin. The pin-control circuit receives the pin-control values, a source ID, and write data generated by a core, and updates a pin data bit stored in the memory with a corresponding bit of the write data when the core is allowed to access the I/O pin. The pin-control circuit does not change the pin data bit when the core is denied write access to the I/O pin.

Abstract: In a debugging method for an integrated circuit device which has multiple processing cores, a debugging breakpoint is activated at a first processor core in the integrated circuit device. Upon activation, the debugging breakpoint stops execution of instructions in the first processor core and the debugging breakpoint is communicated to a second processor core in the integrated circuit device.

Abstract: A method of monitoring operations of a set of ICs. The method loads a first set of configuration data into a first IC for configuring a group of configurable circuits of the first IC to perform operations of a user design. The method receives a definition of an event based on values of a set of signals in the user design and a set of corresponding actions to take when the event occurs. The set of signals includes at least one signal received from a second IC. The method generates an incremental second set of configuration data based on the definition of the event and the set of corresponding actions. While the first IC is performing the operations of the user design, the method loads the incremental second set of configuration data into the first IC and monitors the signals received from the second IC at the first IC.

Abstract: In one or more embodiments, one or more systems, method, and/or processes described herein can change/switch from a first trace mode to a second trace mode without halting a system under development and/or under test. For example, a debug/trace unit can switch a trace mode without halting a processing unit of a system under development and/or under test. For instance, a debug/trace unit can switch a trace mode that can occur on a change of flow boundary of program instructions executable by a processing unit, at a branch instruction, if a region of program instructions is entered or exited, and/or if a capacity of a buffer changes. In one or more embodiments, Nexus messages can be utilized, and trace mode switches can include switches to and/or from traditional and history traces modes.

Abstract: Embodiments include methods, computing systems and computer program products for identifying and tracking frequently accessed registers in a processor of a computing system. Aspects include: creating a list of top accessed registers of certain registers in processor, each register having a corresponding register usage counter, initializing each register usage counter, starting a register usage monitoring mode, examining each register usage counter, and updating list of top accessed registers, stopping register usage monitoring mode, and updating a register file partition assignment when the list of top accessed registers is identified. Once the list of top accessed registers is identified, stopping the programs and bring its threads of execution to quiescent, moving registers between register file partitions until all registers on the list of top accessed registers are in the fully-ported register file partition, and resuming executions of the program and its threads.

Abstract: An application such as a virtual machine are executed securely using a software-based, full-system emulator within a hardware-protected enclave, such as an SGX enclave. The emulator may thereby be secure even against a malicious underlying host operating system. In some cases, paging is used to allow even a large application may run within a small enclave using paging. Where the application itself uses enclaves, these guest enclaves may themselves be emulated within an emulator enclave such that the guest enclave(s) are nested as sibling enclaves by the emulator.

Abstract: A testbench for testing a device under test (DUT), wherein the testbench has a verification environment including a reference model, a scoreboard and a customized agent for each interface that the DUT needs to receive input from and/or transmit output on. The testbench system is able to be generated by a testbench builder that automatically creates a scoreboard, a reference model, a dispatcher and generic agents including generic drivers, loopback ports, sequencers and/or generic monitors for each interface and then automatically customize the generic agents based on their corresponding interface such that the agents meet the requirements of the interface for the DUT.

Abstract: An electronic apparatus and a data verification method using the same are provided. The electronic apparatus includes a first read-only memory having first data, a second read-only memory having second data and a controller. A correspondence relation exists between the first data and the second data. The controller is coupled to the first read-only memory and the second read-only memory. The controller reads first sub-data of the first data from the first read-only memory, and reads second sub-data of the second data corresponding to the first sub-data from the second read-only memory according to the correspondence relation. The first sub-data includes to-be-verified data. The controller perfoi ins a verification operation to the to-be-verified data according to the first sub-data, the second sub-data and the correspondence relation.

Abstract: A facility is described for optimizing the copying of virtual machine storage files. In various embodiments, the facility refrains from copying portions of the virtual machine storage file that do not contain any meaningful data for the purposes of the guest file system within the virtual machine storage file. In some embodiments, the facility refrains from copying portions of the file that are in use by the guest file system, but are of no practical value.

Abstract: Techniques for automatic repair of corrupt files (e.g., malware sample files) for a detonation engine are disclosed. In some embodiments, a system, process, and/or computer program for automatic repair of corrupt files for a detonation engine includes receiving a malware sample from a network device; determining whether the malware sample includes a corrupt file; and in an event that the malware sample is determined to include the corrupt file, repairing the corrupt file for the detonation engine.

Abstract: Methods and systems for concurrent diagnostics in a functional verification system are disclosed and claimed herein. The methods and systems enable testing the interconnections of a functional verification system while the system implements a hardware design. In one embodiment, a first emulation chip of the functional verification system generates an encoded data word comprising a data word and error correction code (ECC) check bits. The ECC check bits enable a second emulation chip receiving the encoded word to determine whether the data word was received without error. In another embodiment, test patters may be transmitted along the unused interconnections while the functional verification system implements a hardware design in other interconnections. In another embodiment, a dedicated pattern generator generates test patterns to transmit across the interconnection.

Abstract: A logic circuit emulator comprises multiple sub-systems, in which each sub-system outputs to another one of the sub-systems a permission notification to permit the another sub-system to proceed to next emulation clock cycle depending on whether or not the state of an own sub-circuit has advanced. In case a signal that is output from an own sub-circuit and that is to be sent to a sub-circuit of the other sub-system has changed, each sub-system outputs a transfer request to transfer the signal to the another sub-system before the next emulation clock cycle. In case a signal is not being sent from the own sub-circuit to the sub-circuit of the another sub-system, and a permission notification is received but no transfer request is being received from the other sub-system, a clock signal is output for the own sub-circuit to advance the own sub-circuit to the next emulation clock cycle.

Abstract: Troubleshooting data can be collected to debug a computer appliance running in a production environment. A computer system can record inbound and outbound transactions and monitor for the occurrence of an error. Upon detection of an error, transactional data associated with the error can be copied to a container. The relevant transactions and user sessions can be run in the container on debug firmware and rich troubleshooting data can be collected from the execution. If the same error occurs again during this simulated execution, then the troubleshooting data that was collected, as well a product key, can be encrypted and included in an error report. The container can then be deleted from the appliance.

Abstract: A display controller device for processing image data has a data processor for generating a display signal. The device has a writeback unit having an input coupled to the display signal and an output coupled to a debug interface. The writeback unit has a slice controller for defining a set of slices of the image and consecutively selecting slices of the set, and a slice selector for sampling pixel data from a selected slice. A slice buffer is coupled between the slice selector and the debug output for temporarily storing the selected pixel data. The slice controller transfers the selected pixel data to the debugger and subsequently selects a next slice until all slices of the set have been transferred. The debug system receives the slices and regenerates and displays the image.

Abstract: A touch sensor includes a substrate, a touch sensing layer, a first processor and a second processor. The substrate includes a first area and a second area. The first area and the second area are on the same surface of the substrate. The touch sensing layer is disposed on the substrate, and includes a first group of conductive patterns and a second group of conductive patterns. The first group of conductive patterns is disposed on the first area, and includes a plurality of first conductive patterns. The second group of conductive patterns is disposed on the second area, and includes a plurality of second conductive patterns. The first processor is electrically connected to the first conductive patterns. The second processor is electrically connected to the second conductive patterns.

Abstract: The present patent document relates to a method to compact trace data generated by emulation processors during emulation of a circuit design, and a hardware functional verification system that compacts trace data. Compaction logic within emulation processor clusters accumulated data bits output from the emulation processors and compacts them into trace data bytes in registers based on enable bits identifying valid trace data according to a compaction scheme. Trace data bytes are further accumulated and compacted into larger trace data bytes in higher level processor clusters of the emulation chip according to a compaction hierarchy, with the compacted trace data bytes stored into a trace array of the emulation chip.

Abstract: A system for configuring a semiconductor device to generate an output signal. The system includes a temperature sensor configured to sense a plurality of operating temperatures of the semiconductor device, the plurality of operating temperatures including at least a first operating temperature and a second operating temperature. A controller is configured to determine a plurality of operating frequencies of the output signal at respective operating temperatures of the plurality of operating temperatures. The plurality of operating frequencies include a first operating frequency of the output signal when the semiconductor device is at the first operating temperature and a second operating frequency of the output signal when the semiconductor device is at the second operating temperature. Memory is configured to store calibration information that associates each of the plurality of operating temperatures of the semiconductor device with respective operating frequencies of the plurality of operating frequencies.

Abstract: An automatic test apparatus for embedded software and an automatic testing method thereof, the automatic testing apparatus for embedded software, includes an output detector which collects interface status information in accordance with data transmission/reception from at least one of first and second electronic devices respectively loaded with first and second embedded software and exchanging data therebetween, and extracts a keyword from the collected interface status information, a scenario composer which uses identification information about the first and second embedded software and the extracted keyword, and composes a scenario corresponding to a predetermined event status and a control command generator which generates a control command to reproduce the event status based on the composed scenario.

Abstract: Timings of data traffic in a test system are modified by introducing dependencies that would arise in response to data requiring access to a resource comprising a buffer for storing pending data related to an access to the resource that cannot currently complete. A maximum value of a counter is set to a value corresponding to the buffer size. Data traffic is input, and the counter is updated in response to the data requiring the resource and being stored in the buffer and in response to the data traffic indicating a buffer entry has become available. Where the data requires the buffer and the counter is at its maximum value indicating the buffer is full, a timing of the data access requiring the buffer is modified indicating that the data is stalled until the buffer has capacity again, and the data traffic is updated with the modified timing.

Abstract: An emulation environment includes a host system and an emulator. The host system configures the emulator to emulate a design under test (DUT) and the emulator emulates the DUT accordingly. During emulation, the emulator traces limited signals of the DUT and stores values of the traced signals. When values of certain signals of the DUT are needed for analysis or verification of the DUT but the signals were not traced by the emulator, the host system simulates one or more sections of the DUT to obtain values of the signals. Signals traced by the emulator are used as inputs to simulate the one or more sections.

Abstract: A printhead includes a plurality of element substrates, each including a plurality of printing elements, arranged in the arrayed direction of the printing elements. Each element substrate includes a temperature detection element for detecting the temperature of the element substrate. The printhead includes a head control IC connected to each element substrate and configured to control driving of the printing elements integrated on the element substrates. The head control IC and the element substrates are connected via a head terminal by a signal wire for transferring a signal between the head control IC and each element substrate. A temperature detection signal output from the temperature detection element and an image data signal are multiplexed on part of the signal wires.

Abstract: A method of managing a debug trace data stream by detecting conditions where the trace data generated exceeds the available transmission bandwidth, and inserting a trace data gap into the trace data stream. The gap may contain additional information relating to the amount and type of data that is being lost during the overflow condition. In an alternate embodiment the generated trace may be throttled to ensure the available bandwidth is not exceeded.