Emulation Patents (Class 703/23)
  • Patent number: 10256972
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: April 9, 2019
    Assignee: Intel Corporation
    Inventors: Shay Gueron, Wajdi K Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G Dixon, Srinivas Chennupaty, Michael E Kounavis
  • Patent number: 10255196
    Abstract: An apparatus and method for sub-page extended page table protection. For example, one embodiment of an apparatus comprises: a page miss handler to perform a page walk using a guest physical address (GPA) and to detect whether a page identified with the GPA is mapped with sub-page permissions; a sub-page control storage to store at least one GPA and other data related to a sub-page; the page miss handler to determine whether the GPA is programmed in the sub-page control storage; and the page miss handler to send a translation to a translation lookaside buffer (TLB) with a sub-page protection indication set to cause a matching of the sub-page control storage when an access matches a TLB entry with sub-page protection indication.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: April 9, 2019
    Assignee: Intel Corporation
    Inventors: Vedvyas Shanbhogue, Christopher Bryant, Jeff Wiedemeier
  • Patent number: 10256971
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: April 9, 2019
    Assignee: Intel Corporation
    Inventors: Shay Gueron, Wajdi K Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G Dixon, Srinivas Chennupaty, Michael E Kounavis
  • Patent number: 10243914
    Abstract: Exemplary methods, apparatuses, and systems include a first network edge device configuring a mapping between a physical network interface and a plurality of logical interfaces. A second network edge device also configures a mapping between a physical network interface and a copy of the plurality of logical interfaces. Each of the logical interfaces is assigned a corresponding set of first and second layer networking addresses that is replicated across the first and second network edge devices. The first network edge device receives a first address resolution request via the physical network interface of the first network edge device that includes a source and a destination. The destination is an address assigned to one of the plurality of logical interfaces. The first network edge device determines a second layer networking address assigned to the destination logical interface and transmits an address resolution response including the determined second layer networking address.
    Type: Grant
    Filed: July 15, 2015
    Date of Patent: March 26, 2019
    Assignee: Nicira, Inc.
    Inventor: Sreeram Ravinoothala
  • Patent number: 10235177
    Abstract: In an example, an apparatus includes a binary translator (BT) including circuitry to: analyze a code block; determine that an architectural register mapped to a physical register in the physical register file is available for early reclamation; and insert a reclamation hint into the code block. In another example, a processor reclaims the physical register based at least in part on the reclamation hint.
    Type: Grant
    Filed: July 2, 2016
    Date of Patent: March 19, 2019
    Assignee: Intel Corporation
    Inventors: Vineeth Mekkat, Janghaeng Lee, Youfeng Wu
  • Patent number: 10229268
    Abstract: System, method and media are shown for detecting potentially malicious code by iteratively emulating potentially malicious code, that involve, for each offset of a memory image, emulating execution of an instruction at the offset on a first platform and, if execution fails, determining whether the instruction at the offset has relevance to at least a second platform and, if so, emulating execution of the instruction at the offset on the second platform. If execution succeeds, it involves checking the behavior of the executing code for suspect behavior, and identifying the executing code as malicious code if suspect behavior is detected. Refinements involve applying this process to also determine aspects of information related to the target of any discovered code, malicious or otherwise.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: March 12, 2019
    Assignee: LEVIATHAN, INC.
    Inventor: Falcon Momot
  • Patent number: 10218641
    Abstract: Techniques for handling dynamic cascade port/LAG changes in an extended bridge are provided. According to one embodiment, a first network device in an extended bridge can maintain a shadow table that stores information regarding one or more ports and one or more LAGs used to interconnect the network devices in the extended bridge. The first network device can further receive, from a user via a device UI, a command relating to a change to a port or a LAG, update the shadow table based on the change, transmit a change message to one or more other network devices affected by the change, and start a timer associated with the one or more other network devices. In various embodiments, the updating and the transmitting can be performed without blocking the user from entering further commands via the device UI.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: February 26, 2019
    Assignee: ARRIS Enterprises LLC
    Inventors: Kwun-Nan Kevin Lin, Bipin Agarwal
  • Patent number: 10216496
    Abstract: An approach to dynamic run-time alias checking comprising creating a main thread and a helper thread, computing an optimized first region of code in a rollback-only transactional memory associated with the main thread checking for one or more alias dependencies in an un-optimized first region of code, responsive to a determination in a predetermined amount of time that no alias dependencies are present in the un-optimized first region of code, committing a transaction and responsive to at least one of a failure to determine results of the check for one or more alias dependencies in the predetermined amount of time and a determination in the predetermined amount of time that alias dependencies are present in the un-optimized first region of code, performing a rollback of the transaction and executing the un-optimized first region of code.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: February 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Yaoqing Gao, William G. O'Farrell, Denis Palmeiro
  • Patent number: 10215805
    Abstract: The disclosure describes a novel method and apparatus for providing a shadow access port within a device. The shadow access port is accessed to perform operations in the device by reusing the TDI, TMS, TCK and TDO signals that are used to operate a test access port within the device. The presence and operation of the shadow access port is transparent to the presence and operation of the test access port. According to the disclosure, the shadow access port operates on the falling edge of the TCK signal while the test access port conventionally operates on the rising edge of the TCK signal.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: February 26, 2019
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 10187201
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: January 22, 2019
    Assignee: Intel Corporation
    Inventors: Shay Gueron, Wajdi K Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G Dixon, Srinivas Chennupaty, Michael E Kounavis
  • Patent number: 10181016
    Abstract: An information processing device includes an identification part configured to, in response to a user's operation to start any given one of a plurality of first application programs, determine whether the start of the one of the first application programs is allowed; and a request part configured to request the one of the first application programs to display a first screen which indicates the start of the one of the first application programs is not allowed when the identification part determines that the start of the one of the first application programs is not allowed, and request a second application program to display a second screen including a message when the identification part determines that the start of the one of the first application programs is allowed and when the message needs to be given.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: January 15, 2019
    Assignee: Ricoh Company, Ltd.
    Inventors: Hideki Ohhashi, Kohichi Hirai
  • Patent number: 10181945
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: January 15, 2019
    Assignee: INTEL CORPORATION
    Inventors: Shay Gueron, Wajdi K. Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G. Dixon, Srinivas Chennupaty, Michael E. Kounavis
  • Patent number: 10176210
    Abstract: The methods and systems can include a database management component configured to manage database instances, the database management component also configured to receive a first data request operation on the distributed database, an execution component configured to process the first data request operation including at least one write request on at least one database instance managed by the database management component, and a fault prediction component configured to detect a potential page fault responsive to a target data of the write request, wherein the execution component is further configured to suspend execution of the first data request operation, request access a physical storage to read the target data into active memory, and re-execute the first data request operation after a period of time for suspending the first data request operation.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: January 8, 2019
    Assignee: MongoDB, Inc.
    Inventors: Dwight Merriman, Eliot Horowitz
  • Patent number: 10171232
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: January 1, 2019
    Assignee: Intel Corporation
    Inventors: Shay Gueron, Wajdi K Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G Dixon, Srinivas Chennupaty, Michael E Kounavis
  • Patent number: 10171231
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: January 1, 2019
    Assignee: Intel Corporation
    Inventors: Shay Gueron, Wajdi K Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G Dixon, Srinivas Chennupaty, Michael E Kounavis
  • Patent number: 10164769
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: December 25, 2018
    Assignee: Intel Corporation
    Inventors: Shay Gueron, Wajdi K Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G Dixon, Srinivas Chennupaty, Michael E Kounavis
  • Patent number: 10158478
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: December 18, 2018
    Assignee: Intel Corporation
    Inventors: Shay Gueron, Wajdi K Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G Dixon, Srinivas Chennupaty, Michael E Kounavis
  • Patent number: 10152404
    Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for providing a framework for collaborative debugging. In one aspect, a method includes generating a session for an application executing on a remote debugging system and during the session, receiving one or more application inputs for the application from one or more remote users and providing outputs generated by the application for presentation to the one or more remote users. The method further includes receiving a request to restart the session from a particular remote user, in response to receiving the request to restart the session, resubmitting the one or more application inputs to the application to replicate an ending application state for the session, and providing, for presentation to the particular remote user, a restarted session for the application starting from the ending application state.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: December 11, 2018
    Assignee: VMware, Inc.
    Inventors: Vijay Somasundaram, Sanath Kumar Manavarte
  • Patent number: 10146461
    Abstract: A method of operation of an automatic back-up system includes: providing a mobile device; coupling a removable media device to the mobile device; automatically launching an application on the mobile device; and backing-up user data selected by the application from the mobile device to the removable media device.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: December 4, 2018
    Assignee: ClevX, LLC
    Inventors: Alex Lemelev, Lev M Bolotin
  • Patent number: 10140025
    Abstract: A memory system may include a memory device suitable for storing data requested from a host, and a controller suitable for generating information on the data and transmitting/receiving the data and the information to/from the memory device through first and second data buses, respectively, during a first operation mode, or for transmitting/receiving the data to/from the memory device through one of the first and second data buses based on the data size, during a second operation mode.
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: November 27, 2018
    Assignee: SK Hynix Inc.
    Inventors: Hyung-Gyun Yang, Yong-Ju Kim, Hong-Sik Kim
  • Patent number: 10127170
    Abstract: A baseboard management controller (BMC) of a system can receive a first serial output from a first server device and a second serial output from a second server device. The BMC can send the first serial output and the second serial output to a network interface controller (NIC) for transmission over a network to a computing device.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: November 13, 2018
    Assignee: QUANTA COMPUTER INC.
    Inventors: Te-Hsien Lai, Kai-Pei Chou
  • Patent number: 10127014
    Abstract: A round-for-reround mode (preferably in a BID encoded Decimal format) of a floating point instruction prepares a result for later rounding to a variable number of digits by detecting that the least significant digit may be a 0, and if so changing it to 1 when the trailing digits are not all 0. A subsequent reround instruction is then able to round the result to any number of digits at least 2 fewer than the number of digits of the result. An optional embodiment saves a tag indicating the fact that the low order digit of the result is 0 or 5 if the trailing bits are non-zero in a tag field rather than modify the result. Another optional embodiment also saves a half-way-and-above indicator when the trailing digits represent a decimal with a most significant digit having a value of 5. An optional subsequent reround instruction is able to round the result to any number of digits fewer or equal to the number of digits of the result using the saved tags.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: November 13, 2018
    Assignee: International Business Machines Corporation
    Inventors: Michael F Cowlishaw, Eric M Schwarz, Ronald M Smith, Sr., Phil C Yeh
  • Patent number: 10120773
    Abstract: Methods and systems are disclosed for determining a CPU usage adjustment factor and for automatically applying the CPU usage adjustment factor to provide a CPU usage estimate for an SMT processor. In one implementation, the methods and systems obtain samples of CPU usage reported by the operating system at a predefined sampling rate over a predefined sampling interval. Thread states for the threads substantially corresponding to the reported CPU usage are so obtained at the predefined sampling rate and over the predefined sampling interval. This sampling may be performed for servers running different applications and having diverse processing loads. An estimate of the distribution of the number of threads running for the CPU usages reported may then be determined from the sampled data. A CPU usage adjustment factor may then be derived, based on the distribution, and used to provide a CPU usage estimate.
    Type: Grant
    Filed: September 17, 2013
    Date of Patent: November 6, 2018
    Assignee: United Services Automobile Association (USAA)
    Inventor: Glen A. Becker
  • Patent number: 10114849
    Abstract: Changes to information are managed by storing information as a plurality of objects. Each object has one or more states. One or more temporal histories are maintained for each object based on the plurality of states of the object at a plurality of time instances. For each state of the object, whether or not the state is a user of another state of the object or another object is determined. When a request to change the information is received, at least one state of at least one of the plurality of objects is selectively changed. When it is determined that the at least one state is the user of another state, then the changing is further responsive to changes in the another state.
    Type: Grant
    Filed: February 20, 2014
    Date of Patent: October 30, 2018
    Assignee: Quick Eye Technologies Inc.
    Inventor: Andrei Paraschivescu
  • Patent number: 10114752
    Abstract: A processor in a multi-processor configuration is configured perform dynamic address translation from logical addresses to real address and to detect memory conflicts for shared logical memory in transactional memory based on logical (virtual) addresses comparisons.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: October 30, 2018
    Assignee: International Business Machines Corporation
    Inventors: Michael Karl Gschwind, Eric M. Schwarz, Chung-Lung K. Shum, Timothy J. Slegel
  • Patent number: 10114572
    Abstract: Systems and methods for use in enhancing and dynamically allocating random data bandwidth among requesting cores in multi-core processors to reduce system latencies and increase system performance. In one arrangement, a multicore processor includes a vertical pre-fetch random data buffer structure that stores random data being continuously generated by a random data generator (RNG) so that such random data is ready for consumption upon request from one or more of a plurality of processing cores of the multicore processor. Random data received at one data buffer from a higher level buffer may be automatically deposited into the lower level buffer if room exists in the lower level buffer. Requesting strands of a core may fetch random data directly from its corresponding first level pre-fetch buffer on demand rather than having to trigger a PIO access or the like to fetch random data from the RNG.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: October 30, 2018
    Assignee: Oracle International Corporation
    Inventors: Bruce J. Chang, Fred Tsai, John D. Pape
  • Patent number: 10102017
    Abstract: A computing system in which a software component executing on a platform can reliably and efficiently obtain state information about a component supported by the platform through the use of a shared memory page. State information may be supplied by the platform, but any state translation information needed to map the state information as supplied to a format as used may be provided through the shared page. In a virtualized environment, the state translation information can be used to map the value of a virtual timer counter or other component from a value provided by a virtual processor to a normalized reference time that will yield the same result, regardless of whether the software component is migrated to or from another virtual processor. Use of a shared page avoids the inefficiency of an intercept into a virtualized environment or a system calls in native mode operation.
    Type: Grant
    Filed: February 19, 2013
    Date of Patent: October 16, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Shuvabrata Ganguly, Jason S. Wohlgemuth, Allen Marshall
  • Patent number: 10095433
    Abstract: A data storage system implements out-of-order data transfer. In one embodiment, the data storage system can retrieve from a host system a scatter gather list (SGL) associated with a data read command and generate a memory access table based on the retrieved SGL. The data storage system can further retrieve data from memory, and at least some data may be retrieved out of order. Retrieved data can be provided to the host system using the memory access table, and at least some data may be provided out of order. Data retrieval performance can be increased.
    Type: Grant
    Filed: October 24, 2012
    Date of Patent: October 9, 2018
    Assignee: Western Digital Technologies, Inc.
    Inventor: Jianxun Gao
  • Patent number: 10089425
    Abstract: A system and method is disclosed in an emulation environment that dynamically remaps user designs. In one embodiment, a request is received to load an integrated circuit design to be emulated in a desired partition within the emulator. The emulator automatically determines the availability of the partition requested. If the partition is not available, the design is dynamically remapped to a different partition that is available. In another embodiment, clocks associated with the integrated circuit design are also dynamically remapped. In yet another embodiment, the user can control the size of the partitions (e.g., the number of printed circuit boards in a partition).
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: October 2, 2018
    Assignee: MENTOR GRAPHICS CORPORATION
    Inventors: Eric Durand, Gregoire Brunot, Estelle Reymond, Laurent Buchard
  • Patent number: 10068041
    Abstract: Described herein are a processor and a method of operating the processor to simulate a many-core target machine. The processor includes a plurality of processing cores arranged in a predetermined manner and a global target clock counter (GTCC) configured to count a number of simulated clock cycles in the target machine. A global stall controller (GSC) configured to halt execution of all the processing cores based on a determination of at least one processing core being in a fault condition; and wherein the processor acquires a base clock per instruction (CPI) of a target machine, the CPI corresponding to an average number of clock cycles required by the target machine to execute a single instruction, translates an application of the target machine to a compact executable trace to be executed by the processor, and adjusts a speed of simulation by adjusting an update rate of the global target clock counter.
    Type: Grant
    Filed: February 1, 2016
    Date of Patent: September 4, 2018
    Assignee: King Fahd University of Petroleum and Minerals
    Inventors: Muhammad Elnasir Elrabaa, Ayman Ali Hroub
  • Patent number: 10061568
    Abstract: An approach to dynamic run-time alias checking comprising creating a main thread and a helper thread, computing an optimized first region of code in a rollback-only transactional memory associated with the main thread checking for one or more alias dependencies in an un-optimized first region of code, responsive to a determination in a predetermined amount of time that no alias dependencies are present in the un-optimized first region of code, committing a transaction and responsive to at least one of a failure to determine results of the check for one or more alias dependencies in the predetermined amount of time and a determination in the predetermined amount of time that alias dependencies are present in the un-optimized first region of code, performing a rollback of the transaction and executing the un-optimized first region of code.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: August 28, 2018
    Assignee: International Business Machines Corporation
    Inventors: Yaoqing Gao, William G. O'Farrell, Denis Palmeiro
  • Patent number: 10025590
    Abstract: A multiprocessor system having plural heterogeneous processing units schedules instruction sets for execution on a selected of the processing units by matching workload processing characteristics of processing units and the instruction sets. To establish an instruction set's processing characteristics, the homogeneous instruction set is executed on each of the plural processing units with one or more performance metrics tracked at each of the processing units to determine which processing unit most efficiently executes the instruction set. Instruction set workload processing characteristics are stored for reference in scheduling subsequent execution of the instruction set.
    Type: Grant
    Filed: November 23, 2016
    Date of Patent: July 17, 2018
    Assignee: International Business Machines Corporation
    Inventors: Louis B. Capps, Jr., Ronald E. Newhart, Thomas E. Cook, Robert H. Bell, Jr., Michael J. Shapiro
  • Patent number: 10025286
    Abstract: A programmable controller includes a command executing engine unit that performs a user program and performs a computing process and nonvolatile memory that stores the result of the computing process. The command executing engine unit transitions to a temporary stop state in which a new cycle of computing process is not performed and stores the result of a cycle of computing process in the nonvolatile memory when the cycle of computing process of the user program ends, and releases the temporary stop state and transmits the result of the cycle of computing process stored in the nonvolatile memory to a simulation device when a stop release instructing command instructing to release the temporary stop state is received from the simulation device.
    Type: Grant
    Filed: April 30, 2014
    Date of Patent: July 17, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hajime Tanide, Kazuki Maeda
  • Patent number: 10019994
    Abstract: Methods and systems for recognizing textual identifiers within a plurality of words are described. A textual representation of a voice input is received from a user. The textual representation includes a plurality of words. A keyword is identified in the textual representation. It is determined whether one or more words adjacent to the keyword correspond to a textual identifier of a collection of textual identifiers. Responsive to a determination that the one or more adjacent words correspond to a textual identifier, the keyword and the one or more adjacent words are replaced with the textual identifier.
    Type: Grant
    Filed: June 7, 2013
    Date of Patent: July 10, 2018
    Assignee: Apple Inc.
    Inventor: Daniel Keen
  • Patent number: 10019243
    Abstract: The subject disclosure relates to a method and system for packaging a post-processed definition of a programming module. Contents of a constraint-based and/or order-independent execution model are received, in which the contents include a declarative source code. The contents are stored into an extensible storage abstraction such that the source code is stored in a declarative format. Metadata describing attributes of the contents stored in the extensible storage abstraction is also defined. A file is then created, which includes the extensible storage abstraction and the metadata.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: July 10, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Haroon Ahmed, Chris L. Anderson, Steve Antoch
  • Patent number: 10007720
    Abstract: Example embodiments provide a system and method for analyzing conversations and determining whether to participate with a response. A networked system receives, over a network, a communication that is a part of a conversation involving one or more users, whereby the networked system is a participant in the conversation. The networked system analyzes the communication including parsing key terms from the communication. The networked system then identifies a sentiment of a user among the one or more users based on the parsed key terms. Based on the identified sentiment, the networked system determines whether to respond to the communication. In response to a determination to respond, the networked system generates a customized response and transmits the customized response, over the network, to a device of the user. The customized response may comprise questions or a set of options related to the conversation.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: June 26, 2018
    Assignee: Hipmunk, Inc.
    Inventors: Adam Julian Goldstein, Alex Quintana, Eric Palm, Gregory Millam, Zohaib Ahmed
  • Patent number: 9992153
    Abstract: Exemplary methods, apparatuses, and systems include a first network edge device configuring a physical network interface to be included within a link aggregation group (LAG). The physical network interface of a second network edge device is also included within the LAG. The first network edge device receives, via the LAG, a first address resolution packet including a source and a destination. The first network edge device determines that the destination of the address resolution packet is a networking address assigned to a logical interface that is unique to the second network edge device. In response, first network edge device transmits the address resolution packet from a synchronization network interface to a synchronization network interface of the second network edge device. The synchronization network interface of each network edge device is excluded from sharing a LAG with network edge device ports of the other network edge device.
    Type: Grant
    Filed: July 15, 2015
    Date of Patent: June 5, 2018
    Assignee: NICIRA, INC.
    Inventor: Sreeram Ravinoothala
  • Patent number: 9990114
    Abstract: Customizing publication via multiple outlets includes presenting a user interface for publishing a communication on a plurality of outlets; receiving an initial version of a communication; displaying the initial version of the communication in each of a plurality of editing windows simultaneously, wherein each of the plurality of editing windows corresponds to one of the plurality of outlets or a platform associated with one or more of the plurality outlets; receiving a customization to at least one of the displayed initial versions of the communication; and publishing the communication on each of the plurality of outlets, including the customization to at least one of the displayed initial versions of the communication.
    Type: Grant
    Filed: January 11, 2011
    Date of Patent: June 5, 2018
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Noah Horton, Salman Ansari, Eran Cedar
  • Patent number: 9983965
    Abstract: According to an embodiment of the present invention, a computer implemented method and system for automated test and retesting using an interactive interface provided by a computer processor comprising: an input configured to receive a set of rules for a virtual user, the set of rules comprising a plurality of conditional statements for the virtual user; a memory component configured to store the set of rules; and a rules engine, comprising at least one processor, configured to generate a plurality of test flows based on the set of rules wherein the test flow tool provides modeling capability through an interface comprising a canvas configured to manage one or more rules and a palette that contains a collection of modeling components; and further configured to automatically execute the plurality of test flows on a system under test.
    Type: Grant
    Filed: December 12, 2014
    Date of Patent: May 29, 2018
    Assignee: INNOVATIVE DEFENSE TECHNOLOGIES, LLC
    Inventors: Bernard Gauf, Scott Bindas, William Richard Stubbs
  • Patent number: 9973351
    Abstract: Embodiments of the present invention provide a data processing method, where, after being encapsulated according to an Ethernet protocol, a data processing command is sent to a cabinet by using an Ethernet switch, so that a storage controller in a storage engine can communicate with the cabinet by using the Ethernet switch, thereby effectively utilizing advantages such as ease of expansion and simple operation of the Ethernet switch.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: May 15, 2018
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Bin Fan, Yu Zhang, Haitao Guo
  • Patent number: 9971705
    Abstract: Embodiments of apparatuses and methods including virtual address memory range registers are disclosed. In one embodiment, a processor includes a memory interface, address translation hardware, and virtual memory address comparison hardware. The memory interface is to access a system memory using a physical memory address. The address translation hardware is to support translation of a virtual memory address to the physical memory address. The virtual memory address is used by software to access a virtual memory location in the virtual memory address space of the processor. The virtual memory address comparison hardware is to determine whether the virtual memory address is within a virtual memory address range.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: May 15, 2018
    Assignee: Intel Corporation
    Inventors: Gur Hildesheim, Shlomo Raikin, Ittai Anati, Gideon Gerzon, Uday Savagaonkar, Francis Mckeen, Carlos Rozas, Michael Goldsmith, Prashant Dewan
  • Patent number: 9967346
    Abstract: Passing data over virtual links is disclosed, including: encapsulating a layer three data packet as an inner payload of a network data packet; and generating an outer header of the network data packet with a layer two header and a layer three header, wherein the network data packet is configured to communicate over a virtual link between a first interface of a first network appliance and a first interface of a second network appliance.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: May 8, 2018
    Assignee: Cisco Technology, Inc.
    Inventors: Marco Di Benedetto, Pierluigi Rolando, Thomas Vincent Flynn
  • Patent number: 9967140
    Abstract: Creating virtual links including: determining a first network appliance to configure to communicate with a second network appliance using a virtual link, wherein the virtual link comprises a layer three overlay point-to-point data link; and determining the second network appliance to configure to communicate with the first network appliance using the virtual link.
    Type: Grant
    Filed: May 12, 2016
    Date of Patent: May 8, 2018
    Assignee: Cisco Technology, Inc.
    Inventors: Marco Di Benedetto, Pierluigi Vincent Rolando, Thomas Vincent Flynn
  • Patent number: 9967632
    Abstract: Television tuner emulation techniques are described. In an implementation, a television tuner is emulated through execution of software on a processing system by a computing device, the emulated television tuner includes functionality to obtain television content over an Internet Protocol (IP) based network. The functionality of the emulated television tuner is exposed to one or more applications that are executed by the computing device such that the application is not aware that the television tuner is emulated through execution of the software.
    Type: Grant
    Filed: March 8, 2010
    Date of Patent: May 8, 2018
    Assignee: Rovi Technologies Corporation
    Inventors: Paul R. Cooper, Yvonne N. Ellefson, Arleen Camaganacan Fernando, Imran Arif Maskatia, Matthew Ryan Patterson, Matt Henry Van der Staay, Chad Michael Williams
  • Patent number: 9959376
    Abstract: For a design under test (DUT) that is to be emulated, a host system partitions the DUT into multiple partitions and maps each partition to an FPGA of an emulator which will emulate the partition. The host system stores information describing to which FPGAs each component of the DUT has been mapped. Additionally, mapped to each FPGA is trace and injection logic that traces signals exchanged by the FPGA with other FPGAs during emulation of the DUT. After the emulation of the DUT is complete, if a user wishes to debug a component of the DUT, the FPGAs that are configured to emulate the component are identified. For each identified FPGA, the trace and injection logic injects previously traced signals into the logic of the FPGA in order to reemulate the component. The host system generates waveforms for the user that include signals traced during the reemulation of the component.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: May 1, 2018
    Assignee: Synopsys, Inc.
    Inventor: Ludovic Marc Larzul
  • Patent number: 9954728
    Abstract: A network environment can include a proxy management server. The proxy management server can have access to multiple disparately located MDM servers. A mobile device receives configuration information including a network address of the proxy management server. The mobile device stores the network address of the proxy management server. In response to receiving a management notification such as notification that one or more of the multiple MDM servers has management information (e.g., commands, data, etc., to be executed by the mobile device) available for the mobile device, the mobile device utilizes the stored network address to communicate with the proxy management server. The proxy management server checks availability of the management information from multiple disparately located MDM management servers. The proxy management server retrieves the management information from the management servers and forwards it to the mobile device.
    Type: Grant
    Filed: April 9, 2015
    Date of Patent: April 24, 2018
    Assignee: ARXAN TECHNOLOGIES, INC.
    Inventors: Jeremy Debate, Aaron A. Alexander
  • Patent number: 9952907
    Abstract: A method and apparatus for managing data is provided, including determining one or more network services associated with user-uploaded data stored in a database, and linking the user-uploaded data with the one or more network services to provide the user-uploaded data via the one or more network services.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: April 24, 2018
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Hyung-rae Cho, Hyun-joo Oh, Ji-hyeon Kweon
  • Patent number: 9921921
    Abstract: Data files can be backed up by copying, in response to a backup request, files from a client device to a backup archive and recording the status of the files. Transformed copies of files in the backup archive can be created by automatically applying a transform to the files received from the client device. Upon receiving a subsequent backup request, differences can be identified between transformed files in the backup archive and files on the client device, and in response to identified differences in the files, the transformed files can be copied back to the client device.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: March 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Gabriel Alatorre, Eric K. Butler, Thomas D. Griffin, Divyesh Jadav, Nagapramod S. Mandagere, Aameek Singh, Yang Song
  • Patent number: 9923969
    Abstract: A method comprising receiving one or more data storage specifications from a tenant, determining that a plurality of physical storage units in a physical storage system comprises a sufficient system capacity to provision data storage for the tenant, sending a storage request message to request creation of a network storage entity for the tenant according to the data storage specifications, and receiving a storage response message indicating a first of a plurality of logical storage units allocated to the network storage entity according to the data storage specifications, wherein the plurality of logical storage units are distributed across the plurality of physical storage units, and wherein the plurality of logical storage units are arranged in a sequential order to form a logical circular buffer.
    Type: Grant
    Filed: August 5, 2015
    Date of Patent: March 20, 2018
    Assignee: Futurewei Technologies, Inc.
    Inventors: Masood Mortazavi, Chi Young Ku, Stephen Morgan
  • Patent number: 9910714
    Abstract: The described embodiments include a system for executing a load using a first processor and a seond processor in a computer system. During operation, a load balancer executing on the first processor obtains one or more attributes of a load to be executed on the computer system. Next, the load balancer applies a set of configurable rules to the one or more attributes to select a processor from the first and second processors for executing the load. Finally, the system executes the load on the selected processor.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: March 6, 2018
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Kent F. Knox, Jian Liu