Emulation Patents (Class 703/23)
  • Patent number: 11360934
    Abstract: Embodiments are directed to a processor having a functional slice architecture. The processor is divided into tiles (or functional units) organized into a plurality of functional slices. The functional slices are configured to perform specific operations within the processor, which includes memory slices for storing operand data and arithmetic logic slices for performing operations on received operand data (e.g., vector processing, matrix manipulation). The processor includes a plurality of functional slices of a module type, each functional slice having a plurality of tiles. The processor further includes a plurality of data transport lanes for transporting data in a direction indicated in a corresponding instruction. The processor also includes a plurality of instruction queues, each instruction queue associated with a corresponding functional slice of the plurality of functional slices, wherein the instructions in the instruction queues comprise a functional slice specific operation code.
    Type: Grant
    Filed: November 27, 2020
    Date of Patent: June 14, 2022
    Assignee: GROQ, INC.
    Inventors: Dennis Charles Abts, Jonathan Alexander Ross, John Thompson, Gregory Michael Thorson
  • Patent number: 11336690
    Abstract: A method for emulating threats in virtual network computing environment is provided. The method comprises creating a number of virtual machines in the virtual network computing environment. A number of threat actors are emulated, wherein each threat actor comprises a number of threat artifacts that form a sequence of attack steps against the virtual network computing environment. The threat actors are then deployed against the virtual network computing environment. Behavioral data about actions of the threat actors in the virtual network computing environment is collected, as is performance data about the virtual network computing environment in response to the threat actors. The collected behavioral and performance data is then presented to a user via an interface.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: May 17, 2022
    Assignee: National Technology & Engineering Solutions of Sandia, LLC
    Inventors: Vincent Urias, David Jakob Fritz, Michael Kunz, Caleb Loverro
  • Patent number: 11327858
    Abstract: Systems and processes are disclosed to preserve data integrity during a storage controller failure. In some examples, a storage controller of an active-active controller configuration can back-up data and corresponding cache elements to allow a surviving controller to construct a correct state of a failed controller's write cache. To accomplish this, the systems and processes can implement a relative time stamp for the cache elements that allow the backed-up data to be merged on a block-by-block basis.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: May 10, 2022
    Assignee: Seagate Technology LLC
    Inventors: Adithya Uligere Narasimhamurthy, Ritvik Viswanatha, Michael Barrell
  • Patent number: 11321131
    Abstract: According to one embodiment, an evaluation device includes one or more processors. The one or more processors performs detecting a process of activating a hardware of a system LSI from an application, interrupting execution of the application when the process of activating the hardware is detected, setting, as a load, a memory access pattern of the hardware estimated by simulating performance of the hardware, adding the load to resume the execution of the application, and collecting a profile related to a memory access during the execution of the application, including the load when the execution of the application is resumed.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: May 3, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, Toshiba Electronic Devices & Storage Corporation
    Inventor: Yuji Ishikawa
  • Patent number: 11314413
    Abstract: A tool for adjusting available physical tape storage capacities. The tool determines an initial capacity size for one or more tapes, wherein the initial capacity size is a maximum physical storage capacity provided by the one or more tapes. The tool assigns the one or more tapes to a logical cluster based, at least in part, on the initial capacity size for the one or more tapes. The tool determines an initial storage capacity for the one or more tapes, wherein the initial storage capacity is a starting logical storage capacity that is less than the maximum physical storage capacity provided by the one or more tapes. The tool determines an incremental growth threshold for the one or more tapes. Responsive to a determination that the incremental growth threshold is exceeded, the tool increments a logical storage capacity of the one or more tapes by an incremental growth assignment.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: April 26, 2022
    Assignee: International Business Machines Corporation
    Inventors: David A. Brettell, Alan J. Fisher, Duke A. Lee, Alexander Nieves
  • Patent number: 11295021
    Abstract: Approaches for monitoring a host operating system. A threat model is stored and maintained in an isolated execution environment. The threat model identifies for any process executing on a host operating system how trustworthy the process should be deemed based on a pattern of observed behavior. The execution of the process and those processes in a monitoring circle relationship thereto are monitored. The monitoring circle relationship includes a parent process, any process in communication with a member of monitoring circle relationship, and any process instantiated by a present member of monitoring circle relationship. Observed process behavior is correlated with the threat model. Upon determining that a particular process has behaved in a manner inconsistent with a pattern of allowable behavior identified by the threat model for that process, a responsive action is taken.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: April 5, 2022
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Ian Pratt, Rahul Kashyap, Adrian Taylor, James McKenzie
  • Patent number: 11283524
    Abstract: A storage system includes a connection to one or more optical transceivers, each having one or more Field Programmable Gate Arrays (FPGAs); and a processor and memory storing instructions that, when executed, cause the processor to receive a request for one or more applications for a specific optical transceiver of the one or more optical transceivers, and provide the one or more applications to the specific optical transceiver, wherein the one or more applications are utilized in the specific optical transceiver to dynamically configure digital functionality in its one or more FPGAs for operation in an optical network.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: March 22, 2022
    Assignee: Ciena Corporation
    Inventors: Michael Y. Frankel, Stephen B. Alexander
  • Patent number: 11245660
    Abstract: Techniques for utilizing virtual edge switches of cloud computing networks to send, receive, and store in respective virtual memory, associations between virtual resource and virtual edge switches for better convergence in virtual application centric infrastructure networks. Each virtual memory acts as a virtual endpoint database and contains a number of records indicating associations between each virtual endpoint and the virtual edge switch attached to the virtual endpoint. Each virtual edge switch is hosted by a physical server and is configured to forward communications received from separate physical servers in the cloud computing network to the virtual endpoints attached to the virtual edge switch. The advertisement messages are configured to be sent upon a new virtual resource or a migrated virtual resource spinning-up on a physical server. The advertisement message may be configured to store additional network routing information associated with the virtual machine hosting the virtual endpoint.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: February 8, 2022
    Assignee: Cisco Technology, Inc.
    Inventors: Geetha Anandakrishnan, Paramjeet Rajpaul
  • Patent number: 11216909
    Abstract: An information processing apparatus, connectable with an image output apparatus, includes circuitry to receive image data of an image from a memory, acquire information of an image placement region of the image output apparatus, the image placement region being variable depending on a type of the image output apparatus, and the image is to be output on the image placement region of the image output apparatus, generate an output image by placing the image within the image placement region based on the image data of the image to be output, and the image placement region of the image output apparatus, and transmit the generated output image to the image output apparatus.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: January 4, 2022
    Assignee: Ricoh Company, Ltd.
    Inventors: Tomoyuki Takahira, Akio Ishida
  • Patent number: 11199557
    Abstract: Experimental studies can be conducted in an environment where one or more laboratories communicate with a network instrument monitoring center over a network. In such an environment, an individual at the network instrument monitoring center can be enabled to simultaneously oversee studies at multiple remote laboratories, rather than requiring dedicated individuals at each of the laboratories to oversee the studies at their respective labs.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: December 14, 2021
    Assignee: Beckman Coulter, Inc.
    Inventors: Caren E. Parker, Craig R. Cole, Sadasiva R. Guntupalli
  • Patent number: 11200098
    Abstract: A technique for operating a system including a plurality of processors and a shared resource includes executing a first instruction by a first processor of the plurality of processors. The first instruction generates a reservation of the shared resource for the first processor. The technique includes, after generating the reservation of the shared resource for the first processor, executing a spin lock by the first processor until successful execution of a second instruction acquires a lock of the shared resource. The technique includes disabling interrupts of the first processor in response to an indicator of the successful execution of the second instruction. The first instruction may be a load and reserve instruction and the second instruction may be a conditional store instruction.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: December 14, 2021
    Assignee: NXP USA, Inc.
    Inventors: Sourav Roy, Sneha Mishra
  • Patent number: 11194606
    Abstract: Aspects of the disclosure provide for mechanisms for managing related devices for virtual machines in a computer system. A method of the disclosure includes: associating, by a processing device executing a hypervisor, hypervisor data with a first bridge device; attaching a first device associated with a virtual machine to the first bridge device; identifying a second device related to the first device; associating, by the processing device, the hypervisor data with the second device. In some embodiments, the second device is a failover device of the first device.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: December 7, 2021
    Assignee: Red Hat, Inc.
    Inventor: Michael Tsirkin
  • Patent number: 11188476
    Abstract: A method for preserving a media access control (MAC) address of a virtual server is provided. The method includes assigning a physical computing resource to a virtual server, assigning a physical storage memory resource to the virtual server, and assigning a physical network resource to the virtual server. The method includes assigning a virtual MAC address to the virtual server, the virtual MAC address to remain with the virtual server despite reassignment of one or more of the physical computing resource, the physical storage memory resource or the physical network resource, wherein at least one method operation is performed by a processor. A computing and storage system is also provided.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: November 30, 2021
    Assignee: Pure Storage, Inc.
    Inventors: John Hayes, Par Botes, Robert Lee, Peter Vajgel
  • Patent number: 11188695
    Abstract: Synthesis of functional coverage (e.g., covergroups) is optimized for hardware emulation. The optimization may reduce the number of logic gates used to implement the hardware emulator circuits or reduce the computer resources used to synthesize the hardware emulator circuits. The optimization may also prevent the synthesis of unnecessary circuits. In another aspect, the optimization may result in a representation that may be used both to synthesize hardware emulation circuits and as part of formal verification. This may result in a model that can be used for formal verification, hardware emulation, and software simulation.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: November 30, 2021
    Assignee: Synopsys, Inc.
    Inventors: Dmitry Korchemny, Ashok Kumar Bhatt, Eduard Rudolf Cerny, Hanish Singla
  • Patent number: 11175933
    Abstract: Responsive to a detected user access by a user to help content of an application, at least one subsequent detected user interaction with the application is recorded that documents the user's actual use of the application in response to instructions within the accessed help content. The help content includes tracking metrics that include at least one configured expected user interaction with the application to perform the instructions within the accessed help content. The usability of the application is improved by automatically changing the application based upon results of a comparison of the recorded at least one subsequent detected user interaction with the application after the help content was accessed with the at least one configured expected user interaction with the application to perform the instructions within the accessed help content reaching a threshold for modification of the application.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: November 16, 2021
    Assignee: International Business Machines Corporation
    Inventors: Andrew A. Armstrong, Richard W. Pilot
  • Patent number: 11163826
    Abstract: The invention relates to a computerized method and computer-based system for generating elements of recorded information for a secondary user in response to the secondary user's natural language input. The recorded information could be in the form of, for example, video, audio, audiovisual, text files, or other recordable media. The method and system of the invention permit a secondary user to access, in real time, information of an original source (e.g., allows a descendant to obtain a multimedia response stored by or on behalf of an ancestor) via a computer network, with the response being accessible via a television, audio player, Bluetooth or wireless device, or any other electronic and digital system. The access to such information can be initiated by the secondary user's input provided through use of, for example, voice response technology, including speech recognition and natural language software.
    Type: Grant
    Filed: March 1, 2020
    Date of Patent: November 2, 2021
    Inventor: Daniel Joseph Qualiano
  • Patent number: 11134025
    Abstract: The present disclosure relates to a 5G or pre-5G communication system to be provided for supporting a data rate higher than that of a 4G communication system such as LTE. A dynamic resource allocation method of an intelligent orchestrator in a software-defined network (SDN) according to the present invention includes acquiring operation data related to resource allocation in the SDN, adjusting at least one of virtual switch and host parameters based on the operation data and a preconfigured scheduling policy, and allocating resources dynamically according to the adjustment result.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: September 28, 2021
    Inventors: Ashish Billore, Sergey Dyasli, Jonghan Park, Heetae Ahn, Kibeom Nam
  • Patent number: 11128632
    Abstract: Capturing user presence at a workstation of a local network using an identity directory comprises detecting an unlock event, generating first and second arrays of all instances of respective first and second processes currently occurring in the local network, each instance being associated with a session ID, comparing the first and second arrays to ascertain whether any of the session IDs present in the second array are missing from the first array, performing a query in the identity directory to locate a user account associated with any session ID present in the first array and missing from the second array, and updating a record of the user accounts found in the query in regard to the user presence having been captured in association with the detected unlock event.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: September 21, 2021
    Assignee: Saudi Arabian Oil Company
    Inventor: Gary Simmons
  • Patent number: 11106846
    Abstract: A compaction circuit in an emulation system may store in a data array emulation data that may be read in subsequent emulation steps. For each emulation step, the compaction circuit may receive keeptags from a local control store word of the emulation step and store portions of emulation data identified by the keeptags. The keeptags in the control store words may be inserted by a compiler based upon whether a corresponding read port of emulation processor reads the stored data in the subsequent steps. The compaction circuit may also translate the logical read address of the stored data to a physical read address in the shared data array. A dynamic modification engine may enable dynamic modification of netlists while using the compacted data array. In response to a request, the dynamic modification engine may modify one or more keeptags and update read addresses in the control store words.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: August 31, 2021
    Inventors: Mitchell G. Poplack, Yuhei Hayashi
  • Patent number: 11107465
    Abstract: The present application discloses a multi-media interactive story-telling system that provides natural conversational interactions between a human user and a contributor who appears in multi-media recordings. The multi-media interactive story-telling system includes an intake device for recording interview sessions in which a contributor tells a life story about her life experience. The contributor may rely on a script when creating the life story. The multi-media interactive story-telling system further comprises storage devices for storing the recorded interview sessions and processors for organizing the recorded interview sessions. The multi-media interactive story-telling system further comprises an interactive device for retrieving and playing a recorded interview session in response to a query from a user.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: August 31, 2021
    Assignee: StoryFile, LLC
    Inventors: Samuel Gustman, Stephen Smith, Heather Maio-Smith, Julia Campbell, Andrew Jones
  • Patent number: 11089636
    Abstract: A network connectivity mode is activated at a vehicle during which an on-board wireless LAN interface and an on-board wireless WAN interface are collectively operated in a higher-power consumption state with respect to a set of on-board batteries to collectively support communications between one or more LAN-side client devices and one or more WAN-side network resources. Operation of the vehicle entering a predefined operating state is detected, and in response thereto, the network connectivity mode is deactivated after a period of time during which the on-board wireless LAN interface and the on-board wireless WAN interface are collectively operated in a lower-power consumption state with respect to the set of on-board batteries and communications are discontinued between the one or more LAN-side client devices and the one or more WAN-side network resources via the on-board wireless LAN interface and the on-board wireless WAN interface.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: August 10, 2021
    Assignee: MOJ.IO, Inc.
    Inventor: Markus Hummel
  • Patent number: 11068424
    Abstract: A computer system includes a BMC and a host of the BMC. The BMC receives a first message from a first remote device on a management network. The BMC determines whether the first message is directed to a storage service or fabric service executed on a central processing unit of the host. The host is a storage device. The central processing unit is in commutation with a RDMA controller through an external communication channel. The RDMA controller being managed by the storage service. The BMC extracts a service management command from the first message, when the first message is directed to the storage service or fabric service. The BMC sends, through a BMC communication channel to the host, a second message containing the service management command to the host. The BMC communication channel has been established for communicating baseboard management commands between the BMC and the host.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: July 20, 2021
    Inventors: Anurag Bhatia, Jason Messer, Sanjoy Maity
  • Patent number: 11061810
    Abstract: A system and method of stopping program execution includes tagging an entry in a virtual cache with an indicator bit where the virtual address of the entry corresponds to a virtual address range in a break point register, in response to a second virtual cache data access demand matching the entry tagged with the indicator bit, determining whether the second data access demand matches the virtual address range of the breakpoint register, and in response to the second data access demand matching the virtual address range of the break point register, flagging an exception and stopping execution of the program. In an embodiment, the method or system enters a slow-mode in response to the second data access demand matching the virtual cache entry with the indicator bit, and performs a full comparison between the second data access demand and the break point register virtual address range.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: July 13, 2021
    Assignee: International Business Machines Corporation
    Inventors: David Campbell, Dwain A. Hicks, David A. Hrusecky, Bryan Lloyd
  • Patent number: 11044241
    Abstract: Systems and methods for providing one or more services to a device are disclosed. The device may be remote from a first network. The one or more services may be associated with the first network.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: June 22, 2021
    Inventor: Yiu L. Lee
  • Patent number: 11023311
    Abstract: Systems and methods are described for modifying input and output (I/O) to an object storage service by implementing one or more owner-specified functions to I/O requests. A function can implement a data manipulation, such as filtering out sensitive data before reading or writing the data. The functions can be applied prior to implementing a request method (e.g., GET or PUT) specified within the I/O request, such that the data to which the method is applied my not match the object specified within the request. For example, a user may request to obtain (e.g., GET) a data set. The data set may be passed to a function that filters sensitive data to the data set, and the GET request method may then be applied to the output of the function. In this manner, owners of objects on an object storage service are provided with greater control of objects stored or retrieved from the service.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: June 1, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Ramyanshu Datta, Timothy Lawrence Harris, Kevin C. Miller, Haripriya Devnath, Robert Devers Wilson
  • Patent number: 10977235
    Abstract: Changes to information are managed by storing information as a plurality of objects. Each object has one or more states. One or more temporal histories are maintained for each object based on the plurality of states of the object at a plurality of time instances. For each state of the object, whether or not the state is a user of another state of the object or another object is determined. When a request to change the information is received, at least one state of at least one of the plurality of objects is selectively changed. When it is determined that the at least one state is the user of another state, then the changing is further responsive to changes in the another state.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: April 13, 2021
    Inventor: Andrei Paraschivescu
  • Patent number: 10972350
    Abstract: Examples described herein include imaging servers which may support asynchronous imaging of one or more computers (e.g., computing nodes). The imaging server may use out-of-band communication to install requested images on one or more computing nodes. The imaging server may support multiple concurrent installation sessions, and may maintain a log specific to each session. This may facilitate session-specific status reporting. In this manner, operating systems, hypervisors, or other software may be installed on computing nodes.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: April 6, 2021
    Assignee: Nutanix, Inc.
    Inventors: Toms Varghese, Jaspal Singh Dhillon, Raghu Rapole, Avi Bhandari
  • Patent number: 10963239
    Abstract: According to a computer-implemented method, an update package that includes update operational files is received at a computing device. At least one update operational file is to replace a corresponding original operational file for the computing device. It is determined which of the original operational files are to be replaced with corresponding update operational files. A delta file is stored at the computing device, which delta file indicates the original operational files that are replaced with corresponding update operational files and the update package is installed at the computing device.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: March 30, 2021
    Inventors: Leo M. Farrell, Scott Exton, Anthony B. Ferguson
  • Patent number: 10949588
    Abstract: A method of capturing signals during hardware verification of a circuit design utilizes at least one field-programmable gate array (FPGA) and includes selecting, at run time and using one or more pre-compiled macros, a group of signals to be captured during verification of the circuit design and storing values of the group of signals in at least first and second random access memories disposed in the at least one FPGA. The first and second random access memories may be addressable spaces of the same random access memory.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: March 16, 2021
    Assignee: SYNOPSYS, INC.
    Inventors: Arturo Salz, Ching-Ping Chou, Jean-Philippe Colrat, Sébastien Roger Delerse, Luc François Vidal, Arnold Mbotchak
  • Patent number: 10942663
    Abstract: Techniques are provided for inlining data in inodes of a file system. In an example, data (e.g., a file) is to be written to storage. Where the data is small enough to fit in an inode, it can be written to a dynamic area of the inode. Where dynamic attributes of the inode conflict with storing the data, the dynamic attributes can be spilled to a metadata block. Where the inlined data becomes too large to be stored in the inode, it can be spilled to a data block, and a metadata tree can be written to the inode. Where data that was previously too large to inline is truncated so that now it can be written to the inode, the data is inlined in the inode from a data block.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: March 9, 2021
    Inventors: Attilio Rao, Dmitri Chmelev
  • Patent number: 10942838
    Abstract: An electronic device is described herein. In accordance with one embodiment, the electronic device includes an embedded controller having a debug logic, an interface circuit coupled to the debug logic, and a memory coupled to the interface circuit. The interface circuit is operative to read debug information stored in the debug logic and to transmit the read debug information to the memory. The interface circuit is further operative to receive debug information stored in the memory and write the received debug information into the debug logic.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: March 9, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Matthias Schneider, Arndt Pauschardt, Yuanfen Zheng
  • Patent number: 10928442
    Abstract: Computer implemented methods of designing integrated circuits and computing systems are provided. A computer implemented method of designing an integrated circuit according to the inventive concepts may be performed by a processor and may include performing a placement and routing (P&R) operation for standard cells defining the integrated circuit, extracting characteristic values from a result of the P&R operation, generating a physical-aware annotation file by determining a plurality of representative characteristic values that respectively correspond to a plurality of groups based on the extracted characteristic values, and performing a physical-aware synthesis operation to generate a netlist from input data for the integrated circuit, based on the generated physical-aware annotation file.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: February 23, 2021
    Inventors: Tae-il Kim, Jae-hoon Kim, Hyung-ock Kim, Jung-yun Choi
  • Patent number: 10917335
    Abstract: Method and systems for data switching, including receiving first input data at a network switching system comprising a crosspoint switch and a data processing card; transmitting the first input data from the crosspoint switch to the data processing card; making a first determination, by the data processing card, that the first input data meets a first pre-determined filtering criterion; and transmitting, based on the first determination, the first input data from a first crosspoint switch port of the crosspoint switch towards a first client.
    Type: Grant
    Filed: April 5, 2019
    Date of Patent: February 9, 2021
    Assignee: Arista Networks, Inc.
    Inventors: Robert James Walker, Stefan Josef Gratzl, Sergey Sardaryan, Vahan Sardaryan
  • Patent number: 10915371
    Abstract: A system for providing automatic management of low latency computational capacity is provided. The system may be configured to maintain a plurality of virtual machine instances. The system may be further configured to identify a trend in incoming code execution requests to execute program code on a virtual compute system, determine, based on the identified trend, that the plurality of virtual machine instances should be adjusted, and adjust the plurality of virtual machine instances based on the identified trend.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: February 9, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Timothy Allen Wagner, Sean Philip Reque, Dylan Chandler Thomas, Derek Steven Manwaring, Bradley Nathaniel Burkett
  • Patent number: 10877792
    Abstract: An example method comprises receiving a begin time to initiate storage network traffic data collection from a plurality of data probes integrated within an enterprise network, collecting network data identifying HBA ports used to communicate with storage ports from the probes, analyzing the network data to determine attributes of network traffic, determining for each storage unit: a penalty score for each of the storage ports determining a reconfiguration of a storage unit or HBA based at least in part on the total penalty score, simulating changes of the reconfiguration of the storage unit or the HBA and simulate storage network traffic, applying the simulated storage network traffic on the simulated changes of the reconfiguration of the storage unit or HBA to determine improvements, and outputting instructions to enable reconfiguration of the storage unit or HBA.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: December 29, 2020
    Assignee: Virtual Instruments Corporation
    Inventors: Francis Niestemski, Ryan E. Perkowski, Nicholas York
  • Patent number: 10853071
    Abstract: A method and apparatus for simulating target program code on a host data processing apparatus, the simulation mapping load-exclusive instructions in the target program code to load instructions, and mapping store-exclusive instructions in the target program code to compare-and-swap instructions.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: December 1, 2020
    Assignee: Arm Limited
    Inventors: Adam James McNeeney, Gareth James Evans
  • Patent number: 10838748
    Abstract: Disclosed are systems and methods for emulating execution of a file based on emulation time. In one aspect, an exemplary method comprises, generating an image of a file, emulating an execution of instructions from the image for a predetermined emulation time, the emulation including: when an emulation of an execution of instruction from an image of another file is needed, generating an image of the another file, detecting known set of instructions in portions read from the image, inserting a break point into a position in the generated image corresponding to a start of the detected set of instructions, emulating execution of the another file by emulating execution of instructions from the generated image, and adding corresponding records to an emulation log, and reading a next portion from the image of the another file and repeating the emulation until the predetermined emulation time has elapsed.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: November 17, 2020
    Assignee: AO Kaspersky Lab
    Inventors: Alexander V. Liskin, Vladimir V. Krylov
  • Patent number: 10789405
    Abstract: An event-driven simulation system is provided. The simulation system classifies events into bypass-events and perform-events. The simulation system performs simulation by executing instructions based on the perform-events and skips simulation for the bypass-events. The simulation system produces partial simulation result data based events that are actually simulated but not the events that are skipped. A post processor is provided to generate the missing simulation result data for the bypass-events and to merge the bypass-event with the partial simulation result to generate a complete simulation result.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: September 29, 2020
    Assignee: Montana Systems Inc.
    Inventors: Vivian Chou, Sherman Lee
  • Patent number: 10769817
    Abstract: A system and method for image testing is configured to apply at least one display property to a test image to generate a display modified test image and applying the at least one display property to a reference image to generate a display modified reference image. The system also applies a human eye model to the display modified test image to generate an eye modified test image and applies the human eye model to the display modified reference image to generate an eye modified reference image. The system may compare the eye modified test image with the eye modified reference image to determine human perceivable differences between the test image and the reference image.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: September 8, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Gregory W. Cook, Javier Ribera Prat, Shiva Moballegh
  • Patent number: 10742776
    Abstract: Isochronous endpoints of a redirected USB device can be accelerated. When a USB device is redirected, each of the device's endpoints can be identified. A UDP socket can then be created between the client-side proxy and the server-side agent for each isochronous endpoint, while a TCP socket can be created for each other endpoint. A lookup table can also be created which maps pipe handles to socket IDs. The lookup table can be employed to route USB request blocks pertaining to a particular endpoint over the corresponding socket. In this way, USB request blocks pertaining to an isochronous endpoint will be transferred over the network using UDP while USB request blocks pertaining to non-isochronous endpoints will be transferred using TCP.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: August 11, 2020
    Assignee: Dell Products L.P.
    Inventors: Gokul Thiruchengode Vajravel, Ankit Kumar
  • Patent number: 10740220
    Abstract: Performing breakpoint detection via a cache includes detecting an occurrence of a memory access and identifying whether any cache line of the cache matches an address associated with the memory access. When a cache line does match the address associated with the memory access no breakpoint was encountered. When no cache line matches the address associated with the memory access embodiments identify whether any cache line matches the address associated with the memory access when one or more flag bits are ignored. When a cache line does match the address associated with the memory access when the one or more flag bits are ignored, embodiment perform a check for whether a breakpoint was encountered. Otherwise, embodiments process a cache miss.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: August 11, 2020
    Inventor: Jordi Mola
  • Patent number: 10698731
    Abstract: A system and method is provided for performing computations on a virtual machine without a special hardware computation unit, such as a discrete graphics processing unit (GPU). The described method uses a computation module to intercept requests from a user application executing in a virtual machine on a first physical computer. The intercepted requests may include requests to configure GPU computation grids, start and finish accelerated code execution, and transfer data to and from the special computation unit. The computation module offloads accelerated code to a second physical computer having a physical special hardware unit (e.g., discrete GPU).
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: June 30, 2020
    Inventors: Anton Zelenov, Nikolay Dobrovolskiy, Serguei M. Beloussov, Alexey Koryakin
  • Patent number: 10664600
    Abstract: Apparatus, systems, or methods for a programmable circuit to facilitate a processor to boot a computing device having the processor. A programmable circuit may include non-volatile storage and firmware stored in the non-volatile storage. The firmware may configure the programmable circuit as a memory controller of a memory device coupled to the programmable circuit, to facilitate the processor to boot the computing device having the processor, the programmable circuit, and the memory device, into operation. Other embodiments may also be described and claimed.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: May 26, 2020
    Assignee: Intel Corporation
    Inventors: Yah Wen Ho, Tung Lun Loo, Yan Fei Lee
  • Patent number: 10634723
    Abstract: The present invention facilitates efficient and effective device testing and debugging. In one embodiment, a tester system includes a controller processor; a plurality of programmable accelerator circuits coupled to and controlled by the controller processor; and a plurality of load boards respectively coupled to the plurality of programmable accelerator circuits. The plurality of load boards can apply the input test signals to a plurality of devices under test (DUTs) and capture the output test signals therefrom. The plurality of programmable accelerator circuits can provide input test signals and capture output test signals. In one exemplary implementation, each of the plurality of load boards comprises: a first set of connections for transmitting input test signals to a respective DUT; a second set of connections for receiving output test signals from the respective DUT; and sideband connectors. The sideband connectors receive test related information from the DUT.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: April 28, 2020
    Inventors: Ben Rogel-Favila, Mei-Mei Su, John Frediani, Shunji Tachibana
  • Patent number: 10594790
    Abstract: A method for execution by a dispersed storage and task (DST) processing unit includes receiving a write request that includes a data object. Characterization data is generated by determining a data type of the data object. Object constraint data is generated by determining a compressibility of the data type and a processing cost of the data type. Optimized trade-off data is generated by optimizing a plurality of trade-off constraints based on the object constraint data. A compression algorithm is selected from a plurality of compression algorithm options based on the optimized trade-off data. A compressed data object is generated by performing the selected compression algorithm on the data object. A plurality of data slices are generated for transmission to a plurality of storage units for storage by performing an information dispersal algorithm on the compressed data object.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: March 17, 2020
    Inventors: Adam M. Gray, Ravi V. Khadiwala, Greg R. Dhuse, Jason K. Resch, Praveen Viraraghavan, Russell C. Fordyce
  • Patent number: 10581590
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: March 3, 2020
    Assignee: Intel Corporation
    Inventors: Shay Gueron, Wajdi K Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G Dixon, Srinivas Chennupaty, Michael E Kounavis
  • Patent number: 10554782
    Abstract: A stream application may use small chunks of executable code configured to process data tuples flowing into a processing element. A scheduler allocates the processing elements to individual compute nodes or hosts for execution. However, the stream application may assign various constraints that stipulate which hosts are suitable for a particular processing element. To assign hosts to processing elements such that the constraints are satisfied, the scheduler may use hostpools associated with the processing elements. Once a host is identified that satisfies the constraints, it may be pinned at a particular index within the hostpool.
    Type: Grant
    Filed: December 1, 2011
    Date of Patent: February 4, 2020
    Assignee: International Business Machines Corporation
    Inventor: Bradley W. Fawcett
  • Patent number: 10540347
    Abstract: Methods, systems, computer-readable media, and apparatuses for providing search disambiguation using contextual information and domain ontologies are presented. In some embodiments, a computing device may receive a natural language input from a user. The computing device may identify a plurality of hypotheses for the natural language input. The computing device may map the plurality of hypotheses to one or more concepts of a plurality of concepts of an ontology by annotating the one or more concepts. The ontology may include the plurality of concepts respectively connected by a plurality of relations. The computing device may determine that there is an imperfect match between the annotated one or more concepts and annotations of answers. In response, the computing device may disambiguate the annotated one or more concepts using the ontology. The computing device may present output to the user based on the disambiguation.
    Type: Grant
    Filed: October 27, 2014
    Date of Patent: January 21, 2020
    Assignee: Nuance Communications, Inc.
    Inventors: Ladislav Kunc, Martin Labský, Tomá{hacek over (s)} Macek, Jan Vystr{hacek over (c)}il, Jan Kleindienst
  • Patent number: 10528690
    Abstract: A computer-aided method for configuring a hardware verification system is presented. The method includes receiving, by the computer, a first data representative of a first design of an integrated circuit, when the computer is invoked to configure the verification system, and transforming, using the computer, the first data into a second data representative of a second design. The second design includes a functionality of the first design, and a first circuit adapted to compute a third data representative of a power consumption of a first portion of the first design when the hardware verification system is configured with the second data and run. The first circuit is programmable without reconfiguring the second design.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: January 7, 2020
    Assignee: Synopsys, Inc.
    Inventor: Ching-Ping Chou
  • Patent number: 10496461
    Abstract: A method of emulating an instruction includes identifying a fault instruction. The fault instruction is saved in a register. The fault instruction is associated with a software emulated operation. The software emulated operation is initiated with an access to the fault instruction in the register.
    Type: Grant
    Filed: June 15, 2011
    Date of Patent: December 3, 2019
    Assignee: ARM Finance Overseas Limited
    Inventor: David Yiu-Man Lau