Emulation Patents (Class 703/23)
  • Patent number: 10698731
    Abstract: A system and method is provided for performing computations on a virtual machine without a special hardware computation unit, such as a discrete graphics processing unit (GPU). The described method uses a computation module to intercept requests from a user application executing in a virtual machine on a first physical computer. The intercepted requests may include requests to configure GPU computation grids, start and finish accelerated code execution, and transfer data to and from the special computation unit. The computation module offloads accelerated code to a second physical computer having a physical special hardware unit (e.g., discrete GPU).
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: June 30, 2020
    Assignee: PARALLELS INTERNATIONAL GMBH
    Inventors: Anton Zelenov, Nikolay Dobrovolskiy, Serguei M. Beloussov, Alexey Koryakin
  • Patent number: 10664600
    Abstract: Apparatus, systems, or methods for a programmable circuit to facilitate a processor to boot a computing device having the processor. A programmable circuit may include non-volatile storage and firmware stored in the non-volatile storage. The firmware may configure the programmable circuit as a memory controller of a memory device coupled to the programmable circuit, to facilitate the processor to boot the computing device having the processor, the programmable circuit, and the memory device, into operation. Other embodiments may also be described and claimed.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: May 26, 2020
    Assignee: Intel Corporation
    Inventors: Yah Wen Ho, Tung Lun Loo, Yan Fei Lee
  • Patent number: 10634723
    Abstract: The present invention facilitates efficient and effective device testing and debugging. In one embodiment, a tester system includes a controller processor; a plurality of programmable accelerator circuits coupled to and controlled by the controller processor; and a plurality of load boards respectively coupled to the plurality of programmable accelerator circuits. The plurality of load boards can apply the input test signals to a plurality of devices under test (DUTs) and capture the output test signals therefrom. The plurality of programmable accelerator circuits can provide input test signals and capture output test signals. In one exemplary implementation, each of the plurality of load boards comprises: a first set of connections for transmitting input test signals to a respective DUT; a second set of connections for receiving output test signals from the respective DUT; and sideband connectors. The sideband connectors receive test related information from the DUT.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: April 28, 2020
    Assignee: ADVANTEST CORPORATION
    Inventors: Ben Rogel-Favila, Mei-Mei Su, John Frediani, Shunji Tachibana
  • Patent number: 10594790
    Abstract: A method for execution by a dispersed storage and task (DST) processing unit includes receiving a write request that includes a data object. Characterization data is generated by determining a data type of the data object. Object constraint data is generated by determining a compressibility of the data type and a processing cost of the data type. Optimized trade-off data is generated by optimizing a plurality of trade-off constraints based on the object constraint data. A compression algorithm is selected from a plurality of compression algorithm options based on the optimized trade-off data. A compressed data object is generated by performing the selected compression algorithm on the data object. A plurality of data slices are generated for transmission to a plurality of storage units for storage by performing an information dispersal algorithm on the compressed data object.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: March 17, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Adam M. Gray, Ravi V. Khadiwala, Greg R. Dhuse, Jason K. Resch, Praveen Viraraghavan, Russell C. Fordyce
  • Patent number: 10581590
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: March 3, 2020
    Assignee: Intel Corporation
    Inventors: Shay Gueron, Wajdi K Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G Dixon, Srinivas Chennupaty, Michael E Kounavis
  • Patent number: 10554782
    Abstract: A stream application may use small chunks of executable code configured to process data tuples flowing into a processing element. A scheduler allocates the processing elements to individual compute nodes or hosts for execution. However, the stream application may assign various constraints that stipulate which hosts are suitable for a particular processing element. To assign hosts to processing elements such that the constraints are satisfied, the scheduler may use hostpools associated with the processing elements. Once a host is identified that satisfies the constraints, it may be pinned at a particular index within the hostpool.
    Type: Grant
    Filed: December 1, 2011
    Date of Patent: February 4, 2020
    Assignee: International Business Machines Corporation
    Inventor: Bradley W. Fawcett
  • Patent number: 10540347
    Abstract: Methods, systems, computer-readable media, and apparatuses for providing search disambiguation using contextual information and domain ontologies are presented. In some embodiments, a computing device may receive a natural language input from a user. The computing device may identify a plurality of hypotheses for the natural language input. The computing device may map the plurality of hypotheses to one or more concepts of a plurality of concepts of an ontology by annotating the one or more concepts. The ontology may include the plurality of concepts respectively connected by a plurality of relations. The computing device may determine that there is an imperfect match between the annotated one or more concepts and annotations of answers. In response, the computing device may disambiguate the annotated one or more concepts using the ontology. The computing device may present output to the user based on the disambiguation.
    Type: Grant
    Filed: October 27, 2014
    Date of Patent: January 21, 2020
    Assignee: Nuance Communications, Inc.
    Inventors: Ladislav Kunc, Martin Labský, Tomá{hacek over (s)} Macek, Jan Vystr{hacek over (c)}il, Jan Kleindienst
  • Patent number: 10528690
    Abstract: A computer-aided method for configuring a hardware verification system is presented. The method includes receiving, by the computer, a first data representative of a first design of an integrated circuit, when the computer is invoked to configure the verification system, and transforming, using the computer, the first data into a second data representative of a second design. The second design includes a functionality of the first design, and a first circuit adapted to compute a third data representative of a power consumption of a first portion of the first design when the hardware verification system is configured with the second data and run. The first circuit is programmable without reconfiguring the second design.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: January 7, 2020
    Assignee: Synopsys, Inc.
    Inventor: Ching-Ping Chou
  • Patent number: 10496461
    Abstract: A method of emulating an instruction includes identifying a fault instruction. The fault instruction is saved in a register. The fault instruction is associated with a software emulated operation. The software emulated operation is initiated with an access to the fault instruction in the register.
    Type: Grant
    Filed: June 15, 2011
    Date of Patent: December 3, 2019
    Assignee: ARM Finance Overseas Limited
    Inventor: David Yiu-Man Lau
  • Patent number: 10484268
    Abstract: A digital crosspoint switch of a network switching system (NSS) replicates input data received via a first network interface to a first data processing port of a data processing card. The input data includes a digital market data feed comprising market-data packets. The crosspoint switch has internal crosspoint ports and external crosspoint ports. The data processing card includes a programmable logic device and a plurality of data processing ports connected to the internal crosspoint ports. The NSS includes a plurality of network interfaces connected to the external crosspoint ports. The data processing card processes the input data and generates processed data on the second data processing port at least in part by only including market-data packets that meet a first predetermined filtering criterion in the processed data. The crosspoint switch replicates the processed data from the second data processing port to the second network interface.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: November 19, 2019
    Assignee: METAMAKO GENERAL PTY LTD ACN 163 573 331 IN ITS CAPACITY AS GENERAL PARTNER OF METAMAKO TECHNOLOGY LP ABN 11 872 058 101
    Inventors: Robert James Walker, Stefan Josef Gratzl, Sergey Sardaryan, Vahan Sardaryan
  • Patent number: 10467368
    Abstract: A computer-implemented method generates a plurality of clusters based on components included in a design under test (DUT); classifies a subset of clusters of the plurality of clusters as tangled clusters; modifies at least two tangled clusters of the subset of clusters based on overlap between the at least two tangled clusters; determines, for each tangled cluster in the subset of clusters, a gate count based on the interconnectivity of the tangled cluster; and partitions the DUT among a plurality of field-programmable gate arrays (FPGAs) based on the gate count determined for each tangled cluster from the subset of clusters.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: November 5, 2019
    Assignee: Synopsys, Inc.
    Inventors: Etienne Lepercq, Jiahua Zhu, Jiong Cao, Marc-Andre Daigneault
  • Patent number: 10467131
    Abstract: Performance analysis for test automation frameworks is described. A test is executed of an application. Performance indicators are logged during execution of the test, wherein the performance indicators include a first performance indicator. A correlation is identified between the first performance indicator and a second performance indicator recorded during the execution of the test or an execution of a previous test of the application. An output device outputs the correlation as a performance issue.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: November 5, 2019
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Rajendra Kumar Gupta, Anupam Sharma, Sanjeev Kumar Lohchab, Naveen Kumar Surendra Rao, Swapnadeep Deb Kanunjna
  • Patent number: 10437432
    Abstract: Methods, systems, and computer programs for integration of user interface technologies. One of the methods includes receiving, from a user device, a user request to execute a web application, the web application being associated with one or more rendering systems, and each of the rendering systems executing one or more respective remote applications. Respective video streams for the remote applications are obtained from each of the rendering systems. Each of the video streams is provided for presentation on the user device. While the video streams are provided, data identifying a user event is received from the user device. The user event is determined to be intended for a first rendering system. The user event is provided to the first rendering system.
    Type: Grant
    Filed: September 17, 2014
    Date of Patent: October 8, 2019
    Assignee: VMware, Inc.
    Inventors: Antoan Arnaudov, Tony Ganchev, Boian Tzonev
  • Patent number: 10423354
    Abstract: A memory manager of a processor identifies a block of data for eviction from a first memory module to a second memory module. In response, the processor copies only those portions of the data block that have been identified as modified portions to the second memory module. The amount of data to be copied is thereby reduced, improving memory management efficiency and reducing processor power consumption.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: September 24, 2019
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Philip Rogers, Benjamin T. Sander, Anthony Asaro, Gongxian Jeffrey Cheng
  • Patent number: 10423537
    Abstract: A method is provided for controlling processing of target program code on a host data processing apparatus to simulate processing of the target program code on a target data processing apparatus. In response to a target memory access instruction of the target program code specifying a target address within a simulated address space having a larger size than a host address space supported by a memory management unit of the host data processing apparatus, an address space resizing table is looked up to map the target address to a transformed address within said host address space, and information is generated for triggering a memory access based on translation of the transformed address by the memory management unit of the host data processing apparatus.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: September 24, 2019
    Assignee: ARM Limited
    Inventors: Adam James McNeeney, Matthew Lucien Evans
  • Patent number: 10412115
    Abstract: Behavioral analysis of a mobile application is performed to determine whether the application is malicious. During analysis, various user interactions are simulated in an emulated environment to activate many possible resulting behaviors of an application. The behaviors are classified as hard or soft signals. A probability of the application being malicious is determined through combining soft signals, and the application is classified as malicious or non-malicious. Users of the application, the developer of the application, or a distributor of the application are notified of the application classification to enable responsive action.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: September 10, 2019
    Assignee: Twitter, Inc.
    Inventors: Neilkumar Murli Daswani, Ameet Ranadive, Shariq Rizvi, Michael Gagnon, Tufan Demir, Gerald E. Eisenhaur
  • Patent number: 10409624
    Abstract: Disclosed herein are systems and methods of an emulation system. A hardware emulator of an emulation system includes one or more processors configured to generate data in an emulation cycle. Each bit of the generated data is associated with a tag. The hardware emulator may include a compaction unit configured to receive the data generated by the one or more processors, and select one or more bits from total bits of the data based on valid tags associated with the bits of the data. The hardware emulator further includes a data array comprising non-transitory machine-readable storage media configured to store the one or more bits of the data received from the compaction unit.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: September 10, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventor: Beshara Elmufdi
  • Patent number: 10372497
    Abstract: A system and method is provided for performing computations on a virtual machine without a special hardware computation unit, such as a discrete graphics processing unit (GPU). The described method uses a computation module to intercept requests from a user application executing in a virtual machine on a first physical computer. The intercepted requests may include requests to configure GPU computation grids, start and finish accelerated code execution, and transfer data to and from the special computation unit. The computation module offloads accelerated code to a second physical computer having a physical special hardware unit (e.g., discrete GPU).
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: August 6, 2019
    Assignee: Parallels International GmbH
    Inventors: Anton Zelenov, Nikolay Dobrovolskiy, Serguei M. Beloussov, Alexey Koryakin
  • Patent number: 10359999
    Abstract: A method for configuring and executing card content management (CCM) operations in a declarative manner includes composing a CCM operation declaration, wherein each CCM operation includes one or more CCM scripts and storing the CCM operation declaration in memory. When provisioning is needed, applicable scripts for the CCM operation declaration are fetched from the memory. An execution context needed for each script in the CCM operation declaration is prepared. The scripts are executed in an order specified in the CCM operation declaration.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: July 23, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Youngjin Eo, Jinho Lee, Jooho Lee
  • Patent number: 10339236
    Abstract: A computer implemented method receives a request to run a group of instruction sets. Each instruction set is associated with a sequence of common instructions. The method executes the sequence of common instructions in a first virtual machine (VM) to generate a result which is stored in a first memory associated with the first VM. The method then clones a second VM that shares the first memory with the first VM. The method continues by executing a first instruction set in the second VM. Since the second VM shares memory with the first VM, the second VM can use the result stored in the first memory and the sequence of common instructions does not need to be executed on the second VM. In one example, the result is a run-time model of a circuit and the second VM runs the first instruction set on the run-time model.
    Type: Grant
    Filed: September 10, 2013
    Date of Patent: July 2, 2019
    Assignee: VMware, Inc.
    Inventors: Kalyan Saladi, Aravind Pavuluri, Nikhil Bhatia
  • Patent number: 10327138
    Abstract: Systems and methods for providing one or more services via a remote device are disclosed. One method can comprise identifying one or more services available at a location, transmitting identification data to a remote device disposed remotely from the location, the identification data relating to the one or more services identified, receiving a selection of the one or more services available, and providing the selected one or more services available to the remote device.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: June 18, 2019
    Assignee: Comcast Cable Communications, LLC
    Inventor: Yiu L. Lee
  • Patent number: 10324740
    Abstract: A control-circuit of an emulation system may include one or more serial link inputs communicatively coupled to a serial bus, a serial link input receiving an input control bit from the serial bus. A configurable logic circuit may be configured to receive multiple control bits from the one or more serial link inputs, execute one or more operations on the plurality of input control bits according to programmable logic, and transmit an output control bit to a serial output link.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: June 18, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Mitchell G. Poplack, Yuhei Hayashi
  • Patent number: 10318459
    Abstract: Example implementations relate to a server including a platform controller hub (PCH), where the PCH includes a peripheral device manager, a management processor coupled to the peripheral device manager, and a peripheral device interface to couple with a peripheral device and provide out of band access of the peripheral device via the management processor and peripheral device manager to a memory of the server.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: June 11, 2019
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: Suhas Shivanna, Luis E. Luciani, Jr., Mohammed Saleem, Andrew Brown
  • Patent number: 10320880
    Abstract: Disclosed are various embodiments enabling a saved state of an application to be stored at a central location and to be retrieved by multiple computing devices executing the application. Accordingly, saved states of applications and interfaces are also enabled to follow a user from one personal computing device to the next.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: June 11, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Michael Anthony Frazzini, Ethan Zane Evans
  • Patent number: 10313107
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: June 4, 2019
    Inventors: Shay Gueron, Wajdi K Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G Dixon, Srinivas Chennupaty, Michael E Kounavis
  • Patent number: 10303331
    Abstract: Techniques to facilitate demonstrating changes to mobile applications are disclosed herein. In at least one implementation, an instance of a virtual mobile device is executed on a computing system, wherein the virtual mobile device comprises at least one mobile application. Instructions are received to change at least one visual element of the at least one mobile application. The instructions are processed to generate a screenshot of the change to the at least one visual element. The screenshot of the change is transferred for delivery to a remote computing system, wherein the remote computing system displays the screenshot of the change.
    Type: Grant
    Filed: August 4, 2016
    Date of Patent: May 28, 2019
    Assignee: Apptimize, Inc.
    Inventor: Dustin L. Howett
  • Patent number: 10291394
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Grant
    Filed: October 1, 2015
    Date of Patent: May 14, 2019
    Assignee: Intel Corporation
    Inventors: Shay Gueron, Wajdi K Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G Dixon, Srinivas Chennupaty, Michael Kounavis
  • Patent number: 10289337
    Abstract: Systems and methods are disclosed for initiating data transfer operations between data storage devices based at least in part on relative physical orientation or position of the data storage devices. Data storage devices are disclosed that include a physical enclosure, a non-volatile memory disposed within the physical enclosure, one or more sensors, and a controller configured to determine a physical orientation of the data storage device relative to another data storage device using the one or more sensors and initiate a data storage operation involving the data storage device and the other data storage device based on the physical orientation.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: May 14, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ameen Manghi, Eric W. Chang, Maria Nzembi Kala, Saurabh Agarwal, Muhammad Zeeshan Razzaque
  • Patent number: 10282501
    Abstract: A method is provided that includes selecting an assertion checker for a design under test. The design under test includes hardware and firmware for a system on a chip, the method including instantiating the assertion checker in a compilation file, annotating the compilation file to define an assertion control signal for the assertion checker, and selecting one of a DISABLE or an ENABLE definition for the assertion control signal. The method also includes configuring a clock in a prototyping platform to stop when the assertion control signal is enabled in the assertion checker and a logic condition for the assertion control signal is satisfied in the prototyping platform. A system and a computer readable medium including instructions to perform the above method are also provided.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: May 7, 2019
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventor: Vasant Ramabadran
  • Patent number: 10275597
    Abstract: Disclose are systems and methods for execution of program code by an interpreter. One exemplary method comprises: executing, by the interpreter, instructions of the program code in an emulated computer environment; when detecting, by the interpreter, an instruction of the program code associated with an unknown object for which the interpreter lacks a rule of interpretation, halting by the interpreter further execution of the instructions of the program code; obtaining, by the interpreter, an auxiliary code whose result of execution corresponds to the result of the execution of the unknown object, wherein the auxiliary code contains known objects for which the interpreter has a rule of interpretation; executing, by the interpreter, the instructions of the auxiliary code; and after completion of the execution of the auxiliary code, by the interpreter, resuming the execution of the instructions of the program code.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: April 30, 2019
    Assignee: AO KASPERSKY LAB
    Inventors: Vasily A. Davydov, Dmitry V. Vinogradov, Roman Y. Gavrilchenko, Dmitry A. Kirsanov
  • Patent number: 10270589
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: April 23, 2019
    Assignee: INTEL CORPORATION
    Inventors: Shay Gueron, Wajdi K. Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G. Dixon, Srinivas Chennupaty, Michael E. Kounavis
  • Patent number: 10271407
    Abstract: A load control device is able to receive radio-frequency (RF) signals from a Wi-Fi-enabled device, such as a smart phone, via a wireless local area network. The load control device comprises a controllably conductive device adapted to be coupled in series between an AC power source and an electrical load, a controller for rendering the controllably conductive device conductive and non-conductive, and a Wi-Fi module operable to receive the RF signals from the wireless network. The controller controls the controllably conductive device to adjust the power delivered to the load in response to the wireless signals received from the wireless network. The load control device may further comprise an optical module operable to receive an optical signal, such that the controller may obtain an IP address from the received optical signal and control the power delivered to the load in response to a wireless signal that includes the IP address.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: April 23, 2019
    Assignee: LUTRON ELECTRONICS CO., INC.
    Inventors: Michael W. Pessina, Theodore F. Economy, John C. Browne, Jr.
  • Patent number: 10263769
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: April 16, 2019
    Assignee: Intel Corporation
    Inventors: Shay Gueron, Wajdi K Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G Dixon, Srinivas Chennupaty, Michael E Kounavis
  • Patent number: 10256972
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: April 9, 2019
    Assignee: Intel Corporation
    Inventors: Shay Gueron, Wajdi K Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G Dixon, Srinivas Chennupaty, Michael E Kounavis
  • Patent number: 10256971
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: April 9, 2019
    Assignee: Intel Corporation
    Inventors: Shay Gueron, Wajdi K Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G Dixon, Srinivas Chennupaty, Michael E Kounavis
  • Patent number: 10255196
    Abstract: An apparatus and method for sub-page extended page table protection. For example, one embodiment of an apparatus comprises: a page miss handler to perform a page walk using a guest physical address (GPA) and to detect whether a page identified with the GPA is mapped with sub-page permissions; a sub-page control storage to store at least one GPA and other data related to a sub-page; the page miss handler to determine whether the GPA is programmed in the sub-page control storage; and the page miss handler to send a translation to a translation lookaside buffer (TLB) with a sub-page protection indication set to cause a matching of the sub-page control storage when an access matches a TLB entry with sub-page protection indication.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: April 9, 2019
    Assignee: Intel Corporation
    Inventors: Vedvyas Shanbhogue, Christopher Bryant, Jeff Wiedemeier
  • Patent number: 10243914
    Abstract: Exemplary methods, apparatuses, and systems include a first network edge device configuring a mapping between a physical network interface and a plurality of logical interfaces. A second network edge device also configures a mapping between a physical network interface and a copy of the plurality of logical interfaces. Each of the logical interfaces is assigned a corresponding set of first and second layer networking addresses that is replicated across the first and second network edge devices. The first network edge device receives a first address resolution request via the physical network interface of the first network edge device that includes a source and a destination. The destination is an address assigned to one of the plurality of logical interfaces. The first network edge device determines a second layer networking address assigned to the destination logical interface and transmits an address resolution response including the determined second layer networking address.
    Type: Grant
    Filed: July 15, 2015
    Date of Patent: March 26, 2019
    Assignee: Nicira, Inc.
    Inventor: Sreeram Ravinoothala
  • Patent number: 10235177
    Abstract: In an example, an apparatus includes a binary translator (BT) including circuitry to: analyze a code block; determine that an architectural register mapped to a physical register in the physical register file is available for early reclamation; and insert a reclamation hint into the code block. In another example, a processor reclaims the physical register based at least in part on the reclamation hint.
    Type: Grant
    Filed: July 2, 2016
    Date of Patent: March 19, 2019
    Assignee: Intel Corporation
    Inventors: Vineeth Mekkat, Janghaeng Lee, Youfeng Wu
  • Patent number: 10229268
    Abstract: System, method and media are shown for detecting potentially malicious code by iteratively emulating potentially malicious code, that involve, for each offset of a memory image, emulating execution of an instruction at the offset on a first platform and, if execution fails, determining whether the instruction at the offset has relevance to at least a second platform and, if so, emulating execution of the instruction at the offset on the second platform. If execution succeeds, it involves checking the behavior of the executing code for suspect behavior, and identifying the executing code as malicious code if suspect behavior is detected. Refinements involve applying this process to also determine aspects of information related to the target of any discovered code, malicious or otherwise.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: March 12, 2019
    Assignee: LEVIATHAN, INC.
    Inventor: Falcon Momot
  • Patent number: 10216496
    Abstract: An approach to dynamic run-time alias checking comprising creating a main thread and a helper thread, computing an optimized first region of code in a rollback-only transactional memory associated with the main thread checking for one or more alias dependencies in an un-optimized first region of code, responsive to a determination in a predetermined amount of time that no alias dependencies are present in the un-optimized first region of code, committing a transaction and responsive to at least one of a failure to determine results of the check for one or more alias dependencies in the predetermined amount of time and a determination in the predetermined amount of time that alias dependencies are present in the un-optimized first region of code, performing a rollback of the transaction and executing the un-optimized first region of code.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: February 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Yaoqing Gao, William G. O'Farrell, Denis Palmeiro
  • Patent number: 10215805
    Abstract: The disclosure describes a novel method and apparatus for providing a shadow access port within a device. The shadow access port is accessed to perform operations in the device by reusing the TDI, TMS, TCK and TDO signals that are used to operate a test access port within the device. The presence and operation of the shadow access port is transparent to the presence and operation of the test access port. According to the disclosure, the shadow access port operates on the falling edge of the TCK signal while the test access port conventionally operates on the rising edge of the TCK signal.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: February 26, 2019
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 10218641
    Abstract: Techniques for handling dynamic cascade port/LAG changes in an extended bridge are provided. According to one embodiment, a first network device in an extended bridge can maintain a shadow table that stores information regarding one or more ports and one or more LAGs used to interconnect the network devices in the extended bridge. The first network device can further receive, from a user via a device UI, a command relating to a change to a port or a LAG, update the shadow table based on the change, transmit a change message to one or more other network devices affected by the change, and start a timer associated with the one or more other network devices. In various embodiments, the updating and the transmitting can be performed without blocking the user from entering further commands via the device UI.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: February 26, 2019
    Assignee: ARRIS Enterprises LLC
    Inventors: Kwun-Nan Kevin Lin, Bipin Agarwal
  • Patent number: 10187201
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: January 22, 2019
    Assignee: Intel Corporation
    Inventors: Shay Gueron, Wajdi K Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G Dixon, Srinivas Chennupaty, Michael E Kounavis
  • Patent number: 10181945
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: January 15, 2019
    Assignee: INTEL CORPORATION
    Inventors: Shay Gueron, Wajdi K. Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G. Dixon, Srinivas Chennupaty, Michael E. Kounavis
  • Patent number: 10181016
    Abstract: An information processing device includes an identification part configured to, in response to a user's operation to start any given one of a plurality of first application programs, determine whether the start of the one of the first application programs is allowed; and a request part configured to request the one of the first application programs to display a first screen which indicates the start of the one of the first application programs is not allowed when the identification part determines that the start of the one of the first application programs is not allowed, and request a second application program to display a second screen including a message when the identification part determines that the start of the one of the first application programs is allowed and when the message needs to be given.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: January 15, 2019
    Assignee: Ricoh Company, Ltd.
    Inventors: Hideki Ohhashi, Kohichi Hirai
  • Patent number: 10176210
    Abstract: The methods and systems can include a database management component configured to manage database instances, the database management component also configured to receive a first data request operation on the distributed database, an execution component configured to process the first data request operation including at least one write request on at least one database instance managed by the database management component, and a fault prediction component configured to detect a potential page fault responsive to a target data of the write request, wherein the execution component is further configured to suspend execution of the first data request operation, request access a physical storage to read the target data into active memory, and re-execute the first data request operation after a period of time for suspending the first data request operation.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: January 8, 2019
    Assignee: MongoDB, Inc.
    Inventors: Dwight Merriman, Eliot Horowitz
  • Patent number: 10171232
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: January 1, 2019
    Assignee: Intel Corporation
    Inventors: Shay Gueron, Wajdi K Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G Dixon, Srinivas Chennupaty, Michael E Kounavis
  • Patent number: 10171231
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: January 1, 2019
    Assignee: Intel Corporation
    Inventors: Shay Gueron, Wajdi K Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G Dixon, Srinivas Chennupaty, Michael E Kounavis
  • Patent number: 10164769
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: December 25, 2018
    Assignee: Intel Corporation
    Inventors: Shay Gueron, Wajdi K Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G Dixon, Srinivas Chennupaty, Michael E Kounavis
  • Patent number: 10158478
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: December 18, 2018
    Assignee: Intel Corporation
    Inventors: Shay Gueron, Wajdi K Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G Dixon, Srinivas Chennupaty, Michael E Kounavis