Emulation Patents (Class 703/23)
  • Patent number: 11023311
    Abstract: Systems and methods are described for modifying input and output (I/O) to an object storage service by implementing one or more owner-specified functions to I/O requests. A function can implement a data manipulation, such as filtering out sensitive data before reading or writing the data. The functions can be applied prior to implementing a request method (e.g., GET or PUT) specified within the I/O request, such that the data to which the method is applied my not match the object specified within the request. For example, a user may request to obtain (e.g., GET) a data set. The data set may be passed to a function that filters sensitive data to the data set, and the GET request method may then be applied to the output of the function. In this manner, owners of objects on an object storage service are provided with greater control of objects stored or retrieved from the service.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: June 1, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Ramyanshu Datta, Timothy Lawrence Harris, Kevin C. Miller, Haripriya Devnath, Robert Devers Wilson
  • Patent number: 10977235
    Abstract: Changes to information are managed by storing information as a plurality of objects. Each object has one or more states. One or more temporal histories are maintained for each object based on the plurality of states of the object at a plurality of time instances. For each state of the object, whether or not the state is a user of another state of the object or another object is determined. When a request to change the information is received, at least one state of at least one of the plurality of objects is selectively changed. When it is determined that the at least one state is the user of another state, then the changing is further responsive to changes in the another state.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: April 13, 2021
    Assignee: QUICK EYE TECHNOLOGIES INC.
    Inventor: Andrei Paraschivescu
  • Patent number: 10972350
    Abstract: Examples described herein include imaging servers which may support asynchronous imaging of one or more computers (e.g., computing nodes). The imaging server may use out-of-band communication to install requested images on one or more computing nodes. The imaging server may support multiple concurrent installation sessions, and may maintain a log specific to each session. This may facilitate session-specific status reporting. In this manner, operating systems, hypervisors, or other software may be installed on computing nodes.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: April 6, 2021
    Assignee: Nutanix, Inc.
    Inventors: Toms Varghese, Jaspal Singh Dhillon, Raghu Rapole, Avi Bhandari
  • Patent number: 10963239
    Abstract: According to a computer-implemented method, an update package that includes update operational files is received at a computing device. At least one update operational file is to replace a corresponding original operational file for the computing device. It is determined which of the original operational files are to be replaced with corresponding update operational files. A delta file is stored at the computing device, which delta file indicates the original operational files that are replaced with corresponding update operational files and the update package is installed at the computing device.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: March 30, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Leo M. Farrell, Scott Exton, Anthony B. Ferguson
  • Patent number: 10949588
    Abstract: A method of capturing signals during hardware verification of a circuit design utilizes at least one field-programmable gate array (FPGA) and includes selecting, at run time and using one or more pre-compiled macros, a group of signals to be captured during verification of the circuit design and storing values of the group of signals in at least first and second random access memories disposed in the at least one FPGA. The first and second random access memories may be addressable spaces of the same random access memory.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: March 16, 2021
    Assignee: SYNOPSYS, INC.
    Inventors: Arturo Salz, Ching-Ping Chou, Jean-Philippe Colrat, Sébastien Roger Delerse, Luc François Vidal, Arnold Mbotchak
  • Patent number: 10942663
    Abstract: Techniques are provided for inlining data in inodes of a file system. In an example, data (e.g., a file) is to be written to storage. Where the data is small enough to fit in an inode, it can be written to a dynamic area of the inode. Where dynamic attributes of the inode conflict with storing the data, the dynamic attributes can be spilled to a metadata block. Where the inlined data becomes too large to be stored in the inode, it can be spilled to a data block, and a metadata tree can be written to the inode. Where data that was previously too large to inline is truncated so that now it can be written to the inode, the data is inlined in the inode from a data block.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: March 9, 2021
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Attilio Rao, Dmitri Chmelev
  • Patent number: 10942838
    Abstract: An electronic device is described herein. In accordance with one embodiment, the electronic device includes an embedded controller having a debug logic, an interface circuit coupled to the debug logic, and a memory coupled to the interface circuit. The interface circuit is operative to read debug information stored in the debug logic and to transmit the read debug information to the memory. The interface circuit is further operative to receive debug information stored in the memory and write the received debug information into the debug logic.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: March 9, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Matthias Schneider, Arndt Pauschardt, Yuanfen Zheng
  • Patent number: 10928442
    Abstract: Computer implemented methods of designing integrated circuits and computing systems are provided. A computer implemented method of designing an integrated circuit according to the inventive concepts may be performed by a processor and may include performing a placement and routing (P&R) operation for standard cells defining the integrated circuit, extracting characteristic values from a result of the P&R operation, generating a physical-aware annotation file by determining a plurality of representative characteristic values that respectively correspond to a plurality of groups based on the extracted characteristic values, and performing a physical-aware synthesis operation to generate a netlist from input data for the integrated circuit, based on the generated physical-aware annotation file.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: February 23, 2021
    Inventors: Tae-il Kim, Jae-hoon Kim, Hyung-ock Kim, Jung-yun Choi
  • Patent number: 10917335
    Abstract: Method and systems for data switching, including receiving first input data at a network switching system comprising a crosspoint switch and a data processing card; transmitting the first input data from the crosspoint switch to the data processing card; making a first determination, by the data processing card, that the first input data meets a first pre-determined filtering criterion; and transmitting, based on the first determination, the first input data from a first crosspoint switch port of the crosspoint switch towards a first client.
    Type: Grant
    Filed: April 5, 2019
    Date of Patent: February 9, 2021
    Assignee: Arista Networks, Inc.
    Inventors: Robert James Walker, Stefan Josef Gratzl, Sergey Sardaryan, Vahan Sardaryan
  • Patent number: 10915371
    Abstract: A system for providing automatic management of low latency computational capacity is provided. The system may be configured to maintain a plurality of virtual machine instances. The system may be further configured to identify a trend in incoming code execution requests to execute program code on a virtual compute system, determine, based on the identified trend, that the plurality of virtual machine instances should be adjusted, and adjust the plurality of virtual machine instances based on the identified trend.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: February 9, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Timothy Allen Wagner, Sean Philip Reque, Dylan Chandler Thomas, Derek Steven Manwaring, Bradley Nathaniel Burkett
  • Patent number: 10877792
    Abstract: An example method comprises receiving a begin time to initiate storage network traffic data collection from a plurality of data probes integrated within an enterprise network, collecting network data identifying HBA ports used to communicate with storage ports from the probes, analyzing the network data to determine attributes of network traffic, determining for each storage unit: a penalty score for each of the storage ports determining a reconfiguration of a storage unit or HBA based at least in part on the total penalty score, simulating changes of the reconfiguration of the storage unit or the HBA and simulate storage network traffic, applying the simulated storage network traffic on the simulated changes of the reconfiguration of the storage unit or HBA to determine improvements, and outputting instructions to enable reconfiguration of the storage unit or HBA.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: December 29, 2020
    Assignee: Virtual Instruments Corporation
    Inventors: Francis Niestemski, Ryan E. Perkowski, Nicholas York
  • Patent number: 10853071
    Abstract: A method and apparatus for simulating target program code on a host data processing apparatus, the simulation mapping load-exclusive instructions in the target program code to load instructions, and mapping store-exclusive instructions in the target program code to compare-and-swap instructions.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: December 1, 2020
    Assignee: Arm Limited
    Inventors: Adam James McNeeney, Gareth James Evans
  • Patent number: 10838748
    Abstract: Disclosed are systems and methods for emulating execution of a file based on emulation time. In one aspect, an exemplary method comprises, generating an image of a file, emulating an execution of instructions from the image for a predetermined emulation time, the emulation including: when an emulation of an execution of instruction from an image of another file is needed, generating an image of the another file, detecting known set of instructions in portions read from the image, inserting a break point into a position in the generated image corresponding to a start of the detected set of instructions, emulating execution of the another file by emulating execution of instructions from the generated image, and adding corresponding records to an emulation log, and reading a next portion from the image of the another file and repeating the emulation until the predetermined emulation time has elapsed.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: November 17, 2020
    Assignee: AO Kaspersky Lab
    Inventors: Alexander V. Liskin, Vladimir V. Krylov
  • Patent number: 10789405
    Abstract: An event-driven simulation system is provided. The simulation system classifies events into bypass-events and perform-events. The simulation system performs simulation by executing instructions based on the perform-events and skips simulation for the bypass-events. The simulation system produces partial simulation result data based events that are actually simulated but not the events that are skipped. A post processor is provided to generate the missing simulation result data for the bypass-events and to merge the bypass-event with the partial simulation result to generate a complete simulation result.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: September 29, 2020
    Assignee: Montana Systems Inc.
    Inventors: Vivian Chou, Sherman Lee
  • Patent number: 10769817
    Abstract: A system and method for image testing is configured to apply at least one display property to a test image to generate a display modified test image and applying the at least one display property to a reference image to generate a display modified reference image. The system also applies a human eye model to the display modified test image to generate an eye modified test image and applies the human eye model to the display modified reference image to generate an eye modified reference image. The system may compare the eye modified test image with the eye modified reference image to determine human perceivable differences between the test image and the reference image.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: September 8, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Gregory W. Cook, Javier Ribera Prat, Shiva Moballegh
  • Patent number: 10742776
    Abstract: Isochronous endpoints of a redirected USB device can be accelerated. When a USB device is redirected, each of the device's endpoints can be identified. A UDP socket can then be created between the client-side proxy and the server-side agent for each isochronous endpoint, while a TCP socket can be created for each other endpoint. A lookup table can also be created which maps pipe handles to socket IDs. The lookup table can be employed to route USB request blocks pertaining to a particular endpoint over the corresponding socket. In this way, USB request blocks pertaining to an isochronous endpoint will be transferred over the network using UDP while USB request blocks pertaining to non-isochronous endpoints will be transferred using TCP.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: August 11, 2020
    Assignee: Dell Products L.P.
    Inventors: Gokul Thiruchengode Vajravel, Ankit Kumar
  • Patent number: 10740220
    Abstract: Performing breakpoint detection via a cache includes detecting an occurrence of a memory access and identifying whether any cache line of the cache matches an address associated with the memory access. When a cache line does match the address associated with the memory access no breakpoint was encountered. When no cache line matches the address associated with the memory access embodiments identify whether any cache line matches the address associated with the memory access when one or more flag bits are ignored. When a cache line does match the address associated with the memory access when the one or more flag bits are ignored, embodiment perform a check for whether a breakpoint was encountered. Otherwise, embodiments process a cache miss.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: August 11, 2020
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventor: Jordi Mola
  • Patent number: 10698731
    Abstract: A system and method is provided for performing computations on a virtual machine without a special hardware computation unit, such as a discrete graphics processing unit (GPU). The described method uses a computation module to intercept requests from a user application executing in a virtual machine on a first physical computer. The intercepted requests may include requests to configure GPU computation grids, start and finish accelerated code execution, and transfer data to and from the special computation unit. The computation module offloads accelerated code to a second physical computer having a physical special hardware unit (e.g., discrete GPU).
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: June 30, 2020
    Assignee: PARALLELS INTERNATIONAL GMBH
    Inventors: Anton Zelenov, Nikolay Dobrovolskiy, Serguei M. Beloussov, Alexey Koryakin
  • Patent number: 10664600
    Abstract: Apparatus, systems, or methods for a programmable circuit to facilitate a processor to boot a computing device having the processor. A programmable circuit may include non-volatile storage and firmware stored in the non-volatile storage. The firmware may configure the programmable circuit as a memory controller of a memory device coupled to the programmable circuit, to facilitate the processor to boot the computing device having the processor, the programmable circuit, and the memory device, into operation. Other embodiments may also be described and claimed.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: May 26, 2020
    Assignee: Intel Corporation
    Inventors: Yah Wen Ho, Tung Lun Loo, Yan Fei Lee
  • Patent number: 10634723
    Abstract: The present invention facilitates efficient and effective device testing and debugging. In one embodiment, a tester system includes a controller processor; a plurality of programmable accelerator circuits coupled to and controlled by the controller processor; and a plurality of load boards respectively coupled to the plurality of programmable accelerator circuits. The plurality of load boards can apply the input test signals to a plurality of devices under test (DUTs) and capture the output test signals therefrom. The plurality of programmable accelerator circuits can provide input test signals and capture output test signals. In one exemplary implementation, each of the plurality of load boards comprises: a first set of connections for transmitting input test signals to a respective DUT; a second set of connections for receiving output test signals from the respective DUT; and sideband connectors. The sideband connectors receive test related information from the DUT.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: April 28, 2020
    Assignee: ADVANTEST CORPORATION
    Inventors: Ben Rogel-Favila, Mei-Mei Su, John Frediani, Shunji Tachibana
  • Patent number: 10594790
    Abstract: A method for execution by a dispersed storage and task (DST) processing unit includes receiving a write request that includes a data object. Characterization data is generated by determining a data type of the data object. Object constraint data is generated by determining a compressibility of the data type and a processing cost of the data type. Optimized trade-off data is generated by optimizing a plurality of trade-off constraints based on the object constraint data. A compression algorithm is selected from a plurality of compression algorithm options based on the optimized trade-off data. A compressed data object is generated by performing the selected compression algorithm on the data object. A plurality of data slices are generated for transmission to a plurality of storage units for storage by performing an information dispersal algorithm on the compressed data object.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: March 17, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Adam M. Gray, Ravi V. Khadiwala, Greg R. Dhuse, Jason K. Resch, Praveen Viraraghavan, Russell C. Fordyce
  • Patent number: 10581590
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: March 3, 2020
    Assignee: Intel Corporation
    Inventors: Shay Gueron, Wajdi K Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G Dixon, Srinivas Chennupaty, Michael E Kounavis
  • Patent number: 10554782
    Abstract: A stream application may use small chunks of executable code configured to process data tuples flowing into a processing element. A scheduler allocates the processing elements to individual compute nodes or hosts for execution. However, the stream application may assign various constraints that stipulate which hosts are suitable for a particular processing element. To assign hosts to processing elements such that the constraints are satisfied, the scheduler may use hostpools associated with the processing elements. Once a host is identified that satisfies the constraints, it may be pinned at a particular index within the hostpool.
    Type: Grant
    Filed: December 1, 2011
    Date of Patent: February 4, 2020
    Assignee: International Business Machines Corporation
    Inventor: Bradley W. Fawcett
  • Patent number: 10540347
    Abstract: Methods, systems, computer-readable media, and apparatuses for providing search disambiguation using contextual information and domain ontologies are presented. In some embodiments, a computing device may receive a natural language input from a user. The computing device may identify a plurality of hypotheses for the natural language input. The computing device may map the plurality of hypotheses to one or more concepts of a plurality of concepts of an ontology by annotating the one or more concepts. The ontology may include the plurality of concepts respectively connected by a plurality of relations. The computing device may determine that there is an imperfect match between the annotated one or more concepts and annotations of answers. In response, the computing device may disambiguate the annotated one or more concepts using the ontology. The computing device may present output to the user based on the disambiguation.
    Type: Grant
    Filed: October 27, 2014
    Date of Patent: January 21, 2020
    Assignee: Nuance Communications, Inc.
    Inventors: Ladislav Kunc, Martin Labský, Tomá{hacek over (s)} Macek, Jan Vystr{hacek over (c)}il, Jan Kleindienst
  • Patent number: 10528690
    Abstract: A computer-aided method for configuring a hardware verification system is presented. The method includes receiving, by the computer, a first data representative of a first design of an integrated circuit, when the computer is invoked to configure the verification system, and transforming, using the computer, the first data into a second data representative of a second design. The second design includes a functionality of the first design, and a first circuit adapted to compute a third data representative of a power consumption of a first portion of the first design when the hardware verification system is configured with the second data and run. The first circuit is programmable without reconfiguring the second design.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: January 7, 2020
    Assignee: Synopsys, Inc.
    Inventor: Ching-Ping Chou
  • Patent number: 10496461
    Abstract: A method of emulating an instruction includes identifying a fault instruction. The fault instruction is saved in a register. The fault instruction is associated with a software emulated operation. The software emulated operation is initiated with an access to the fault instruction in the register.
    Type: Grant
    Filed: June 15, 2011
    Date of Patent: December 3, 2019
    Assignee: ARM Finance Overseas Limited
    Inventor: David Yiu-Man Lau
  • Patent number: 10484268
    Abstract: A digital crosspoint switch of a network switching system (NSS) replicates input data received via a first network interface to a first data processing port of a data processing card. The input data includes a digital market data feed comprising market-data packets. The crosspoint switch has internal crosspoint ports and external crosspoint ports. The data processing card includes a programmable logic device and a plurality of data processing ports connected to the internal crosspoint ports. The NSS includes a plurality of network interfaces connected to the external crosspoint ports. The data processing card processes the input data and generates processed data on the second data processing port at least in part by only including market-data packets that meet a first predetermined filtering criterion in the processed data. The crosspoint switch replicates the processed data from the second data processing port to the second network interface.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: November 19, 2019
    Assignee: METAMAKO GENERAL PTY LTD ACN 163 573 331 IN ITS CAPACITY AS GENERAL PARTNER OF METAMAKO TECHNOLOGY LP ABN 11 872 058 101
    Inventors: Robert James Walker, Stefan Josef Gratzl, Sergey Sardaryan, Vahan Sardaryan
  • Patent number: 10467131
    Abstract: Performance analysis for test automation frameworks is described. A test is executed of an application. Performance indicators are logged during execution of the test, wherein the performance indicators include a first performance indicator. A correlation is identified between the first performance indicator and a second performance indicator recorded during the execution of the test or an execution of a previous test of the application. An output device outputs the correlation as a performance issue.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: November 5, 2019
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Rajendra Kumar Gupta, Anupam Sharma, Sanjeev Kumar Lohchab, Naveen Kumar Surendra Rao, Swapnadeep Deb Kanunjna
  • Patent number: 10467368
    Abstract: A computer-implemented method generates a plurality of clusters based on components included in a design under test (DUT); classifies a subset of clusters of the plurality of clusters as tangled clusters; modifies at least two tangled clusters of the subset of clusters based on overlap between the at least two tangled clusters; determines, for each tangled cluster in the subset of clusters, a gate count based on the interconnectivity of the tangled cluster; and partitions the DUT among a plurality of field-programmable gate arrays (FPGAs) based on the gate count determined for each tangled cluster from the subset of clusters.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: November 5, 2019
    Assignee: Synopsys, Inc.
    Inventors: Etienne Lepercq, Jiahua Zhu, Jiong Cao, Marc-Andre Daigneault
  • Patent number: 10437432
    Abstract: Methods, systems, and computer programs for integration of user interface technologies. One of the methods includes receiving, from a user device, a user request to execute a web application, the web application being associated with one or more rendering systems, and each of the rendering systems executing one or more respective remote applications. Respective video streams for the remote applications are obtained from each of the rendering systems. Each of the video streams is provided for presentation on the user device. While the video streams are provided, data identifying a user event is received from the user device. The user event is determined to be intended for a first rendering system. The user event is provided to the first rendering system.
    Type: Grant
    Filed: September 17, 2014
    Date of Patent: October 8, 2019
    Assignee: VMware, Inc.
    Inventors: Antoan Arnaudov, Tony Ganchev, Boian Tzonev
  • Patent number: 10423537
    Abstract: A method is provided for controlling processing of target program code on a host data processing apparatus to simulate processing of the target program code on a target data processing apparatus. In response to a target memory access instruction of the target program code specifying a target address within a simulated address space having a larger size than a host address space supported by a memory management unit of the host data processing apparatus, an address space resizing table is looked up to map the target address to a transformed address within said host address space, and information is generated for triggering a memory access based on translation of the transformed address by the memory management unit of the host data processing apparatus.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: September 24, 2019
    Assignee: ARM Limited
    Inventors: Adam James McNeeney, Matthew Lucien Evans
  • Patent number: 10423354
    Abstract: A memory manager of a processor identifies a block of data for eviction from a first memory module to a second memory module. In response, the processor copies only those portions of the data block that have been identified as modified portions to the second memory module. The amount of data to be copied is thereby reduced, improving memory management efficiency and reducing processor power consumption.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: September 24, 2019
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Philip Rogers, Benjamin T. Sander, Anthony Asaro, Gongxian Jeffrey Cheng
  • Patent number: 10412115
    Abstract: Behavioral analysis of a mobile application is performed to determine whether the application is malicious. During analysis, various user interactions are simulated in an emulated environment to activate many possible resulting behaviors of an application. The behaviors are classified as hard or soft signals. A probability of the application being malicious is determined through combining soft signals, and the application is classified as malicious or non-malicious. Users of the application, the developer of the application, or a distributor of the application are notified of the application classification to enable responsive action.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: September 10, 2019
    Assignee: Twitter, Inc.
    Inventors: Neilkumar Murli Daswani, Ameet Ranadive, Shariq Rizvi, Michael Gagnon, Tufan Demir, Gerald E. Eisenhaur
  • Patent number: 10409624
    Abstract: Disclosed herein are systems and methods of an emulation system. A hardware emulator of an emulation system includes one or more processors configured to generate data in an emulation cycle. Each bit of the generated data is associated with a tag. The hardware emulator may include a compaction unit configured to receive the data generated by the one or more processors, and select one or more bits from total bits of the data based on valid tags associated with the bits of the data. The hardware emulator further includes a data array comprising non-transitory machine-readable storage media configured to store the one or more bits of the data received from the compaction unit.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: September 10, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventor: Beshara Elmufdi
  • Patent number: 10372497
    Abstract: A system and method is provided for performing computations on a virtual machine without a special hardware computation unit, such as a discrete graphics processing unit (GPU). The described method uses a computation module to intercept requests from a user application executing in a virtual machine on a first physical computer. The intercepted requests may include requests to configure GPU computation grids, start and finish accelerated code execution, and transfer data to and from the special computation unit. The computation module offloads accelerated code to a second physical computer having a physical special hardware unit (e.g., discrete GPU).
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: August 6, 2019
    Assignee: Parallels International GmbH
    Inventors: Anton Zelenov, Nikolay Dobrovolskiy, Serguei M. Beloussov, Alexey Koryakin
  • Patent number: 10359999
    Abstract: A method for configuring and executing card content management (CCM) operations in a declarative manner includes composing a CCM operation declaration, wherein each CCM operation includes one or more CCM scripts and storing the CCM operation declaration in memory. When provisioning is needed, applicable scripts for the CCM operation declaration are fetched from the memory. An execution context needed for each script in the CCM operation declaration is prepared. The scripts are executed in an order specified in the CCM operation declaration.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: July 23, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Youngjin Eo, Jinho Lee, Jooho Lee
  • Patent number: 10339236
    Abstract: A computer implemented method receives a request to run a group of instruction sets. Each instruction set is associated with a sequence of common instructions. The method executes the sequence of common instructions in a first virtual machine (VM) to generate a result which is stored in a first memory associated with the first VM. The method then clones a second VM that shares the first memory with the first VM. The method continues by executing a first instruction set in the second VM. Since the second VM shares memory with the first VM, the second VM can use the result stored in the first memory and the sequence of common instructions does not need to be executed on the second VM. In one example, the result is a run-time model of a circuit and the second VM runs the first instruction set on the run-time model.
    Type: Grant
    Filed: September 10, 2013
    Date of Patent: July 2, 2019
    Assignee: VMware, Inc.
    Inventors: Kalyan Saladi, Aravind Pavuluri, Nikhil Bhatia
  • Patent number: 10324740
    Abstract: A control-circuit of an emulation system may include one or more serial link inputs communicatively coupled to a serial bus, a serial link input receiving an input control bit from the serial bus. A configurable logic circuit may be configured to receive multiple control bits from the one or more serial link inputs, execute one or more operations on the plurality of input control bits according to programmable logic, and transmit an output control bit to a serial output link.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: June 18, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Mitchell G. Poplack, Yuhei Hayashi
  • Patent number: 10327138
    Abstract: Systems and methods for providing one or more services via a remote device are disclosed. One method can comprise identifying one or more services available at a location, transmitting identification data to a remote device disposed remotely from the location, the identification data relating to the one or more services identified, receiving a selection of the one or more services available, and providing the selected one or more services available to the remote device.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: June 18, 2019
    Assignee: Comcast Cable Communications, LLC
    Inventor: Yiu L. Lee
  • Patent number: 10320880
    Abstract: Disclosed are various embodiments enabling a saved state of an application to be stored at a central location and to be retrieved by multiple computing devices executing the application. Accordingly, saved states of applications and interfaces are also enabled to follow a user from one personal computing device to the next.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: June 11, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Michael Anthony Frazzini, Ethan Zane Evans
  • Patent number: 10318459
    Abstract: Example implementations relate to a server including a platform controller hub (PCH), where the PCH includes a peripheral device manager, a management processor coupled to the peripheral device manager, and a peripheral device interface to couple with a peripheral device and provide out of band access of the peripheral device via the management processor and peripheral device manager to a memory of the server.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: June 11, 2019
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: Suhas Shivanna, Luis E. Luciani, Jr., Mohammed Saleem, Andrew Brown
  • Patent number: 10313107
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: June 4, 2019
    Inventors: Shay Gueron, Wajdi K Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G Dixon, Srinivas Chennupaty, Michael E Kounavis
  • Patent number: 10303331
    Abstract: Techniques to facilitate demonstrating changes to mobile applications are disclosed herein. In at least one implementation, an instance of a virtual mobile device is executed on a computing system, wherein the virtual mobile device comprises at least one mobile application. Instructions are received to change at least one visual element of the at least one mobile application. The instructions are processed to generate a screenshot of the change to the at least one visual element. The screenshot of the change is transferred for delivery to a remote computing system, wherein the remote computing system displays the screenshot of the change.
    Type: Grant
    Filed: August 4, 2016
    Date of Patent: May 28, 2019
    Assignee: Apptimize, Inc.
    Inventor: Dustin L. Howett
  • Patent number: 10289337
    Abstract: Systems and methods are disclosed for initiating data transfer operations between data storage devices based at least in part on relative physical orientation or position of the data storage devices. Data storage devices are disclosed that include a physical enclosure, a non-volatile memory disposed within the physical enclosure, one or more sensors, and a controller configured to determine a physical orientation of the data storage device relative to another data storage device using the one or more sensors and initiate a data storage operation involving the data storage device and the other data storage device based on the physical orientation.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: May 14, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ameen Manghi, Eric W. Chang, Maria Nzembi Kala, Saurabh Agarwal, Muhammad Zeeshan Razzaque
  • Patent number: 10291394
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Grant
    Filed: October 1, 2015
    Date of Patent: May 14, 2019
    Assignee: Intel Corporation
    Inventors: Shay Gueron, Wajdi K Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G Dixon, Srinivas Chennupaty, Michael Kounavis
  • Patent number: 10282501
    Abstract: A method is provided that includes selecting an assertion checker for a design under test. The design under test includes hardware and firmware for a system on a chip, the method including instantiating the assertion checker in a compilation file, annotating the compilation file to define an assertion control signal for the assertion checker, and selecting one of a DISABLE or an ENABLE definition for the assertion control signal. The method also includes configuring a clock in a prototyping platform to stop when the assertion control signal is enabled in the assertion checker and a logic condition for the assertion control signal is satisfied in the prototyping platform. A system and a computer readable medium including instructions to perform the above method are also provided.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: May 7, 2019
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventor: Vasant Ramabadran
  • Patent number: 10275597
    Abstract: Disclose are systems and methods for execution of program code by an interpreter. One exemplary method comprises: executing, by the interpreter, instructions of the program code in an emulated computer environment; when detecting, by the interpreter, an instruction of the program code associated with an unknown object for which the interpreter lacks a rule of interpretation, halting by the interpreter further execution of the instructions of the program code; obtaining, by the interpreter, an auxiliary code whose result of execution corresponds to the result of the execution of the unknown object, wherein the auxiliary code contains known objects for which the interpreter has a rule of interpretation; executing, by the interpreter, the instructions of the auxiliary code; and after completion of the execution of the auxiliary code, by the interpreter, resuming the execution of the instructions of the program code.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: April 30, 2019
    Assignee: AO KASPERSKY LAB
    Inventors: Vasily A. Davydov, Dmitry V. Vinogradov, Roman Y. Gavrilchenko, Dmitry A. Kirsanov
  • Patent number: 10271407
    Abstract: A load control device is able to receive radio-frequency (RF) signals from a Wi-Fi-enabled device, such as a smart phone, via a wireless local area network. The load control device comprises a controllably conductive device adapted to be coupled in series between an AC power source and an electrical load, a controller for rendering the controllably conductive device conductive and non-conductive, and a Wi-Fi module operable to receive the RF signals from the wireless network. The controller controls the controllably conductive device to adjust the power delivered to the load in response to the wireless signals received from the wireless network. The load control device may further comprise an optical module operable to receive an optical signal, such that the controller may obtain an IP address from the received optical signal and control the power delivered to the load in response to a wireless signal that includes the IP address.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: April 23, 2019
    Assignee: LUTRON ELECTRONICS CO., INC.
    Inventors: Michael W. Pessina, Theodore F. Economy, John C. Browne, Jr.
  • Patent number: 10270589
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: April 23, 2019
    Assignee: INTEL CORPORATION
    Inventors: Shay Gueron, Wajdi K. Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G. Dixon, Srinivas Chennupaty, Michael E. Kounavis
  • Patent number: 10263769
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: April 16, 2019
    Assignee: Intel Corporation
    Inventors: Shay Gueron, Wajdi K Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G Dixon, Srinivas Chennupaty, Michael E Kounavis