Abstract: Roughly described, an integrated circuit chip comprises a plurality of peripheral circuits, each peripheral circuit connected to a respective debug unit, the respective debug unit configured to generate debug information of that peripheral circuit; and a plurality of separate stores for receiving debug information, storing debug information, and outputting debug information; wherein in response to a single trigger signal, the debug units are configured to stream their generated debug information to the plurality of separate stores; and wherein each of the plurality of separate stores is configured to receive debug information at a higher stream rate than it outputs debug information.

Abstract: Performing trio-based phasing includes: obtaining a set of preliminary phased haplotype data of an individual; establishing a dynamic Bayesian network based at least in part on the set of preliminary phased haplotype data of the individual and phased haplotype data of at least one parent of the individual; and determining, based on the dynamic Bayesian network, a set of refined haplotype data of the individual.

Abstract: Ancestry deconvolution includes obtaining unphased genotype data of an individual; phasing, using one or more processors, the unphased genotype data to generate phased haplotype data; using a learning machine to classify portions of the phased haplotype data as corresponding to specific ancestries respectively and generate initial classification results; and correcting errors in the initial classification results to generate modified classification results.

Abstract: Disclosed is a debug system that suppresses the supply of extra electrical power for functions disused in the future while maintaining the performance of communication between an electronic control unit and an external unit for development. The debug system includes an electronic control unit that has a microcomputer for controlling the operation of a control target, a transceiver circuit that is capable of communicating data with the microcomputer, and an external unit for development that is capable of rapidly communicating data with the transceiver circuit. The electronic control unit includes a power supply unit for supplying electrical power to the microcomputer. The transceiver circuit operates on electrical power supplied from an external power supply unit, which differs from the power supply unit included in the electronic control unit.

Abstract: One particular example implementation may include an apparatus that includes logic, at least a portion of which is in hardware, the logic configured to: determine that a first device maintains a link to a platform in a selective suspend state; assign a first latency value to the first device; identify at least one user detectable artifact when a second device exits the selective suspend state; and assign, to the second device, a second latency value that is different from the first value.

Abstract: A system and method of cluster debugging includes detecting debug events occurring in one or more first virtual machines, storing debug records, each of the debug records including information associated with a respective debug event selected from the debug events and a timestamp associated with the respective debug event, merging the debug records based on information associated with each timestamp, starting one or more second virtual machines, each of the one or more second virtual machines emulating a selected one of the one or more first virtual machines, synchronizing the one or more second virtual machines, retrieving the merged debug records, and playing the merged debug records back in chronological order on the one or more second virtual machines. In some examples, the method further includes collecting clock synchronization records. In some examples, merging the debug records includes altering an order of one or more of the debug records based on the clock synchronization records.

Abstract: A crystal oscillator emulator having a plurality of predetermined operating configurations. The crystal oscillator emulator includes a measurement circuit configured to measure a value of an impedance connected to a select pin of the crystal oscillator emulator, wherein the impedance is external to the crystal oscillator emulator, and generate an output having a value corresponding to the value of the impedance. The storage circuit is configured to store a plurality of values corresponding to the plurality of predetermined operating configurations and select one of the plurality of values based on the output of the measurement circuit. A controller is configured to set an output frequency of the crystal oscillator emulator based on the selected one of the plurality of values.

Abstract: In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.

Abstract: According to one embodiment, a data storage device comprises a buffer memory and a controller. The buffer memory stores a data group including sector unit data with addresses specified by a host, the data group in unit of page includes a plurality of addresses. The controller comprises an adding module configured to be operative, if the sector unit data with addresses specified by the host as valid addresses for write targets are stored in the buffer, to add information that identifies a last address included in valid addresses belonging to the same page addresses and specified by the host and starting with a start address, to a single sector unit data with the last address.

Abstract: Disclosed are a system, method and computer-readable medium related to processing debug information from an embedded system. Source code of an application program to be used in an embedded system may be compiled by a computing system. The application program may include a debug code line. A minimum amount of debug information is stored in an embedded system, reducing memory overhead and waste of clock cycles of a processor.

Abstract: Techniques for emulation-based functional qualification are disclosed that use an emulation platform to replace simulation in mutation-based analysis. A method for functional qualification of an integrated circuit design includes receiving an integrated circuit design having one or more mutations. Emulation setup and activation simulation are performed in parallel to maximize computing resources. A prototype board can then be programed according to the integrated circuit design and a verification module. A set of test patterns and response generated by a simulation of the integrated circuit using the set of test patterns are stored in a memory of the prototyping board allowing enumeration of mutants to occur at in-circuit emulation speed.

Abstract: A system for providing a test result from an integrated circuit to a status analyzer. A deserializer is configured to deserialize, into data frames, messages received from the integrated circuit. The messages include the test result and are received from the integrated circuit in a serial data format. A frame sync module is configured to synchronize the data frames, output the synchronized data frames, and generate a clock signal. A gateway module is configured to receive the synchronized data frames from the frame sync module in accordance with the clock signal, convert signal levels and signal timings associated with the synchronized data frames from a first format used by the frame sync module to a second format used by the status analyzer, and provide the synchronized data frames to the status analyzer in accordance with the signal levels and the signal timings in the second format used by the status analyzer.

Abstract: A method and apparatus for redundant communication channels in an emulation system is disclosed. A processor-based emulation system has a plurality of emulation chips on an emulation board. The emulation chips have a plurality of processor clusters. Signals are sent over one or more communication channels between processor clusters, including from a processor cluster on one emulation chip to a processor cluster on another emulation chip. Copies of the same signal may be sent in duplicate over separate communication channels. If a communication channel failure is detected, instruction memory is modified so that a processor cluster's instructions no longer address a first cluster memory location, but instead address a second cluster memory location of a non-failed communication channel. By using redundant communication channels, emulation system interconnect reliability is increased and recompilation of the design under verification may be avoided.

Abstract: The invention provides for the interaction of an emulator emulating an electronic design having a communication bus communicating with a software application over the emulated communication bus. The interaction is facilitated in such a manner as to provide an appropriate latency for the emulated communication bus. According to various implementations of the invention, a protocol proxy is provided. The protocol proxy is designed to be emulated along with an electronic design and configured to communicate to software executing on a computer connected to the emulator. The protocol proxy includes a protocol module that communicates to the electronic design being emulated in the emulator environment. Furthermore, the protocol proxy includes a software control module that communicates to the software outside the emulator through proxy communication channels. Further still, the protocol proxy includes a data storage component.

Abstract: The invention is system for emulating a target application comprises a computer, and a capsular including a microcontroller, a programmable non-volatile memory, a numeric display, a transceiver for transmitting and receiving data, a real time clock and at least one input device interacting with a program run on the microcontroller. The capsular is couplable to the computer and adapted to fit in a housing. The input device is operable both when the capsular is inside the housing and when the capsular is outside the housing.

Abstract: A method includes presenting multiple memory circuits to a system as a virtual memory circuit having at least one characteristic that is different from a corresponding characteristic of one of the physical memory circuits; receiving, at an interface circuit, a first command issued from the system to the virtual memory circuit; and in response to receiving the first command, 1) directing a copy of the first command to a first physical memory circuit of the multiple physical memory circuits, and 2) performing a power-saving operation on at least one other physical memory circuit of the multiple physical memory circuits.

Abstract: The present patent document relates to a method and apparatus for an automatic clock to enable conversion for FPGA-based prototyping systems. A library or netlist is provided having a plurality of state elements of a chip design to be prototyped by a user. The chip design can have dozens of different user clocks and clock islands using these different user clocks. The state elements of an element library or netlist are converted to a circuit having one or more state elements and other logic that receive both a user clock as well as a fast global clock. With the disclosed transformations, the functionality of the original state element is maintained, and a single or low number of global clocks can be distributed in an FPGA of the prototype with user clocks generated locally on the FPGA.

Abstract: An electrical connection defect simulation test method is provided. The electrical connection state simulation test method includes the steps as follows. A device under test is provided, wherein the device under test includes a plurality of pin groups each having a plurality of signal pins. A zero-frequency signal is transmitted from a signal-feeding device to each of the signal pins to simulate an open condition. An open test is performed on each of the signal pins. The signal pins of the device under test are connected to a relay matrix. The relay matrix is controlled to make any two of the signal pins in one of the pin groups electrically connected to simulate a short condition. A short test is performed on any two of the electrically connected signal pins. An electrical connection state simulation test system is disclosed herein as well.

Abstract: A method for modeling power management in an integrated circuit (IC) includes: specifying a circuit design and a power architecture for the IC, the power architecture including a plurality of power domains for specifying power levels in different portions of the IC; determining an emulation module for the IC by including one or more hardware elements for modeling the power architecture in the emulation module; and using the emulation module to simulate changing power levels in one or more power domains of the IC including a power shutoff in at least one power domain.

Abstract: Approaches for simulating an electronic system. In one approach, a software co-simulation platform is configured to produce a first time sequence of values of a plurality of input ports of a design block of the electronic system, consume a second time sequence of values of a plurality of output ports of the design block, and generate access transactions for transferring the first and second sequences of values. The software co-simulation platform generates a plurality of reconfiguration transactions for transferring reconfiguration data for the design block. A PLD is configured to implement a communication block and a control block. The communication block receives the reconfiguration and access transactions from the software co-simulation platform, and the control block reconfigures programmable logic and interconnect resources of the PLD in response to the reconfiguration transactions. The control block also controls the emulation of the design block in response to the access transactions.

Abstract: A method and device for preserving the wired-OR nature of the clock signal connection between two devices without a direct analog connection between the lines and in an infinitely scalable fashion. The method includes detecting a logic state at a first connector and a second connector and driving an appropriate connector of the device to an active state in response to determining that a connector is driving an active state. The device includes first and second connectors for communicating logic states and driving active states in response to detected logic states.

Abstract: According to one embodiment, a self-test system integrated on a chip is provided, the chip including a functional logic module for performing a selected application. The self-test system includes a primary interface a primary interface to the functional logic module, the primary interface configured to interface with a primary device, an input interface protocol generator for generating a pattern to be inserted into the primary interface and a secondary interface to the functional logic module, the secondary interface configured to interface with a secondary device. The system also includes an emulator engine coupled to the secondary interface, the emulator engine for testing a function of the functional logic module based on the inserted patterns, the function being configured to communicate with a secondary device coupled to the secondary interface, wherein the emulator engine tests the function when no secondary device is coupled to the chip.

Abstract: A hybrid electronic design system and a reconfigurable connection matrix thereof are disclosed. The electronic design system includes a virtual unit, a hybrid unit and a communication channel. The virtual unit further includes a plurality of proxy units, a plurality of virtual components and a driver. The virtual components are connected with the driver via the proxy units. The hybrid unit further includes an emulate unit, a physical unit and a chip level transactor. The chip level transactor is connected with the emulate unit and the physical unit. The communication channel is connected with the driver of the virtual unit and the chip level transactor of the hybrid unit.

Abstract: A system for testing an integrated circuit, in which the system includes a deserializer, a frame sync module, and a diagnostic module. The deserializer is external to the integrated circuit and is configured to receive messages in a serial data format, wherein the messages include test results associated with the integrated circuit, and deserialize the messages into data frames. The frame sync module is configured to provide control code based on the data frames, wherein the control code includes, in a digital format, status information associated with the messages deserialized into the data frames. The diagnostic module is configured to generate, based on the control code, diagnostic data associated with states of the integrated circuit.

Abstract: Disclosed are various embodiments for transmission evaluation. In one embodiment, among others, a method includes evaluating a plurality of contingencies to generate a plurality of contingency results, where at least one of the contingency results includes an overload condition. The evaluation is based at least in part upon a case associated with a transmission network. The method further includes sorting the plurality of contingency results based upon corresponding overload-contingency pairs and determining a potential remediation solution to the overload condition based at least in part upon the overload-contingency pair. In another embodiment, a system includes a transmission evaluation application executed in a computing device.

Abstract: A method for operating a data processing system to generate a test for a device under test (DUT) is disclosed. The method utilizes a model of the DUT that includes a plurality of blocks connected by wires and a set of control inputs. Each block includes a plurality of ports, each port being either active or inactive. Each block is also characterized by a set of constraints that limit which ports are active. The active ports of at least one of the blocks are constrained by one of the control inputs. A test vector having one component for each port of each block and one component for each control input is determined such that each set of constraints for each block is satisfied. The test vector defines a test for the DUT.

Abstract: A hardware emulation system may emulate a plurality of cycles of a circuit, and may store state information at each cycle which specifies signal values for one or more signals of the circuit. After the hardware emulation has finished, the state information may be streamed from the memory of the hardware emulation system to a different storage device that is accessible by a computer system that executes one or more software checker routines. The computer system may execute the software checker routines, which may include passing the signal values specified in the state information to the software checker routines on a cycle-by-cycle basis similarly as if the software checker routines were receiving them in real time directly from the hardware emulation system.

Abstract: A system and method is disclosed in an emulation environment that dynamically remaps user designs. In one embodiment, a request is received to load an integrated circuit design to be emulated in a desired partition within the emulator. The emulator automatically determines the availability of the partition requested. If the partition is not available, the design is dynamically remapped to a different partition that is available. In another embodiment, clocks associated with the integrated circuit design are also dynamically remapped. In yet another embodiment, the user can control the size of the partitions (e.g., the number of printed circuit boards in a partition).

Abstract: Techniques related to remotely boundary scanning of an integrated circuit embedded in a target computing system are disclosed herein. In an example, a host computing system includes a first peripheral port and a second peripheral port. A port-to-port boundary scan assembly is to interface boundary scan data between the first and the second peripheral ports. Thereby the boundary scan data can be routed from the second peripheral bus to the target computing system via a network port at the host computing system.

Abstract: Hardware emulation produces relevant and irrelevant trace data. Verification of a design under test requires knowledge of the relevant trace data. Data lines are provided to capture trace data from the hardware emulator's logic elements during emulation. The data lines connect the outputs of these logic elements to the inputs of a configurable interconnect circuit. The configurable interconnect circuit is capable of being programmed to select from a plurality of these inputs to connect a number of the data lines to a scan chain or trace data storage circuit. The configurable interconnect circuit can then selectively connect those data lines carrying relevant trace data to a trace data processing circuit. The trace data processing circuit may be a scan chain, analysis device or storage device or other suitable trace data processing device.

Abstract: A hardware emulation system having a heterogeneous cluster of processors is described. The apparatus for emulating a hardware design comprises a plurality of processors, where each processor performs a different function during an emulation cycle. The method performed by the apparatus comprises using a data fetch processor to retrieve data from a data array, evaluating the retrieved data using the data fetch processor to produce an output bit, supplying the output bit to an intracluster crossbar and using a data store processor to store the output bit in the data array.

Abstract: A method of running a target device in a hardware-in-the-loop network simulation via a host computer may include launching a network application on a host computer each having a protocol stack and a network device connected to a simulated network of target devices, interposing, on the host computer, a target device interface and adaptor between the protocol stack and the network device and transferring data and control information between the network application and the target device via the network device, whereby the target device runs on the host computer as if the target device were running directly on a host computer having a network device directly compatible with the target device.

Abstract: A memory mapping system for compactly mapping dissimilar memory systems and methods for manufacturing and using same. The mapping system maps a source memory system into a destination memory system by partitioning the source memory system and disposing memory contents within the partitioned source memory system into the destination memory system. In one embodiment, the mapping system factorizes a source data width of the source memory system in terms of a destination data width of the destination memory system to form at least one data sub-width. A source memory sub-region is defined for each data sub-width. The memory contents associated with each source memory sub-region are disposed within the destination memory system in a side-by-side manner across selected destination memory registers of the destination memory system. The mapping system thereby can compactly map the memory contents into the destination memory system without a loss of valuable memory space.

Abstract: A method and apparatus for generating user clocks in a prototyping system is disclosed. A prototyping system has a plurality of programmable logic chips that are each programmed with one or more partition of a prototyped circuit design. For a circuit design having multiple user clock signals, each partition uses some or all of the user clocks. A reference clock signal is externally generated, and received by each of the programmable logic chips. Using a phase-locked loop, a plurality of in-phase higher frequency clock signals are generated from the reference clock signal. The user clock signals are then generated from these higher frequency signals using a plurality of divider circuits. Reset circuitry implemented in one of the programmable logic chips transmits a common reset signal to the divider circuits, maintaining the phase relationship of each user clock across the programmable logic chips.

Abstract: A computerized apparatus, method and computer product for generating tests.

Abstract: A modular circuit emulation system includes a global clock generator that generates a plurality of clock signals. A plurality of emulation boards each include at least one programmable circuit and a clock buffer. The clock buffer generates at least one synchronized clock signal for clocking the programmable circuit or circuits, based on at least one of the plurality of global clock signals.

Abstract: A crosstalk emulator for a cable, preferably a xDSL telecommunication cable, represented by several emulation paths each comprising a first segment (L1a/L4a) serially connected to a second segment (L1b/L4b) on a printed circuit board PCB. The first and second segments of a same emulation path form an angle, e.g. of about 90 degrees, at their junction point. All the emulation paths have a same length and preferably run in parallel over the PCB. As a result, each emulation path crosses only once (X21) any other emulation path at a cross-point. Furthermore, the area occupied by the crosstalk emulator on the PCB is reduced with respect to a matrix topology, whereby the present topology can easily be extended to large numbers of couplings, allowing design guidance for a passive coupling emulator with a large amount of coupling elements (CP) at the cross-points.

Abstract: The execution environment provides for scalability where components will execute in parallel and exploit various patterns of parallelism. Dataflow applications are represented by reusable dataflow graphs called map components, while the executable version is called a prepared map. Using runtime properties the prepared map is executed in parallel with a thread allocated to each map process. The execution environment not only monitors threads, detects and corrects deadlocks, logs and controls program exceptions, but also data input and output ports of the map components are processed in parallel to take advantage of data partitioning schemes. Port implementation supports multi-state null value tokens to more accurately report exceptions. Data tokens are batched to minimize synchronization and transportation overhead and thread contention.

Abstract: The present invention allows a verification environment to be used to control and coordinate interaction with a design running on an accelerator or emulator without significant speed penalty. For example, an interface capable of communicating with test software running on an embedded processor is used to control and monitor the flow of data into the external interface of the design. Thus, a connection is made between the verification environment and the design under test running on the accelerator/emulator via a connection formed directly between the verification environment and embedded software running on the emulator for simulation and monitoring purpose at a very low frequency so that high-speed acceleration may still be achieved.

Abstract: A method may include creating an Extensible Markup Language (XML) instruction file based on screen shots of a host system, providing the XML instruction file to a screen scraper program, executing screen scraping operations based on the XML instruction file, and outputting a user interface file based on the screen scraping operations that corresponds to extracted data output from the host system.

Abstract: A circuit emulation apparatus includes an emulator unit configured to emulate an operation of a circuit, a replacement unit configured to replace one or more redundant bits with a predetermined bit pattern when information bits and the one or more redundant bits of read data that is read from a first memory by the circuit are all zeros, and a supply unit configured to supply the information bits and the predetermined bit pattern as the read data to the circuit.

Abstract: A method for emulating and debugging a microcontroller is described. In one embodiment, an event thread is executed on an emulator that operates in lock-step with the microcontroller. Event information is sampled at selected points. Trace information is also recorded at the selected points. As such, the event information and trace information are effectively pre-filtered. Accordingly, it is not incumbent on a designer to read and understand the event and trace information and sort out the information that is of interest. Instead, this task is essentially done automatically, helping the designer and reducing the probability of error. Furthermore, because only selected event and trace information is recorded, the resources of the in-circuit emulator system are not taxed.

Abstract: A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and all remote devices follow during operation of the system. The method further comprises powering up a second remote device while the host device and first remote device are actively operating according to the state diagram. The second remote device waits for a synchronization point sequence. Upon detecting the synchronization point sequence, the second remote device implements a predetermined feature set and synchronizes itself to the state diagram at a common point as the host device and first remote device.

Abstract: This invention is a method and apparatus for monitoring an electronic apparatus. Capture units capture data to be monitored. A first-in-first-out buffer corresponding to each capture unit buffers the captured data. The buffered data supplies a utilization unit. Captured data may be merged after or before buffering. This merged data may be further merged with other buffered data.

Abstract: Systems and methods for testing and validation of translated memory banks used in an emulated system are disclosed. One method includes translating one or more banks of non-native instructions into one or more banks of native instructions executable in a computing system having a native instruction set architecture. The one or more banks of non-native instructions define one or more tests of execution of a non-native instruction set architecture. The method also includes loading a memory with instructions and data defined according to the non-native instruction set architecture and addressed by the one or more tests, and triggering, by an emulator, execution of the translated one or more banks of native instructions. The method further includes, upon detection of an error during execution of the translated one or more banks of native instructions, identifying an error in execution of the non-native instruction set architecture by the computing system.

Abstract: A custom prototyping board and a controller are integrated to form an emulation system for emulating a circuit design. The controller may be disposed on an adaptor board. The custom prototyping board is defined by a set of board description files which further define the FPGA device(s) used in the system as well as the wire connections among the FPGA devices and connectors on the custom prototyping board. The FPGA device(s) is configured in accordance with the partitioned circuit design. Each partitioned circuit in the FPGA device is associated with a verification module for communicating with the controller to control and probe the emulation. A host workstation may be used to link with the controller to support co-simulation or co-emulation of the circuit design.

Abstract: Generation of a test based on a test template comprising of branch instructions. The test template may be a layout test template, defining a set of possible control flows possibilities between template instructions in the layout test template. The test is generated by a test generator which may simulate a state of a target computerized system executing the test. The simulation may be performed during generation of the test. The test generator may further verify previously generated instructions. The test generator may further generate instructions associated with leftover template instructions.

Abstract: Systems, methods, and other embodiments associated with performance counters are described. In one embodiment, a method includes generating a first register transfer level (RTL) description of an integrated circuit that includes a performance counter. The integrated circuit is emulated in hardware and statistical data is collected with the performance counter. The performance counter is then removed from the integrated circuit.

Abstract: Systems and methods for testing a component by using encapsulation are described. The systems and methods facilitate communication between two components that use two different languages in a test environment. Such communication is allowed by encapsulating an identifier of a function to create a call message, encapsulating an identifier of an event to create an event message, or encapsulating an identifier of the function to create a return message.

Abstract: A technique for reliably replaying operations in electronic-design-automation (EDA) software is described. In this technique, the EDA software stores operations performed by a user during a design session, as well as any replay look-ahead instructions, in a log file. When repeating the first operation, the replay look-ahead instruction ensures that the same state is obtained in the EDA environment as was previously obtained. For example, if an interrupt occurred when the first operation was previously performed, the replay look-ahead instruction may specify when the interrupt occurred during the performance of the operation so that the effect of the interrupt may be simulated when replaying the first operation.