Maximum/minimum Determination Patents (Class 708/207)
  • Patent number: 10284224
    Abstract: A system for compressed sensing comprising: a compressive sampling module configured for providing a CS-sampled signal and a signal reconstruction module configured for receiving and allocating a first plurality of measurement windows comprising a number of samples from the CS-sampled signal, calculating a corresponding first plurality of reconstruction windows based on the first plurality of measurement windows and calculating a first version of a reconstructed signal based on the first plurality of reconstruction windows.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: May 7, 2019
    Assignees: IMEC VZW, Katholieke Universiteit Leuven, KU LEUVEN R&D
    Inventor: Venkata Rajesh Pamula
  • Patent number: 10025594
    Abstract: A data processing apparatus includes a plurality of processing units configured to process packets each including data and extended identification information added to the data, the extended identification information including identification information for identifying the data and instruction information indicating one or more processing instructions to the data, each processing unit in the plurality of processing units including: an input/output unit configured to obtain, in the packets, only a packet whose address information indicates said each processing unit in the plurality of processing units, the address information determined in accordance with the extended identification information; and an operation unit configured to execute the processing instruction in the packet obtained by the input/output unit.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: July 17, 2018
    Assignee: Mush-A Co., Ltd.
    Inventor: Mitsuru Mushano
  • Patent number: 9824317
    Abstract: A method includes forming a working mixed integer linear program (MILP) from a given MILP for job allocation to allocate people to jobs at least by choosing a subset of variables from the MILP. Only person/job combinations that are deemed most valuable are chosen for the subset. The working MILP includes the chosen subset of variables but no other variables from the given MILP. The working MILP is solved to determine a solution. Using the solution, a special linear program is formed and solved to determine a price of each constraint relative to the solution. Using the prices, variables that are not in the working MILP are evaluated to determine any variables that can contribute to an improved solution. The variables evaluated as contributing to an improved solution are added to the working MILP. The working MILP with the added variables is solved. Apparatus and program products are also disclosed.
    Type: Grant
    Filed: July 6, 2016
    Date of Patent: November 21, 2017
    Assignee: International Business Machines Corporation
    Inventor: Irvin J. Lustig
  • Patent number: 9778979
    Abstract: An operating method of an error correction decoder includes receiving data, setting initial log-likelihood values of variable nodes, and decoding the received data by updating a log-likelihood value of a selected variable node by use of a minimum value and a minimum candidate value associated with the selected variable node. The minimum value indicates a minimum value of absolute values of log-likelihood values of first variable nodes sharing a check node with the selected variable node and including the selected variable node. The minimum candidate value indicates one from among absolute values of log-likelihood values of second variable nodes that has the smallest value greater than the minimum value. The second variable nodes are selected later than one from among the first variable nodes corresponding to the minimum value.
    Type: Grant
    Filed: July 15, 2015
    Date of Patent: October 3, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Min Shin, Myungkyu Lee, Beom Kyu Shin, Kijun Lee
  • Patent number: 9697176
    Abstract: A method of multiplication of a sparse matrix and a vector to obtain a new vector and a system for implementing the method are claimed. Embodiments of the method are intended to optimize the performance of sparse matrix-vector multiplication in highly parallel processors, such as GPUs. The sparse matrix is stored in compressed sparse row (CSR) format.
    Type: Grant
    Filed: November 14, 2014
    Date of Patent: July 4, 2017
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Mayank Daga, Joseph L. Greathouse
  • Patent number: 9678715
    Abstract: An apparatus 8 for performing a selectable one of multi-element comparison and multi-element addition is formed from a carry propagate adders stage 12 supplied with four non-final intermediate operands formed from the input vector, a non-final limit value selecting stage 14, which when performing a multi-element comparison serves to select, in dependence upon at least carry save values generated by the carry propagate adder, limit values that are of a larger or a smaller value of a pair of elements. A final intermediate operand forming stage 16 forms final intermediate operands from two non-final intermediate sum values from the carry propagate adders stage 12 and supplies these to a final output adder stage 18 which forms a sum of these two final intermediate operands to generate an output operand which can be either one or more candidates for limit values that will be a maximum or minimum value, or a sum value, or partial sum values in the case of a multi-element addition.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: June 13, 2017
    Assignee: ARM Limited
    Inventors: Neil Burgess, David Raymond Lutz
  • Patent number: 9678753
    Abstract: Method, apparatus, and program means for nonlinear filtering and deblocking applications utilizing SIMD sign and absolute value operations. The method of one embodiment comprises receiving first data for a first block and second data for a second block. The first data and said second data are comprised of a plurality of rows and columns of pixel data. A block boundary between the first block and the second block is characterized. A correction factor for a deblocking algorithm is calculated with a first instruction for a sign operation that multiplies and with a second instruction for an absolute value operation. Data for pixels located along said block boundary between the first and second block are corrected.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: June 13, 2017
    Assignee: Intel Corporation
    Inventors: William W. Macy, Jr., Huy V. Nguyen
  • Patent number: 9449675
    Abstract: The present disclosure includes apparatuses and methods related to identifying an extremum value using sensing circuitry. An example method can include determining a location of an extremum value of a set of N data values stored as vectors in a memory array. A number of operations to determine the location of the extremum value can remain constant with respect to a value of N. The method can include determining the value of the extremum by reading memory cells coupled to the sense line based on the determined location of the extremum value.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: September 20, 2016
    Assignee: Micron Technology, Inc.
    Inventor: Kyle B. Wheeler
  • Patent number: 9450602
    Abstract: A query of time series data stored in a database is received that specifies at least one value. The database includes (i) an index table specifying groups of segments of compressed time series data with corresponding ranges each having a lowest value and a highest value, and (ii) a segments table specifying individual segments of compressed time series data. Thereafter, using the index table, at least one group for which the specified at least one value falls within the corresponding range is identified. The segments table is then queried for the segments corresponding to the identified at least one group to generate a new segments table specifying at least one segment. Next, the at least one segment specified by the new segments table is decompressed. Data responsive to the query within the decompressed at least one segment is then identified using the specified at least one value.
    Type: Grant
    Filed: January 2, 2014
    Date of Patent: September 20, 2016
    Assignee: SAP SE
    Inventors: Frank Eichinger, Dennis Kurfiss
  • Patent number: 9391621
    Abstract: Field programmable gate arrays (FPGA) contain, in addition to random logic, also other components, such as processing units, multiply-accumulate (MAC) units, analog circuits, and other elements, configurable with respect of the random logic, to enhance the capabilities of the FPGA. A circuit for a filed configurable MAC unit is provided to allow various configurations of ADD, SUBTRACT, MULTIPLY and SHIFT functions. Optionally, registered input and registered output support a multi-cycle path. A configuration of a constant facilitates the configuration of the circuit to perform infinite impulse response (IIR) and finite impulse response (FIR) functions in hardware.
    Type: Grant
    Filed: December 10, 2013
    Date of Patent: July 12, 2016
    Assignee: Silicon Mobility
    Inventors: Loic Vezier, Farid Tahiri
  • Patent number: 9165023
    Abstract: An integrated circuit device comprises at least one digital signal processor, DSP, module, the at least one DSP module comprising a plurality of data registers and at least one data execution unit, DEU, module arranged to execute operations on data stored within the data registers. The at least one DEU module is arranged to, in response to receiving an extreme value index instruction, compare a previous extreme value located within a first data register set of the DSP module with at least one input vector data value located within a second data register set of the DSP module, and determine an extreme value thereof. The at least one DEU module is further arranged to, if the determined extreme value comprises an input vector data value located within the second data register set, store the determined extreme value in the first data register set, determine an index value for the determined extreme value, and store the determined index value in the first data register set.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: October 20, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Ilia Moskovich, Aviram Amir, Itzhak Barak, Eliezer Ben Zeev
  • Patent number: 9098121
    Abstract: A comparator (231) for determining a peak number, representing a maximum or minimum of a set of numbers, includes a multi-element comparator (232) for comparing different pages of the set of numbers in a page comparison mode to output a candidate set of winning numbers, and for automatically switching to a leaf/tree search of the candidate set of winning numbers in an element comparison mode. Operating in parallel with the multi-element comparator (232), an index generation unit (233) processes flag/sign bits from the multi-element comparator in conjunction with state machine control logic (230) to keep track of the index/indices for the peak value. Upon completion of final stage, the index generation unit returns the absolute index (235) of the peak value.
    Type: Grant
    Filed: January 22, 2013
    Date of Patent: August 4, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jayakrishnan C. Mundarath, Leo G. Dehner, Eric J. Jackowski
  • Patent number: 8954483
    Abstract: Provided are an arithmetic circuit and an arithmetic apparatus capable of performing comparison involving conditional branch of three or more values at high speed. The arithmetic circuit includes a plurality of computing units, a plurality of selection circuits and a decision unit. The plurality of computing units perform arithmetic computations on input data and output flag information generated based on a result of the computations. The plurality of selection circuits select any one of the data input to the plurality of computing units. The decision unit receives the flag information from the plurality of computing units and controls select operation of each of the plurality of selection circuits.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: February 10, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Yuki Kobayashi
  • Patent number: 8943115
    Abstract: A group of numbers from which the smallest and second-smallest are to be selected are compared in a cascaded tree. Each comparison stage will select the smallest number from two numbers output by the previous stage, into which four numbers are input. The second-smallest number is one of the other three inputs to the previous stage and, as before, all bits of the second-smallest number will not be known until the smallest number is determined. However, because at each stage of the determination, the next stage is reached because the bit values being examined are the same, those bit values of the second-smallest number (and indeed of the smallest number) are known ahead of the final determination of the smallest number. Accordingly, one can begin to output bits of the second-smallest number (as well as of the smallest number) even before that final determination.
    Type: Grant
    Filed: July 10, 2012
    Date of Patent: January 27, 2015
    Assignee: Marvell International Ltd.
    Inventor: Engling Yeo
  • Patent number: 8935308
    Abstract: A method recovers an uncorrupted low-rank matrix, noise in corrupted data and a subspace from the data in a form of a high-dimensional matrix. An objective function minimizes the noise to solve for the low-rank matrix and the subspace without estimating the rank of the low-rank matrix. The method uses group sparsity and the subspace is orthogonal. Random subsampling of the data can recover subspace bases and their coefficients from a much smaller matrix to improve performance. Convergence efficiency can also be improved by applying an augmented Lagrange multiplier, and an alternating stepwise coordinate descent. The Lagrange function is solved by an alternating direction method.
    Type: Grant
    Filed: January 20, 2012
    Date of Patent: January 13, 2015
    Assignee: Mitsubishi Electric Research Laboratories, Inc.
    Inventors: Fatih Porikli, Xianbiao Shu
  • Publication number: 20150006598
    Abstract: Certain aspects of the present disclosure relate to a method for quantizing signals and reconstructing signals, and/or encoding or decoding data for storage or transmission. Points of a signal may be determined as local extrema or points where an absolute rise of the signal is greater than a threshold. The tread and value of the points may be quantized, and certain of the quantizations may be discarded before the quantizations are transmitted. After being received, the signal may be reconstructed from the quantizations using an iterative process.
    Type: Application
    Filed: September 16, 2014
    Publication date: January 1, 2015
    Inventors: Harinath Garudadri, Pawan Kumar Baheti, Somdeb Majumdar
  • Publication number: 20140365544
    Abstract: Multi-way partitioning is dramatically improved based on “weakest-link” optimality. The set of numbers to be partitioned is subjected to pairwise decomposition with a first partition having a candidate subset (P1={S1}), and a lower cost bound cmin is set equal to a maximum cost of this subset. A recursive call is then invoked to resolve the subproblem of the second partition (P2={S2, S3, . . . , Sk}). If each second candidate subset in the second partition has a cost which is less than or equal to the lower cost bound, then the first partition is returned with the second partition as an optimal solution regardless of whether the second partition is an optimal decomposition. Additional efficiency may be achieved by excluding any subset having a cost which is greater than or equal to the best cost so far. Dominated and symmetric solutions can also be excluded.
    Type: Application
    Filed: June 11, 2013
    Publication date: December 11, 2014
    Inventor: Michael D. Moffitt
  • Publication number: 20140365545
    Abstract: Multi-way partitioning is dramatically improved based on “weakest-link” optimality. The set of numbers to be partitioned is subjected to pairwise decomposition with a first partition having a candidate subset (P1={S1}), and a lower cost bound cmin is set equal to a maximum cost of this subset. A recursive call is then invoked to resolve the subproblem of the second partition (P2={S2, S3, . . . , Sk}). If each second candidate subset in the second partition has a cost which is less than or equal to the lower cost bound, then the first partition is returned with the second partition as an optimal solution regardless of whether the second partition is an optimal decomposition. Additional efficiency may be achieved by excluding any subset having a cost which is greater than or equal to the best cost so far. Dominated and symmetric solutions can also be excluded.
    Type: Application
    Filed: December 6, 2013
    Publication date: December 11, 2014
    Applicant: International Business Machines Corporation
    Inventor: Michael D. Moffitt
  • Publication number: 20140351302
    Abstract: A machine-implemented method for computerized digital signal processing including obtaining a digital signal from data storage or from conversion of an analog signal, and determining, from the digital signal, one or more measuring matrices. Each measuring matrix has a plurality of cells, and each cell has an amplitude corresponding to the signal energy in a frequency bin for a time slice. Cells in each measuring matrix having maximum amplitudes along a time slice and/or frequency bin are identified as maximum cells. Maxima that coincide in time and frequency are identified and a correlated maxima matrix, called a “Precision Measuring Matrix” is constructed showing the coinciding maxima and the adjacent marked maxima are linked into partial chains.
    Type: Application
    Filed: December 20, 2013
    Publication date: November 27, 2014
    Applicant: Paul Reed Smith Guitars Limited Partnership
    Inventors: Paul Reed SMITH, Jack W. Smith, Frederick M. Slay
  • Patent number: 8898210
    Abstract: For determining a minimum/maximum of a plurality of binary values a bit position in the plurality of binary values is determined subsequent to which all bit values are the same. From the plurality of binary values those binary values are selected the bit values of which at the bit position determined in the preceding step and all subsequent positions, if any, has a predetermined value. The preceding steps are then repeated until only one binary value remains which is provided as the minimum or maximum.
    Type: Grant
    Filed: August 5, 2008
    Date of Patent: November 25, 2014
    Assignee: Advantest (Singapore) Pte Ltd
    Inventor: Michael Mueller
  • Publication number: 20140344320
    Abstract: Solving a multidimensional multicriteria optimization problem is difficult because the correlations and dependencies between solutions, target functions, and variation variables can be detected only with difficulty. In order to facilitate this, it is proposed that a model space (1) and a variation space (2) are displayed simultaneously and in an interactively linked fashion.
    Type: Application
    Filed: November 8, 2012
    Publication date: November 20, 2014
    Applicant: AVL LIST GMBH
    Inventors: Klemens Wallner, Alejandra Garcia, Adnand Dragoti
  • Publication number: 20140297703
    Abstract: A mechanism for reconstructing a signal (e.g., an image) based on a vector s, which includes measurements of the signal. The measurements have been acquired using at least a portion of a measurement vector set represented by a matrix H. Each of the measurements corresponds to a respective row of the matrix H. (For example, each of the measurements may correspond to an inner product between the signal and a respective row of the matrix product HD, wherein D is a generalized permutation matrix.) A total-variation primal-dual hybrid gradient (TV-PDHG) algorithm is executed based on data including the matrix H and the vector s, to determine an estimate for the signal. The TV-PDHG algorithm is implemented in fixed-point arithmetic.
    Type: Application
    Filed: December 20, 2013
    Publication date: October 2, 2014
    Applicant: InView Technology Corporation
    Inventors: Thomas A. Goldstein, Matthew A. Herman
  • Patent number: 8849881
    Abstract: A logic circuit computes various modal interval arithmetic values using a plurality of arithmetic function units. A multiplexer gates the desired arithmetic values to a storage register.
    Type: Grant
    Filed: May 24, 2011
    Date of Patent: September 30, 2014
    Assignee: Sunfish Studio, LLC
    Inventor: Nathan T. Hayes
  • Publication number: 20140258352
    Abstract: A method of identifying a set of parameters representative of a data set is provided. An eigen decomposition of a covariance matrix is calculated to form a decomposed matrix and an eigenvalue vector. The covariance matrix is calculated for a matrix of data including a plurality of data values for each of a plurality of parameters. The decomposed matrix includes a number of eigenvectors equal to a number of the plurality of parameters with each eigenvector including a coefficient for each parameter. The eigenvalue vector includes an eigenvalue defined for each eigenvector. A first matrix is created by rank ordering the coefficient within each parameter of the plurality of parameters for each of the plurality of parameters. A score is determined for each parameter using the created first matrix and the eigenvalue vector. A parameter set is identified based on the determined score for each parameter.
    Type: Application
    Filed: July 3, 2013
    Publication date: September 11, 2014
    Inventors: Brian Oneal Miles, Dan Kelly
  • Patent number: 8793294
    Abstract: A floating point max/min circuit for determining the maximum or minimum of two floating point operands includes a first analysis circuit configured to determine a format of a first floating point operand of the two floating point operands based upon floating point status information encoded within the first floating point operand, a second analysis circuit configured to determine a format of a second floating point operand of the two floating point operands based upon floating point status information encoded within the second floating point operand, a decision circuit, coupled to the first analysis circuit and to the second analysis circuit and responding to a function control signal that indicates the threshold condition is one of a maximum of the two floating point operands and a minimum of the two floating point operands, for generating at least one assembly control signal based on the format of a first floating point operand, the format of a second floating point operand, and the function control signal,
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: July 29, 2014
    Assignee: Oracle America, Inc.
    Inventor: Guy L. Steele, Jr.
  • Publication number: 20140207837
    Abstract: A calculating device selects an action and a corresponding state; acquires an evaluation value by evaluating the combination of the selected action and the selected state; identifies for each selected action, a lowest evaluation value among acquired evaluation values; determines the lowest evaluation value among evaluation values of all the states selected for each action as a minimax candidate, and determines, as a minimax, an evaluation value that is highest among the lowest evaluation values corresponding to the actions; each time an evaluation value is acquired for a combination of a state and an action after the minimax candidate is determined, compares the acquired evaluation value and the minimax candidate, and terminates selection of a state corresponding to the action when the evaluation value is lower than the minimax candidate and selects an unselected action from the action set; and outputs an action corresponding to the determined minimax.
    Type: Application
    Filed: March 19, 2014
    Publication date: July 24, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Tsuyoshi Taniguchi, Yoshio Nakao
  • Publication number: 20140207836
    Abstract: A comparator (231) for determining a peak number, representing a maximum or minimum of a set of numbers, includes a multi-element comparator (232) for comparing different pages of the set of numbers in a page comparison mode to output a candidate set of winning numbers, and for automatically switching to a leaf/tree search of the candidate set of winning numbers in an element comparison mode. Operating in parallel with the multi-element comparator (232), an index generation unit (233) processes flag/sign bits from the multi-element comparator in conjunction with state machine control logic (230) to keep track of the index/indices for the peak value. Upon completion of final stage, the index generation unit returns the absolute index (235) of the peak value.
    Type: Application
    Filed: January 22, 2013
    Publication date: July 24, 2014
    Inventors: Jayakrishnan C. Mundarath, Leo G. Dehner, Eric J. Jackowski
  • Publication number: 20140136582
    Abstract: A method for scaling a plurality of data values includes storing a first subset of data values of the plurality of data values into a first vector register, determining a maximum data value of the first subset of data values, and storing the greater of the maximum data value and a value stored in a scalar register to the scalar register. Each data value of the subset of data values is stored in a different element of the first vector register. The method further includes determining an adjustment factor based on the value stored in the scalar register and adjusting each data value of the plurality of data values by the adjustment factor.
    Type: Application
    Filed: November 12, 2012
    Publication date: May 15, 2014
    Applicant: Futurewei Technologies, Inc.
    Inventors: Weizhong Chen, Yuanpei Jiao, Tong Sun
  • Publication number: 20140122551
    Abstract: An arithmetic logic unit (ALU) including a first routing grid connected to multiple data lanes to drive first data to the data lanes. A second routing grid is connected to the data lanes to drive second data to the data lanes. Each of the data lanes include multiple, e.g. N, functional units with first inputs from the first routing grid and second inputs from the second routing grid. The functional units compute pairwise a function of the respective first data on the respective first inputs and the respective second data on the respective second inputs. Each of the data lanes include a reduction unit with inputs adapted to receive K? bits per word from the functional units. The reduction unit is configured to perform a reduction operation configured to output an output result having a reduced number J? bits per word, wherein J? is less than N multiplied by K?.
    Type: Application
    Filed: October 31, 2012
    Publication date: May 1, 2014
    Applicant: MOBILEYE TECHNOLOGIES LIMITED
    Inventors: Gil Israel Dogon, Yosi Arbeli, Yosef Kreinin
  • Patent number: 8682946
    Abstract: A method for determining a peak value of a histogram or a sequence of sampled data is disclosed. The method may include fitting a curve to the sequence of data, the curve being modeled based on an orthonormal expansion; obtaining a differential curve, the differential curve describing changes in slope of the curve fitted to the sequence of data; finding at least one root for the differential curve; for each of the at least one root for the differential curve, calculating a corresponding value on the curve fitted to the sequence of data; and determining the peak value of the sequence of data based on a maximum value among the corresponding value calculated for each of the at least one root.
    Type: Grant
    Filed: May 26, 2011
    Date of Patent: March 25, 2014
    Assignee: KLA-Tencor Corporation
    Inventors: Harish P. Hiriyannaiah, Donald D. Walker
  • Patent number: 8666688
    Abstract: A system and a method is provided for the detection and capture, and in particular for an ultra high speed detection and capture, of transients in input voltages by an intelligent electronic device. The system and method detects transients for input voltages in either phase to phase or phase to neutral measurements and permits a user to set threshold levels for detecting transients in input voltages. In an embodiment, the system and method further provides a field programmable gate array as a controller for managing transient detection. The field programmable gate array includes a state machine for determining the state of the sampled signal with respect to a threshold level at a specified waveform sample period.
    Type: Grant
    Filed: March 13, 2008
    Date of Patent: March 4, 2014
    Assignee: Electro Industries/Gauge Tech
    Inventors: Joseph Spanier, Hai Zhu, Wei Wang
  • Publication number: 20140059095
    Abstract: In various example embodiments, systems and methods for estimating the mean of a dataset having a fat tail. Data sets may be partitioned into components, a “torso” component and a “tail” component. For the “tail” component of the data set a more efficient estimator can be obtained (versus the traditionally calculated mean) by using the tail data to estimate parameters for a specific distribution and then deriving the mean from the estimated parameters. The estimated mean from the torso and the estimated mean from the tail may then be combined to obtain the estimated mean for the full data. This can be applied to gross merchandise bought (GMB) by various samples of visitors and apply the experience that was provided to the sample with the highest GMB to all visitors to increase gross revenue.
    Type: Application
    Filed: August 21, 2012
    Publication date: February 27, 2014
    Applicant: eBay Inc.
    Inventors: Greg D. Adams, Timothy W. Amato, Kumar R. Dandapani, Yiping Dou, Gurudev Karanth, Anthony Douglas Thrall, Mithun Yarlagadda
  • Patent number: 8648873
    Abstract: A system including a processor for adjusting the dynamic range of an image including a plurality of pixels. The processor segments the pixels into blocks, and computes statistical values for each block based on intensity values of the pixels. The processor also adjusts the dynamic range of the image by controlling the intensity values of the pixels based on the statistical values.
    Type: Grant
    Filed: November 19, 2010
    Date of Patent: February 11, 2014
    Assignee: Exelis, Inc.
    Inventors: Theodore Anthony Tantalo, Kenneth Michael Brodeur
  • Patent number: 8649508
    Abstract: A system and method for implementing the Elliptic Curve scalar multiplication method in cryptography, where the Double Base Number System is expressed in decreasing order of exponents and further on using it to determine Elliptic curve scalar multiplication over a finite elliptic curve.
    Type: Grant
    Filed: September 29, 2008
    Date of Patent: February 11, 2014
    Assignee: Tata Consultancy Services Ltd.
    Inventor: Natarajan Vijayarangan
  • Patent number: 8650232
    Abstract: A system for fast determination of a horizontal minimum of multiple digital values including a difference circuit and a compare circuit. The difference circuit may include first and second adders in which the first adder compares upper bits of a first digital value with upper bits of a second digital value and provides a first carry output and a propagate output. The second adder compares lower bits of the first digital value with lower bits of the second digital value and provides a second carry output. The compare circuit determines whether the first digital value is greater than the second digital value based on the carry and propagate outputs. Multiple difference circuits may be used to compare each of multiple digital values with every other digital value to provide corresponding compare bits, which are then used to determine a minimum one of the digital values and its corresponding location.
    Type: Grant
    Filed: October 26, 2009
    Date of Patent: February 11, 2014
    Assignee: VIA Technologies, Inc.
    Inventors: Rochelle L. Stortz, Raymond A. Bertram
  • Patent number: 8635258
    Abstract: The problem of aligning multiple liquid chromatography mass spectrometry (LC-MS) runs to a common reference time frame is solved to facilitate comparison among LC-MS runs. The alignment of multiple LCMS can be achieved by solving a sparse system of linear equations to optimally stretch or compress local retention times for maximal similarity among the multiple runs. The multiple LCMS runs can be aligned simultaneously, thereby providing the advantage of efficient use of data by employing a sparse solver. A method of quality control in retention time alignment is also provided.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: January 21, 2014
    Assignee: International Business Machines Corporation
    Inventors: Peicheng Du, Frank Suits
  • Patent number: 8631057
    Abstract: The problem of aligning multiple liquid chromatography mass spectrometry (LC-MS) runs to a common reference time frame is solved to facilitate comparison among LC-MS runs. The alignment of multiple LCMS can be achieved by solving a sparse system of linear equations to optimally stretch or compress local retention times for maximal similarity among the multiple runs. The multiple LCMS runs can be aligned simultaneously, thereby providing the advantage of efficient use of data by employing a sparse solver. A method of quality control in retention time alignment is also provided.
    Type: Grant
    Filed: August 25, 2009
    Date of Patent: January 14, 2014
    Assignee: International Business Machines Corporation
    Inventors: Peicheng Du, Frank Suits
  • Patent number: 8620976
    Abstract: A machine-implemented method for computerized digital signal processing including obtaining a digital signal from data storage or from conversion of an analog signal, and determining, from the digital signal, one or more measuring matrices. Each measuring matrix has a plurality of cells, and each cell has an amplitude corresponding to the signal energy in a frequency bin for a time slice. Cells in each measuring matrix having maximum amplitudes along a time slice and/or frequency bin are identified as maximum cells. Maxima that coincide in time and frequency are identified and a correlated maxima matrix, called a “Precision Measuring Matrix” is constructed showing the coinciding maxima and the adjacent marked maxima are linked into partial chains.
    Type: Grant
    Filed: May 11, 2011
    Date of Patent: December 31, 2013
    Assignee: Paul Reed Smith Guitars Limited Partnership
    Inventors: Paul Reed Smith, Frederick M. Slay, Ernestine M. Smith
  • Publication number: 20130339411
    Abstract: Systems and methods pertaining to nearness calculations of points in n-space. Among the embodiments is associating points of interest with point records in a data store, and efficient retrieval of subsets of those point records which meet arbitrary criteria. Criteria can limit retrieval to neighbors of a reference point (i.e., point records associated with points of interest whose home cells that share at least one interface with another designated home cell. Computationally expensive, at-retrieval range calculations are avoided by performing complimentary calculations at-storage and saving them with related records. The invention is appropriate for use with data storage mechanisms which limit inequality or range operations, or for which such operations result in inefficiencies. When used to model neighboring points on a planetary surface in 3-space, the invention does not suffer from polar distortion (where spherical coordinate systems have difficulty).
    Type: Application
    Filed: August 20, 2013
    Publication date: December 19, 2013
    Inventor: Matthew Thomas Bogosian
  • Publication number: 20130325393
    Abstract: A method for determining the coordinates of a point on the surface of an object is provided. A source system, such as an OBIRCH system, is used to analyze and detect faults in an integrated circuit on a semiconductor die. The die includes three reference points and the detected fault(s) are defined with reference to the reference points. When the die is transferred to a FIB or other system for fault analysis, a processor determines the coordinates of the fault(s) for the FIB system using the three reference points.
    Type: Application
    Filed: June 5, 2012
    Publication date: December 5, 2013
    Applicant: FREESCALE SEMICONDUCTOR, INC
    Inventor: Motohiko Masuda
  • Patent number: 8581872
    Abstract: A method for finding local maxima in a two-dimensional array includes generating a row array for each row in the array and a column array for each column in the array. The values in a given generated row array are indicative of local maxima of values in the corresponding row, and values in a given generated column array are indicative of local maxima of values in the corresponding column. The method may also include the computer multiplying values in the generated row and column arrays to determine local maxima of the array.
    Type: Grant
    Filed: January 3, 2012
    Date of Patent: November 12, 2013
    Assignee: Silicon Laboratories Inc.
    Inventor: Soh Kok Hong
  • Patent number: 8577947
    Abstract: The present invention relates to a solution-finding method, which finds an approximate solution of an equation having difficulty in obtaining an actual solution and a complicated equation in numerical analysis. The method obtains an approximate solution of an equation having a solution in a predetermined interval. Initial values are calculated based on upper and lower limits of the interval. The initial values are applied to a solution-finding equation, including a sign function and the upper and lower limits, and the solution-finding equation is arranged so that a definite integral formula for the sign function is included in the equation. The definite integral formula in the solution-finding equation is calculated using numerical integration, and results of the definite integral formula are applied to the solution-finding equation, thus obtaining an approximate solution. This performance is iterated until the approximate solution satisfies an allowable error.
    Type: Grant
    Filed: March 5, 2010
    Date of Patent: November 5, 2013
    Assignee: Kunsan National University Industry-Academic Cooperation Foundation
    Inventor: Beong-in Yun
  • Patent number: 8527566
    Abstract: An optimization system and method includes determining a best gradient as a sparse direction in a function having a plurality of parameters. The sparse direction includes a direction that maximizes change of the function. This maximum change of the function is determined by performing an optimization process that gives maximum growth subject to a sparsity regularized constraint. An extended Baum Welch (EBW) method can be used to identify the sparse direction. A best step size is determined along the sparse direction by finding magnitudes of entries of direction that maximizes the function restricted to the sparse direction. A solution is recursively refined for the function optimization using a processor and storage media.
    Type: Grant
    Filed: May 11, 2010
    Date of Patent: September 3, 2013
    Assignee: International Business Machines Corporation
    Inventors: Dimitri Kanevsky, David Nahamoo, Bhuvana Ramabhadran, Tara N. Sainath
  • Patent number: 8515879
    Abstract: Supervised kernel nonnegative matrix factorization generates a descriptive part-based representation of data, based on the concept of kernel nonnegative matrix factorization (kernel NMF) aided by the discriminative concept of graph embedding. An iterative procedure that optimizes suggested formulation based on Pareto optimization is presented. The present formulation removes any dependence on combined optimization schemes.
    Type: Grant
    Filed: August 11, 2010
    Date of Patent: August 20, 2013
    Assignee: Seiko Epson Corporation
    Inventors: Seung-il Huh, Mithun Das Gupta, Jing Xiao
  • Patent number: 8499017
    Abstract: A data processing apparatus is arranged to perform a fused multiply add operation. The apparatus 100 has multiplying circuitry 110 configured to multiply operands B and C to generate a product B*C having a high order portion 160 and a low order portion 170. The apparatus has adding circuitry 130 configured to: (i) add an operand A to one of the high order portion 160 and the low order portion 170 to generate an intermediate sum value; and (ii) add the intermediate sum value to a remaining one of the high order portion 160 and the low order portion 170 to generate a result A+B*C.
    Type: Grant
    Filed: August 12, 2009
    Date of Patent: July 30, 2013
    Assignee: ARM Limited
    Inventors: Antony John Penton, Simon John Craske, Ian Michael Caulfield
  • Publication number: 20130191425
    Abstract: A method recovers an uncorrupted low-rank matrix, noise in corrupted data and a subspace from the data in a form of a high-dimensional matrix. An objective function minimizes the noise to solve for the low-rank matrix and the subspace without estimating the rank of the low-rank matrix. The method uses group sparsity and the subspace is orthogonal. Random subsampling of the data can recover subspace bases and their coefficients from a much smaller matrix to improve performance. Convergence efficiency can also be improved by applying an augmented Lagrange multiplier, and an alternating stepwise coordinate descent. The Lagrange function is solved by an alternating direction method.
    Type: Application
    Filed: January 20, 2012
    Publication date: July 25, 2013
    Inventors: Fatih Porikli, Xianbiao Shu
  • Patent number: 8495117
    Abstract: A system and method for parallelization of saturated accumulation is provided. In the method, an input sequence is divided into a plurality of subsequences. For each subsequence, three parallel saturating additions are performed. The local saturation minimum is the saturating addition of the global saturation minimum and the values of the subsequence. The local midpoint is the saturating addition of the values of the subsequence and the local saturation maximum is the saturating addition of the global saturation maximum and the values of the subsequence. In embodiments, the accumulation total for a subsequence is calculated as the saturating addition of the accumulation total for prior subsequences and the local midpoint of the current subsequence, wherein the accumulation total of the last subsequence is the result of the saturated accumulation for the sequence. In another embodiment, the saturated addition of subsequence results are further parallelized before the final result is reached.
    Type: Grant
    Filed: March 17, 2009
    Date of Patent: July 23, 2013
    Assignee: Broadcom Corporation
    Inventors: Alexander J. Burr, Timothy M. Dobson
  • Publication number: 20130179112
    Abstract: A method to accurately detect true peaks and true valleys in a real-time incoming signal is provided. The method includes segmenting the real-time incoming signal into short-time intervals; determining an initial estimated frequency by fast Fourier transforming data in the short-time intervals, setting a sliding window width based on the initial estimated frequency, determining at least one peak data element or valley data element based on analysis of the real-time incoming signal within a first sliding window; and determining at least one peak data element or valley data element based on analysis of the real-time incoming signal within a second sliding window. A first portion of the second sliding window overlaps a second portion of the first sliding window.
    Type: Application
    Filed: January 9, 2012
    Publication date: July 11, 2013
    Applicant: Honeywell International Inc.
    Inventors: Yunqian Ma, Kyle Zakrzewski
  • Patent number: 8468185
    Abstract: A method of data processing. The method comprises applying a filter to an input sample set comprising sample values selected from an input sequence of input sample values, so as to generate a corresponding output sample value having an output sample value position with respect to the input sample set, in which the filter has a maximum output range. The method further comprises deriving a permissible output value range from an input group of two or more input sample values in the input sample set which surround the output sample value position, detecting whether the output of the filter is outside the permissible output value range and, if so, limiting the output of the filter to lie within the permissible output value range.
    Type: Grant
    Filed: October 2, 2009
    Date of Patent: June 18, 2013
    Assignee: Sony United Kingdom Limited
    Inventors: Manish Devshi Pindoria, Karl James Sharman
  • Patent number: 8463834
    Abstract: A floating point multiplier includes a data path in which a plurality of partial products are calculated and then reduced to a first partial product and a second partial product. Shift amount determining circuitry 100 analyzes the exponents of the input operands A and B as well as counting the leading zeros in the fractional portions of these operands to determine an amount of left shift or right shift to be applied by shifting circuitry 200, 202 within the multiplier data path. This shift amount is applied so as to align the partial products so that when they are added they will produce the result C without requiring this to be further shifted. Furthermore, shifting the partial products to the correct alignment in this way in advance of adding these partial products permits injection rounding combined with the adding of the partial products to be employed for cases including subnormal values.
    Type: Grant
    Filed: November 3, 2009
    Date of Patent: June 11, 2013
    Assignee: ARM Limited
    Inventor: David Raymond Lutz