Maximum/minimum Determination Patents (Class 708/207)
  • Patent number: 11215591
    Abstract: A chromatographic data system processing apparatus performs data processing based on plot data measured by a chromatograph. The chromatographic data system processing apparatus includes a virtual curve calculation portion which obtains a virtual curve based on the measured plot data, a tentative feature point acquisition portion which obtains a tentative feature point based on the obtained virtual curve, and an actual plot data feature point extraction portion which extracts an actual plot data feature point corresponding to the tentative feature point from the measured plot data.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: January 4, 2022
    Assignee: Hitachi High-Tech Science Corporation
    Inventors: Masahito Ito, Masato Fukuda
  • Patent number: 11216534
    Abstract: An information processing apparatus includes a data acquisition unit that acquires data including a missing value, a missing rate calculation unit that calculates a missing rate indicating a ratio of missing values included in the data, and a covariance matrix estimation unit that estimates a covariance matrix based on the missing rate. According to the information processing apparatus, since the covariance matrix is estimated based on the missing rate, the estimation accuracy of the covariance matrix can be improved.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: January 4, 2022
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masaaki Takada, Hironori Fujisawa, Takeichiro Nishikawa
  • Patent number: 11210067
    Abstract: A computer processing system having at least one accelerator operably configured to compute modular multiplication with a modulus of special form and having a systolic carry-save architecture configured to implement Montgomery multiplication and reduction and having multiple processing element types composed of Full Adders and AND gates.
    Type: Grant
    Filed: November 27, 2020
    Date of Patent: December 28, 2021
    Assignee: PQSecure Technologies, LLC
    Inventors: Brian Craig Koziel, Rami El Khatib
  • Patent number: 11188302
    Abstract: Top-k is a process by which the largest elements among a set of elements is found. In various implementations, a top-k computation can be executed by a neural network accelerator, where the top-k computation is performed using a process that makes use of the accelerators memory array. A set of numerical values on which to perform top-k can be stored in the memory array. The accelerator can locate the maximum value from among the set of numerical values, and can store the maximum value back into the memory array. The accelerator can next remove the maximum value from the set of numerical values, so that a next largest value can be found. To remove the maximum value, the accelerator can write a value representing negative infinity to the memory array at each location of the maximum value.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: November 30, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Ron Diamant, Randy Renfu Huang, Richard John Heaton
  • Patent number: 11157238
    Abstract: Embodiments described herein are generally directed to an improved vector normalization instruction. An embodiment of a method includes responsive to receipt by a GPU of a single instruction specifying a vector normalization operation to be performed on V vectors: (i) generating V squared length values, N at a time, by a first processing unit, by, for each N sets of inputs, each representing multiple component vectors for N of the vectors, performing N parallel dot product operations on the N sets of inputs. Generating V sets of outputs representing multiple normalized component vectors of the V vectors, N at a time, by a second processing unit, by, for each N squared length values of the V squared length values, performing N parallel operations on the N squared length values, wherein each of the N parallel operations implement a combination of a reciprocal square root function and a vector scaling function.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: October 26, 2021
    Assignee: Intel Corporation
    Inventors: Abhishek Rhisheekesan, Supratim Pal, Shashank Lakshminarayana, Subramaniam Maiyuran
  • Patent number: 10963252
    Abstract: A method to compare first and second source data in a processor in response to a vector maximum with indexing instruction includes specifying first and second source registers containing first and second source data, a destination register storing compared data, and a predicate register. Each of the registers includes a plurality of lanes. The method includes executing the instruction by, for each lane in the first and second source register, comparing a value in the lane of the first source register to a value in the corresponding lane of the second source register to identify a maximum value, storing the maximum value in a corresponding lane of the destination register, asserting a corresponding lane of the predicate register if the maximum value is from the first source register, and de-asserting the corresponding lane of the predicate register if the maximum value is from the second source register.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: March 30, 2021
    Assignee: Texas Instruments Incorporated
    Inventors: Duc Bui, Peter Richard Dent, Timothy D. Anderson
  • Patent number: 10860390
    Abstract: A computing apparatus, including: a hardware computing platform; and logic to operate on the hardware computing platform, configured to: receive a microservice instance registration for a microservice accelerator, wherein the registration includes a microservice that the microservice accelerator is configured to provide, and a microservice connection capability indicating an ability of the microservice instance to communicate directly with other instances of the same or a different microservice; and log the registration in a microservice registration database.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: December 8, 2020
    Assignee: Intel Corporation
    Inventors: Vadim Sukhomlinov, Kshitij A. Doshi
  • Patent number: 10846366
    Abstract: In a general aspect, values of input parameters for a quantum approximate optimization algorithm (QAOA) are selected by a Bayesian optimizer. The QAOA can be configured to solve a combinatorial optimization problem (COP), such as Maximum Cut. A hybrid classical-quantum computing system can be used to execute the QAOA and select the input parameters.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: November 24, 2020
    Assignee: Rigetti & Co, Inc.
    Inventors: Johannes Sebastian Otterbach, Jonathan Ward, Marcus Palmer da Silva, Nicholas C. Rubin
  • Patent number: 10832155
    Abstract: A method of computing a solution to a computational problem using a quantum system comprising a plurality of qubits is provided. The method includes encoding the computational problem into a problem Hamiltonian of the quantum system, wherein the problem Hamiltonian is a single-body Hamiltonian including a plurality of adjustable parameters, and wherein the encoding includes determining, from the computational problem, a problem-encoding configuration for the plurality of adjustable parameters. The method further includes evolving the quantum system from an initial quantum state towards a ground state of a final Hamiltonian of the quantum system, wherein the final Hamiltonian is the sum of the problem Hamiltonian and a short-range Hamiltonian, wherein the plurality of adjustable parameters of the problem Hamiltonian are in the problem-encoding configuration and wherein the short-range Hamiltonian is a d-body Hamiltonian, wherein d is independent of the computational problem.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: November 10, 2020
    Assignee: Parity Quantum Computing GmbH
    Inventors: Wolfgang Lechner, Philipp Hauke, Peter Zoller
  • Patent number: 10671396
    Abstract: A method for operating a processing unit, including a memory and at least one processor core that executes a plurality of program functions of a computer program, includes ascertaining all program instructions that belong to a program function to be executed at a future execution point in time and providing the ascertained program instructions in the memory before the execution point in time.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: June 2, 2020
    Assignee: Robert Bosch GmbH
    Inventors: Jens Gladigau, Dirk Ziegenbein
  • Patent number: 10585679
    Abstract: Processing cores with the ability to suppress operations based on a contribution estimate for those operation for purposes of increasing the overall performance of the core are disclosed. Associated methods that can be conducted by such processing cores are also disclosed. One such method includes generating a reference value for a composite computation. A complete execution of the composite computation generates a precise output and requires execution of a set of component computations. The method also includes generating a component computation approximation. The method also includes evaluating the component computation approximation with the reference value. The method also includes executing a partial execution of the composite computation using the component computation approximation to produce an estimated output.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: March 10, 2020
    Assignee: Tenstorrent Inc.
    Inventors: Ljubisa Bajic, Milos Trajkovic, Ivan Hamer, Syed Gilani
  • Patent number: 10545727
    Abstract: An arithmetic logic unit is disclosed that includes a first logical circuit that generates a first partial sum result from three operands in a first stage of a single clock cycle of a processor; a second circuit that generates a second partial result in the same first stage of the clock cycle of the processor; and an adder that receives the first partial result from the first logical circuit and the second partial result from the second circuit and generates a secondary result during a second stage of the single clock cycle of the processor. The arithmetic logic unit may optionally further include a backend circuit that performs additional arithmetic and logic functions in the same single clock cycle of the processor.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: January 28, 2020
    Assignee: International Business Machines Corporation
    Inventors: Maarten J. Boersma, Niels Fricke
  • Patent number: 10521488
    Abstract: A matrix computation unit includes a systolic array of cells arranged along a first and second dimension, in which the systolic array of cells includes a first multiple of cells, each cell of the first multiple of cells including: a weight register configured to store a weight input; multiple activation registers, each activation register of the multiple activation registers configured to store a corresponding activation input; multiplexer circuitry communicatively coupled to the multiple activation registers and configured to select, from the multiple activation registers, one of the activation inputs as a selected activation input; and multiplication circuitry communicatively coupled to the weight register and to the multiplexer, in which the multiplication circuitry is configured to output a product of the weight input and the selected activation input.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: December 31, 2019
    Assignee: X Development LLC
    Inventors: Jonathan Ross, Charles Henry Leichner, IV
  • Patent number: 10521367
    Abstract: Message exchange techniques for content information communication between a primary device and a companion device are described. Content information may include service guide data. Message exchange techniques may include subscription techniques and request-response techniques. Example message exchange formats may include defined elements. Elements may be defined according an element name, a type, cardinality, a description, and a data type. In one example, an Extensible Markup Language (XML) based schema is defined for content identification information message. In one example, a JavaScript Object Notation (JSON) schema is defined for content identification information message.
    Type: Grant
    Filed: April 22, 2016
    Date of Patent: December 31, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Sachin G. Deshpande, Peter T. Moser
  • Patent number: 10489485
    Abstract: A computing device computes a quantile value for a variable value extracted from an event block object by computing a bin number for the variable value. If the computed bin number is between a before bin number and an after bin number computed for a quantile, the quantile is identified. Frequency data is updated to include the extracted variable value as a key value. A frequency value associated with the key value indicates a number of occurrences of the variable value in previously processed data. A cumulative rank value of the identified quantile is updated. A quantile adjustment value is computed based on a comparison between the variable value and a current quantile value of the identified quantile. An updated quantile value associated with the identified quantile is computed using the updated frequency data, the computed quantile adjustment value, and the updated cumulative rank value of the identified quantile.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: November 26, 2019
    Assignee: SAS INSTITUTE INC.
    Inventors: Xinmin Wu, Tao Wang, Scott Russell Pope
  • Patent number: 10379854
    Abstract: Processor instructions for determining two minimum and two maximum values and associated apparatus and methods. The instructions include various 2MIN instructions for determining the two smallest values among three or four input values and 2MAX instructions for determining the two largest values among three or four input values. The 2MIN instructions employ two operands, with the first operand in some of the variations storing concatenated min1 and min2 values in a first register and a scr2 comparison value or two src2 concatenated src2 values in a second register. Comparators are used to implement hardware logic for determining whether the scr2 value(s) is/are less than each of min1 and min2. Based on the hardware logic, the smallest two values among min1, min2, and src2 (or both src2 values) are stored as concatenated values in the first register. The 2MAX instructions are implemented in a similar manner, except the comparisons are whether the scr2 value(s) is/are greater than each of max1 and max2 values.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: August 13, 2019
    Assignee: Intel Corporation
    Inventors: Vinodh Gopal, James D. Guilford
  • Patent number: 10330802
    Abstract: A method for determining a pair of compliance events is provided. A set of event data collected by a PET detector may be divided into N sub-sets, and each of the N sub-sets of event data may be sorted according to an occurrence time of each event included in the event data, wherein N is an integer greater than or equal to 2. A K stage heapsort may be performed on the sorted N sub-sets of event data according to the occurrence time of each event, so as to sequentially output data of each event in the sorting order, wherein K is an integer greater than or equal to 1. A time compliance determination and a space compliance determination may be performed on the sequentially-outputted event data, and a pair of compliance events may be determined if both the time compliance determination and the space compliance determination are passed.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: June 25, 2019
    Assignee: Shenyang Neusoft Medical Systems Co., Ltd.
    Inventors: Zhuxia Yin, Zhiguo Wang, Guoxu Zhang, Guodong Liang, Long Yang
  • Patent number: 10311128
    Abstract: A computing device computes a quantile value. A maximum value and a minimum value are computed for unsorted variable values to compute an upper bin value and a lower bin value for each bin of a plurality of bins. A frequency counter is computed for each bin by reading the unsorted variable values a second time. A bin number and a cumulative rank value are computed for a quantile. When an estimated memory usage value exceeds a predefined memory size constraint value, a subset of the plurality of bins are split into a plurality of bins, the frequency counter is recomputed for each bin, and the bin number and the cumulative rank value are recomputed. Frequency data is computed using the frequency counters. The quantile value is computed using the frequency data and the cumulative rank value for the quantile and output.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: June 4, 2019
    Assignee: SAS INSTITUTE INC.
    Inventors: Xinmin Wu, Xiangqian Hu, Tao Wang, Xunlei Wu
  • Patent number: 10284224
    Abstract: A system for compressed sensing comprising: a compressive sampling module configured for providing a CS-sampled signal and a signal reconstruction module configured for receiving and allocating a first plurality of measurement windows comprising a number of samples from the CS-sampled signal, calculating a corresponding first plurality of reconstruction windows based on the first plurality of measurement windows and calculating a first version of a reconstructed signal based on the first plurality of reconstruction windows.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: May 7, 2019
    Assignees: IMEC VZW, Katholieke Universiteit Leuven, KU LEUVEN R&D
    Inventor: Venkata Rajesh Pamula
  • Patent number: 10025594
    Abstract: A data processing apparatus includes a plurality of processing units configured to process packets each including data and extended identification information added to the data, the extended identification information including identification information for identifying the data and instruction information indicating one or more processing instructions to the data, each processing unit in the plurality of processing units including: an input/output unit configured to obtain, in the packets, only a packet whose address information indicates said each processing unit in the plurality of processing units, the address information determined in accordance with the extended identification information; and an operation unit configured to execute the processing instruction in the packet obtained by the input/output unit.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: July 17, 2018
    Assignee: Mush-A Co., Ltd.
    Inventor: Mitsuru Mushano
  • Patent number: 9824317
    Abstract: A method includes forming a working mixed integer linear program (MILP) from a given MILP for job allocation to allocate people to jobs at least by choosing a subset of variables from the MILP. Only person/job combinations that are deemed most valuable are chosen for the subset. The working MILP includes the chosen subset of variables but no other variables from the given MILP. The working MILP is solved to determine a solution. Using the solution, a special linear program is formed and solved to determine a price of each constraint relative to the solution. Using the prices, variables that are not in the working MILP are evaluated to determine any variables that can contribute to an improved solution. The variables evaluated as contributing to an improved solution are added to the working MILP. The working MILP with the added variables is solved. Apparatus and program products are also disclosed.
    Type: Grant
    Filed: July 6, 2016
    Date of Patent: November 21, 2017
    Assignee: International Business Machines Corporation
    Inventor: Irvin J. Lustig
  • Patent number: 9778979
    Abstract: An operating method of an error correction decoder includes receiving data, setting initial log-likelihood values of variable nodes, and decoding the received data by updating a log-likelihood value of a selected variable node by use of a minimum value and a minimum candidate value associated with the selected variable node. The minimum value indicates a minimum value of absolute values of log-likelihood values of first variable nodes sharing a check node with the selected variable node and including the selected variable node. The minimum candidate value indicates one from among absolute values of log-likelihood values of second variable nodes that has the smallest value greater than the minimum value. The second variable nodes are selected later than one from among the first variable nodes corresponding to the minimum value.
    Type: Grant
    Filed: July 15, 2015
    Date of Patent: October 3, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Min Shin, Myungkyu Lee, Beom Kyu Shin, Kijun Lee
  • Patent number: 9697176
    Abstract: A method of multiplication of a sparse matrix and a vector to obtain a new vector and a system for implementing the method are claimed. Embodiments of the method are intended to optimize the performance of sparse matrix-vector multiplication in highly parallel processors, such as GPUs. The sparse matrix is stored in compressed sparse row (CSR) format.
    Type: Grant
    Filed: November 14, 2014
    Date of Patent: July 4, 2017
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Mayank Daga, Joseph L. Greathouse
  • Patent number: 9678753
    Abstract: Method, apparatus, and program means for nonlinear filtering and deblocking applications utilizing SIMD sign and absolute value operations. The method of one embodiment comprises receiving first data for a first block and second data for a second block. The first data and said second data are comprised of a plurality of rows and columns of pixel data. A block boundary between the first block and the second block is characterized. A correction factor for a deblocking algorithm is calculated with a first instruction for a sign operation that multiplies and with a second instruction for an absolute value operation. Data for pixels located along said block boundary between the first and second block are corrected.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: June 13, 2017
    Assignee: Intel Corporation
    Inventors: William W. Macy, Jr., Huy V. Nguyen
  • Patent number: 9678715
    Abstract: An apparatus 8 for performing a selectable one of multi-element comparison and multi-element addition is formed from a carry propagate adders stage 12 supplied with four non-final intermediate operands formed from the input vector, a non-final limit value selecting stage 14, which when performing a multi-element comparison serves to select, in dependence upon at least carry save values generated by the carry propagate adder, limit values that are of a larger or a smaller value of a pair of elements. A final intermediate operand forming stage 16 forms final intermediate operands from two non-final intermediate sum values from the carry propagate adders stage 12 and supplies these to a final output adder stage 18 which forms a sum of these two final intermediate operands to generate an output operand which can be either one or more candidates for limit values that will be a maximum or minimum value, or a sum value, or partial sum values in the case of a multi-element addition.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: June 13, 2017
    Assignee: ARM Limited
    Inventors: Neil Burgess, David Raymond Lutz
  • Patent number: 9450602
    Abstract: A query of time series data stored in a database is received that specifies at least one value. The database includes (i) an index table specifying groups of segments of compressed time series data with corresponding ranges each having a lowest value and a highest value, and (ii) a segments table specifying individual segments of compressed time series data. Thereafter, using the index table, at least one group for which the specified at least one value falls within the corresponding range is identified. The segments table is then queried for the segments corresponding to the identified at least one group to generate a new segments table specifying at least one segment. Next, the at least one segment specified by the new segments table is decompressed. Data responsive to the query within the decompressed at least one segment is then identified using the specified at least one value.
    Type: Grant
    Filed: January 2, 2014
    Date of Patent: September 20, 2016
    Assignee: SAP SE
    Inventors: Frank Eichinger, Dennis Kurfiss
  • Patent number: 9449675
    Abstract: The present disclosure includes apparatuses and methods related to identifying an extremum value using sensing circuitry. An example method can include determining a location of an extremum value of a set of N data values stored as vectors in a memory array. A number of operations to determine the location of the extremum value can remain constant with respect to a value of N. The method can include determining the value of the extremum by reading memory cells coupled to the sense line based on the determined location of the extremum value.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: September 20, 2016
    Assignee: Micron Technology, Inc.
    Inventor: Kyle B. Wheeler
  • Patent number: 9391621
    Abstract: Field programmable gate arrays (FPGA) contain, in addition to random logic, also other components, such as processing units, multiply-accumulate (MAC) units, analog circuits, and other elements, configurable with respect of the random logic, to enhance the capabilities of the FPGA. A circuit for a filed configurable MAC unit is provided to allow various configurations of ADD, SUBTRACT, MULTIPLY and SHIFT functions. Optionally, registered input and registered output support a multi-cycle path. A configuration of a constant facilitates the configuration of the circuit to perform infinite impulse response (IIR) and finite impulse response (FIR) functions in hardware.
    Type: Grant
    Filed: December 10, 2013
    Date of Patent: July 12, 2016
    Assignee: Silicon Mobility
    Inventors: Loic Vezier, Farid Tahiri
  • Patent number: 9165023
    Abstract: An integrated circuit device comprises at least one digital signal processor, DSP, module, the at least one DSP module comprising a plurality of data registers and at least one data execution unit, DEU, module arranged to execute operations on data stored within the data registers. The at least one DEU module is arranged to, in response to receiving an extreme value index instruction, compare a previous extreme value located within a first data register set of the DSP module with at least one input vector data value located within a second data register set of the DSP module, and determine an extreme value thereof. The at least one DEU module is further arranged to, if the determined extreme value comprises an input vector data value located within the second data register set, store the determined extreme value in the first data register set, determine an index value for the determined extreme value, and store the determined index value in the first data register set.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: October 20, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Ilia Moskovich, Aviram Amir, Itzhak Barak, Eliezer Ben Zeev
  • Patent number: 9098121
    Abstract: A comparator (231) for determining a peak number, representing a maximum or minimum of a set of numbers, includes a multi-element comparator (232) for comparing different pages of the set of numbers in a page comparison mode to output a candidate set of winning numbers, and for automatically switching to a leaf/tree search of the candidate set of winning numbers in an element comparison mode. Operating in parallel with the multi-element comparator (232), an index generation unit (233) processes flag/sign bits from the multi-element comparator in conjunction with state machine control logic (230) to keep track of the index/indices for the peak value. Upon completion of final stage, the index generation unit returns the absolute index (235) of the peak value.
    Type: Grant
    Filed: January 22, 2013
    Date of Patent: August 4, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jayakrishnan C. Mundarath, Leo G. Dehner, Eric J. Jackowski
  • Patent number: 8954483
    Abstract: Provided are an arithmetic circuit and an arithmetic apparatus capable of performing comparison involving conditional branch of three or more values at high speed. The arithmetic circuit includes a plurality of computing units, a plurality of selection circuits and a decision unit. The plurality of computing units perform arithmetic computations on input data and output flag information generated based on a result of the computations. The plurality of selection circuits select any one of the data input to the plurality of computing units. The decision unit receives the flag information from the plurality of computing units and controls select operation of each of the plurality of selection circuits.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: February 10, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Yuki Kobayashi
  • Patent number: 8943115
    Abstract: A group of numbers from which the smallest and second-smallest are to be selected are compared in a cascaded tree. Each comparison stage will select the smallest number from two numbers output by the previous stage, into which four numbers are input. The second-smallest number is one of the other three inputs to the previous stage and, as before, all bits of the second-smallest number will not be known until the smallest number is determined. However, because at each stage of the determination, the next stage is reached because the bit values being examined are the same, those bit values of the second-smallest number (and indeed of the smallest number) are known ahead of the final determination of the smallest number. Accordingly, one can begin to output bits of the second-smallest number (as well as of the smallest number) even before that final determination.
    Type: Grant
    Filed: July 10, 2012
    Date of Patent: January 27, 2015
    Assignee: Marvell International Ltd.
    Inventor: Engling Yeo
  • Patent number: 8935308
    Abstract: A method recovers an uncorrupted low-rank matrix, noise in corrupted data and a subspace from the data in a form of a high-dimensional matrix. An objective function minimizes the noise to solve for the low-rank matrix and the subspace without estimating the rank of the low-rank matrix. The method uses group sparsity and the subspace is orthogonal. Random subsampling of the data can recover subspace bases and their coefficients from a much smaller matrix to improve performance. Convergence efficiency can also be improved by applying an augmented Lagrange multiplier, and an alternating stepwise coordinate descent. The Lagrange function is solved by an alternating direction method.
    Type: Grant
    Filed: January 20, 2012
    Date of Patent: January 13, 2015
    Assignee: Mitsubishi Electric Research Laboratories, Inc.
    Inventors: Fatih Porikli, Xianbiao Shu
  • Publication number: 20150006598
    Abstract: Certain aspects of the present disclosure relate to a method for quantizing signals and reconstructing signals, and/or encoding or decoding data for storage or transmission. Points of a signal may be determined as local extrema or points where an absolute rise of the signal is greater than a threshold. The tread and value of the points may be quantized, and certain of the quantizations may be discarded before the quantizations are transmitted. After being received, the signal may be reconstructed from the quantizations using an iterative process.
    Type: Application
    Filed: September 16, 2014
    Publication date: January 1, 2015
    Inventors: Harinath Garudadri, Pawan Kumar Baheti, Somdeb Majumdar
  • Publication number: 20140365545
    Abstract: Multi-way partitioning is dramatically improved based on “weakest-link” optimality. The set of numbers to be partitioned is subjected to pairwise decomposition with a first partition having a candidate subset (P1={S1}), and a lower cost bound cmin is set equal to a maximum cost of this subset. A recursive call is then invoked to resolve the subproblem of the second partition (P2={S2, S3, . . . , Sk}). If each second candidate subset in the second partition has a cost which is less than or equal to the lower cost bound, then the first partition is returned with the second partition as an optimal solution regardless of whether the second partition is an optimal decomposition. Additional efficiency may be achieved by excluding any subset having a cost which is greater than or equal to the best cost so far. Dominated and symmetric solutions can also be excluded.
    Type: Application
    Filed: December 6, 2013
    Publication date: December 11, 2014
    Applicant: International Business Machines Corporation
    Inventor: Michael D. Moffitt
  • Publication number: 20140365544
    Abstract: Multi-way partitioning is dramatically improved based on “weakest-link” optimality. The set of numbers to be partitioned is subjected to pairwise decomposition with a first partition having a candidate subset (P1={S1}), and a lower cost bound cmin is set equal to a maximum cost of this subset. A recursive call is then invoked to resolve the subproblem of the second partition (P2={S2, S3, . . . , Sk}). If each second candidate subset in the second partition has a cost which is less than or equal to the lower cost bound, then the first partition is returned with the second partition as an optimal solution regardless of whether the second partition is an optimal decomposition. Additional efficiency may be achieved by excluding any subset having a cost which is greater than or equal to the best cost so far. Dominated and symmetric solutions can also be excluded.
    Type: Application
    Filed: June 11, 2013
    Publication date: December 11, 2014
    Inventor: Michael D. Moffitt
  • Publication number: 20140351302
    Abstract: A machine-implemented method for computerized digital signal processing including obtaining a digital signal from data storage or from conversion of an analog signal, and determining, from the digital signal, one or more measuring matrices. Each measuring matrix has a plurality of cells, and each cell has an amplitude corresponding to the signal energy in a frequency bin for a time slice. Cells in each measuring matrix having maximum amplitudes along a time slice and/or frequency bin are identified as maximum cells. Maxima that coincide in time and frequency are identified and a correlated maxima matrix, called a “Precision Measuring Matrix” is constructed showing the coinciding maxima and the adjacent marked maxima are linked into partial chains.
    Type: Application
    Filed: December 20, 2013
    Publication date: November 27, 2014
    Applicant: Paul Reed Smith Guitars Limited Partnership
    Inventors: Paul Reed SMITH, Jack W. Smith, Frederick M. Slay
  • Patent number: 8898210
    Abstract: For determining a minimum/maximum of a plurality of binary values a bit position in the plurality of binary values is determined subsequent to which all bit values are the same. From the plurality of binary values those binary values are selected the bit values of which at the bit position determined in the preceding step and all subsequent positions, if any, has a predetermined value. The preceding steps are then repeated until only one binary value remains which is provided as the minimum or maximum.
    Type: Grant
    Filed: August 5, 2008
    Date of Patent: November 25, 2014
    Assignee: Advantest (Singapore) Pte Ltd
    Inventor: Michael Mueller
  • Publication number: 20140344320
    Abstract: Solving a multidimensional multicriteria optimization problem is difficult because the correlations and dependencies between solutions, target functions, and variation variables can be detected only with difficulty. In order to facilitate this, it is proposed that a model space (1) and a variation space (2) are displayed simultaneously and in an interactively linked fashion.
    Type: Application
    Filed: November 8, 2012
    Publication date: November 20, 2014
    Applicant: AVL LIST GMBH
    Inventors: Klemens Wallner, Alejandra Garcia, Adnand Dragoti
  • Publication number: 20140297703
    Abstract: A mechanism for reconstructing a signal (e.g., an image) based on a vector s, which includes measurements of the signal. The measurements have been acquired using at least a portion of a measurement vector set represented by a matrix H. Each of the measurements corresponds to a respective row of the matrix H. (For example, each of the measurements may correspond to an inner product between the signal and a respective row of the matrix product HD, wherein D is a generalized permutation matrix.) A total-variation primal-dual hybrid gradient (TV-PDHG) algorithm is executed based on data including the matrix H and the vector s, to determine an estimate for the signal. The TV-PDHG algorithm is implemented in fixed-point arithmetic.
    Type: Application
    Filed: December 20, 2013
    Publication date: October 2, 2014
    Applicant: InView Technology Corporation
    Inventors: Thomas A. Goldstein, Matthew A. Herman
  • Patent number: 8849881
    Abstract: A logic circuit computes various modal interval arithmetic values using a plurality of arithmetic function units. A multiplexer gates the desired arithmetic values to a storage register.
    Type: Grant
    Filed: May 24, 2011
    Date of Patent: September 30, 2014
    Assignee: Sunfish Studio, LLC
    Inventor: Nathan T. Hayes
  • Publication number: 20140258352
    Abstract: A method of identifying a set of parameters representative of a data set is provided. An eigen decomposition of a covariance matrix is calculated to form a decomposed matrix and an eigenvalue vector. The covariance matrix is calculated for a matrix of data including a plurality of data values for each of a plurality of parameters. The decomposed matrix includes a number of eigenvectors equal to a number of the plurality of parameters with each eigenvector including a coefficient for each parameter. The eigenvalue vector includes an eigenvalue defined for each eigenvector. A first matrix is created by rank ordering the coefficient within each parameter of the plurality of parameters for each of the plurality of parameters. A score is determined for each parameter using the created first matrix and the eigenvalue vector. A parameter set is identified based on the determined score for each parameter.
    Type: Application
    Filed: July 3, 2013
    Publication date: September 11, 2014
    Inventors: Brian Oneal Miles, Dan Kelly
  • Patent number: 8793294
    Abstract: A floating point max/min circuit for determining the maximum or minimum of two floating point operands includes a first analysis circuit configured to determine a format of a first floating point operand of the two floating point operands based upon floating point status information encoded within the first floating point operand, a second analysis circuit configured to determine a format of a second floating point operand of the two floating point operands based upon floating point status information encoded within the second floating point operand, a decision circuit, coupled to the first analysis circuit and to the second analysis circuit and responding to a function control signal that indicates the threshold condition is one of a maximum of the two floating point operands and a minimum of the two floating point operands, for generating at least one assembly control signal based on the format of a first floating point operand, the format of a second floating point operand, and the function control signal,
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: July 29, 2014
    Assignee: Oracle America, Inc.
    Inventor: Guy L. Steele, Jr.
  • Publication number: 20140207837
    Abstract: A calculating device selects an action and a corresponding state; acquires an evaluation value by evaluating the combination of the selected action and the selected state; identifies for each selected action, a lowest evaluation value among acquired evaluation values; determines the lowest evaluation value among evaluation values of all the states selected for each action as a minimax candidate, and determines, as a minimax, an evaluation value that is highest among the lowest evaluation values corresponding to the actions; each time an evaluation value is acquired for a combination of a state and an action after the minimax candidate is determined, compares the acquired evaluation value and the minimax candidate, and terminates selection of a state corresponding to the action when the evaluation value is lower than the minimax candidate and selects an unselected action from the action set; and outputs an action corresponding to the determined minimax.
    Type: Application
    Filed: March 19, 2014
    Publication date: July 24, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Tsuyoshi Taniguchi, Yoshio Nakao
  • Publication number: 20140207836
    Abstract: A comparator (231) for determining a peak number, representing a maximum or minimum of a set of numbers, includes a multi-element comparator (232) for comparing different pages of the set of numbers in a page comparison mode to output a candidate set of winning numbers, and for automatically switching to a leaf/tree search of the candidate set of winning numbers in an element comparison mode. Operating in parallel with the multi-element comparator (232), an index generation unit (233) processes flag/sign bits from the multi-element comparator in conjunction with state machine control logic (230) to keep track of the index/indices for the peak value. Upon completion of final stage, the index generation unit returns the absolute index (235) of the peak value.
    Type: Application
    Filed: January 22, 2013
    Publication date: July 24, 2014
    Inventors: Jayakrishnan C. Mundarath, Leo G. Dehner, Eric J. Jackowski
  • Publication number: 20140136582
    Abstract: A method for scaling a plurality of data values includes storing a first subset of data values of the plurality of data values into a first vector register, determining a maximum data value of the first subset of data values, and storing the greater of the maximum data value and a value stored in a scalar register to the scalar register. Each data value of the subset of data values is stored in a different element of the first vector register. The method further includes determining an adjustment factor based on the value stored in the scalar register and adjusting each data value of the plurality of data values by the adjustment factor.
    Type: Application
    Filed: November 12, 2012
    Publication date: May 15, 2014
    Applicant: Futurewei Technologies, Inc.
    Inventors: Weizhong Chen, Yuanpei Jiao, Tong Sun
  • Publication number: 20140122551
    Abstract: An arithmetic logic unit (ALU) including a first routing grid connected to multiple data lanes to drive first data to the data lanes. A second routing grid is connected to the data lanes to drive second data to the data lanes. Each of the data lanes include multiple, e.g. N, functional units with first inputs from the first routing grid and second inputs from the second routing grid. The functional units compute pairwise a function of the respective first data on the respective first inputs and the respective second data on the respective second inputs. Each of the data lanes include a reduction unit with inputs adapted to receive K? bits per word from the functional units. The reduction unit is configured to perform a reduction operation configured to output an output result having a reduced number J? bits per word, wherein J? is less than N multiplied by K?.
    Type: Application
    Filed: October 31, 2012
    Publication date: May 1, 2014
    Applicant: MOBILEYE TECHNOLOGIES LIMITED
    Inventors: Gil Israel Dogon, Yosi Arbeli, Yosef Kreinin
  • Patent number: 8682946
    Abstract: A method for determining a peak value of a histogram or a sequence of sampled data is disclosed. The method may include fitting a curve to the sequence of data, the curve being modeled based on an orthonormal expansion; obtaining a differential curve, the differential curve describing changes in slope of the curve fitted to the sequence of data; finding at least one root for the differential curve; for each of the at least one root for the differential curve, calculating a corresponding value on the curve fitted to the sequence of data; and determining the peak value of the sequence of data based on a maximum value among the corresponding value calculated for each of the at least one root.
    Type: Grant
    Filed: May 26, 2011
    Date of Patent: March 25, 2014
    Assignee: KLA-Tencor Corporation
    Inventors: Harish P. Hiriyannaiah, Donald D. Walker
  • Patent number: 8666688
    Abstract: A system and a method is provided for the detection and capture, and in particular for an ultra high speed detection and capture, of transients in input voltages by an intelligent electronic device. The system and method detects transients for input voltages in either phase to phase or phase to neutral measurements and permits a user to set threshold levels for detecting transients in input voltages. In an embodiment, the system and method further provides a field programmable gate array as a controller for managing transient detection. The field programmable gate array includes a state machine for determining the state of the sampled signal with respect to a threshold level at a specified waveform sample period.
    Type: Grant
    Filed: March 13, 2008
    Date of Patent: March 4, 2014
    Assignee: Electro Industries/Gauge Tech
    Inventors: Joseph Spanier, Hai Zhu, Wei Wang
  • Publication number: 20140059095
    Abstract: In various example embodiments, systems and methods for estimating the mean of a dataset having a fat tail. Data sets may be partitioned into components, a “torso” component and a “tail” component. For the “tail” component of the data set a more efficient estimator can be obtained (versus the traditionally calculated mean) by using the tail data to estimate parameters for a specific distribution and then deriving the mean from the estimated parameters. The estimated mean from the torso and the estimated mean from the tail may then be combined to obtain the estimated mean for the full data. This can be applied to gross merchandise bought (GMB) by various samples of visitors and apply the experience that was provided to the sample with the highest GMB to all visitors to increase gross revenue.
    Type: Application
    Filed: August 21, 2012
    Publication date: February 27, 2014
    Applicant: eBay Inc.
    Inventors: Greg D. Adams, Timothy W. Amato, Kumar R. Dandapani, Yiping Dou, Gurudev Karanth, Anthony Douglas Thrall, Mithun Yarlagadda