Abstract: A machine-implemented method for computerized digital signal processing including obtaining a digital signal from data storage or from conversion of an analog signal, and determining, from the digital signal, one or more measuring matrices. Each measuring matrix has a plurality of cells, and each cell has an amplitude corresponding to the signal energy in a frequency bin for a time slice. Cells in each measuring matrix having maximum amplitudes along a time slice and/or frequency bin are identified as maximum cells. Maxima that coincide in time and frequency are identified and a correlated maxima matrix, called a “Precision Measuring Matrix” is constructed showing the coinciding maxima and the adjacent marked maxima are linked into partial chains.

Abstract: Supervised kernel nonnegative matrix factorization generates a descriptive part-based representation of data, based on the concept of kernel nonnegative matrix factorization (kernel NMF) aided by the discriminative concept of graph embedding. An iterative procedure that optimizes suggested formulation based on Pareto optimization is presented. The present formulation removes any dependence on combined optimization schemes.

Abstract: A method and system of converting an ASCII timing report to a timing waveform to evaluate the behavior of an electrical signal in an ASIC is described. In the method, a timing report is read into memory, and selected timing points are extracted therefrom. A timing waveform is generated from the extracted timing points for display and review by a designer to evaluate whether a given external port or internal pin of the ASIC meets required timing specifications. To create a combined timing waveform, max and min timing waveforms are generated from selected timing points extracted from max and min timing reports. The x-y coordinates of the min timing waveform are shifted by an adjustment factor so as to align with x-y coordinates the max timing waveform, then a combined timing waveform is generated from the x-y coordinates of both the max and min timing waveforms.

Abstract: Certain aspects of the present disclosure relate to a method for quantizing signals and reconstructing signals, and/or encoding or decoding data for storage or transmission. Points of a signal may be determined as local extrema or points where an absolute rise of the signal is greater than a threshold. The tread and value of the points may be quantized, and certain of the quantizations may be discarded before the quantizations are transmitted. After being received, the signal may be reconstructed from the quantizations using an iterative process.

Abstract: A fast batch verification method and apparatus are provided. In the method of batch-verifying a plurality of exponentiations, (a) a predetermined bit value t is set to an integer equal to or greater than 1; (b) a maximum Hamming weight k is set to an integer equal to or greater than 0 and less than or equal than the predetermined bit value t; (c) n verification exponents si are randomly selected from a set of verification exponents S (n is an integer greater than 1, i is an integer such that 1?i?n), where the set of verification exponents S include elements whose bit values are less than or equal to the predetermined bit value t and to which a Hamming weight less than or equal to the maximum Hamming weight k is allocated; (d) a value of verification result is computed by a predetermined verification formula; and (e) the verification of the signatures is determined to be passed when the value of verification result satisfies a pre-determined pass condition.

Abstract: An optimization system and method includes determining a best gradient as a sparse direction in a function having a plurality of parameters. The sparse direction includes a direction that maximizes change of the function. This maximum change of the function is determined by performing an optimization process that gives maximum growth subject to a sparsity regularized constraint. An extended Baum Welch (EBW) method can be used to identify the sparse direction. A best step size is determined along the sparse direction by finding magnitudes of entries of direction that maximizes the function restricted to the sparse direction. A solution is recursively refined for the function optimization using a processor and storage media.

Abstract: A circuit and design structure for a streaming digital data filter embodied in a machine readable medium, the design structure including: a data processing unit and a pointer processing unit, the data processing unit and the pointer unit connected to a control logic; the pointer processing unit consisting of n serially connected pointer processing stages from a first to a last pointer processing stage, each pointer processing stage except for the first and last processing stages of the pointer processing unit including a pointer register and a multiplexer, wherein n is a positive integer greater than 2; the data processing unit consisting of n serially connected data processing stages from a first data processing stage to a last data processing stage, each data processing stage including a multiplexer, a data register and a comparator; and one or more filter output stages connected to the data processing unit.

Abstract: A smoothing apparatus for peak windowing includes an operator for generating a first input signal for smoothing using an input signal for peak windowing and a predetermined clipping threshold level. The apparatus also includes a subtractor for subtracting a feedback signal from the first input signal, and a maximum operator for generating a second input signal. The apparatus also includes a feedback path for generating a feedback signal for a next smoothed input signal by multiplying samples of the second input signal by window coefficients in a first window coefficient combination and a predetermined gain and summing up the multiplication results. The apparatus further includes a convolutional operator for generating a smoothed signal by multiplying samples of the second input signal by window coefficients in a second window coefficient combination for low pass filtering and summing up the multiplication results.

Abstract: A Montgomery multiplication device calculates a Montgomery product of an operand X and an operand Y with respect to a modulus M and includes a plurality of processing elements. In a first clock cycle, two intermediate partial sums are created by obtaining an input of length w?1 from a preceding processing element as w?1 least significant bits. The most significant bit is configured as either zero or one. Then, two partial sums are calculated using a word of the operand Y, a word of the modulus M, a bit of the operand X, and the two intermediate partial sums. In a second clock cycle, a selection bit is obtained and one of the two partial sums is selected based on the value of the selection bit. Then, the selected partial sum is used for calculation of a word of the Montgomery product.

Abstract: A logic circuit computes various modal interval arithmetic values using a plurality of arithmetic function units. A multiplexer gates the desired arithmetic values to a storage register.

Abstract: A microcontroller-based electronic device and its operating methods are operable to learn a critical voltage value for a microprocessor control unit residing in the microcontroller-based electronic device. The microprocessor control unit receives power from a battery. An exemplary embodiment detects an operating voltage provided to the microprocessor control unit by a supplemental power reservoir after removal of the battery, stores information corresponding to a value of the operating voltage in a nonvolatile memory, repeats the detecting and the saving information as the operating voltage decays in response to a discharge of the supplemental power reservoir, and determines the actual minimum operating voltage for the microprocessor control unit based on a last one of the stored information corresponding to the value of the operating voltage. A learned critical voltage value is based upon the defined actual minimum operating voltage.

Abstract: For determining a minimum/maximum of a plurality of binary values a bit position in the plurality of binary values is determined subsequent to which all bit values are the same. From the plurality of binary values those binary values are selected the bit values of which at the bit position determined in the preceding step and all subsequent positions, if any, has a predetermined value. The preceding steps are then repeated until only one binary value remains which is provided as the minimum or maximum.

Abstract: There are provided a computation method for scalar multiplication or exponentiation and a scalar multiplication program or an exponentiation program which can compute at high speed. In the computation method for scalar multiplication and the scalar multiplication program for computing scalar multiplication by n of a rational point Q in G with respect to a non-negative integer n using an electronic computer, since ?q(Q)=[q]Q=[t?1]Q holds true with respect to the rational point Q in G, (t?1)-adic expansion of a scalar n is performed and a Frobenius endomorphism ?q with respect to a rational point is used in place of t?1.

Abstract: An audio fingerprint is generated by transforming an audio sample of a recording to a time-frequency domain and storing each time-frequency pair in a matrix array, detecting a plurality of local maxima for a predetermined number of time slices, selecting a predetermined number of largest-magnitude maxima from the plurality of local maxima detected by said detecting, and generating one or more hash values corresponding to the predetermined number of largest-magnitude maxima.

Abstract: A method and structure for a computerized method for providing an optimization solution, includes, for a process, wherein is defined a linear functional form y=f(X,c), where X comprises a set of independent variables X={x1, . . . xn}, c includes a set of functional parameters c={c1, . . . cn}, and y comprises a dependent variable, where the independent variables set X is partitioned into two subsets, X1 and X2, receiving data for the process and minimizing y with respect to X1. Dependent variable y is maximized with respect to X2, subject to a set of constraints. The maximizing y includes a global optimum for the process.

Abstract: A first systolic array receives an input set of time division multiplexed matrices from a plurality of channel matrices. In a first mode, the first systolic array performs triangularization on the input matrices, producing a first set of matrices, and in a second mode performs back-substitution on the first set, producing a second set of matrices. In a first mode, a second systolic array performs left multiplication on the second set of matrices with the input set of matrices, producing a third set of matrices. In a second mode, the second systolic array performs cross diagonal transposition on the third set of matrices, producing a fourth set of matrices, and performs right multiplication on the second set of matrices with the fourth set of matrices. The first systolic array switches from the first mode to the second mode after the triangularization, and the second systolic array switches from the first mode to the second mode after the left multiplication.

Abstract: A method for evaluating a received signal varying over an interval includes: (a) obtaining a data sample and a sample time; (b) determining whether the sample exceeds a previous exceeded extremum of the signal; (c) if the sample does not exceed an exceeded extremum, storing the sample; (d) if the sample exceeds the an exceeded extremum, in no particular order: (1) extracting and storing cycle information involving the exceeded extremum; and (2) replacing an earliest exceeded extremum with the sample; (e) outputting first selected data from a storage unit; (f) determining whether the interval has completed; (g) if the interval has not completed, repeating steps (a) through (f); (h) if the interval has completed, checking whether an output buffer is empty; (i) if the buffer is not empty, outputting second selected data from the buffer; j) if the buffer is empty, terminating the method.

Abstract: A floating point multiplier includes a data path in which a plurality of partial products are calculated and then reduced to a first partial product and a second partial product. Shift amount determining circuitry 100 analyses the exponents of the input operands A and B as well as counting the leading zeros in the fractional portions of these operands to determine an amount of left shift or right shift to be applied by shifting circuitry 200, 202 within the multiplier data path. This shift amount is applied so as to align the partial products so that when they are added they will produce the result C without requiring this to be further shifted. Furthermore, shifting the partial products to the correct alignment in this way in advance of adding these partial products permits injection rounding combined with the adding of the partial products to be employed for cases including subnormal values.

Abstract: A system which uses common adder circuitry to perform either one of a horizontal minimum instruction and a sum of absolute differences instruction including multiple adders, a sum circuit, a compare circuit, and a routing circuit. The input operands include multiple digital values which are delivered by the routing circuit to the adders depending upon which instruction is indicated. Each adder determines a difference between a pair of digital values. The differences are grouped and summed together by the sum circuit for the sum of absolute differences instruction. The adders are paired together for the horizontal minimum instruction, in which each pair provides carry and propagate outputs. The upper portions of a pair of digital values are compared by the upper adder and the lower portions are compared by the lower adder, and the carry and propagate outputs are collectively used to determine the minimum value.

Abstract: A method and apparatus for compressing signal samples uses block floating point representations where the number of bits per mantissa is determined by the maximum magnitude sample in the group. The compressor defines groups of signal samples having a fixed number of samples per group. The maximum magnitude sample in the group determines an exponent value corresponding to the number of bits for representing the maximum sample value. The exponent values are encoded to form exponent tokens. Exponent differences between consecutive exponent values may be encoded individually or jointly. The samples in the group are mapped to corresponding mantissas, each mantissa having a number of bits based on the exponent value. Removing LSBs depending on the exponent value produces mantissas having fewer bits. Feedback control monitors the compressed bit rate and/or a quality metric. This abstract does not limit the scope of the invention as described in the claims.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, some embodiments of the present invention provide data processing circuits that include both a main data processing circuit and an adaptive setting determination circuit. The main data processing circuit receives a series of data samples and includes: an equalizer circuit and a data detector circuit. The equalizer circuit receives the series of data samples and provides an equalized output. The equalizer circuit is controlled at least in part by a coefficient. The data detector circuit receives the equalizer output and provides a main data output based at least in part on a target. The adaptive setting determination circuit receives the series of data samples and the main data output, and operates in parallel with the main data processing circuit to adaptively determine the coefficient and the target.

Abstract: A comparator circuit is disclosed that determines whether a first binary value is greater than, equal to, and/or less than a second binary value without employing binary adder circuits, and therefore is simpler, occupies less circuit area, and consumes less power than conventional comparator circuits having binary adders. For some embodiments, the comparator circuit is capable of performing full comparison operations on two or more arbitrary binary values. The comparator circuit can be implemented in TCAM devices to perform regular expression search operations.

Abstract: Quantum annealing may include applying and gradually removing disorder terms to qubits of a quantum processor, for example superconducting flux qubits of a superconducting quantum processor. A problem Hamiltonian may be established by applying control signals to the qubits, an evolution Hamiltonian established by applying disorder terms, and annealing by gradually removing the disorder terms. Change in persistent current in the qubits may be compensated. Multipliers may mediate coupling between various qubits and a global signal line, for example by applying respective scaling factors. Two global signal lines may be arranged in an interdigitated pattern to couple to respective qubits of a communicatively coupled pair of qubits. Pairs of qubits may be communicatively isolated and used to measure a response of one another to defined signals.

Abstract: The problem of aligning multiple liquid chromatography mass spectrometry (LC-MS) runs to a common reference time frame is solved to facilitate comparison among LC-MS runs. The alignment of multiple LCMS can be achieved by solving a sparse system of linear equations to optimally stretch or compress local retention times for maximal similarity among the multiple runs. The multiple LCMS runs can be aligned simultaneously, thereby providing the advantage of efficient use of data by employing a sparse solver. A method of quality control in retention time alignment is also provided.

Abstract: A numeric decision device for determining a numeric of a specific order in a plurality of numerics includes a plurality of reception ends, a plurality of multiplexer modules each for outputting a numeric received by a reception end or a default value, a comparison module for comparing output signals of the plurality of multiplexer modules to generate a plurality of comparison results and for determining an extreme value, a decoding module for generating a plurality of decoding results according to the plurality of comparison result, a driving module for controlling the plurality of multiplexer modules, the comparison module and the decoding module to operate a default time corresponding to the specific order, and an output unit for outputting the extreme value after the comparison module operates for the default time to determine the numeric of the specific order.

Abstract: A data processing apparatus includes a first correlation operation unit which performs a mutual correlation operation of a first input series and a second input series, a threshold value operation unit which calculates a threshold value based on the first input series, a first comparison unit which compares a first mutual correlation value with the threshold value, a search window setting unit which sets a search window for detecting the second input series to the first input series on the basis of the comparison result, a hard decision unit which performs binarization of the first input series, a second correlation operation unit which performs a mutual correlation operation of a first input hard decision value, and a detection position determining unit which searches for a maximum value of the mutual correlation value within the search window and determines the detection time of the maximum value.

Abstract: A method for determining a price of a contract for booking advertising space in a networked environment includes receiving, via a web server, a request to book a number of impressions from available impression inventory, where each impression corresponds to the delivery of an advertisement to a browser. The method also includes assembling user samples that represent a total amount of impression inventory, where each user sample represents a number of internet users, calculating a value associated with each piece of remaining impression inventory of the total impression inventory, and evaluating the value of all remaining impression inventory before and after allocation to a contract by maximizing and equation subject to a set of constraints. The base price for the contract corresponds to the difference between the value of the inventory before and after allocation.

Abstract: A method and apparatus for spatio-temporal compressive sensing, which allows accurate reconstruction of missing values in any digital information represented in matrix or tensor form, is disclosed. The method of embodiments comprises three main components: (i) a method for finding sparse, low-rank approximations of the data of interest that account for spatial and temporal properties of the data, (ii) a method for finding a refined approximation that better satisfies the measurement constraints while staying close to the low-rank approximations obtained by SRMF, and (iii) a method for combining global and local interpolation. The approach of embodiments also provides methods to perform common data analysis tasks, such as tomography, prediction, and anomaly detection, in a unified fashion.

Abstract: Non-negative matrix factorization, NMF, is combined with identification of a maximum margin classifier by minimizing a cost function that contains a generative component and the discriminative component. The relative weighting between the generative component and the discriminative component are adjusting during subsequent iterations such that initially, when confidence is low, the generative model is favored. But as the iterations proceed, confidence increases and the weight of the discriminative component is steadily increased until it is of equal weight as the generative model. Preferably, the cost function to be minimized is: min F , G ? 0 ? ? X - FG ? 2 + ? ? ( ? w ? 2 + C ? ? i = 1 n ? L ? ( y i , w · g i + b ) ) .

Abstract: A system and method for solving a decision problem having Boolean combinations of linear and non-linear operations includes translating the non-linear real operations using a COordinate Rotation DIgital Computer (CORDIC) method programmed on a computer device into linear operations maintaining a given accuracy. Linear and translated linear operations are combined into a formula. Satisfiablity of the formula is solved using a decision procedure for Boolean combinations of linear operations over integers and reals.

Abstract: A solver for a constraint satisfaction problem includes a plurality of variables and a plurality of constraints. A floating point variable has a domain and is assigned a value by first determining if a predetermined value can be assigned to the floating point variable if the predetermined value is in the domain. If not, the solver determines if a bound of the domain can be assigned to the floating point variable. If the predetermined value can not be assigned to the floating point variable and the bound of the domain can not be assigned to the floating point variable, the solver assigns a value to the floating point variable using domain splitting.

Abstract: The present invention relates to a solution-finding method, which finds an approximate solution of an equation having difficulty in obtaining an actual solution and a complicated equation in numerical analysis. The method obtains an approximate solution of an equation having a solution in a predetermined interval. Initial values are calculated based on upper and lower limits of the interval. The initial values are applied to a solution-finding equation, including a sign function and the upper and lower limits, and the solution-finding equation is arranged so that a definite integral formula for the sign function is included in the equation. The definite integral formula in the solution-finding equation is calculated using numerical integration, and results of the definite integral formula are applied to the solution-finding equation, thus obtaining an approximate solution. This performance is iterated until the approximate solution satisfies an allowable error.

Abstract: Detection of one or more abnormal situations is performed using various statistical measures, such as a mean, a median, a standard deviation, etc. of one or more process parameters or variable measurements made by statistical process monitoring blocks within a plant. This detection is enhanced in various cases by using specialized data filters and data processing techniques, which are designed to be computationally simple and therefore are able to be applied to data collected at a high sampling rate in a field device having limited processing power. The enhanced data or measurements may be used to provided better or more accurate statistical measures of the data, may be used to trim the data to remove outliers from this data, may be used to fit this data to non-linear functions, or may be use to quickly detect the occurrence of various abnormal situations within specific plant equipment, such as distillation columns and fluid catalytic crackers.

Abstract: A Montgomery multiplication device calculates a Montgomery product of an operand X and an operand Y with respect to a modulus M and includes a plurality of processing elements. In a first clock cycle, two intermediate partial sums are created by obtaining an input of length w?1 from a preceding processing element as w?1 least significant bits. The most significant bit is configured as either zero or one. Then, two partial sums are calculated using a word of the operand Y, a word of the modulus M, a bit of the operand X, and the two intermediate partial sums. In a second clock cycle, a selection bit is obtained from a subsequent processing element and one of the two partial sums is selected based on the value of the selection bit. Then, the selected partial sum is used for calculation of a word of the Montgomery product.

Abstract: In an approximation computation apparatus, a location monitor designates, each time the number of data of a received data sequence exceeds an integer l, a starting location of the received data for calculating reduced received-data; a dimensionality reducer dimensionally reduces each data sequence including the received data after the corresponding designated starting location by random projection to generate the reduced received-data; an object selecting controller controls an object in response to a result of monitoring from the location monitor of the number of the received data reaching another integer n, deletes currently-stored object data, selects the reduced received-data after the oldest reduced received-data in the reduced received-data, and substitutes and updates an object data sequence to the selected reduced received-data; and a coefficient approximator calculates an approximate value of a wavelet coefficient on the basis of the object data and a wavelet matrix.

Abstract: In a determination as to similarity on parts of a piece of data, high-speed processing is performed without the need for a database. Division signal lines (L1 to Lk) that transmit signals corresponding to division data are used.

Abstract: A parallel residue arithmetic operation unit is provided to make it possible to reduce processing delay, and to make an additional multiplier or a residue arithmetic circuit unnecessary, so that a circuit can become small in size. In the parallel residue arithmetic operation unit, a parallel CRC calculation circuit (100) is comprised of input terminals (101)-(104) to which input data are divided into a plurality of sub-blocks and the sub-blocks are input in parallel, an initial value generating unit (110) for generating a part CRC corresponding to the forefront of each sub-block as an initial value, a part CRC generating unit (111)-(114) for receiving the part CRC corresponding to the forefront of each sub-block as the initial value and sequentially generating a residue part CRC in accordance with a recurrent equation, AND units (121)-(124) for calculating logical multiplications of part CRC values, and a cumulative adding unit (130) for cumulatively adding values output from the AND units (121)-(124).

Abstract: Analog iterative decoders are provided that are based on the so-called min-sum algorithm (also referred to as max-sum or max-product, Max-Log-MAP or BP-based decoding) and can be used to decode powerful coding schemes such as low-density parity-check (LDPC) codes and turbo codes. The circuits can be implemented by standard CMOS technology, which means lower fabrication cost and/or simpler design compared to previously reported analog iterative decoders that are based on BiCMOS or sub-threshold CMOS technology. Soft information is passed among variable nodes and parity-check nodes. A low-voltage high-swing Max WTA circuit is also provided. The circuit can be implemented by short channel MOSFET transistors and yet provide a reasonably high degree of accuracy. Applications include soft computing, and analog signal processing, in general. A Min WTA circuit can also be built based on this circuit by subtracting the input currents from a large reference current.

Abstract: Methods and apparatus, including computer systems and program products, for normalizing computer-represented collections of objects. A first minimum value can be normalized based on a second minimum value of a universal set object that corresponds to the first set object. The second minimum value is both a minimum value supported by a data type (e.g., 1-byte integer) and a minimum value defined to be in the universal set object (e.g., 0 for a universal set of all natural numbers). Similarly, a first maximum value can be normalized based on a second maximum value of the universal set object where the second maximum value is both a maximum value supported by a data type and in the universal set object. Intervals can be normalized, which can involve replacing half-open intervals with equivalent half-closed intervals. Also, a consecutively ordered, uninterrupted, sequence of values of a set object can be normalized.

Abstract: A signal processing method for performing hierarchical empirical mode decomposition (H-EMD) and an apparatus therefor are provided. In an embodiment, when empirical mode decomposition is performed on an input signal, an artificial assisting signal and the input signal are combined to assist the search for extrema and frequency reduction is performed in each iteration to eliminate the artificial assisting signal and make mode decomposition convergent so as to avoid mode mixing. In addition, in an embodiment, a hierarchical decomposition method is provided to decompose the input signal into a fewer number of fundamental modes. For needs in application, one of the fundamental modes can be further decomposed to produce a number of supplementary modes. In an embodiment, the H-EMD with appropriate frequency reduction can result in modes substantially independent of the form or the way of envelopes and can be applied to decompose multi-dimensional signals.

Abstract: A method includes providing a bipartite graph having vertices of a first type, vertices of a second type, and a plurality of edges, wherein each edge joins a vertex of the first type with a vertex of the second type. A unipartite edge dual graph is generated from the bipartite graph, and a minimum clique partition of the edge dual graph is recursively determined. A biclique is then created in the bipartite graph corresponding to each clique in the minimum clique partition of the edge dual graph.

Abstract: A modular-3 calculation method for binary number includes: determining whether two 1s consecutive from MSB exist in a binary number, when a target value for modular-3 calculation is inputted, and generating a first binary number by substituting the two 1s with 0 whenever the consecutive two 1s exist; performing a modular-3 calculation on the first binary number; and determining the result of the modular-3 calculation.

Abstract: A system and method for parallelization of saturated accumulation is provided. In the method, an input sequence is divided into a plurality of subsequences. For each subsequence, three parallel saturating additions are performed. The local saturation minimum is the saturating addition of the global saturation minimum and the values of the subsequence. The local midpoint is the saturating addition of the values of the subsequence and the local saturation maximum is the saturating addition of the global saturation maximum and the values of the subsequence. In embodiments, the accumulation total for a subsequence is calculated as the saturating addition of the accumulation total for prior subsequences and the local midpoint of the current subsequence, wherein the accumulation total of the last subsequence is the result of the saturated accumulation for the sequence. In another embodiment, the saturated addition of subsequence results are further parallelized before the final result is reached.

Abstract: The present invention provides techniques for efficiently determining a minimum or maximum of a plurality of values and the index of the minimum using registers of a processor. The present invention also provides for various processor instructions for determining the minimum/maximum and index of two or more values. The present invention finds particular benefit in implementing heaps and in systems utilizing Weighted Fair Queuing (WFQ).

Abstract: Information with respect to users, items, and interactions between the users and items is collected. Each user is associated with a set of user features. Each item is associated with a set of item features. An expected score function is defined for each user-item pair, which represents an expected score a user assigns an item. An objective represents the difference between the expected score and the actual score a user assigns an item. The expected score function and the objective function share at least one common variable. The objective function is minimized to find best fit for some of the at least one common variable. Subsequently, the expected score function is used to calculate expected scores for individual users or clusters of users with respect to a set of items that have not received actual scores from the users. The set of items are ranked based on their expected scores.

Abstract: Disclosed is an apparatus that generates automatically a characteristic pattern in time series data by clustering a plurality of time series subsequences generated from the time series data. The apparatus includes a time series subsequence generation unit that generates a plurality of time series subsequences from the time series data, a phase alignment unit that aligns a phase of the generated time series subsequence, a clustering unit that performs clustering of a plurality of the time series subsequences, each having a phase aligned, a storage apparatus that stores the pattern obtained by the clustering, and an output apparatus that outputs the stored pattern.

Abstract: A method of data processing. The method comprises applying a filter to an input sample set comprising sample values selected from an input sequence of input sample values, so as to generate a corresponding output sample value having an output sample value position with respect to the input sample set, in which the filter has a maximum output range. The method further comprises deriving a permissible output value range from an input group of two or more input sample values in the input sample set which surround the output sample value position, detecting whether the output of the filter is outside the permissible output value range and, if so, limiting the output of the filter to lie within the permissible output value range.

Abstract: A power function is approximated over an applicable data interval with polynomials determined by means of a Chebyshev minimax approximation technique. In some cases, multiple polynomials may be used to approximate the function over respective ranges of the desirable interval, in a piecewise manner. The appropriate polynomial that approximates the power function over the range of interest is derived and stored. When the power function is to be applied to a particular data value, the data value is first evaluated to determine where it lies within the applicable interval. The constants for the polynomial associated with that range of the interval are then retrieved and used to calculate the power of that data value.

Abstract: A technique to accelerate range detection in a spline calcuation. In one embodiment, an instruction and corresponding logic are provided to perform range detection within a computer or processor.

Abstract: An arithmetic process of a quadratic formula that is contained in an exponent of a CAZAC sequence-defining expression is converted to an arithmetic process of a recursion formula to find the above-described exponent, the above-described exponent that was found is used to generate a CAZAC sequence, and the above-described CAZAC sequence that was generated is taken as the reference signal for transmitting and receiving or as a random access preamble signal.